Semiconductor device

Abstract

To provide a semiconductor device including a transistor including an oxide semiconductor, in which the variation in electric characteristic is suppressed and the reliability is improved.SOLUTION: A semiconductor device includes a transistor 100. The transistor includes a gate electrode 104, gate insulating films 106 and 107 on the gate electrode, an oxide semiconductor film 108 on the gate insulating film, and a source electrode 112a and a drain electrode 112b electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film 108a on the gate electrode side and a second oxide semiconductor film 108b on the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which the atomic number ratio of In is more than the atomic number ratio of M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film includes a second region in which the atomic number ratio of In is less than that of the first oxide semiconductor film. The second region includes a part thinner than the first region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention is a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device including an oxide semiconductor film. Regarding the law.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to a product, a method, or a manufacturing method. process, machine, manufacture, or composition of matter In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, The present invention relates to a device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to devices in general. Semiconductor elements such as transistors, semiconductor circuits, computing devices, memory The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices The device may include a semiconductor device. [Background technology]

[0004] A transistor (field-effect transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology that makes up the field-effect transistor (FET) or thin-film transistor (TFT) is attracting attention. The transistor is used in integrated circuits (ICs) and image display devices (display devices). It is widely used in electronic devices. Silicon is a semiconductor thin film that can be used in transistors. Semiconductor materials such as silicon are widely known, but oxide semiconductors are also attracting attention. It is being watched.

[0005] The present invention provides a highly reliable semiconductor by imparting stable electrical characteristics to a transistor using an oxide semiconductor. To obtain the device, oxide semiconductor films with different compositions were stacked to place more In on the channel side. An oxide semiconductor film containing a large amount of stabilizers such as Ga was used on the back channel side. A semiconductor device using a compound semiconductor film has been disclosed (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2013-175715 A Summary of the Invention [Problem to be solved by the invention]

[0007] When an oxide semiconductor film containing a large amount of In is used, the energy band gap (Eg) is small. In this case, the oxide semiconductor with a large Eg may be used. Oxide semiconductors with smaller Eg than conductive films (for example, Eg between 3.0 eV and 3.5 eV) The conductive film is more susceptible to light. Stress test (photo-negative GBT (Gate Bias Temperature) stress test) In a transistor including an oxide semiconductor film having a small Eg, the reliability is decreased. This may be the case.

[0008] The light negative GBT stress test is a type of accelerated test, and is performed under light exposure for a long period of time. The change in transistor characteristics caused by the use of the , the change in the threshold voltage of the transistor before and after the light negative GBT stress test (ΔVth ) is an important indicator for investigating reliability. Before and after the light negative GBT stress test, The smaller the change in threshold voltage (ΔVth), the higher the reliability.

[0009] In view of the above problems, in one embodiment of the present invention, The objective of the present invention is to suppress the fluctuation of electrical characteristics of transistors and to improve their reliability. According to another embodiment of the present invention, there is provided a semiconductor device having reduced power consumption. Another object of the present invention is to provide a novel semiconductor Another object of the present invention is to provide a novel semiconductor device. Another object of the present invention is to provide a method for manufacturing a semiconductor device. In this regard, one of the objects is to provide a novel display device.

[0010] The above description of the problem does not preclude the existence of other problems. The embodiment does not necessarily have to solve all of these problems. Problems other than those mentioned above may be solved by the specification. The above problems are obvious from the description of the specification, etc., and problems other than those mentioned above cannot be extracted from the description of the specification, etc. It is possible to issue it. [Means for solving the problem]

[0011] One embodiment of the present invention is a semiconductor device including a transistor. a gate electrode, a gate insulating film on the gate electrode, an oxide semiconductor film on the gate insulating film, and an oxide A source electrode electrically connected to the semiconductor film and a drain electrode electrically connected to the oxide semiconductor film a gate electrode, and the oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a first and a second oxide semiconductor film on the first oxide semiconductor film, The atomic ratio of is M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film has a first region having an atomic ratio greater than that of the first oxide semiconductor film. The semiconductor film has a second region having a lower atomic ratio of In than the first region. The semiconductor device is characterized in that it has a portion thinner than the

[0012] Another embodiment of the present invention is a semiconductor device including a transistor. The transistor includes a first gate electrode, a first gate insulating film on the first gate electrode, and a first gate insulating film on the first gate electrode. An oxide semiconductor film on an insulating film, a source electrode electrically connected to the oxide semiconductor film, and an oxide a drain electrode electrically connected to the oxide semiconductor film; and a second gate insulator on the oxide semiconductor film. a second gate electrode on the second gate insulating film, A first oxide semiconductor film on a gate electrode side and a second oxide semiconductor film on the first oxide semiconductor film. The first oxide semiconductor film has an atomic ratio of In of M (M is Ti, Ga, Sn , Y, Zr, La, Ce, Nd, or Hf) in a ratio of the number of atoms of the first region. the second oxide semiconductor film has a smaller atomic ratio of In than the first oxide semiconductor film; The second region has a thinner portion than the first region. It is a semiconductor device.

[0013] In each of the above structures, the oxide semiconductor film contains In, M, and Zn. In each of the above structures, the oxide semiconductor film has a crystal part. The crystal part has a portion in which the c-axis of the crystal part is parallel to the normal vector of the surface on which the oxide semiconductor film is formed. This would be preferable.

[0014] In each of the above configurations, the first region has a higher proportion of crystal portions than the second region. In each of the above structures, the first region preferably has a larger diameter than the second region. It is preferable that the hydrogen concentration is low in the hydrogen-containing layer.

[0015] Another embodiment of the present invention is a semiconductor device and a display element according to any one of the above structures. Another embodiment of the present invention is a display device including the display device and a touch sensor. Another embodiment of the present invention is a display module having any one of the above structures. The semiconductor device according to any one of claims 1 to 5, the display device, or the display module, and an operation key or and a battery.

[0016] Another embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, forming a gate electrode on a substrate; and forming a gate insulating film on the gate electrode. forming a first oxide semiconductor film over a gate insulating film; A step of forming a second oxide semiconductor film, and forming a source electrode and a drain electrode on the second oxide semiconductor film. forming a gate electrode, forming an oxide insulating film on the second oxide semiconductor film, and forming an oxide conductive film on the oxide insulating film; and removing the oxide conductive film. In the step of forming the doped electrode, a portion of the second oxide semiconductor film is The oxide insulating film is thinner than the semiconductor film. The process of forming the oxide insulating film is performed in a PECVD device at 180°C. The oxide insulating film is formed at a temperature of 350° C. or higher during a process for manufacturing a transistor. The manufacturing method of the semiconductor device is characterized in that the temperature in the step of forming the semiconductor device is the highest.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device including a transistor, forming a first gate electrode on a substrate; and forming a first gate insulating film on the first gate electrode. forming a first oxide semiconductor film on the first gate insulating film; forming a second oxide semiconductor film on the first oxide semiconductor film; forming a source electrode and a drain electrode on the second oxide semiconductor film; forming an oxide insulating film which functions as a gate insulating film; and adding oxygen to the oxide insulating film through the oxide conductive film. a step of removing the oxide conductive film; and a step of forming a second gate electrode on the oxide insulating film. In the step of forming a source electrode and a drain electrode, The oxide insulating film is formed by forming a first oxide semiconductor film on the first oxide semiconductor film. This is carried out in a PECVD apparatus at a temperature between 180°C and 350°C, and transistor fabrication is performed. A semiconductor device characterized in that the temperature in the step of forming an oxide insulating film is the highest among the steps. A method for making the device.

[0018] In each of the above structures, the first oxide semiconductor film and the second oxide semiconductor film each have Oxygen, In, Zn, and M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). In each of the above structures, the first oxide The semiconductor film and the second oxide semiconductor film each have a crystal part, and the crystal part has a c The axis is parallel to the normal vector of the surface on which the first oxide semiconductor film is formed, or It is preferable that the semiconductor layer has a portion parallel to the normal vector of the surface on which the semiconductor layer is formed. Effect of the Invention

[0019] According to one embodiment of the present invention, a semiconductor device including a transistor including an oxide semiconductor As a result, the fluctuation of the electrical characteristics can be suppressed and the reliability can be improved. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. In the present invention, a method for manufacturing a novel semiconductor device can be provided. According to one embodiment of the present invention, a novel display device can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have to have all of these effects. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other effects from the descriptions in the claims, etc. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1B are a top view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 2] FIG. 1 is a cross-sectional view illustrating one embodiment of a semiconductor device. [Diagram 3] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 4] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Diagram 5] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 6] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. [Figure 8] FIG. 1 is a top view illustrating one embodiment of a display device. [Figure 9] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 10] FIG. 1 is a cross-sectional view showing one embodiment of a display device. [Figure 11] 1A and 1B are a block diagram and a circuit diagram illustrating a display device. [Figure 12] FIG. 2 is a diagram illustrating a display module. [Figure 13] 1A to 1C are diagrams illustrating electronic devices. [Figure 14] FIG. 1 is a diagram illustrating the results of SIMS analysis. [Figure 15] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 16] FIG. 1 is a diagram illustrating the results of TDS analysis. [Figure 17] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 18] FIG. 1 is a diagram illustrating the ESR measurement results. [Figure 19] FIG. 13 is a graph showing ID-VG characteristics of a transistor in the embodiment. [Figure 20] FIG. 13 is a graph showing ID-VG characteristics of a transistor in the embodiment. [Figure 21] FIG. 13 is a graph showing ID-VG characteristics of a transistor in the embodiment. [Figure 22] 13 shows the results of a gate BT stress test of a transistor according to an embodiment. [Figure 23] 13 shows the results of a gate BT stress test of a transistor according to an embodiment. [Figure 24] FIG. 13 is a graph showing ID-VG characteristics of a transistor in the embodiment. [Diagram 25] FIG. 13 is a graph showing ID-VG characteristics of a transistor in the embodiment. [Figure 26] FIG. 13 is a graph showing ID-VG characteristics of a transistor in the embodiment. [Figure 27] 11A and 11B are diagrams for explaining probability distributions of Vth and Ion of a transistor in the embodiment. [Figure 28] 13A to 13C are diagrams illustrating the results of a gate BT stress test of a transistor in the embodiment. [Figure 29] 13A to 13C are diagrams illustrating the results of a gate BT stress test of a transistor in the embodiment. [Diagram 30] FIG. 2 is a top view of a pixel portion of a display device according to the embodiment. [Diagram 31] FIG. 2 is a top view illustrating a frame region of a display device according to an embodiment. [Diagram 32] FIG. 4 is a cross-sectional view of a pixel section and a protection circuit section in the embodiment. [Diagram 33] FIG. 2 is a circuit diagram illustrating a protection circuit according to an embodiment. [Diagram 34] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Diagram 35] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Diagram 36] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Figure 37] Electron diffraction pattern of CAAC-OS. [Figure 38] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 39] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Diagram 40] A diagram explaining InGaZnO4 crystals and pellets. [Diagram 41] Schematic diagram explaining a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the drawings. It is possible to carry out the present invention in various forms without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details of the present invention. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0023] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The drawings are merely schematic illustrations and are not limited to the shapes or values ​​shown in the drawings.

[0024] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0025] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0026] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) A current flows through the drain, the channel region, and the source. In this specification and the like, the channel region refers to a region through which a current mainly flows. The flow area.

[0027] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0028] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a "device having some electrical function." "of" is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "something that has an electrical effect" includes electrodes, wiring, and transistors. These devices have various functions such as switching elements, resistor elements, inductors, capacitors, etc. This includes elements such as:

[0029] In this specification and the like, a silicon oxynitride film is a film having a composition containing more oxygen than nitrogen. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content of.

[0030] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, The reference numerals are used commonly among different drawings.

[0031] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0032] In this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the term "conductive layer" may be used interchangeably. In some cases, the term "conductive film" may be changed to "conductive film". For example, the term "insulating film" may be changed to the term "insulating layer." .

[0033] (Embodiment 1) In this embodiment, a semiconductor device and a manufacturing method of the semiconductor device according to one embodiment of the present invention will be described. The following description will be given with reference to FIG. 1 to FIG.

[0034] <Configuration Example 1 of Semiconductor Device> FIG. 1A is a top view of a transistor 100 which is a semiconductor device of one embodiment of the present invention. 1B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 1A. FIG. 1C is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 1A. In FIG. 1A, in order to avoid complication, the transistor 100 Some of the components (such as the insulating film that functions as the gate insulating film) are omitted in the figure. The dashed line X1-X2 direction is the channel length direction, and the dashed line Y1-Y2 direction is the channel width direction. In the top view of the transistor, As in FIG. 1(A), some of the components may be omitted.

[0035] The transistor 100 includes a conductive film 104 over a substrate 102, which functions as a gate electrode, and a An insulating film 106 on the plate 102 and the conductive film 104, and an insulating film 107 on the insulating film 106, The oxide semiconductor film 108 on the film 107 and the source electrode 106 electrically connected to the oxide semiconductor film 108 The conductive film 112a serving as a gate electrode and the gate electrode electrically connected to the oxide semiconductor film 108 The transistor 100 has a conductive film 112b which functions as a drain electrode. In more detail, the insulating film 114 is formed over the conductive films 112a and 112b and the oxide semiconductor film 108. , 116, and an insulating film 118 are provided. The insulating films 114, 116, and 118 are It functions as a protective insulating film for the photoresist 100.

[0036] In addition, the oxide semiconductor film 108 is formed by disposing the first oxide semiconductor film 108 on the conductive film 104 side which functions as a gate electrode. The first oxide semiconductor film 108a and the second oxide semiconductor film 10 on the first oxide semiconductor film 108a are The insulating film 106 and the insulating film 107 are formed on the gate of the transistor 100. It functions as an insulating film.

[0037] The oxide semiconductor film 108 is In-M (wherein M is Ti, Ga, Sn, Y, Zr, La , Ce, Nd, or Hf) oxide, In-M-Zn oxide can be used. In particular, it is preferable to use In-M-Zn oxide for the oxide semiconductor film 108.

[0038] The first oxide semiconductor film 108a has a first oxide semiconductor layer in which the atomic ratio of In is larger than the atomic ratio of M. The second oxide semiconductor film 108b has a region similar to that of the first oxide semiconductor film 108. The second region has a lower atomic ratio of In than the first region a. It has a thinner portion than

[0039] A first region in which the atomic ratio of In is larger than the atomic ratio of M is formed in the first oxide semiconductor film 108a. By having such a structure, the field effect mobility (simply called mobility, or μFE) of the transistor 100 can be improved. In particular, the field effect transport (FEM) of the transistor 100 can be increased. Degree is 10cm 2 / Vs, and more preferably the field effect mobility of the transistor 100 30cm 2 / Vs can be exceeded.

[0040] For example, the above-mentioned high field effect mobility transistor is used as a gate driver for generating a gate signal. A driver (especially a demux connected to the output terminal of a shift register of a gate driver) By using it in a semiconductor device or display device with a narrow frame (also called a narrow frame), Locations can be provided.

[0041] On the other hand, a first oxide semiconductor having a first region in which the atomic ratio of In is greater than the atomic ratio of M is By using the solid film 108a, the electrical characteristics of the transistor 100 are less likely to change when irradiated with light. However, in the semiconductor device according to one embodiment of the present invention, the first oxide semiconductor film 10 A second oxide semiconductor film 108b is formed on the second oxide semiconductor film 8a. The thickness of the first oxide semiconductor film 108b in the vicinity of the channel region is smaller than the thickness of the first oxide semiconductor film 108a. .

[0042] The second oxide semiconductor film 108b has a higher In content than the first oxide semiconductor film 108a. Since the second region has a smaller atomic ratio, Eg is smaller than that of the first oxide semiconductor film 108a. Therefore, the first oxide semiconductor film 108a and the second oxide semiconductor film 10 The oxide semiconductor film 108 having a stacked structure with 8b has a resistance to a negative bias stress test using light irradiation. will become higher.

[0043] By using the oxide semiconductor film having the above structure, the oxide semiconductor film 108 can be prevented from being damaged by light irradiation. Therefore, the amount of absorption of the transistor 100 during light irradiation can be reduced. Fluctuations in electrical characteristics can be suppressed. Since the insulating film 114 or the insulating film 116 contains excess oxygen, the insulating film 114 or the insulating film 116 is not irradiated with light. This can further suppress the fluctuation in the electrical characteristics of the transistor 100.

[0044] Here, the oxide semiconductor film 108 will be described in detail with reference to FIG.

[0045] FIG. 2 is an enlarged view of the oxide semiconductor film 108 and its surroundings in the transistor 100 shown in FIG. FIG.

[0046] In FIG. 2, the thickness of the first oxide semiconductor film 108a is t1, and the thickness of the second oxide semiconductor film 108b is t2. The thicknesses of the oxide film 108b are indicated as t2-1 and t2-2, respectively. Since the second oxide semiconductor film 108b is provided on the oxide semiconductor film 108a, When the films 112a and 112b are formed, the first oxide semiconductor film 108a is etched by the etching gas. Therefore, the first oxide semiconductor film 1 is not exposed to gas, etching solution, or the like. In the case of 08a, the film thickness is not reduced or is very small. In the case of 108b, when the conductive films 112a and 112b are formed, the second oxide semiconductor The portions of the film 108b that do not overlap the conductive films 112a and 112b are etched to form recesses. That is, the second oxide semiconductor film 108b overlaps with the conductive films 112a and 112b. The thickness of the region is t2-1, and the conductive films 112a and 112b of the second oxide semiconductor film 108b are The thickness of the region not overlapping with b is t2-2.

[0047] The relationship between the thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is as follows: It is preferable that -1>t1>t2-2. By making such a film thickness relationship, high A transistor having a high field effect mobility and a small change in threshold voltage when irradiated with light. It is possible to make it a gyroscope.

[0048] In addition, when oxygen vacancies are formed in the oxide semiconductor film 108 of the transistor 100, This generates electrons as carriers, and the device is prone to normally-on characteristics. By reducing oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a, This is also important in obtaining stable transistor characteristics. In the configuration of the transistor, an insulating film on the oxide semiconductor film 108, By introducing excess oxygen into the insulating film 114 and / or the insulating film 116 on the insulating film 108, Oxygen is transferred from the insulating film 114 and / or the insulating film 116 into the oxide semiconductor film 108, and the oxide semiconductor film 108 is oxidized. To compensate for oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a. It is characterized by:

[0049] The insulating films 114 and 116 are formed from a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating films 114 and 116 preferably have an oxygen excess region. The insulating films 114 and 116 are insulating films capable of releasing oxygen. To provide a region, for example, oxygen is introduced into the insulating films 114 and 116 after film formation to form an oxygen-excess region. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, plasma treatment, or the like can be used.

[0050] In addition, in order to compensate for oxygen deficiency in the first oxide semiconductor film 108a, it is preferable to reduce the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b. Therefore, the relationship of t2-2 < t1 may be satisfied. For example, the film thickness in the vicinity of the channel region of the second oxide semiconductor film 108b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less.

[0051] Hereinafter, other components included in the semiconductor device of the present embodiment will be described in detail.

[0052] <Substrate> There is no significant limitation on the material of the substrate 102, etc., but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc., using silicon or silicon carbide as a material can also be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 102. When using a glass substrate as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), etc. By using large-area substrates such as 10th generation (2950mm x 3400mm), Larger display devices can be manufactured.

[0053] In addition, a flexible substrate is used as the substrate 102, and the transistor 10 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistor 100. The release layer is preferably removed from the substrate 102 after a semiconductor device is partially or completely completed thereon. The transistor 100 can be separated and transferred to another substrate. It can also be transferred to substrates with poor thermal properties or flexible substrates.

[0054] <Conductive films functioning as gate electrode, source electrode, and drain electrode> A conductive film 104 functioning as a gate electrode and a conductive film 112 functioning as a source electrode. The conductive film 112b functioning as a drain electrode is made of chromium (Cr), copper (C u), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (M o), Tantalum (Ta), Titanium (Ti), Tungsten (W), Manganese (Mn), Ni A metal element selected from nickel (Ni), iron (Fe), and cobalt (Co), or the above-mentioned The alloys are made of metal elements or alloys combining the above metal elements. It can be formed.

[0055] The conductive films 104, 112a, and 112b may have a single-layer structure or a laminated structure of two or more layers. For example, a single layer structure of an aluminum film containing silicon, titanium on an aluminum film, A two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a titanium nitride film A two-layer structure in which a tungsten film is laminated on top of a tantalum nitride film or a tungsten nitride film A two-layer structure in which a tungsten film is laminated, a titanium film, and an aluminum film is laminated on the titanium film. There are three-layer structures, such as a titanium film on top of an aluminum film. Select from tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Alternatively, an alloy film or a nitride film made by combining one or more of these may be used.

[0056] The conductive films 104, 112a, and 112b are made of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide A conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. It is also possible.

[0057] The conductive films 104, 112a, and 112b are made of a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied. This allows processing using a wet etching process, which reduces manufacturing costs. It becomes possible.

[0058] <Insulating film that functions as a gate insulating film> The insulating films 106 and 107 functioning as the gate insulating film of the transistor 100 are Plasma Enhanced Chemical Vapor Deposition (PECVD) Silicon oxide is deposited by vapor deposition, sputtering, etc. silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film , hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, oxide Tantalum film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film Each of the insulating films 106 and 107 can be an insulating layer including one or more films. A single-layer insulating film selected from the above materials, or an insulating film having three or more layers, without using a laminated structure. may also be used.

[0059] The insulating film 106 also functions as a blocking film that suppresses oxygen permeation. For example, the insulating films 107, 114, and 116 and / or the oxide semiconductor film 108 may contain an excess of acid. When oxygen is supplied, the insulating film 106 can suppress oxygen permeation.

[0060] Note that the oxide semiconductor film 108 functioning as a channel region of the transistor 100 The insulating film 107 is preferably an oxide insulating film, and has an oxide content in excess of the stoichiometric composition. It is more preferable that the insulating film 1 has a region containing oxygen (an oxygen excess region). The insulating film 107 is capable of releasing oxygen. In order to provide the insulating film 107, for example, the insulating film 107 may be formed in an oxygen atmosphere. Oxygen may be introduced into the insulating film 107 to form an oxygen excess region. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma Zuma processing or the like can be used.

[0061] When hafnium oxide is used as the insulating film 107, the following effects are obtained. Hafnium has a higher dielectric constant than silicon oxide and silicon oxynitride. Compared to the case where silicon oxide is used, the thickness of the insulating film 107 can be made larger, so that the tunnel This reduces the leakage current caused by the current. Furthermore, hafnium oxide having a crystalline structure can be used to realize an amorphous structure. It has a higher relative dielectric constant than hafnium oxide, which has a low off-current. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic. The types are not limited to these.

[0062] In this embodiment, a silicon nitride film is formed as the insulating film 106, and the insulating film 107 The silicon oxide film is formed as a result of the above. The silicon nitride film has a lower dielectric constant than the silicon oxide film. The film thickness required to obtain the same capacitance as a silicon oxide film is large, so it is suitable for transistors. The gate insulating film of the transistor 100 can be made thick by including a silicon nitride film. Therefore, the decrease in the dielectric strength of the transistor 100 can be suppressed, and the dielectric strength can be increased. This can improve the resistance of the transistor 100 and suppress electrostatic damage to the transistor 100.

[0063] <Oxide semiconductor film> The oxide semiconductor film 108 can be formed using the above-mentioned materials. In the case where 108 is an In-M-Zn oxide, the sintered body used for forming the In-M-Zn oxide film is The atomic ratio of the metal elements in the sputtering target preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in such a sputtering target is preferably In:M: Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, I The preferred ranges are n:M:Zn=3:1:2 and In:M:Zn=4:2:4.1. When the semiconductor film 108 is an In-M-Zn oxide, the sputtering target is preferably It is preferable to use a target containing crystalline In-M-Zn oxide. By using a target containing Zn oxide, a crystalline oxide semiconductor film 108 was formed. Note that the atomic ratio of the oxide semiconductor film 108 to be formed is subject to an error and The atomic ratio of the metal elements contained in the sputtering target is ±4. For example, a sputtering target with an atomic ratio of In:Ga: When Zn=4:2:4.1 is used, the atomic ratio of the oxide semiconductor film 108 to be formed is I In some cases, the n:Ga:Zn ratio is approximately 4:2:3.

[0064] For example, the first oxide semiconductor film 108a may be formed using the above-mentioned In:M:Zn=2:1:3 , In:M:Zn=3:1:2, In:M:Zn=4:2:4.1, etc. The second oxide semiconductor film 108b may be formed using the above-described oxide semiconductor film 108b. If the material is formed using In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, etc. Note that the metal element of the sputtering target used for the second oxide semiconductor film 108b is The atomic ratio of elements does not necessarily have to satisfy In≧M, Zn≧M, but In≧M, Zn <Mを A specific example of the composition is In:M:Zn=1:3:2.

[0065] The oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. By using a nitride semiconductor, the off-state current of the transistor 100 can be reduced. In particular, the first oxide semiconductor film 108a is preferably made of a material having an energy gap of 2 eV or more. The second oxide semiconductor film 108b is an oxide semiconductor film having a conductivity of 2 eV to 3.0 eV. When an oxide semiconductor film having an energy gap of 2.5 eV or more and 3.5 eV or less is used, In addition, the second oxide semiconductor film 108b is more preferable than the first oxide semiconductor film 108a. It is preferable that the energy gap is large.

[0066] The thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are Each of them is 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, and more preferably Preferably, the thickness is 3 nm or more and 50 nm or less. It is preferable that the thickness relationship described above is satisfied. .

[0067] The second oxide semiconductor film 108b is an oxide semiconductor film with low carrier density. For example, the second oxide semiconductor film 108b has a carrier density of 1×10 17 pcs / c m 3 Less than or equal to 1×10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 Less than or equal to 1×10 11 pieces / cm 3 The following applies.

[0068] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of the transistor, The carrier density, impurity concentration, defect density, metal element and oxygen atoms of the oxide semiconductor film 108b It is preferable to make the numerical ratio, interatomic distance, density, etc. appropriate.

[0069] Note that the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are By using an oxide semiconductor film having a low impurity concentration and a low density of defect states, This is preferable because it allows the fabrication of a transistor with excellent electrical characteristics. The term "high purity intrinsic or substantially intrinsic" refers to a material with a low oxygen concentration and a low defect level density (low oxygen vacancies). A highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film is called a highly pure intrinsic oxide semiconductor film. Since the number of rear generation sources is small, the carrier density can be reduced. The transistor in which the channel region is formed in the semiconductor film has a negative threshold voltage. It is also rare for the material to become normally on. A highly pure intrinsic oxide semiconductor film has a low density of defect states and therefore a low density of trap states. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film may be formed by The off-state current is extremely small, and the channel width is 1×10 6 μm and channel length L is 10 μm However, the voltage between the source and drain electrodes (drain voltage) is in the range of 1V to 10V. In the range, the off-state current is below the measurement limit of the semiconductor parameter analyzer, that is, 1×1 0 -13 It is possible to obtain a characteristic of A or less.

[0070] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is provided with a channel. The transistors in which the regions are formed have small variations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are dissipated. It takes a long time for the charge to reach a certain level, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states has a high current density. Impurities include hydrogen, nitrogen, alkali metals, or Alkaline earth metals, etc.

[0071] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. In this case, oxygen vacancies are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). When hydrogen enters the electron carrier, it can generate electrons. It can combine with oxygen, which combines with metal atoms, to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen has normally-on characteristics. For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor film 108 be reduced as much as possible. Specifically, in the oxide semiconductor film 108, a hydrogen concentration obtained by SIMS analysis is Degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 below Let us assume that.

[0072] The first oxide semiconductor film 108a has a higher hydrogen concentration than the second oxide semiconductor film 108b. It is preferable that the first oxide semiconductor film 108a has a portion where the degree of oxidation is small compared to that of the second oxide semiconductor film 108b. By having a portion with a lower hydrogen concentration than the semiconductor film 108b, The present invention can be an apparatus.

[0073] In addition, the first oxide semiconductor film 108a contains silicon and carbon, which are group 14 elements. When the first oxide semiconductor film 108a contains oxygen, oxygen vacancies are increased in the first oxide semiconductor film 108a, and the first oxide semiconductor film 108a becomes an n-type oxide semiconductor. Therefore, the concentrations of silicon and carbon in the first oxide semiconductor film 108a and The concentrations of silicon and carbon in the vicinity of the interface with the oxide semiconductor film 108a in FIG. 1 (by SIMS analysis) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0074] In addition, in the first oxide semiconductor film 108a, the alkali metal oxide film The concentration of metal or alkaline earth metal is 1×10 18 atoms / cm 3 The following is preferably is 2 × 10 16 atoms / cm 3 The following are the alkali metals and alkaline earth metals: When a compound is bonded to an oxide semiconductor, carriers may be generated, increasing the off-state current of a transistor. For this reason, the alkali metal or It is preferable to reduce the concentration of alkaline earth metals.

[0075] When the first oxide semiconductor film 108a contains nitrogen, electrons serving as carriers This increases the carrier density and makes it easier to become n-type. A transistor using a conductor film tends to have a normally-on characteristic. In the solid film, it is preferable that nitrogen is reduced as much as possible. For example, SIMS analysis The nitrogen concentration obtained is 5×10 18 atoms / cm 3 It is preferable to do the following: .

[0076] The first oxide semiconductor film 108a and the second oxide semiconductor film 108b are The non-single crystal structure may be, for example, CAAC-OS (CAx is Aligned Crystalline Oxide Semiconductor or), polycrystalline, microcrystalline, or amorphous structures. The crystalline structure has the highest density of defect states, while the CAAC-OS has the lowest density of defect states.

[0077] <An insulating film that functions as a protective insulating film for transistors> The insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108. The insulating film 118 functions as a protective insulating film for the transistor 100. The films 114 and 116 contain oxygen. The insulating film 114 is also impermeable to oxygen. The insulating film 114 is an insulating film formed by etching when the insulating film 116 is formed later. It also functions as a film for reducing damage to the compound semiconductor film 108 .

[0078] The insulating film 114 has a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 1 nm or less can be used.

[0079] In addition, it is preferable that the insulating film 114 has a small amount of defects. Typically, the insulating film 114 has a small amount of defects as determined by ESR measurement. The spin density of the signal at g=2.001 originating from the silicon dangling bond is is 3×10 17 spins / cm 3 This is because the insulating film 114 is preferably If the density of defects is high, oxygen will be bonded to the defects, and the oxygen in the insulating film 114 will The amount of transmission of the light is reduced.

[0080] In the insulating film 114, all of the oxygen that has entered the insulating film 114 from the outside is Some oxygen does not move to the outside of the insulating film 114 and remains in the insulating film 114. At the same time, oxygen contained in the insulating film 114 moves to the outside of the insulating film 114, In some cases, oxygen may move through the film 114. When the oxide insulating film capable of forming the insulating film 116 is formed over the insulating film 114, The desorbed oxygen can be transferred to the oxide semiconductor film 108 through the insulating film 114. .

[0081] The insulating film 114 is formed using an oxide insulating film having a low density of states caused by nitrogen oxides. Note that the density of states due to the nitrogen oxides can be determined by the valence Energy of the upper edge of the electronic band (Ev_os) and the lower edge of the conduction band of the oxide semiconductor film (Ec_os) may be formed during the v_os and E c_os Nitrogen oxide during As the oxide insulating film having a low density of states of the semiconductor, a silicon oxynitride film which emits a small amount of nitrogen oxide is used. It is possible to use aluminum oxide nitride film, which emits less nitrogen oxide, or aluminum oxynitride film, which emits less nitrogen oxide. Cut.

[0082] In addition, the silicon oxynitride film, which emits a small amount of nitrogen oxide, is This membrane releases more ammonia than nitrogen oxides, and typically releases ammonia. The amount of emission is 1×10 18 pieces / cm 3 5×10 or more 19 pieces / cm 3 The following is the case. The amount of monia released is determined when the surface temperature of the membrane is 50°C or higher and 650°C or lower, preferably 50°C or higher and 55°C or lower. This is the amount released by heating at 0℃ or below.

[0083] Nitrogen oxides (NO x , x is 0 or more and 2 or less, preferably 1 or more and 2 or less), typically NO 2 or NO forms a level in the insulating film 114 or the like. Therefore, the nitrogen oxide is in the insulating film 114 and the oxide When the electrons diffuse to the interface of the semiconductor film 108, the level traps the electrons on the insulating film 114 side. As a result, the trapped electrons may be trapped in the insulating film 114 and the oxide semiconductor film 115. 108The threshold voltage of the transistor is shifted in the positive direction because it remains near the interface. Put away.

[0084] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. The nitrogen oxide contained in the insulating film 116 reacts with ammonia contained in the insulating film 116 during the heat treatment. Therefore, the amount of nitrogen oxide contained in the insulating film 114 is reduced. Electrons are less likely to be trapped at the interface between the oxide semiconductor film 106 and the oxide semiconductor film 108.

[0085] By using the oxide insulating film as the insulating film 114, the threshold voltage of the transistor It is possible to reduce the shift in the electrical characteristics of the transistor. can.

[0086] Heat treatment in the manufacturing process of a transistor is typically performed at a temperature of 300° C. or higher and lower than 350° C. By the heat treatment, the insulating film 114 shows the following characteristics in the spectrum obtained by ESR measurement at 100K or less: The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2.001 to 2.002. A second signal with a g value of .003 or less and a third signal with a g value between 1.964 and 1.966, inclusive. A null is observed. Note that the split width of the first signal and the second signal, The split width of the second and third signals is about 5 in the X-band ESR measurement. mT. The first signal has a g value of 2.037 to 2.039, and the second signal has a g value of 2. A second signal between 0.001 and 2.003, and a g value between 1.964 and 1.966 The total spin density of the third signal is 1×10 18 spins / cm 3 is less than Typically 1×10 17 spins / cm 3 More than 1×10 18 spins / cm 3 Less than be.

[0087] In addition, the g value in the ESR spectrum below 100K is 2.037 to 2.039. The first signal has a g value of 2.001 to 2.003, and the second signal has a g value of 1 The third signal, between .964 and 1.966, is nitrogen oxide (NO x , x is 0 to 2 Representative examples of nitrogen oxides include: , nitrogen monoxide, nitrogen dioxide, etc. That is, the first group with a g value of 2.037 to 2.039. a signal with a g value between 2.001 and 2.003, and a second signal with a g value between 1.9 The lower the sum of the spin densities of the third signals (between 64 and 1.966), the higher the oxide insulation. It can be said that the nitrogen oxide content in the coating is low.

[0088] The nitrogen concentration of the oxide insulating film measured by SIMS is 6×10 20 atoms / cm 3 The following is the result.

[0089] The substrate temperature is between 220℃ and 350℃, and PEC using silane and nitrous oxide is used. By forming the oxide insulating film by the VD method, a dense and hard film can be obtained. It can be formed.

[0090] The insulating film 116 is an oxide insulating film containing more oxygen than the oxygen required for the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is formed using When heated, some of the oxygen is released. The oxygen content is greater than the stoichiometric composition. The oxide insulating film had a loss of oxygen of 1.0×10 in terms of oxygen atoms as determined by TDS analysis. 1 9 atoms / cm 3 More than 3.0×10 20 atoms / cm 3 That's all. The oxide insulating film is a thin film. The surface temperature of the film during the TDS analysis was 100°C or less. The temperature range is preferably from 100° C. to 500° C. or from 100° C. to 700° C.

[0091] The insulating film 116 has a thickness of 30 nm to 500 nm, preferably 50 nm or more. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or less can be used.

[0092] In addition, it is preferable that the insulating film 116 has a small amount of defects. The spin density of the signal at g=2.001 originating from the silicon dangling bond is is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the insulating film 116 is preferably an oxide semiconductor compared to the insulating film 114. Since it is separated from the insulating film 108, it may have a higher defect density than the insulating film 114.

[0093] In addition, the insulating films 114 and 116 can be made of the same material, so that the insulating films In some cases, the interface between the film 114 and the insulating film 116 cannot be clearly seen. In this embodiment, the interface between the insulating film 114 and the insulating film 116 is shown by a dashed line. In the embodiment, the two-layer structure of the insulating film 114 and the insulating film 116 has been described. For example, the insulating film 114 may have a single-layer structure without being limited thereto.

[0094] The insulating film 118 contains nitrogen. The insulating film 118 also contains nitrogen and silicon. The insulating film 118 is also resistant to blockages such as oxygen, hydrogen, water, alkali metals, and alkaline earth metals. By providing the insulating film 118, the oxide semiconductor film 108 can prevent the oxidation of the oxide semiconductor film 108. The diffusion of oxygen contained in the insulating films 114 and 116 to the outside, and the diffusion of oxygen from the outside This can prevent hydrogen, water, and the like from entering the oxide semiconductor film 108. For example, a nitride insulating film can be used. Silicon nitride oxide, aluminum nitride, aluminum oxide nitride, etc. Nitride insulating material with blocking effect against hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of the insulating film, an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc. may be provided. As an oxide insulating film having a blocking effect against oxygen, hydrogen, water, etc., aluminum oxide is preferably used. nium, aluminum oxide nitride, gallium oxide, gallium oxide nitride, yttrium oxide, Examples include yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

[0095] Note that the various films described above, such as the conductive film, the insulating film, and the oxide semiconductor film, are formed by sputtering. It can be formed by the CVD method or PECVD method, but other methods such as thermal CVD (Ch emical vapor deposition (ALD) method or Atomic The thermal CVD method may be used. OCVD(Metal Organic Chemical Vapor Deposit) tion method.

[0096] Thermal CVD is a film formation method that does not use plasma, so defects can occur due to plasma damage. This has the advantage that no additional steps are required.

[0097] In the thermal CVD method, the source gas and the oxidizing agent are fed into the chamber at the same time, and the chamber is heated to atmospheric pressure. Alternatively, a film is formed by reacting the reactants near or on the substrate under reduced pressure and depositing the reactants on the substrate. You may go.

[0098] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases may be introduced into the chamber in sequence, and the film may be formed by repeating the gas introduction sequence. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first layer. The second layer is deposited on the first layer by reacting with the second source gas introduced later. This process is repeated several times while controlling the gas introduction sequence until a thin film of the desired thickness is formed. By doing so, a thin film with excellent step coverage can be formed. The thickness of the thin film depends on the order of gas introduction. The thickness can be precisely adjusted by changing the number of times the process is repeated. This is suitable for producing thin FETs.

[0099] Thermal CVD methods such as MOCVD can be used to form the conductive film, insulating film, oxide semiconductor film, It is possible to form various films such as metal oxide films. For example, an In-Ga-ZnO film can be formed. In this case, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula for trimethylindium is In(CH3)3. The chemical formula for gallium is Ga(CH3)3. The chemical formula for dimethylzinc is Zn( CH3)2. In addition, the combination is not limited to these, and instead of trimethylgallium, Alternatively, triethylgallium (chemical formula Ga(C2H5)3) can be used, and dimethylzinc Alternatively, diethylzinc (chemical formula Zn(C2H5)2) can be used.

[0100] For example, when forming a hafnium oxide film using a film forming apparatus that uses ALD, the solvent and liquids containing hafnium precursor compounds (hafnium alkoxides, tetrakisdimethyl The raw material gas is made by vaporizing hafnium amide (such as TDMAH) and acid. Two types of gases are used: tetrakisdimethylamide (TDA) and ozone (O3) as a chlorine gas. The chemical formula for fluorine is Hf[N(CH3)2]4. Other liquid materials include tetrahydrofuran. Examples include rakis(ethylmethylamido)hafnium.

[0101] For example, when forming an aluminum oxide film using an ALD deposition system, A liquid containing a catalyst and an aluminum precursor compound (e.g., trimethylaluminum (TMA)) is added. Two types of gases are used: vaporized source gas and H2O as an oxidizing agent. The chemical formula for aluminum is Al(CH3)3. Other liquid materials include Tris( Dimethylamido)aluminum, triisobutylaluminum, aluminum tris(2 ,2,6,6-tetramethyl-3,5-heptanedionate).

[0102] For example, when forming a silicon oxide film using a deposition system that uses ALD, Chlorodisilane is adsorbed onto the surface to be coated, removing the chlorine contained in the adsorbed matter, and the oxidizing gas (O 2. Nitrous oxide (NO) radicals are supplied to react with the adsorbed material.

[0103] For example, when forming a tungsten film using an ALD deposition system, WF6 The initial tungsten film was formed by repeatedly introducing B2H6 gas and WF 6 gas and H2 gas are introduced simultaneously to form a tungsten film. Alternatively, SiH4 gas may be used.

[0104] For example, an oxide semiconductor film, such as In-Ga-ZnO, can be formed by a film formation apparatus using ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced in sequence and repeatedly to form an In- Then, Ga(CH3)3 gas and O3 gas are repeatedly introduced to form a GaO Then, Zn(CH3)2 and O3 gases were repeatedly introduced to form a ZnO layer. The order of these layers is not limited to this example. Even if a mixed compound layer such as an n-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer is formed, It is good. In addition, H2O gas obtained by bubbling inert gas such as Ar instead of O3 gas is However, it is preferable to use O3 gas that does not contain H. In(CH3) Instead of the In(C2H5)3 gas, Ga(CH3)3 gas may be used. Instead of gas, Ga(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used. You may use it.

[0105] <Configuration Example 2 of Semiconductor Device> Next, examples of a configuration different from that of the transistor 100 shown in FIGS. 3(A), (B), and (C) will be used. Note that the functions described above are the same as those described above. In some cases, the hatch patterns may be the same and no particular reference numbers may be used.

[0106] FIG. 3A is a top view of a transistor 170 which is a semiconductor device of one embodiment of the present invention. 3B corresponds to a cross-sectional view taken along dashed line X1-X2 in FIG. 3A. FIG. 3(C) is a cross-sectional view taken along the dashed line Y1-Y2 in FIG. 3(A). Correct.

[0107] The transistor 170 includes a conductive film 104 over a substrate 102, the conductive film 104 serving as a first gate electrode. an insulating film 106 on the substrate 102 and the conductive film 104; and an insulating film 107 on the insulating film 106. , an oxide semiconductor film 108 on the insulating film 107, and an insulating film 114 on the oxide semiconductor film 108. , an insulating film 116 on the insulating film 114, and a source The conductive film 112a serving as an electrode and the drain electrically connected to the oxide semiconductor film 108 112b functioning as an in-electrode, an insulating film 114 on the oxide semiconductor film 108, and an insulating film An insulating film 116 on the insulating film 114, an insulating film 118 on the insulating film 116, and a conductive film on the insulating film 118. 120a and a conductive film 120b on the insulating film 118. The conductive film 18 functions as a second gate insulating film of the transistor 170. The conductive layer 120a is electrically connected to the insulating film 114, 116, and 118 through an opening 142c. In the transistor 170, the conductive film 120a is electrically connected to the conductive film 112b. For example, the transistor 17 functions as a pixel electrode used in a display device. In FIG. 1, the conductive film 120b is used as a second gate electrode (also called a back gate electrode). It works.

[0108] As shown in FIG. 3C, the conductive film 120b is formed by insulating films 106, 107, 114, and 1 In the openings 142a and 142b provided in the gate electrodes 16 and 118, Therefore, the conductive film 120b and the conductive film 104 are the same. A potential is applied.

[0109] In this embodiment, openings 142a and 142b are provided, and the conductive film 120b and Although the configuration in which the conductive film 104 is connected has been illustrated, the present invention is not limited to this. Only one of the openings 142a and 142b is formed, and the conductive film 120b and The conductive film 104 is connected, or the openings 142a and 142b are not provided, and the conductive film 104 is not connected. The conductive film 120b and the conductive film 104 may not be connected to each other. In the case where the conductive film 104 is not connected, the conductive film 120b and the conductive film 104 are each provided with different It is possible to apply a voltage to the

[0110] As shown in FIG. 3B, the oxide semiconductor film 108 functions as a gate electrode. The conductive film 104 and the conductive film 120b functioning as the second gate electrode are opposed to each other. The second gate electrode is located between two conductive films that function as gate electrodes. The length in the channel length direction and the length in the channel width direction of the conductive film 120b functioning as an electrode are The length of the oxide semiconductor film 108 in the channel length direction and the length of the oxide semiconductor film 108 in the channel width direction are The entire oxide semiconductor film 108 is covered by the conductive film 1 through the insulating films 114, 116, and 118. The gate electrode is covered with a conductive film 120b. The conductive film 104 functioning as an electrode is made up of insulating films 106, 107, 114, 116, and 118. Since the oxide semiconductor film 108 is connected through the openings 142 a and 142 b provided in the The side surface of the second gate electrode in the channel width direction is connected to the second gate electrode via insulating films 114, 116, and 118. The conductive film 120b functions as a conductive film.

[0111] In other words, in the channel width direction of the transistor 170, The conductive film 104 functioning as the second gate electrode and the conductive film 120b functioning as the second gate electrode are used as a gate insulating film. the insulating films 106 and 107 functioning as a second gate insulating film and the insulating film 114 functioning as a second gate insulating film. , 116, 118 are connected through openings and function as gate insulating films. and insulating films 114 and 116 functioning as second gate insulating films. 118 surrounds the oxide semiconductor film 108 .

[0112] With such a structure, the oxide semiconductor film 108 included in the transistor 170 The conductive film 104 functions as a gate electrode and the conductive film 105 functions as a second gate electrode. 120b. an oxide semiconductor film in which a channel region is formed by the electric field of the first electrode and the second gate electrode; The device structure of a transistor that electrically surrounds the This can be called an s-channel structure.

[0113] The transistor 170 has an s-channel structure and therefore functions as a gate electrode. The conductive film 104 is used to effectively apply an electric field for inducing a channel to the oxide semiconductor film 1 08, the current driving capability of the transistor 170 is improved, and a high It is also possible to increase the on-current, It is possible to miniaturize the transistor 170. In addition, the transistor 170 has a gate The conductive film 104 functions as a first electrode and the conductive film 120b functions as a second gate electrode. Since the transistor 170 has a structure surrounded by the insulating film, the mechanical strength of the transistor 170 can be increased. Cut.

[0114] The other configuration of the transistor 170 is the same as that of the transistor 100 shown above. Yes, and it has the same effect.

[0115] In addition, the transistor according to the present embodiment can be freely combined with each of the above structures. For example, the transistor 100 shown in FIG. 3 is used as a transistor for the gate driver of the display device. It can be used for data.

[0116] <Method 1 for manufacturing semiconductor device> Next, a method for manufacturing the transistor 100 which is a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 4 to 6 are used to explain the manufacturing method of a semiconductor device. FIG.

[0117] Note that the films constituting the transistor 100 (the insulating film, the oxide semiconductor film, the conductive film, and the like) are Sputtering, Chemical Vapor Deposition (CVD), Vacuum Evaporation, Pulsed Laser Deposition (PLD) Alternatively, the insulating layer 14 can be formed by a coating method or a printing method. The most common deposition methods are sputtering and plasma enhanced chemical vapor deposition (PECVD). However, thermal CVD or ALD (atomic layer deposition) may also be used. Examples of thermal CVD include One example is the MOCVD (metal organic chemical vapor deposition) method.

[0118] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The reaction is carried out in the chamber near or on the substrate, where it is deposited on the substrate to form a film. As described above, the thermal CVD method is a film formation method that does not generate plasma. This has the advantage that defects are not generated due to damage.

[0119] In addition, in the ALD method, the pressure inside the chamber is set at atmospheric pressure or reduced pressure, and the source gas for the reaction is The gases are introduced into the chamber in sequence, and the film is formed by repeating the gas introduction sequence. For example, By switching each switching valve (also called high-speed valve), two or more types of raw materials can be The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so that multiple source gases do not mix. Simultaneously with or after the second gas, an inert gas (such as argon or nitrogen) is introduced. Introduce the raw material gas. If an inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, an inert gas may be introduced at the same time as the second source gas is introduced. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation, and then the second source gas is introduced. The first source gas may be adsorbed on the surface of the substrate to form a first monoatomic layer. The second monoatomic layer is formed by reacting with the second source gas introduced later. Layer upon layer is laminated to form a thin film.

[0120] This gas introduction sequence is controlled and repeated several times until the desired thickness is achieved. The thickness of the thin film increases depending on the number of times the gas introduction sequence is repeated. This allows precise film thickness control, making it possible to fabricate minute transistors. It is suitable for fabrication.

[0121] First, a conductive film is formed on the substrate 102, and the conductive film is then subjected to a lithography process and an etching process. Then, the conductive film 104 is formed to function as a gate electrode. On the insulating film 104, insulating films 106 and 107 that function as gate insulating films are formed (see FIG. 4(A)). ).

[0122] The conductive film 104 that functions as the gate electrode is formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. The thin-film transistor can be formed by using a method such as a vacuum deposition method, a pulsed laser deposition (PLD) method, etc. Alternatively, the film can be formed by a coating method or a printing method. The plasma enhanced chemical vapor deposition (PECVD) method is representative, but the previously explained organometallic chemical vapor deposition method is also used. Thermal CVD techniques such as metal-organic chemical vapor deposition (MOCVD) or atomic layer deposition (ALD) techniques may also be used.

[0123] In this embodiment, a glass substrate is used as the substrate 102, and a conductive layer that functions as a gate electrode is used. As the conductive film 104, a tungsten film having a thickness of 100 nm is formed by sputtering.

[0124] The insulating films 106 and 107 that function as gate insulating films are formed by sputtering, PECVD, etc. The insulating film can be formed by using a method such as a thermal CVD method, a vacuum deposition method, a PLD method, or the like. Then, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 106 by the PECVD method. Then, a silicon oxynitride film is formed as the insulating film 107 to a thickness of 50 nm.

[0125] The insulating film 106 may have a stacked structure of a silicon nitride film. The insulating film 106 is made of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. A three-layer laminate structure with a silicon film can be formed. An example of the three-layer laminate structure is as follows: It can be formed as follows:

[0126] The first silicon nitride film is formed by, for example, silane at a flow rate of 200 sccm, PE-CV was performed using nitrogen at a flow rate of 100 sccm and ammonia gas at a flow rate of 100 sccm as source gas. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency If a power of 2000 W is supplied using a frequency power supply and the thickness is formed to be 50 nm, good.

[0127] For the second silicon nitride film, silane at a flow rate of 200 sccm, The nitrogen gas and the ammonia gas with a flow rate of 2000sccm were used as raw material gases in the PECVD equipment. The pressure in the reaction chamber was controlled to 100 Pa, and a 27.12 MHz high-frequency power supply was used. A power of 2000 W may be supplied using the above method to form a film having a thickness of 300 nm.

[0128] The third silicon nitride film was prepared by using silane at a flow rate of 200 sccm and 5000 sccm. The pressure in the reaction chamber was kept at 100 The thickness was measured by controlling the temperature to 50 Pa and supplying 2000 W of power using a 27.12 MHz high frequency power source. It is sufficient to form it so that the thickness is 50 nm.

[0129] The first silicon nitride film, the second silicon nitride film, and the third silicon nitride film The substrate temperature during formation can be 350° C. or less.

[0130] By forming the insulating film 106 in a three-layered structure of silicon nitride films, for example, the conductive film 10 When a conductive film containing copper (Cu) is used for 4, the following effects are achieved.

[0131] The first silicon nitride film can suppress the diffusion of copper (Cu) elements from the conductive film 104. The second silicon nitride film has the function of releasing hydrogen and functions as a gate insulating film. The third silicon nitride film can improve the breakdown voltage of the insulating film. Hydrogen release from the silicon nitride film is small, and hydrogen released from the second silicon nitride film is diffused. can be suppressed.

[0132] The insulating film 107 is an oxide semiconductor film 108 (more specifically, a first In order to improve the interface characteristics with the oxide semiconductor film 108a), It would be preferable if this could be done.

[0133] Next, a first oxide semiconductor film 108a is formed over the insulating film 107. A second oxide semiconductor film 108b is formed over the oxide semiconductor film 108a (see FIG. 4B). see).

[0134] In this embodiment, an In-Ga-Zn metal oxide target (In:Ga:Zn=3: A first oxide semiconductor film was formed by sputtering using a SiO2 / SiO2 (atomic ratio of 1:2). Then, in vacuum, the In-Ga-Zn metal oxide target (In:Ga:Zn = 1: 1: 1.2 (atomic ratio)) by sputtering a second oxide semiconductor By forming a film, a stacked oxide semiconductor film is formed. A mask is formed on the oxide semiconductor film by a lithography process, and the oxide semiconductor film is formed in a desired region. By this process, an island-shaped oxide semiconductor film 108 is formed.

[0135] When the oxide semiconductor film 108 is formed by a sputtering method, a sputtering gas In the case of the above, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used. In the case of a mixed gas, it is preferable to increase the ratio of oxygen to rare gas. It is also necessary to increase the purity of the sputtering gas. For example, oxygen used as a sputtering gas The gas or argon gas has a dew point of -40°C or less, preferably -80°C or less, and more preferably By using gas that has been highly purified to temperatures below -100℃, and more preferably below -120℃, This can prevent moisture and the like from being absorbed into the oxide semiconductor film 108 as much as possible.

[0136] In addition, when the oxide semiconductor film 108 is formed by a sputtering method, a sputtering apparatus The chamber is designed to remove water and other impurities that may be contained in the oxide semiconductor film 108 as much as possible. In order to remove the gas, a high vacuum (1×10 -4 Pa to 5 × 10 -7 It is preferable to evacuate the gas to a temperature of about 10 Pa. A combination of a filter and a cold trap is used to extract gas, especially carbon or water, from the exhaust system into the chamber. It is preferable to prevent backflow of oxygen-containing gas.

[0137] Next, a source electrode and a drain electrode are formed over the insulating film 107 and the oxide semiconductor film 108a. Then, a conductive film 112 that functions as a conductive film is formed (see FIG. 4C).

[0138] In this embodiment, the conductive film 112 is a tungsten film having a thickness of 50 nm and a SiO 2 film having a thickness of 40 A laminate film in which a SiO2 film and a 0 nm aluminum film are laminated in this order is formed by sputtering. In this embodiment, the conductive film 112 has a two-layered structure, but the present invention is not limited to this. For example, the conductive film 112 may be a tungsten film having a thickness of 50 nm and a 400 nm thick The aluminum film with a thickness of 100 nm and the titanium film with a thickness of 100 nm were laminated in this order. You may do so.

[0139] Next, masks 140a and 140b are formed in desired regions on the conductive film 112 (FIG. 4(D) )reference).

[0140] In this embodiment, the masks 140a and 140b are formed by applying a photosensitive resin film. The photosensitive resin film is then patterned by a lithography process to form the insulating film.

[0141] Next, etching gas 138 is used to remove the conductive film 112 and the masks 140a and 140b. Then, the conductive film 112 and the second oxide semiconductor film 108b are processed (see FIG. 5A).

[0142] In this embodiment, the conductive film 112 and the second acid are removed by using a dry etching apparatus. However, the method for forming the conductive film 112 is not limited to this. For example, a chemical solution may be used as the etching gas 138 to perform wet etching. The conductive film 112 and the second oxide semiconductor film 108b may be processed by using a processing device. Then, the conductive film 112 and the second oxide semiconductor film 108 are etched using a wet etching apparatus. Rather than processing step b, the conductive film 112 and the second oxide semiconductor film 113 are processed by using a dry etching apparatus. Processing the conductive film 108b is preferable because it allows for the formation of finer patterns. It is.

[0143] Next, the masks 140a and 140b are removed, so that the second oxide semiconductor film 108b is left The conductive film 112a serving as a source electrode of the second oxide semiconductor film 108b and the drain electrode of the second oxide semiconductor film 108b are A conductive film 112b functioning as an in-electrode is formed. The semiconductor device has a stacked structure of a first oxide semiconductor film 108a and a second oxide semiconductor film 108b. (See FIG. 5(B)).

[0144] In addition, a chemical solution was sprayed onto the second oxide semiconductor film 108b and the conductive films 112a and 112b. The surface (back channel side) of the second oxide semiconductor film 108b may be cleaned by applying the solution. The cleaning method may be, for example, cleaning with a chemical solution such as phosphoric acid. By cleaning with a chemical solution, impurities attached to the surface of the second oxide semiconductor film 108b are removed. (For example, elements contained in the conductive films 112a and 112b) can be removed. However, the washing is not necessarily required, and in some cases, washing may not be performed.

[0145] In addition, during the formation of the conductive films 112a and 112b and / or during the above-mentioned cleaning process, The oxide semiconductor film 108b has a second region having a smaller thickness than the first oxide semiconductor film 108a. A region is formed.

[0146] Next, the insulating films 114 and 112 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b. Form 6 (see FIG. 5(C)).

[0147] After the insulating film 114 is formed, the insulating film 116 is successively formed without exposing it to the air. After the insulating film 114 is formed, it is preferable to adjust the flow rate, pressure, and temperature of the source gas without exposing the insulating film 114 to the air. By adjusting one or more of the frequency power and the substrate temperature, the insulating film 116 is continuously formed. The concentration of impurities derived from atmospheric components can be reduced at the interface between the insulating film 114 and the insulating film 116. At the same time, oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. As a result, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0148] For example, a silicon oxynitride film is formed as the insulating film 114 by using a PECVD method. In this case, the source gas may be a deposition gas containing silicon and an oxidizing gas. Representative examples of deposition gases containing silicon include silane, disilane, etc. Examples of oxidizing gases include nitrous oxide, nitrous oxide, and trisilane. In addition, the oxidizing gas is more than 20 times and less than 100 times the deposition gas. and the pressure in the treatment chamber is less than 100 Pa, preferably 40 times or more and 80 times or less. By using the PECVD method at a pressure of 50 Pa or less, the insulating film 114 contains nitrogen, and This results in an insulating film with fewer defects.

[0149] In this embodiment, the insulating film 114 is formed by heating the substrate 102 at a temperature of 220° C. The source gases were silane at a flow rate of 50 sccm and dinitrogen monoxide at a flow rate of 2000 sccm. The pressure in the treatment chamber was set to 20 Pa, and the high frequency power supplied to the parallel plate electrodes was set to 13.56 M. Hz, 100W (power density is 1.6×10 -2 W / cm 2 ) PECVD method A silicon oxynitride film is formed using this.

[0150] The insulating film 116 is formed by depositing a substrate in a vacuum-evacuated processing chamber of a PECVD apparatus. The temperature is kept at 180°C or higher and 350°C or lower, and the raw material gas is introduced into the treatment chamber to increase the pressure in the treatment chamber. is set to 100 Pa or more and 250 Pa or less, and more preferably set to 100 Pa or more and 200 Pa or less. 0.17 W / cm2 at the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 Below are some more Preferably 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power supply conditions are met: In this way, a silicon oxide film or a silicon oxynitride film is formed.

[0151] The conditions for forming the insulating film 116 are as follows: high frequency power density in a reaction chamber with the above pressure; By supplying power, the efficiency of decomposition of the source gas in the plasma increases, and the number of oxygen radicals increases. As the oxidation of the source gas progresses, the oxygen content in the insulating film 116 becomes lower than the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, the bonding strength between silicon and oxygen is Since the oxygen in the film is weak, some of the oxygen in the film is released by the heat treatment in the subsequent process. An oxide that contains more oxygen than satisfies the theoretical composition and loses some of the oxygen when heated. An insulating film can be formed.

[0152] The process of forming the insulating film 116 is carried out in a PECVD apparatus at a temperature of 180° C. to 350° C. The insulating film 116 is formed during the manufacturing process of the transistor 100. It is preferable that the temperature in the process is the highest. For example, the temperature at which the insulating film 116 is formed is set to 350° C. By carrying out the above steps, it is possible to form the transistor 100 directly on a flexible substrate, etc. .

[0153] In the step of forming the insulating film 116, the insulating film 114 serves as a protection film for the oxide semiconductor film 108. Therefore, the power density can be reduced while reducing damage to the oxide semiconductor film 108. The insulating film 116 can be formed using high radio frequency power.

[0154] In the deposition conditions for the insulating film 116, a deposition gas containing silicon is mixed with an oxidizing gas. By increasing the flow rate of the gas, it is possible to reduce the amount of defects in the insulating film 116. In the first place, ESR measurements revealed that the g value was 2.001, which is due to the dangling bonds of silicon. The spin density of the signal is 6×10 17 spins / cm 3 Less than 3 x 10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 The following is a missing It is possible to form an oxide insulating layer with few defects. As a result, the reliability of the transistor is improved. It can be done.

[0155] After the insulating films 114 and 116 are formed, heat treatment may be performed. This can reduce the amount of nitrogen oxide contained in the insulating films 114 and 116. By the heat treatment, part of oxygen contained in the insulating films 114 and 116 is transferred to the oxide semiconductor film 108. By this, the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0156] The temperature for the heat treatment of the insulating films 114 and 116 is typically 150° C. or higher and 350° C. or lower. Heat treatment should be performed using nitrogen, oxygen, or ultra-dry air (water content 20 ppm or less, preferably air, preferably at 1 ppm or less, more preferably at 10 ppb or less), or a rare gas (argon, The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas atmosphere may be used. It is preferable that the gas does not contain hydrogen, water, etc. For the heat treatment, an electric furnace, an RTA device, etc. It can be used.

[0157] In this embodiment, heat treatment is performed in a nitrogen atmosphere at 350° C. for 1 hour. In the step of forming the transistor 100, the temperature at which the insulating film 116 is formed should be the highest. Alternatively, heat treatment at a temperature similar to that for forming the insulating film 116 may be performed in a different step.

[0158] Next, an oxide conductive film 131 is formed over the insulating film 116 (see FIG. 5D).

[0159] The oxide conductive film 131 is a film made of oxygen and a metal (indium, zinc, titanium, aluminum, tantalum, etc.). At least one selected from the group consisting of tin, tantalum, and molybdenum. do.

[0160] Examples of the oxide conductive film 131 include a tantalum oxynitride film, a titanium oxide film, and an indium Tin oxide (ITO) film, aluminum oxide film, oxide semiconductor film (e.g., I A GZO film (In:Ga:Zn=1:4:5 (atomic ratio)) can be used. The oxide conductive film 131 can be formed by a sputtering method. The thickness of the oxide conductive film 131 is 1 nm or more and 20 nm or less, or 2 nm or more and 10 nm or less. In this embodiment, the oxide conductive film 131 has a thickness of 50 nm or less. Indium tin oxide doped with silicon oxide (hereinafter referred to as ITSO) is used.

[0161] Next, the insulating films 114 and 116 and the oxide semiconductor film 108 are Oxygen 139 is added (see FIG. 6(A)).

[0162] The insulating films 114 and 116 and the oxide semiconductor film 108 are filled with oxygen through the oxide conductive film 131. Methods for adding 39 include ion doping, ion implantation, plasma treatment, etc. In addition, when oxygen 139 is added, applying a bias to the substrate side effectively increases the amount of oxygen. The element 139 can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. The bias may be, for example, a power density of 1 W / cm 2 More than 5W / cm 2 Let's say the following: By providing the oxide conductive film 131 over the insulating film 116 and adding oxygen, the oxide conductive film The insulating film 131 functions as a protective film that suppresses oxygen from being released from the insulating film 116. Therefore, more oxygen can be added to the insulating films 114 and 116 and the oxide semiconductor film 108. can.

[0163] Next, the oxide conductive film 131 is removed by an etchant 142 (see FIG. 6B). .

[0164] The oxide conductive film 131 can be removed by dry etching or wet etching. or a combination of dry etching and wet etching. In the case of the dry etching method, the etchant 142 is an etching gas. In the case of wet etching, the etchant 142 is a chemical liquid. In the second step, the oxide conductive film 131 is removed by wet etching.

[0165] Next, the insulating film 118 is formed on the insulating film 116 (see FIG. 6C).

[0166] Note that a heat treatment is performed before or after the insulating film 118 is formed to obtain an insulating film. Excess oxygen contained in the films 114 and 116 is diffused into the oxide semiconductor film 108, and the oxide semiconductor Alternatively, the insulating film 118 can be formed by heating and filling the oxygen vacancies in the insulating film 108. By this, excess oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108. Thus, oxygen vacancies in the oxide semiconductor film 108 can be filled.

[0167] When the insulating film 118 is formed by the PECVD method, the substrate temperature is set to 180° C. or higher and 350° C. or lower. This is preferable because it allows a dense film to be formed.

[0168] For example, when a silicon nitride film is formed as the insulating film 118 by the PECVD method, the silicon It is preferable to use a deposition gas containing carbon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma and becomes active. The active species are generated by reacting with silicon and hydrogen contained in the deposition gas containing silicon. This breaks the triple bond between silicon and nitrogen, promoting the bonding of silicon and nitrogen. To form a dense silicon nitride film with few bonds between silicon and hydrogen and few defects. On the other hand, if the amount of ammonia relative to nitrogen is large, the deposition gas containing silicon and Nitrogen decomposition does not progress, silicon and hydrogen bonds remain, defects increase, and roughness is generated. For these reasons, the source gas should be ammonia-free. The flow rate ratio of nitrogen to oxygen is preferably 5 or more and 50 or less, and more preferably 10 or more and 50 or less.

[0169] In this embodiment, the insulating film 118 is formed by depositing silane, nitrogen, etc., using a PECVD apparatus. A silicon nitride film with a thickness of 50 nm is formed from the raw material gases of nitrogen and ammonia. The flow rate is , silane at 50 sccm, nitrogen at 5000 sccm, and ammonia at 100 sccm The pressure in the processing chamber was 100 Pa, the substrate temperature was 350°C, and a high frequency of 27.12 MHz was used. A high-frequency power of 1000 W is supplied to the parallel plate electrodes using a high-frequency power source. The pole area is 6000cm 2 This is a parallel plate type PECVD device, and the supplied power is expressed as a unit. This translates to 1.7 x 10 power per area (power density). -1 W / cm 2 It is.

[0170] Through the above steps, the transistor 100 shown in FIG. 1 can be formed.

[0171] <Method 2 for manufacturing semiconductor device> Next, a method for manufacturing the transistor 170 of one embodiment of the present invention will be described with reference to FIGS. 7A to 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device. 7A, 7C, 7E, and 7G show the state of the transistor 170 in the channel length direction during the fabrication. 7B, 7D, 7F, and 7H are cross-sectional views of a transistor 170 during its fabrication. FIG. 2 is a cross-sectional view in the width direction of the panel.

[0172] First, the same steps as in the method for manufacturing the transistor 100 described above (the steps shown in FIGS. 4 to 6) are performed. ) is performed, and a conductive film 104, insulating films 106 and 107, and an oxide semiconductor film 108 are formed on the substrate 102. , conductive films 112a and 112b, and insulating films 114, 116, and 118 are formed (FIG. 7(A) )(see B)).

[0173] Next, a mask is formed on the insulating film 118 by a lithography process, and the insulating films 114 and 11 An opening 142c is formed in a desired region of the insulating film 118. A mask is formed by a photolithography process, and the desired insulating films 106, 107, 114, 116, and 118 are formed. In this region, openings 142a and 142b are formed. The openings 142a and 142b are formed so as to reach the conductive film 10 4 (see Figures 7(C) and (D)).

[0174] The openings 142a, 142b and the opening 142c may be formed in the same process or in different processes. The openings 142a, 142b and the opening 142c may be formed in the same process. When forming the insulating film, for example, a gray-tone mask or a half-tone mask may be used. The openings 142a and 142b may be formed in a plurality of steps. For example, First, the insulating films 106 and 107 are processed, and then the insulating films 114, 116 and 118 are processed.

[0175] Next, a conductive film 12 is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. 0 (see Figures 7(E) and (F)).

[0176] The conductive film 120 may be made of, for example, indium (In), zinc (Zn), or tin (Sn). In particular, the conductive film 120 may be made of a material containing one selected from the group consisting of an acid, Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide , indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide (ITO), indium zinc oxide, indium stannate with silicon oxide A conductive material having light transmitting properties, such as an ITSO film, can be used. The film 120 can be formed by using, for example, a sputtering method. In this embodiment, an ITSO film having a thickness of 110 nm is formed by sputtering.

[0177] Next, a mask is formed on the conductive film 120 by a lithography process, and the conductive film 112 is By processing the conductive film 120a and the conductive film 120b into the shape shown in FIG. ).

[0178] The conductive films 120a and 120b can be formed by dry etching, wet etching, or the like. Examples of the method include a combination of dry etching and wet etching. In this embodiment, the conductive film 120 is formed by wet etching. The conductive films 120a and 120b are then processed.

[0179] Through the above steps, the transistor 170 illustrated in FIG. 3 can be manufactured.

[0180] The structures and methods described in this embodiment mode may be appropriately combined with the structures and methods described in other embodiment modes. They can be used in combination.

[0181] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor included in a semiconductor device of one embodiment of the present invention will be described. A detailed explanation will be given below.

[0182] <Structure of oxide semiconductor> Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconductor uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous l Examples include amorphous oxide semiconductors, amorphous oxide semiconductors, etc.

[0183] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- These include OS, polycrystalline oxide semiconductor, and nc-OS.

[0184] The definition of an amorphous structure is generally that it is not fixed in a metastable state and is isotropic. It is known that the bond angle is flexible and the bond length is short. In other words, it is a structure that has discrete order but does not have long-range order.

[0185] On the other hand, in the case of an essentially stable oxide semiconductor, In addition, it cannot be called an oxide semiconductor because it is not isotropic. The oxide semiconductor, which is not amorphous (for example, has a periodic structure in a microscopic region), is transformed into a completely amorphous oxide. However, a-like OS is a semiconductor that can be used in a small area. Although it has a periodic structure, it has voids and is an unstable structure. In terms of physical properties, it can be said that the semiconductor is close to an amorphous oxide semiconductor.

[0186] <caac-os> First, let me explain about CAAC-OS.

[0187] CAAC-OS is an oxide that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of semiconductor.

[0188] Transmission Electron Microscope (TEM) A combined analysis image (high resolution) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing a high-resolution TEM image, multiple pellets can be confirmed. On the other hand, in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is difficult to clearly confirm the presence of the CAAC-OS at the grain boundaries. It can be said that the decrease in electron mobility caused by the above phenomenon is unlikely to occur.

[0189] The following describes the CAAC-OS observed by TEM. 1 shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. For high-resolution TEM imaging, spherical aberration correction is required. The spherical aberration corrector function was used. , specifically called a Cs-corrected high-resolution TEM image. Cs-corrected high-resolution TEM images are obtained, for example, This is performed using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. It is possible.

[0190] A Cs-corrected high-resolution TEM image of the enlarged area (1) in Figure 34(A) is shown in Figure 34(B). From Figure 34(B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each metal atom layer is determined by the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). Or it reflects the unevenness of the top surface and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0191] As shown in FIG. 34(B), CAAC-OS has a characteristic atomic arrangement. ) shows the characteristic atomic arrangement with auxiliary lines. ) the size of a single pellet can be 1 nm or more, or 3 nm or more. It can be seen that the size of the gap caused by the inclination between the plate and the pellet is about 0.8 nm. Therefore, the pellets can also be called nanocrystals (nc). CAAC-OS is also used as a C-Axis Aligned Nanoclip The semiconductor may also be referred to as an oxide semiconductor having metal ions.

[0192] Here, based on the Cs-corrected high-resolution TEM image, the pellets of CAAC-OS on the substrate 5120 were The layout of the 5100 is shown diagrammatically as a stack of bricks or blocks. (See FIG. 34(D)). Between the pellets observed in FIG. 34(C), The portion where the inclination occurs corresponds to an area 5161 shown in FIG.

[0193] FIG. 35(A) shows the C 35(A) shows the s-corrected high-resolution TEM images of regions (1), (2) and (3) in FIG. ) are enlarged Cs-corrected high-resolution TEM images shown in Fig. 35(B), Fig. 35(C) and Fig. 35(D), respectively. As shown in Figure 35(D), from Figure 35(B), Figure 35(C) and Figure 35(D), the pellet It can be seen that the metal atoms are arranged in a triangular, quadrangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0194] Next, C was analyzed by X-ray diffraction (XRD). We will explain AAC-OS. For example, CAAC-O with InGaZnO4 crystals When the out-of-plane structural analysis is performed on S, the result is as shown in Figure 36(A). As shown in the figure, a peak may appear at a diffraction angle (2θ) of around 31°. Since this is attributed to the (009) plane of the ZnO4 crystal, it is believed that the CAAC-OS crystal has a c-axis orientation. It can be seen that the crystal has a c-axis oriented in a direction substantially perpendicular to the surface on which the crystal is formed or to the upper surface.

[0195] In addition, in the out-of-plane structural analysis of CAAC-OS, 2θ is 31 In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks in the vicinity indicate that some of the CAAC-OS contains crystals that do not have the c-axis orientation. The more preferable CAAC-OS is a structure obtained by the out-of-plane method. The analysis shows a peak at 2θ around 31° and no peak at 2θ around 36°.

[0196] On the other hand, in-pla, X-rays are incident on CAAC-OS from a direction nearly perpendicular to the c-axis. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I It is attributed to the (110) plane of the crystal of nGaZnO4. In the case of CAAC-OS, 2θ is set to 5 The sample was fixed at approximately 6° and analyzed while rotating around the normal vector of the sample surface (φ axis). Even if a φ scan is performed, no clear peak appears, as shown in FIG. 36(B). On the other hand, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ When scanned, it is assigned to a crystal plane equivalent to the (110) plane, as shown in Figure 36(C). Six peaks are observed. Therefore, from the structural analysis using XRD, CAAC-OS It can be seen that the orientation of the a-axis and the b-axis is irregular.

[0197] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with ZnO4 crystals, a probe diameter of 300 nm was used parallel to the sample surface. When an electron beam is incident on the sample, a diffraction pattern (selected area transmission electron diffraction) as shown in FIG. This diffraction pattern may appear due to the InGaZnO4 The spots due to the (009) plane of the crystal are included. Therefore, even by electron diffraction, The pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis faces the surface to be formed or the upper surface. On the other hand, when the probe was applied perpendicular to the sample surface, The diffraction pattern when an electron beam with a diameter of 300 nm was incident is shown in FIG. 7(B), a ring-shaped diffraction pattern is observed. Therefore, electron diffraction also It can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. In addition, the first ring in FIG. 37(B) is the (010) plane of the InGaZnO4 crystal. This is thought to be due to the (100) plane and the like. This is thought to be due to the (110) surface, etc.

[0198] As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Crystallinity can be reduced by the inclusion of impurities or the generation of defects, so the opposite view can be taken. Therefore, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0199] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, metal elements such as silicon have a higher acidity than metal elements that constitute oxide semiconductors. Elements with strong bonds to oxygen remove oxygen from the oxide semiconductor, which changes the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, Carbon dioxide and other molecules have a large atomic radius (or molecular radius), so the atomic arrangement of oxide semiconductors This disrupts the structure and reduces the crystallinity.

[0200] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or In addition, oxygen vacancies in oxide semiconductors can act as carrier traps and In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0201] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Such an oxide semiconductor is a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor. CAAC-OS has low impurity concentration and low defect level density. In other words, it has stable characteristics. It can be said that the oxide semiconductor has the above structure.

[0202] <nc-os> Next, we will explain nc-OS.

[0203] In the high-resolution TEM image, the nc-OS is divided into two regions: one where the crystals can be confirmed, and the other where the clear The crystalline parts in nc-OS are In most cases, the size is between 1 nm and 10 nm, or greater than 1 nm. The oxide semiconductor having a size of 10 nm or more and 100 nm or less is called a microcrystalline oxide semiconductor. For example, in high-resolution TEM images, the grain boundaries of the nc-OS are clearly identified. In addition, the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystalline part of nc-OS is sometimes called a pellet. be.

[0204] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and The atomic arrangement has periodicity in the region of 3 nm or less. There is no regularity in the crystal orientation between the layers. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. For example, the nc-OS may be a pellet with a larger diameter than the pellet. When X-rays are used, the peaks that indicate the crystal planes are In addition, for nc-OS, the probe diameter is larger than the pellet (e.g., 50 When electron diffraction is performed using an electron beam of 1 nm or more, a halo-like diffraction pattern is produced. On the other hand, for nc-OS, pellets with sizes close to or smaller than the pellets were observed. When nanobeam electron diffraction is performed using an electron beam with a lobe diameter, spots are observed. When nanobeam electron diffraction was performed on nc-OS, high brightness regions were observed in a circular (ring-like) pattern. In addition, multiple spots may be observed within a ring-shaped area. There may be cases where this occurs.

[0205] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, so nc -OS with RANC (Random Aligned nanocrystals) The oxide semiconductor or NANC (Non-Aligned Nanocrystal The semiconductor may also be referred to as an oxide semiconductor having a structure including a metal oxide layer.

[0206] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

[0207] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a semiconductor.

[0208] In a-like OS, pores may be observed in high-resolution TEM images. In the high-resolution TEM image, there are areas where crystals can be clearly seen, and areas where crystals can be seen. and areas where it is not possible to

[0209] Because of the porosity, the a-like OS has an unstable structure. e OS has an unstable structure compared with CAAC-OS and nc-OS. This shows the change in structure due to electron irradiation.

[0210] The samples to be irradiated with electrons were a-like OS (referred to as sample A), nc-OS (hereinafter referred to as sample B) and CAAC-OS (hereinafter referred to as sample C) are prepared. Both samples are In-Ga-Zn oxides.

[0211] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that all the materials have crystalline parts.

[0212] The determination of which part is regarded as one crystal part can be made as follows. For example, The unit cell of the InGaZnO4 crystal has three In-O layers and one Ga-Zn-O layer. It is known that the structure has a total of nine layers, six of which are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also called the d value) of the (009) plane. The value is calculated to be 0.29 nm from crystal structure analysis. The areas where the spacing between the crystals is 0.28 nm to 0.30 nm are considered to be crystal parts of InGaZnO4. The lattice fringes correspond to the ab plane of the InGaZnO4 crystal.

[0213] Figure 38 shows an example of the average size of the crystal parts (22 to 45 places) of each sample. However, the length of the lattice fringes is the size of the crystal part. It can be seen that the crystalline part of the ke OS grows in size according to the cumulative dose of electron irradiation. Specifically, as shown by (1) in Figure 38, the initial TEM observation showed a size of about 1.2 nm. The crystal part (also called the initial nucleus), which was 4.2×10 8 e - / n m 2 On the other hand, in the nc-O For S and CAAC-OS, the cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of As shown in (2) and (3) in Fig. 38, the nc-OS and The sizes of the crystal parts of the CAAC-OS and CAAC-OS are approximately 1.4 nm and 2.1 nm, respectively. It can be seen that.

[0214] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. In other words, a-like OS is not seen as a nc-OS or CAAC-OS. It is clear that it has an unstable structure compared to the OS.

[0215] In addition, because of the porosity, a-like OS is more difficult to treat than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is The density of the nc-OS and the CAA The density of C-OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a crystal density of less than 78%.

[0216] For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, The density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 It will be less than. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of nc-OS and the density of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0217] In some cases, single crystals of the same composition do not exist. In such cases, crystals of different compositions may be used in any ratio. By combining single crystals of the desired composition, the density equivalent to that of a single crystal of the desired composition can be estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. The density should be as low as possible. It is preferable to estimate the size of the single crystal by combining different types of single crystals.

[0218] As described above, oxide semiconductors have various structures and each structure has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or an nc-OS. The film may be a laminated film having two or more of the CAAC-OS and CAAC-OS.

[0219] <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0220] FIG. 39(A) shows a process in which a CAAC-OS film is formed by a sputtering method. FIG. 1 is a schematic diagram of the inside of a membrane chamber.

[0221] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130 through the magnets. The magnetic field is generated by a number of magnets. The arrangement and configuration of the magnets are described above. Please refer to the description of the film formation chamber mentioned above. The ring method is called magnetron sputtering.

[0222] The target 5130 has a polycrystalline structure, with each grain including a cleavage plane.

[0223] As an example, the cleavage surface of target 5130 having In-Ga-Zn oxide is described. FIG. 40(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In FIG. 40(A), the c-axis is oriented upward, and the InGaZn This is the structure of an O4 crystal.

[0224] As shown in FIG. 40(A), in two adjacent Ga-Zn-O layers, It can be seen that the oxygen atoms are arranged close to each other. And the oxygen atoms have a negative charge. By this, the two adjacent Ga-Zn-O layers repel each other. A ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0225] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The deposition chamber is mostly filled with deposition gas (e.g., oxygen, argon, or a mixture containing 5% or more by volume of oxygen) and The pressure is controlled to be 1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, a discharge starts and a plasma is generated. It is confirmed that a high-density plasma region is generated near the target 5130 by the magnetic field. In the high-density plasma region, the deposition gas is ionized, and ions 5101 The ion 5101 is, for example, an oxygen cation (O + ) and argon cations ( Ar + ) etc.

[0226] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually At this time, flat or pellet-shaped sputtered particles are ejected from the cleavage plane. The pellets 5100a and 5100b are peeled off and knocked out. The pellet 5100a and the pellet 5100b are structured by the impact of the collision of the ion 5101. Distortion may occur.

[0227] The pellet 5100a is a flat plate or pellet having a triangular, for example equilateral, plane. The pellet 5100b is a sputtered particle having a hexagonal shape, for example, a regular hexagonal plane. The pellets 5100a and 5100b are sputtered particles having a plate-like or pellet-like shape. The term "pellet" refers to flat or pellet-shaped sputter particles such as pellet 5100b. The planar shape of the pellet 5100 is not limited to a triangle or a hexagon, but may be any shape, e.g. For example, a shape may be formed by combining multiple triangles. In some cases, the shape may be a quadrilateral (for example, a rhombus) made up of two joined sides.

[0228] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason will be explained later. It is preferable that the thickness of the pellet 5100 is uniform. A pellet shape with no lumps is preferable to a thick cube shape. The thickness of the 5100 is 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. For example, the pellet 5100 has a width of 1 nm or more. 100 corresponds to the initial nucleus described in (1) of FIG. 38 above. For example, In-Ga- When ions 5101 are collided with a target 5130 having Zn oxide, FIG. As shown in Fig. 1, the ZnO layer has three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer. The pellet 5100 pops out. Note that in FIG. 40(C), the pellet 5100 is aligned along the c-axis. This is the structure when viewed from a parallel direction. Therefore, the pellet 5100 has two G A nano-sized sandwich structure with a-Zn-O layer (bread) and In-O layer (stuffing) It can also be called construction.

[0229] The pellet 5100 receives a charge as it passes through the plasma, causing the sides to become negative or The pellet 5100 has oxygen atoms on the side, and the oxygen atoms In this way, the sides can be charged with the same polarity, The loads repel each other, allowing the flat shape to be maintained. When S is an In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. Or, it may be possible that the indium, gallium or zinc atoms are bonded to The oxygen atoms may become negatively charged. Also, as the pellet 5100 passes through the plasma, When this happens, the atoms bond with indium, gallium, zinc, and oxygen, etc., and grow. This corresponds to the difference in size between (2) and (1) in FIG. 38 above. Here, when the substrate 5120 is at room temperature, the pellet 5100 does not grow any more. As a result, it becomes nc-OS (see Figure 39(B)). Since the temperature at which the film can be formed is about room temperature, Even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow 5100 in plasma, the deposition power in the sputtering method must be increased. It is effective to increase the deposition power to stabilize the structure of the pellet 5100. It is possible.

[0230] As shown in FIG. 39(A) and FIG. 39(B), for example, a pellet 5100 is a plasma It flies like a kite through the air and flutters up to the top of the board 5120. Since the pellet 100 is electrically charged, it will be attracted to the area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, a vertical magnetic field (also called a horizontal magnetic field) is generated between the substrate 5120 and the target 5120. Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is on the upper surface of the substrate 5120. Due to the action of the magnetic field and the electric current, a force (Lorentz force) is exerted on the object. This can be understood using Greg's left-hand rule.

[0231] The pellet 5100 has a large mass compared to a single atom. In order to move the surface, it is important to apply some kind of force from the outside. One of these forces is It is possible that the force is generated by the action of a magnetic field and an electric current. In order to increase the force, the upper surface of the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably Alternatively, a region having a resistance of 50 G or more may be provided on the upper surface of the substrate 5120. A magnetic field oriented parallel to the top surface of the plate 5120 is 1. 5 times or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is advisable to provide an area where

[0232] At this time, the magnet unit and / or the substrate 5120 move relatively. By rotating the substrate 5120, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 is subjected to forces in various directions. can be received and moved in various directions.

[0233] Also, when the substrate 5120 is heated as shown in FIG. 39(A), the pellet 510 0 and the substrate 5120, the resistance due to friction is small. The pellet 5100 glides over the top surface of the substrate 5120. The transfer occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches its side surface, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 00 is removed. The removed oxygen atom causes the Since oxygen vacancies may be filled, the CAAC-OS has a low density of defect states. The temperature of the upper surface of the plate 5120 is, for example, 100° C. or more and less than 500° C., 150° C. or more and 450° C. The temperature may be less than 170°C, 170°C or more and less than 400°C, or 170°C or more and 350°C or less. Even if the substrate 5120 has a large area, the CAAC-OS film can be formed.

[0234] In addition, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged, The structural distortion caused by the collision of the ions 5101 is relieved. The pellet 51 with the distortion relieved is shown in FIG. Pellet 5100 is almost a single crystal. Pellet 5100 is almost a single crystal. Even if the 5100 pellets are heated after bonding, the 5100 pellets themselves hardly expand or contract. Therefore, the gaps between the pellets 5100 are widened, and the grain boundaries and other No defects or crevasses will form.

[0235] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The pellets are made of nano-crystals, and the aggregates resemble bricks or blocks stacked together. In addition, there are no grain boundaries between them. Even if CAAC-OS shrinks or deforms due to subsequent heating or bending, local stress is not a problem. It is therefore possible to reduce forces or release strain. The structure is suitable for semiconductor devices. nc-OS is a collection of pellets 5100 (nanocrystals). The resulting arrangement resembles a chaotic pile of elements.

[0236] When the target is sputtered with ions, not only pellets but also zinc oxide and other substances fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And it reaches 0.1nm to 10nm, 0.2nm to 5nm, or 0. A zinc oxide layer 5102 having a thickness of 5 nm or more and 2 nm or less is formed. A schematic cross-sectional view is shown in FIG.

[0237] As shown in FIG. 41(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are deposited. The pellets 5105c and 5105c are arranged so that their sides are in contact with each other. After being deposited on the pellet 5105b, the pellet 510 slides on the pellet 5105b. In another aspect of FIG. 05a, a plurality of particles 51 ejected from the target along with zinc oxide. The substrate 5120 is heated to crystallize the SiO 2 film 5103, forming a region 5105a1. Particles 5103 may include oxygen, zinc, indium, gallium, and the like.

[0238] Then, as shown in FIG. 41(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a2. It is arranged so as to be in contact with another side surface of 105b.

[0239] Next, as shown in FIG. 41(C), a pellet 5105d is further added to the pellet 5105a2. After being deposited on pellet 5105a2 and pellet 5105b, It slides on the pellet 5105b. It also slides toward the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0240] As shown in FIG. 41(D), the pellet 5105d has a side surface similar to that of the pellet 51. The pellet 5105d is placed so that its side is in contact with the pellet 5105a2. Also, the other side of the pellet 5105d is placed in contact with the other side of the pellet 5105c. At the surface, a plurality of particles 5103 that have come out of the target together with zinc oxide are deposited on the substrate 51. By heating at 20, it is crystallized and a region 5105d1 is formed.

[0241] As described above, the piled pellets are arranged so that they come into contact with each other, and the pellets are Crystal growth occurs, forming a CAAC-OS on the substrate 5120. CAAC-OS has larger individual pellets than nc-OS. This is because This corresponds to the difference in size between (3) and (2) in Figure 38.

[0242] In addition, the gaps between the pellets 5100 are extremely small, so it feels like one large pellet. Large pellets may form. Large pellets have a single crystal structure. For example, large The pellet size, as viewed from above, is between 10 nm and 200 nm, and between 15 nm and 100 nm. m or less, or from 20 nm to 50 nm. If the channel formation area of ​​the pellet is smaller than that of the large pellet, the single crystal is considered as the channel formation area. In addition, the pellets can be enlarged to allow for the formation of a crystalline region. A region having a single crystal structure as a channel forming region, a source region, and a drain region of a transistor. In some cases, a region can be used.

[0243] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0244] Based on the above model, it is considered that the pellet 5100 is deposited on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is formed does not have a crystal structure, For example, the CAAC-OS film can be formed even in the case of a substrate 5120. Even if the structure of the top surface (the surface on which the material is formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of AC-OS.

[0245] In addition, even if the upper surface of the substrate 5120 on which the CAAC-OS is to be formed is uneven, It can be seen that the pellets 5100 are arranged along the shape of the substrate 5120. If the surface is atomically flat, the pellet 5100 will face down on a flat surface that is parallel to the ab plane. Since the layers are aligned toward each other, a layer with uniform thickness, flatness, and high crystallinity is formed. By stacking these layers n times (n is a natural number), we can obtain CAAC-OS. Cut.

[0246] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 51 The structure is made up of n layers (n is a natural number) of 00 arranged side by side along the convex surface. Since the surface of the pellet 5100 is uneven, gaps tend to form between the pellets 5100 in the CAAC-OS. However, intermolecular forces act between the pellets 5100, so even if there are uneven surfaces, the pellets Therefore, even if there are irregularities, high crystallinity is achieved. The CAAC-OS may have the following features:

[0247] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if the thickness is small, a uniform film can be formed.

[0248] Since the CAAC-OS film is formed by such a model, the sputtered particles are distributed evenly throughout the film. It is preferable that the sputtered particles are in the form of thick pellets. In this case, the surface facing the substrate 5120 is not uniform, and the thickness and crystal orientation cannot be made uniform. There is.

[0249] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface having an amorphous structure. Thus, a CAAC-OS having the above properties can be obtained.

[0250] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0251] (Embodiment 3) In this embodiment, a display device including the transistor described in the above embodiment will be An example will be described below with reference to FIGS.

[0252] 8 is a top view showing an example of a display device. The display device 700 shown in FIG. A pixel portion 702 provided on a first substrate 701 and a source driver circuit provided on the first substrate 701 are The path section 704 and the gate driver circuit section 706, the pixel section 702, the source driver circuit section 7 7, a sealant 712 is disposed to surround the gate driver circuit portion 706, and the first and a second substrate 705 disposed opposite to the first substrate 701. The substrate 701 and the second substrate 705 are sealed with a sealant 712. The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 are The first substrate 701, the sealant 712, and the second substrate 705 are used for sealing. Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705. .

[0253] The display device 700 is surrounded by a sealant 712 on the first substrate 701. In a region different from the region, a pixel portion 702, a source driver circuit portion 704, and a gate driver The circuit portion 706 and the FPC terminal portion 708 (FPC: Flexib In addition, the FPC terminal portion 708 is provided with , and the FPC 716 is connected to the pixel section 702 and the source driver circuit section Various signals are supplied to the pixel section 704 and the gate driver circuit section 706. 2, a source driver circuit section 704, a gate driver circuit section 706, and an FPC terminal section 70 8 are connected to signal lines 710. Various signals, etc., supplied by the FPC 716 The pixel section 702, the source driver circuit section 704, the gate driver 706, and the like are connected to each other through a signal line 710. The power supply 704 is provided to a power supply circuit portion 706 and an FPC terminal portion 708 .

[0254] The display device 700 may include a plurality of gate driver circuits 706. The device 700 includes a source driver circuit section 704 and a gate driver circuit section 706. Although an example in which the pixel portion 702 is formed on the same first substrate 701 is shown, the present invention is not limited to this configuration. For example, only the gate driver circuit section 706 may be formed on the first substrate 701. Alternatively, only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, the substrate on which the source driver circuit or the gate driver circuit is formed (for example, A driving circuit board formed of a monocrystalline semiconductor film or a polycrystalline semiconductor film is mounted on a first substrate 701. The method of connecting the separately formed drive circuit board is not particularly limited. Instead, we use COG (Chip On Glass) method, wire bonding method, etc. can be used.

[0255] The display device 700 also includes a pixel portion 702, a source driver circuit portion 704, and a gate The driver circuit portion 706 includes a plurality of transistors. A transistor having a specific position can be applied.

[0256] The display device 700 can also include various elements, such as: Liquid crystal elements, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, Organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs ED, etc.), transistors (transistors that emit light according to the current), electron emitters, electron Ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), a display element using MEMS (microelectromechanical systems) Digital Micromirror Device (DMD), Digital MicroShutter MIRASOL (registered trademark), IMOD (Interference Modulation MEMS display elements using the shutter method, MEMS display elements using the optical interference method, Using chromium-based wetting elements, piezoelectric ceramic displays, and carbon nanotubes In addition to these, the display element has at least one of electrical or magnetic functions. Even if the display medium has a variable contrast, brightness, reflectance, transmittance, etc. depending on the use, An example of a display device using an EL element is an EL display. One example of a display device using an emission element is the field emission display (FED). ) or SED type flat panel display (SED: Surface-conduction LCDs using liquid crystal elements. An example of a display device is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, etc.). LCD, reflective LCD, direct-view LCD, projection LCD An example of a display device using electronic ink or electrophoretic elements is an electronic pen. In addition, there are also other LCDs that can realize semi-transmissive LCDs and reflective LCDs. In this case, a part or the whole of the pixel electrode is made to function as a reflective electrode. For example, a part or the whole of the pixel electrode may be made of aluminum, silver, etc. In this case, a memory circuit such as an SRAM may be provided under the reflective electrode. This makes it possible to further reduce power consumption.

[0257] The display method of the display device 700 may be a progressive method or an interlace method. In addition, the color elements controlled by pixels when displaying in color are R It is not limited to the three colors GB (R stands for red, G stands for green, B stands for blue). For example, It may be composed of four pixels: a pixel, a pixel, and a pixel of white (W). As in the column, two colors of RGB form one color element, and different two colors are generated depending on the color element. You can also select colors to configure the color. Or, you can select one or more colors such as yellow, cyan, and magenta for RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to color display devices, and may be used in monochrome display devices. The present invention can also be applied to display devices.

[0258] In addition, the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) is white light ( In order to display full color on a display device, a colored layer (also called a color filter) is used. The colored layer may be, for example, red (R), green (G), blue (B) , yellow (Y), etc. can be used in appropriate combination. The color reproducibility can be improved compared to when no color layer is used. By disposing a region having a colored layer and a region not having a colored layer, The white light in the region may be directly used for display. This reduces the decrease in brightness caused by the colored layer during bright display, reducing power consumption by 20%. However, it may be possible to reduce the amount of light emitted by organic EL elements and inorganic EL elements by about 30%. When using elements to display full color, R, G, B, Y, and white (W) are It is also possible to emit light from an element having a luminescent color. By using a self-luminous element, it is possible to use a colored layer. In some cases, power consumption can be reduced even further than when the

[0259] In this embodiment, a liquid crystal element and an EL element are used as display elements. 9 and 10. Note that FIG. 9 shows the state of the dashed line QR in FIG. FIG. 10 is a cross-sectional view of the display device shown in FIG. 1 is a cross-sectional view taken along dashed dotted line QR, and shows a configuration in which EL elements are used as display elements.

[0260] First, the common parts shown in FIG. 9 and FIG. 10 will be explained, and then the different parts will be explained. The following is an explanation.

[0261] <Explanation of common parts of display device> The display device 700 shown in FIG. 9 and FIG. 10 includes a wiring portion 711, a pixel portion 702, The display device includes a source driver circuit section 704 and an FPC terminal section 708. The pixel portion 702 includes a transistor 750 and a capacitor 711. The source driver circuit portion 704 includes a transistor 752. do.

[0262] The transistors 750 and 752 may be the transistors shown above. can.

[0263] The transistor used in this embodiment is made of a highly purified oxide film in which the formation of oxygen vacancies is suppressed. The transistor has a semiconductor film. Therefore, the retention time of electric signals such as image signals can be extended, and the power supply When the write interval is on, it is possible to set it longer. This reduces the frequency of refresh operations. This has the effect of reducing power consumption.

[0264] In addition, the transistor used in this embodiment has a relatively high field-effect mobility. For example, a transistor capable of such high speed operation can be used for a liquid crystal display. By using this in a display device, the switching transistor in the pixel section and the driver circuit section In other words, the driver transistor can be formed on the same substrate as the driver circuit. Therefore, it is not necessary to use a semiconductor device formed from a silicon wafer or the like. The number of components can be reduced. By using a register, a high quality image can be provided.

[0265] The capacitor 790 has a structure having a dielectric between a pair of electrodes. One electrode of the transistor 790 is a conductive film that functions as a gate electrode of the transistor 750. The other electrode of the capacitor 790 is formed using a conductive film formed in the same process as that of the transistor. A conductive film is used to function as the source electrode and the drain electrode of the transistor 750. The dielectric sandwiched between the electrodes functions as the gate insulating film of the transistor 750. An insulating film is used.

[0266] 9 and 10, a transistor 750, a transistor 752, and a capacitor Over the element 790, insulating films 764, 766, and 768, an oxide semiconductor film 767, and a planarizing insulating film A veneer 770 is provided.

[0267] The insulating films 764, 766, and 768 are the same as the insulating film 114 shown in the previous embodiment. , 116, 118 can be formed by the same material and manufacturing method. The oxide semiconductor film 767 may be formed of the same material as the oxide semiconductor film 108 described in the above embodiment. The planarization insulating film 770 can be formed by the above-mentioned method. resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin Heat-resistant organic materials such as grease and epoxy resin can be used. The planarization insulating film 770 may be formed by stacking a plurality of insulating films made of the same material. Further, the planarization insulating film 770 does not necessarily have to be provided.

[0268] The signal line 710 is connected to the source and drain electrodes of the transistors 750 and 752. The signal line 710 is formed in the same process as the conductive film that functions as the transistor 75. 0, 752, a conductive film formed in a process different from the source electrode and drain electrode, e.g., The signal line 710 may be a conductive film that functions as a conductive electrode. When this material is used, there is little signal delay caused by wiring resistance, making it possible to display images on a large screen. do.

[0269] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 71. 6. The connection electrode 760 is connected to the source and drain electrodes of the transistors 750 and 752. The connection electrode 760 is formed in the same process as the conductive film that functions as the drain electrode. The terminal of the PC 716 is electrically connected via an anisotropic conductive film 780 .

[0270] The first substrate 701 and the second substrate 705 may be, for example, a glass substrate. In addition, the first substrate 701 and the second substrate 705 may be flexible substrates. The flexible substrate may be, for example, a plastic substrate. do.

[0271] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film. A device for controlling the distance (cell gap) between the first substrate 701 and the second substrate 705 is provided. In addition, a spherical spacer may be used as the structure 778. In this embodiment, the structure 778 is provided on the first substrate 701 side. However, the present invention is not limited to this. For example, a structure 778 may be provided on the second substrate 705 side. Alternatively, the structures 778 may be provided on both the first substrate 701 and the second substrate 705. .

[0272] In addition, on the second substrate 705 side, a light-shielding film 738 functioning as a black matrix and A colored film 736 that functions as a color filter, a light-shielding film 738 that is in contact with the colored film 736, and An insulating film 734 is provided.

[0273] <Example of the configuration of a display device using a liquid crystal element as a display element> The display device 700 shown in FIG. 9 includes a liquid crystal element 775. The conductive film 774 is disposed on the second substrate 705 side. The display device 700 shown in FIG. The alignment state of the liquid crystal layer 776 is changed by the voltage applied to the conductive film 774. This allows the transmission or non-transmission of light to be controlled, thereby enabling images to be displayed.

[0274] The conductive film 772 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 772 is connected to a conductive film that functions as a pixel electrode. The conductive film 772 functions as a reflective electrode, that is, one of the electrodes of the display element. The display device 700 shown in FIG. This is a so-called reflective color liquid crystal display device which reflects and displays light through a colored film 736 .

[0275] The conductive film 772 may be a conductive film that transmits visible light or a conductive film that reflects visible light. A conductive film having a reflectivity can be used. For example, a material containing one of the elements indium (In), zinc (Zn), and tin (Sn) As a conductive film that is reflective in visible light, for example, aluminum In this embodiment, the conductive film 772 may be formed of A conductive film that is reflective in visible light is used.

[0276] In addition, when a conductive film that is reflective to visible light is used as the conductive film 772, the conductive film The film may have a laminated structure. For example, an aluminum film having a thickness of 100 nm is formed on the lower layer, A 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed on the upper layer. The above-mentioned structure provides the following excellent effects.

[0277] (1) The adhesion between the base film and the conductive film 772 can be improved. It is possible to etch the aluminum film and the silver alloy film at the same time. The cross-sectional shape of the conductive film 772 can be made to be a good shape (for example, a tapered shape). The reason for this is that the aluminum film is etched slower by chemicals than the silver alloy film. Or, after etching the upper silver alloy film, the lower aluminum film is exposed. The electrons are taken from aluminum, which is a metal with a lower ionization tendency than gold. Because of this, etching of the silver alloy film is suppressed and etching of the underlying aluminum film is suppressed. This is because the progression is faster.

[0278] In the display device 700 shown in FIG. 9, a part of the planarization insulating film 770 of the pixel section 702 The unevenness is formed, for example, by forming the planarization insulating film 770 with an organic resin film or the like. The reflecting electrode can be formed by forming a reflecting electrode on the surface of the organic resin film. The conductive film 772, which functions as a conductive film, is formed along the unevenness. When light enters the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772. This can improve visibility.

[0279] Although the display device 700 shown in FIG. 9 is an example of a reflective color liquid crystal display device, For example, the conductive film 772 may be a conductive film that transmits visible light. By using the same, a transmissive color liquid crystal display device can be formed. In this case, the unevenness provided in the planarization insulating film 770 does not necessarily have to be provided.

[0280] Although not shown in FIG. 9, the conductive films 772 and 774 are in contact with the liquid crystal layer 776. Although not shown in FIG. 9, the polarizing portion Optical members (optical substrates) such as a retardation member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, a circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. Lights, side lights, etc. may also be used.

[0281] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, For example, a liquid crystal, a polymer-dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Depending on the conditions, the liquid crystal material can have a cholesteric phase, a smectic phase, a cubic phase, or a chiral phase. It shows nematic phase, isotropic phase, etc.

[0282] In addition, when the in-plane switching method is adopted, liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of a cholesteric liquid crystal is increased, the cholesteric The blue phase appears just before the transition from the black phase to the isotropic phase. In order to improve the temperature range, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent is used in the liquid crystal layer. It has a short response time and is optically isotropic. It also contains a liquid crystal that exhibits a blue phase and a chiral agent. The liquid crystal composition does not require alignment treatment and has little viewing angle dependency. Since the rubbing process is unnecessary, the electrostatic breakdown caused by the rubbing process is eliminated. Therefore, defects and damage to the liquid crystal display device during the manufacturing process can be reduced. do.

[0283] In addition, when liquid crystal elements are used as display elements, TN (Twisted Nematic) ) mode, IPS (In-Plane-Switching) mode, FFS (Frin ge Field Switching) mode, ASM (Axially Symme tric aligned Micro-cell) mode, OCB(Optical Compensated Birefringence mode, FLC (Ferrero lectric Liquid Crystal) mode, AFLC (AntiFerr Electrochemical Liquid Crystal (ECC) mode can be used. .

[0284] In addition, normally black type liquid crystal display devices, for example, those using a vertical alignment (VA) mode The vertical alignment mode may be a transmission type liquid crystal display device. For example, MVA (Multi-Domain Vertical Alignment) ) mode, PVA (Patterned Vertical Alignment) mode mode, ASV mode, etc. can be used.

[0285] <Display device using light-emitting elements as display elements> The display device 700 shown in FIG. 10 includes a light-emitting element 782. The light-emitting element 782 is a conductive film The display device 700 shown in FIG. The EL layer 786 of the light element 782 emits light, thereby displaying an image. do.

[0286] The conductive film 784 serves as a source electrode and a drain electrode of the transistor 750. The conductive film 784 is connected to a conductive film that functions as a pixel electrode. The conductive film 784 functions as an electrode, that is, one of the electrodes of the display element. In the above, a conductive film that transmits light or a conductive film that reflects visible light can be used. Examples of conductive films that are transparent to visible light include indium (In), zinc (Zn), and ZnO. It is recommended to use a material containing one of the following elements: Zn (Zn) or tin (Sn). The reflective conductive film may be made of a material containing aluminum or silver. stomach.

[0287] In addition, in the display device 700 shown in FIG. An insulating film 730 is provided. The insulating film 730 covers a part of the conductive film 784. 782 has a top emission structure. Therefore, the conductive film 788 has a light transmitting property, and It transmits the light emitted by the L layer 786. In this embodiment, the top emission The structure is exemplified, but is not limited to this. For example, a bottom emission structure in which light is emitted to both the conductive film 784 and the conductive film 788; It can also be applied to al-emission structures.

[0288] A colored film 736 is provided at a position overlapping the light emitting element 782, and a colored film 736 is provided at a position overlapping the insulating film 730. A light-shielding film 738 is provided at the position where the light-shielding film 738 is to be formed, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with an insulating film 734. In addition, the space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. In the display device 700 shown in FIG. 1, a configuration in which a colored film 736 is provided is illustrated. For example, when the EL layer 786 is formed by coloring, The film 736 may not be provided.

[0289] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0290] (Embodiment 4) In this embodiment, a display device including a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. This will be used to explain.

[0291] The display device shown in FIG. 11A has a region having pixels of a display element (hereinafter, referred to as a pixel portion 502). ) and a circuit section ( hereinafter referred to as a drive circuit section 504) and a circuit having a function of protecting the element (hereinafter referred to as a protection circuit 50 6) and a terminal portion 507. Note that the protection circuit 506 is not provided. This is also fine.

[0292] A part or the whole of the driver circuit portion 504 is formed on the same substrate as the pixel portion 502. This makes it possible to reduce the number of parts and terminals. When a part or the whole of the pixel portion 502 is not formed on the same substrate, the driving circuit A part or the whole of the path portion 504 is COG or TAB (Tape Automated Band). It can be implemented by using the onding.

[0293] The pixel section 502 is arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). The display device has a circuit for driving a plurality of display elements (hereinafter, referred to as pixel circuit 501), The path section 504 is a circuit (hereinafter, a gate driver) that outputs a signal (scanning signal) for selecting a pixel. 504a) to provide a signal (data signal) for driving the display element of the pixel. The pixel circuit 504 includes a driver circuit such as a circuit (hereinafter, referred to as a source driver 504b).

[0294] The gate driver 504a includes a shift register and the like. A signal for driving the shift register is input via a terminal unit 507, and a signal is output. For example, a start pulse signal, a clock signal, etc. are input to the gate driver 504a. The gate driver 504a outputs a pulse signal. The gate has a function of controlling the potential of the scanning lines GL_1 to GL_X. A plurality of drivers 504a are provided, and the scanning lines GL_1 to Alternatively, the gate driver 504a may control the GL_X by dividing it. However, the gate driver 50 has a function of supplying 4a may also provide another signal.

[0295] The source driver 504b includes a shift register and the like. Through the terminal section 507, a signal for driving the shift register as well as a source of a data signal are input. The source driver 504b outputs a pixel circuit based on the image signal. The source driver 504b has a function of generating a data signal to be written to the source driver 501. A data signal is generated according to a pulse signal obtained by inputting a start pulse, a clock signal, etc. The source driver 504b has a function of controlling the output of a data signal. The data lines DL_1 to DL_Y are connected to the data line 101 through the data line 102. Alternatively, the source driver 504b may have a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b may also supply other signals. It is possible.

[0296] The source driver 504b is configured using, for example, a plurality of analog switches. The source driver 504b sequentially turns on a number of analog switches, The image signal can be time-division-multiplexed and output as a data signal. Also, a shift register, etc. This may be used to configure the source driver 504b.

[0297] Each of the plurality of pixel circuits 501 is connected to one of the plurality of scanning lines GL to which a scanning signal is applied. A pulse signal is inputted through the data line DL, and a data signal is given through one of the data lines DL. A data signal is input to each of the pixel circuits 501. 504a controls writing and holding of data of the data signal. For example, The second pixel circuit 501 is connected to a gate driver GL_m (where m is a natural number equal to or smaller than X) via a scanning line GL_m. A pulse signal is input from 504a, and the data line DL_n ( A data signal is input from the source driver 504b via a source driver 504c (n is a natural number equal to or smaller than Y).

[0298] The protection circuit 506 shown in FIG. 11A includes, for example, a gate driver 504a and a pixel circuit 5 01. Alternatively, the protection circuit 506 is connected to the scanning line GL, which is the wiring between the source driver The data line DL is connected between the driver 504b and the pixel circuit 501. The protection circuit 506 can be connected to a wiring between the gate driver 504a and the terminal unit 507. Alternatively, the protection circuit 506 may be a wiring between the source driver 504b and the terminal unit 507. The terminal unit 507 can be connected to a power supply and a power supply line from an external circuit to the display device. This refers to the part provided with terminals for inputting control signals and image signals.

[0299] When a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected, the protection circuit This is a circuit that brings one wire into electrical continuity with another wire.

[0300] As shown in FIG. 11A, a protection circuit 50 is provided in each of a pixel section 502 and a driver circuit section 504. 6, ESD (Electro Static Discharge: This can improve the resistance of the display device to overcurrent caused by electrostatic discharge (ESD) and the like. However, the configuration of the protection circuit 506 is not limited to this. For example, A configuration in which a protection circuit 506 is connected, or a protection circuit 506 is connected to the source driver 504b Alternatively, a protection circuit 506 may be connected to the terminal portion 507. It can also be done like this.

[0301] In FIG. 11A, the gate driver 504a and the source driver 504b Therefore, although an example in which the driver circuit portion 504 is formed is shown, the present invention is not limited to this configuration. For example, only the gate driver 504a is formed, and a source driver circuit is formed separately. A substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is It may also be configured to be equipped with

[0302] In addition, the pixel circuits 501 shown in FIG. 11(A) may be, for example, a pixel circuit having a configuration shown in FIG. It can be said that:

[0303] The pixel circuit 501 shown in FIG. 11B includes a liquid crystal element 570, a transistor 550, and a capacitor. The transistor 550 may be any of the transistors described in the previous embodiment. can be applied.

[0304] The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set by the written data. A common potential is applied to one of a pair of electrodes of the liquid crystal element 570 in each of the pixel circuits 501. A common potential may be applied to the pair of liquid crystal elements 570 of the pixel circuits 501 in each row. A different potential may be applied to one of the electrodes.

[0305] For example, the display device including the liquid crystal element 570 can be driven in a TN mode, an STN mode, or the like. Mode, VA mode, ASM (Axially Symmetric Aligned M icro-cell mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, MVA mode, PVA (Patterned Ve Vertical Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may also be used. In addition to the above-mentioned driving method, the display device can be driven by an ECB (Electric Carrier Bipolar Transistor) or the like. Ally Controlled Birefringence mode, PDLC(P Oligomeric Dispersed Liquid Crystal (PNLC) mode (Polymer Network Liquid Crystal) mode, guest hole However, there are various types of liquid crystal elements and their driving methods, and they are not limited to these. A variety of different types of sensors can be used.

[0306] In the pixel circuit 501 in the mth row and the nth column, One of the electrodes is electrically connected to the data line DL_n, and the other is a pair of electrodes of the liquid crystal element 570. The gate electrode of the transistor 550 is electrically connected to the other of the scan lines G L_m. The transistor 550 can be turned on or off. Thus, the write control circuit 100 has a function of controlling the writing of data of the data signal.

[0307] One of a pair of electrodes of the capacitor 560 is connected to a wiring to which a potential is supplied (hereinafter, a potential supply line VL ) and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The value of the potential of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 501. The capacitor 560 functions as a storage capacitor for storing written data.

[0308] For example, in a display device having the pixel circuit 501 shown in FIG. The pixel circuits 501 in each row are sequentially selected by a gate driver 504a shown in FIG. 550 is turned on to write data of the data signal.

[0309] In the pixel circuit 501 in which data has been written, the transistor 550 is turned off. By repeating this process row by row, an image can be displayed.

[0310] In addition, the pixel circuits 501 shown in FIG. 11A may have a configuration shown in FIG. It can be said that:

[0311] The pixel circuit 501 shown in FIG. 11C includes transistors 552 and 554 and a capacitor. The transistor 552 and the transistor 554 The transistor described in the above embodiment can be used for either or both of the above. .

[0312] A data signal is applied to one of the source and drain electrodes of the transistor 552. The transistor 55 is electrically connected to a wiring (hereinafter, referred to as a signal line DL_n). The gate electrode of 2 is electrically connected to the wiring (hereinafter referred to as the scanning line GL_m) to which the gate signal is applied. are connected to the network.

[0313] Transistor 552 is turned on or off to transfer the data of the data signal. It has the function of controlling the writing of data.

[0314] One of a pair of electrodes of the capacitor 562 is connected to a wiring to which a potential is applied (hereinafter, a potential supply line VL _a), and the other is electrically connected to the source electrode and drain electrode of the transistor 552. The second electrode is electrically connected to the other of the first and second electrodes.

[0315] The capacitor 562 functions as a storage capacitor for storing written data.

[0316] One of the source electrode and the drain electrode of the transistor 554 is connected to the potential supply line VL_a. In addition, the gate electrode of the transistor 554 is electrically connected to the It is electrically connected to the other of the source electrode and the drain electrode.

[0317] One of the anode and the cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b. The other one is electrically connected to the other of the source electrode and drain electrode of the transistor 554. will be done.

[0318] The light-emitting element 572 may be, for example, an organic electroluminescence element (also called an organic EL element). However, the light-emitting element 572 is not limited to this. Alternatively, an inorganic EL element made of an inorganic material may be used.

[0319] A high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b. and the other is supplied with a low power supply potential VSS.

[0320] In a display device having the pixel circuit 501 shown in FIG. 11C, for example, The pixel circuits 501 in each row are sequentially selected by the gate driver 504a, and the transistors 552 are turned on. The data signal is written by turning it on.

[0321] In the pixel circuit 501 to which the data has been written, the transistor 552 is turned off. Furthermore, the transistor 554 is in a holding state in response to the potential of the written data signal. The amount of current flowing between the source electrode and the drain electrode is controlled, and the light emitting element 572 The light is emitted with a brightness that corresponds to the flow rate. By performing this process row by row, an image can be displayed.

[0322] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done.

[0323] (Embodiment 5) In this embodiment, a display module and an electronic device each including a semiconductor device according to one embodiment of the present invention will be described. This will be described with reference to FIG. 12 and FIG.

[0324] The display module 8000 shown in FIG. 12 includes an upper cover 8001 and a lower cover 8002. Between them, touch panel 8004 connected to FPC8003, A display panel 8006, a backlight 8007, a frame 8009, and a printed circuit board 801 0, has battery 8011.

[0325] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0326] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel The shape and dimensions can be changed as appropriate to match the size of 8006.

[0327] The touch panel 8004 is a resistive or capacitive touch panel. The display panel 8006 can be used by overlapping it with the opposing substrate (sealing substrate). It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the display panel 006 to make it into an optical touch panel.

[0328] The backlight 8007 has a light source 8008. In FIG. In the above embodiment, the light source 8008 is disposed on the light source 8007, but the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light-emitting element such as an organic EL element is used, or when a reflective In the case of a flat panel or the like, the backlight 8007 need not be provided.

[0329] The frame 8009 protects the display panel 8006 and also supports the movement of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the operation of the frame. The frame 8009 may also function as a heat sink.

[0330] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is provided with a signal processing circuit. Alternatively, the power source may be a battery 8011 provided separately. , this can be omitted when using a commercial power source.

[0331] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0332] 13(A) to 13(G) are diagrams showing electronic devices. These electronic devices are A body 9000, a display unit 9001, a speaker 9003, and operation keys 9005 (power switch, etc.) includes an operation switch), a connection terminal 9006, a sensor 9007 (force, displacement, position, speed, Acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electricity Measures field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays The device may have a built-in microphone 9008, etc.

[0333] The electronic devices illustrated in FIGS. 13A to 13G can have various functions. For example, the function to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software ( A function to control processing by a program, wireless communication function, and various functions using wireless communication function Functions for connecting to computer networks, transmitting various data using wireless communication functions, or receiving the program or data recorded on the recording medium, and displaying the program or data. The present invention can have a function of displaying information on a display unit, etc. The functions that the electronic device shown in the figure can have are not limited to these, and the electronic device may have a variety of functions. Although not shown in FIG. 13(A) to FIG. 13(G), the electronic device may include The electronic device may have a plurality of display units. The function to take pictures, record videos, and store the images on a recording medium (external or built-in to the camera) ) and a function for displaying the captured image on a display unit.

[0334] The electronic devices shown in FIGS. 13A to 13G will be described in detail below.

[0335] FIG. 13A is a perspective view showing a portable information terminal 9100. The display unit 9001 has flexibility. The display unit 9001 can be incorporated along the screen. The device is equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. By touching the icon displayed on the display 9001, the application can be started. can.

[0336] FIG. 13B is a perspective view showing a portable information terminal 9101. For example, the device has one or more functions selected from a telephone, a notebook, an information viewing device, etc. Specifically, the mobile information terminal 9101 can be used as a smartphone. Although the speaker 9003, the connection terminal 9006, the sensor 9007, etc. are omitted in the figure, The mobile information terminal 9100 shown in FIG. 13(A) can be installed in the same position. The information terminal 9101 can display text and image information on multiple surfaces. For example, Three operation buttons 9050 (also called operation icons or simply icons) are displayed on the display unit 900. The information 9051 shown in the dashed rectangle can be displayed on one side of the display unit 90. 01. An example of the information 9051 is an e-mail Displays to notify you of incoming calls, SNS (social networking services), etc. , subject of email or SNS, sender name of email or SNS, date and time, time, Battery level, antenna reception strength, etc. Or, information 9051 is displayed. Instead of the information 9051, an operation button 9050 or the like may be displayed at that position.

[0337] FIG. 13C is a perspective view showing a portable information terminal 9102. , and has a function of displaying information on three or more faces of the display unit 9001. An example is shown in which information 9053 and information 9054 are displayed on different sides. The user of the portable information terminal 9102 holds the portable information terminal 9102 in the breast pocket of the clothes. In this state, the display (information 9053 in this case) can be confirmed. The telephone number or name of the caller is displayed on the mobile information terminal 9102 so that it can be observed from above. The user can read the display without taking the mobile information terminal 9102 out of his pocket. You can check the number and decide whether to answer the call or not.

[0338] 13D is a perspective view showing a wristwatch-type portable information terminal 9200. The 9200 is used for mobile phone calls, e-mail, document browsing and writing, music playback, and Internet communications. It is possible to execute various applications such as computer games. The display unit 9001 has a curved display surface, and displays information along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 also has a connection terminal 9006. It has a connector and can directly exchange data with other information terminals. Charging can also be performed via the connection terminal 9006. Power may also be supplied wirelessly without going through 6.

[0339] 13(E), (F), and (G) are perspective views showing a foldable portable information terminal 9201. FIG. 13E is a perspective view of the portable information terminal 9201 in an unfolded state. (F) shows the mobile information terminal 9201 being changed from one of the unfolded and folded states to the other. FIG. 13(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded and is unfolded. When the display is turned on, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 9001 is made up of three housings 9000 connected by hinges 9055. The two housings 9000 are supported by the hinge 9055. The portable information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a radius of curvature of 1 mm or more and 150 mm or less. It can be done.

[0340] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is an electronic device that does not have a display portion. The present invention can also be applied to the display unit of the electronic device described in this embodiment. In the case of a display device, the display device may be flexible and capable of displaying information along a curved display surface, or may be folded. Although a foldable display unit has been exemplified, the present invention is not limited to this. A display may be provided on the surface.

[0341] The structure described in this embodiment may be used in appropriate combination with structures described in other embodiments. can be done. EXAMPLES

[0342] In this embodiment, analytical samples of specimens A1 to A3 were prepared. The SIMS analysis was carried out.

[0343] First, the analysis samples prepared in this example will be described below.

[0344] (Samples A1 to A3) First, a 100 nm-thick oxide semiconductor film was formed on a 0.7 mm-thick glass substrate. Note that the compositions of the oxide semiconductor films in Sample A1, Sample A2, and Sample A3 are different from each other. .

[0345] The oxide semiconductor film of Sample A1 was prepared by subjecting the substrate to a substrate temperature of 170° C. and a flow rate of 100 sccm. Argon gas and oxygen gas at a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 Pa and polycrystalline metal oxide sputtering target Polycrystalline metal oxide sputtering The target (In:Ga:Zn=1:1:1.2 [atomic ratio]) was irradiated with 2500W AC Electricity was applied to form a film.

[0346] The oxide semiconductor film of Sample A2 was prepared by subjecting the substrate to a substrate temperature of 170° C. and Argon gas and oxygen gas at a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn = 3:1: 2 [atomic ratio]) and an AC power of 2500 W was applied to form the film.

[0347] The oxide semiconductor film of Sample A3 was prepared by subjecting the substrate to a substrate temperature of 170° C. and Argon gas and oxygen gas at a flow rate of 100 sccm were introduced into the chamber, and the pressure was set to 0.6 The sputtering target was a polycrystalline metal oxide (In:Ga:Zn = 4:2: The film was formed by applying 2500 W of AC power to a sample having an atomic ratio of 4.1.

[0348] Next, a heat treatment was performed at 450° C. for 1 hour in a nitrogen atmosphere. This was followed by a heat treatment at 450°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen. In this embodiment, in order to reduce the hydrogen concentration in the oxide semiconductor film, The samples were heat-treated, but in the actual transistor manufacturing process, the heat treatment was performed at 350°C or less. It is preferable to process it.

[0349] Through the above steps, Samples A1 to A3 of this example were fabricated.

[0350] Next, in order to measure the hydrogen concentrations in the oxide semiconductor films of Samples A1 to A3, The analysis results of samples A1 to A3 are shown in FIG. 4, the vertical axis is hydrogen concentration (atoms / cm 3 ) and the horizontal axis represents depth (nm), Represents.

[0351] From the results shown in FIG. 14, the hydrogen concentration in the oxide semiconductor film of Sample A1 was 6.33×10 1 9 atoms / cm 3 The hydrogen concentration in the oxide semiconductor film of Sample A2 was 8. 64×10 18 atoms / cm 3 In addition, the hydrogen in the oxide semiconductor film of Sample A3 The concentration is 1.46 x 10 19 atoms / cm 3 In addition, the oxide semiconductor The hydrogen concentration in the film was measured at a film thickness of 50 nm.

[0352] For example, the oxide semiconductor film of Sample A1 is formed on the oxide semiconductor film of Sample A2. , IGZO film (In:Ga:Zn=3:1:2)\IGZO film (In:Ga:Zn=1: Alternatively, the oxide semiconductor film of Sample A1 is formed on the oxide semiconductor film of Sample A3. By forming a semiconductor film, IGZO film (In:Ga:Zn=4:2:4.1)\IGZ The structure is an O film (In:Ga:Zn=1:1:1.2).

[0353] In this manner, the semiconductor device according to one embodiment of the present invention has a stacked oxide semiconductor film. It is preferable that the hydrogen concentration of the oxide semiconductor film be higher than that of the oxide semiconductor film. In addition, the atomic ratio of In in the lower oxide semiconductor film is greater than the atomic ratio of Ga. The atomic ratio of In in the upper oxide semiconductor film is smaller than that in the lower oxide semiconductor film. By using a stacked structure of oxide semiconductor films, it is possible to obtain a high field-effect mobility and high reliability. The semiconductor device can be made to have high thermal conductivity.

[0354] The configuration shown in this embodiment may be used in appropriate combination with other embodiment modes or other embodiments. good. EXAMPLES

[0355] In this embodiment, hydrogen and water are released from an insulating film included in a semiconductor device according to one embodiment of the present invention. The amount of insulating material included in the semiconductor device of one embodiment of the present invention was evaluated by TDS. The defects that become carrier traps in the film were evaluated using ESR. prepared the following samples B1 to B4 and samples C1 to C4.

[0356] First, the details of Samples B1 to B4 will be described.

[0357] <Sample B1> Sample B1 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. do.

[0358] The deposition conditions for the silicon nitride film of sample B1 were a substrate temperature of 350° C. and a flow rate of 200 silane gas at a flow rate of 2000 sccm, nitrogen gas at a flow rate of 100 sccm, and Ammonia gas was introduced into the chamber, the pressure was set to 100 Pa, and the PECVD equipment was set A film was formed by supplying RF power of 2000 W between the parallel plate electrodes placed on the substrate.

[0359] <Sample B2> Sample B2 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. .

[0360] The conditions for forming the silicon nitride film of sample B2 were ammonia gas flow rate of 2000 sc The silicon nitride film was formed at a flow rate of 1.0 cm. The thickness was the same as that of sample B1.

[0361] <Sample B3> Sample B3 has a structure in which a silicon oxynitride film with a thickness of 200 nm is formed on a glass substrate. be.

[0362] For the film formation conditions of the silicon oxynitride film of Sample B3, the substrate temperature was set at 350 °C, and a flow rate of 2 0 sccm of silane gas and 3000 sccm of dinitrogen monoxide gas were introduced into the chamber with the pressure set at 40 Pa, and 10 00 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form the film.

[0363] <Sample B4> Sample B4 has a structure in which a silicon oxynitride film with a thickness of 200 nm is formed on a glass substrate and exists.

[0364] For the film formation conditions of the silicon oxynitride film of Sample B4, RF power was set at 100 W to form the silicon oxynitride film. Regarding the conditions other than RF power, they were the same as those of Sample B3 and were used.

[0365] <TDS Measurement> Next, TDS measurements were performed on Samples B1 to B4 prepared above. In the TDS measurement each sample was heated from 50 °C to 550 °C, and the amount of gas released from the insulating film in each sample was evaluated. In Samples B1 and B2, the amount of hydrogen released from the silicon nitride film was evaluated. Regarding the amount of hydrogen released, the amount of gas released corresponding to a mass-to-charge ratio (M / z) of 2 was measured. Also, in Samples B3 and B4, the amount of H2O released from the silicon oxynitride film was evaluated. Regarding the amount of H2O released, the amount of gas released corresponding to a mass-to-charge ratio (M / z) of 18 was measured. In Fig. 15(A), the TDS measurement results of Sample B1 are shown, in Fig. 15(B) the TDS measurement

[0366] results of Sample B2 are shown, in Fig. 16(A) the TDS measurement results of Sample B3 are shown, and in Fig. 16(B) the TDS measurement results of Sample B4 are shown. results of Sample B4 are shown. The measurement results are shown in Figs. 15(A)(B) and 16(A)(B). The vertical axis represents intensity (arbitrary unit) and the horizontal axis represents substrate temperature (° C.).

[0367] From the results shown in Figure 15(A) and (B), it can be seen that the hydrogen It was found that it was possible to form a silicon nitride film with a low emission amount.

[0368] From the results shown in Figures 16(A) and 16(B), it can be seen that increasing the RF power reduces the amount of water released. It was found that a thin silicon oxynitride film could be formed.

[0369] Next, samples C1 to C4 will be described in detail.

[0370] <Sample C1> Sample C1 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. .

[0371] The deposition conditions for the silicon nitride film of sample C1 were a substrate temperature of 350° C. and a flow rate of 200 silane gas at a flow rate of 2000 sccm, nitrogen gas at a flow rate of 100 sccm, and Ammonia gas was introduced into the chamber, the pressure was set to 100 Pa, and the chamber was placed in the PECVD device. An RF power of 2000 W was supplied between the parallel plate electrodes to form the film.

[0372] <Sample C2> Sample C2 has a structure in which a silicon nitride film with a thickness of 100 nm is formed on a glass substrate. .

[0373] The deposition conditions for the silicon nitride film of sample C2 were a substrate temperature of 280° C. and a flow rate of 100 silane gas at a flow rate of 1000 sccm, nitrogen gas at a flow rate of 1000 sccm, and annealing gas at a flow rate of 50 sccm. Amonia gas was introduced into the chamber, the pressure was set to 100 Pa, and 750 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form a film. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus.

[0374] <Sample C3> Sample C3 has a structure in which a silicon oxynitride film with a thickness of 100 nm is formed on a glass substrate. It is.

[0375] As the film formation conditions for the silicon oxynitride film, the substrate temperature was set to 280 °C, and silane gas with a flow rate of 50 sccm and dinitrogen monoxide gas with a flow rate of 1250 sccm were introduced into the chamber. The pressure was set to 20 Pa, and 750 W of RF power was supplied between the parallel plate electrodes installed in the PECVD apparatus to form a film. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus.

[0376] <Sample C4> Sample C4 has a structure in which a silicon oxynitride film with a thickness of 100 nm is formed on a glass substrate. It is.

[0377] For Sample C4, under the film formation conditions of the silicon oxynitride film of Sample C3, the RF power was set to 250 W to form a silicon oxynitride film. For conditions other than RF power, they were the same as those of Sample C3. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus.

[0378] <ESR measurement> Next, ESR measurements were performed on Samples C1 to C4 prepared above. The ESR measurement is performed at a predetermined temperature, and from the value of the magnetic field (H0) at which microwave absorption occurs, the parameter called the g value is obtained using the formula g = hν / βH0. Here, ν is the frequency of the microwave. h is Planck's constant, and β is the Bohr magneton, both of which are constants. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus. The film was formed by supplying 750 W of RF power between the parallel plate electrodes installed in the PECVD apparatus.

[0379] For Samples C1 and C2, ESR measurements were performed under the following conditions. The measurement temperature was room temperature. (25°C), 9.2GHz high frequency power (microwave power) 0.1mW, magnetic The direction of the field was parallel to the film surface of the prepared sample. The detection limit for the spin density of the signal due to enter is 1.5×10 16 spins / cm 3 It was.

[0380] The ESR measurements were performed on samples C3 and C4 under the following conditions: (25°C) and a 9.2GHz high-frequency power (microwave power) of 0.005mW. The direction of the magnetic field was parallel to the film surface of the sample. The detection limit for the spin density of the signal due to the E'-center is 1.5 × 10 16 s pins / cm 3 It was.

[0381] FIG. 17 shows ESR spectra obtained by measuring the ESR of samples C1 and C2. Figure 18 shows the ESR spectra obtained by measuring the ESR of samples C3 and C4. be.

[0382] As shown in Figure 17, sample C1 has a higher K-center-related defect than sample C2. It can be seen that the intensity of the signal is small. This defect is caused by dangling bonds of silicon. By applying high RF power at a higher temperature, the dangling bonds of silicon are reduced. It was found that a silicon nitride film could be formed without any problem.

[0383] As shown in Fig. 18, sample C3 has a higher E'-center than sample C4. As shown in Figure 18, the E'-center is These defects are caused by dangling bonds of silicon. By supplying a higher RF power, the silicon dangling bonds are reduced, and the oxynitride is formed. It was found that a silicon carbide film could be formed using this method.

[0384] The configuration shown in this embodiment may be used in appropriate combination with other embodiment modes or other embodiments. good. EXAMPLES

[0385] In this example, a transistor corresponding to the transistor 170 shown in FIG. The ID-VG characteristics of the transistor were evaluated. Samples D1 to D3 were prepared and evaluated. Samples D1 and D2 are comparative examples. The sample D3 is a sample having a transistor according to one embodiment of the present invention. In addition, samples D1 to D3 have a channel length L of 2 μm and a channel width A transistor with W=50μm and a transistor with channel length L=3μm and channel width W=50μm A total of three types of transistors were used: This is a structure in which a star is formed.

[0386] The sample prepared in this example will be described below. In the following description, FIG. The following description will be given using the reference numerals given to the transistor 170 shown in FIG.

[0387] <Preparation method of sample D1> First, a conductive film 104 was formed on a substrate 102. A glass substrate was used as the substrate 102. The conductive film 104 was a tungsten film having a thickness of 100 nm, which was deposited by sputtering. The film was formed using a magnetron sputtering apparatus.

[0388] Next, insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the substrate 6, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. In addition, as the insulating film 107, a silicon oxynitride film having a thickness of 50 nm was formed by using a PECVD apparatus. It was formed by

[0389] The conditions for forming the insulating film 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50nm. Next, the flow rate of ammonia gas was changed to 2000sccm, and a nitride silicon layer with a thickness of 300nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 A silicon nitride film with a thickness of nm was formed.

[0390] The conditions for forming the insulating film 107 are a substrate temperature of 350° C. and a flow rate of 20 sccm. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber, and the pressure The pressure was set to 40 Pa, and an RF power of 100 W was applied between the parallel plate electrodes installed in the PECVD device. A force was applied to deposit the film.

[0391] Next, the oxide semiconductor film 108 was formed over the insulating film 107. A single-layer IGZO film was formed using a sputtering device. The oxide semiconductor film 108 was an IGZO film having a thickness of 35 nm. The film formation conditions were a substrate temperature of 170° C., an argon gas flow rate of 100 sccm, and Oxygen gas was introduced into the chamber at a rate of 100 sccm, and the pressure was set to 0.6 Pa. Metal oxide sputtering target (In:Ga:Zn=1:1:1.2 [atomic ratio] ) was supplied with 2500 W of AC power to form a film.

[0392] Next, the first heat treatment was carried out at 450° C. for 1 hour in a nitrogen atmosphere. This was followed by a heat treatment at 450°C for 1 hour in a nitrogen and oxygen mixed gas atmosphere. Ta.

[0393] Next, the conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were a tungsten film having a thickness of 50 nm and a SiO2 film having a thickness of 400 nm. A 100 nm thick aluminum film and a 100 nm thick titanium film were deposited on the substrate using a sputtering device. The layers were formed successively in a vacuum.

[0394] Next, an insulating film was formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. The insulating film 114 and the insulating film 116 were formed. The insulating film 114 was a 50 nm thick oxynitride film. The silicon film was formed using a PECVD apparatus. A silicon oxynitride film having a thickness of 1000 nm was formed using a PECVD apparatus. The insulating film 4 and the insulating film 116 were formed successively in a vacuum using a PECVD apparatus.

[0395] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica gel flow rate of 50 sccm. Nitrous oxide gas at a flow rate of 2000 sccm was introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 μm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was placed between the parallel plate electrodes in the PECVD device. An RF power of 1500 W was supplied to the substrate to form the film.

[0396] Next, a second heat treatment was performed at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0397] Next, the following two steps were carried out.

[0398] (1, ITSO film formation process) An ITSO film having a thickness of 5 nm was formed on the insulating film 116 by using a sputtering apparatus. The conditions for forming the ITSO film were: substrate temperature at room temperature, argon gas at a flow rate of 72 sccm, The gas and oxygen gas with a flow rate of 5 sccm were introduced into the chamber, the pressure was set to 0.15 Pa, and the gas A metal oxide target (In2O3:SnO2:SiO 2 = 85:10:5 [wt %]) and a DC power of 1000 W was supplied to form the film.

[0399] (2. Oxygen addition treatment process) Next, oxygen was introduced into the oxide semiconductor film 108 and the insulating films 114 and 116 through the ITSO film. The oxygen addition process was carried out by using an ashing device and setting the substrate temperature at 40°C. The oxygen gas was introduced into the chamber at a flow rate of 250 sccm, the pressure was set to 15 Pa, and the base A bias was applied to the plate side between the parallel plate electrodes installed in the ashing device. An RF power of 4500 W was supplied for 600 seconds.

[0400] Next, the substrate temperature was set to 350°C and heat treatment was performed in a nitrogen atmosphere of 175 Pa. An insulating film 118 was formed on the film. The insulating film 118 was a silicon nitride film having a thickness of 100 nm. The film was formed using a PECVD apparatus.

[0401] Next, an opening 142c reaching the conductive film 112b and an opening 142b reaching the conductive film 104 are formed. The openings 142a, 142b, and 142c were formed by dry etching. The film was formed using a mixing apparatus.

[0402] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. The conductive film was processed to form the conductive films 120a and 120b. 120b is a 100 nm thick ITSO film formed using a sputtering device. The composition of the target used for the ITSO film was the same as that used in the ITSO film formation process described above. The composition was the same as that of the

[0403] Next, a third heat treatment was performed at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0404] The sample D1 of this embodiment was fabricated by the above steps. The temperature was 450°C.

[0405] <Preparation method of sample D2> Sample D2 differs from Sample D1 in the following steps. The same as in sample D1.

[0406] In sample D2, the first heat treatment was not performed.

[0407] In addition, in (2, oxygen addition treatment step) of sample D2, the oxygen addition treatment time was 120 s Next, the ITSO film was removed to expose the insulating film 116. The removal method is to use a wet etching device and a 5% oxalic acid solution. After etching for 300 seconds, the specimen was washed with 0.5% hydrofluoric acid for 15 minutes. Etching was performed for sec.

[0408] Next, the insulating film 118 was formed on the insulating film 116 without performing a heat treatment.

[0409] The sample D2 of this example was fabricated by the above steps. The temperature was 350°C.

[0410] <Preparation method of sample D3> Sample D3 differs from Sample D1 in the following steps. The same as in sample D1.

[0411] In the sample D3, the oxide semiconductor film 108 is formed on the conductive film 104 which functions as a gate electrode. A first oxide semiconductor film 108a on the side of the first oxide semiconductor film 108a and a second oxide semiconductor film 108b on the first oxide semiconductor film 108a are The first oxide semiconductor film 108a was formed by stacking a first oxide semiconductor film 108b and a second oxide semiconductor film 108b. Then, an IGZO film having a thickness of 10 nm is formed as the second oxide semiconductor film 108b. A nm-thick IGZO film was formed.

[0412] Note that the first oxide semiconductor film 108a was formed under the following conditions: the substrate temperature was 170° C. Argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were poured into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn=4:2:4.1 [atomic ratio] .

[0413] The second oxide semiconductor film 108b was formed under the following conditions: the substrate temperature was 170° C. Argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were poured into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn film (atomic ratio: 1:1:1.2). .

[0414] Moreover, the first heat treatment was not carried out on sample D3.

[0415] In addition, in (2, oxygen addition treatment step) of sample D3, the oxygen addition treatment time was 120 s Next, the ITSO film was removed to expose the insulating film 116. The removal method is to use a wet etching device and a 5% oxalic acid solution. After etching for 300 seconds, the specimen was washed with 0.5% hydrofluoric acid for 15 minutes. Etching was performed for sec.

[0416] Next, the insulating film 118 was formed on the insulating film 116 without performing a heat treatment.

[0417] The sample D3 of this example was fabricated by the above steps. The temperature was 350°C.

[0418] Next, the ID-VG characteristics of the samples D1 to D3 prepared as above were measured. The ID-VG characteristic results of sample D3 are shown in Figs. 19 to 21. Note that Fig. 19 shows the ID-VG characteristic results of sample D1. FIG. 20 shows the ID-VG characteristic results of sample D1, and FIG. 21 shows the ID-VG characteristic results of sample D2. 19 to 21 show the ID-VG characteristic results of sample D3. The horizontal axis represents D(A) and the horizontal axis represents VG(V). A) shows the ID-VG characteristics of a transistor with a channel length L = 2 μm and a channel width W = 50 μm. (B) shows the performance results for a transistor with a channel length L = 3 μm and a channel width W = 50 μm. (C) shows the ID-VG characteristic results for the MOSFET with a channel length of L = 6 μm and a channel width of W = 50 4 shows the ID-VG characteristics of a 2.5 μm transistor.

[0419] In addition, the conductive film 104 serving as the first gate electrode of the transistor 170 is applied with A voltage (hereinafter also referred to as gate voltage (VG)) and a conductor functioning as a second gate electrode. The voltage (VBG) applied to the conductive film 120b is set to a value ranging from -15V to +20V in increments of 0.25V. The voltage applied to the conductive film 112a functioning as the source electrode was (hereinafter, also referred to as source voltage (VS)) is set to 0V (common), and the drain electrode The voltage applied to the conductive film 112b that functions as a drain voltage (hereinafter also referred to as drain voltage (VD)) was set to 1V or 10V.

[0420] From the results shown in Figs. 19 to 21, the maximum temperature in the process was reduced from 450°C to 350°C. It was confirmed that there was no significant difference in the ID-VG characteristics of the transistor even when the temperature was lowered to 1000 V. In addition, compared with Sample D2, Sample D3 has improved electrical characteristics by using a stacked structure of oxide semiconductor films. The variation is reduced. In addition, the on-current of sample D3 is improved, and the S value (subth Thus, the semiconductor device according to one embodiment of the present invention has a low threshold swing value. The device was found to have excellent electrical properties.

[0421] Next, the reliability of the samples D1 to D3 was evaluated. A bias-thermal stress test (hereinafter referred to as a GBT test) was used.

[0422] In this embodiment, the GBT test conditions are: gate voltage (VG) of ±30V; The gate voltage (VD) and source voltage (VS) are set to 0V (COMMON), and the stress temperature is set to 60 The temperature was set at ℃, the stress application time was set at 1 hour, and the measurement environment was set to a dark environment and a light irradiation environment (white L The experiment was carried out in two different environments: The source and drain electrodes of the transistor are at the same potential, and the gate electrode is connected to the source and drain electrodes. A potential different from that of the drain electrode was applied to the gate electrode for a certain period of time (here, 1 hour). When the applied potential is higher than the potential of the source electrode and the drain electrode, it is considered a positive stress. When the potential applied to the gate electrode is lower than the potentials of the source and drain electrodes, it is called negative. Therefore, in accordance with the measurement environment, plus GBT stress (dark), Negative GBT stress (dark), positive GBT stress (light exposure), and negative G Reliability evaluation was performed under a total of four conditions of BT stress (light irradiation).

[0423] The GBT test results of samples D1 to D3 are shown in FIG. 22. In FIG. The change in the threshold voltage (ΔVth) and the change in the shift value (ΔShift) of the transistor are The horizontal axis indicates the sample name, process conditions, etc. The drain current (ID)-gate voltage (VG) characteristic of a transistor is expressed as a logarithm. The maximum slope of the tangent of the in-current (ID) is 1×10 -12 Gate voltage at the intersection with the A axis (V G). Also, ΔShift is the amount of change in the Shift value.

[0424] From the results shown in FIG. 22, the amount of change in threshold voltage (Δ On the other hand, sample D3 according to one embodiment of the present invention had a Vth of about three times that of the conventional GBT test. The change in threshold voltage (ΔVth) was about twice that of sample D1. Even if the maximum temperature at which the oxide semiconductor film is grown is reduced from 450° C. to 350° C., the oxide semiconductor film can be formed into a stacked structure. It was confirmed that this can suppress the decline in reliability.

[0425] Next, a positive gate BT stress test (Dark +GBT) and negative gate BT stress test (Dark -GBT) are alternately repeated. The amount of change in threshold voltage was measured when the transistor was turned on. The D-VG characteristics were measured (initial). Then, the positive gate BT stress test and the The inus gate BT stress test was performed twice, alternating between each gate BT stress. The test was performed at a stress temperature of 60°C and for a stress time of 3600 seconds. The measurements were performed on a transistor with a channel length L of 6 μm and a channel width W of 50 μm.

[0426] FIG. 23 shows the results of the initial and final stress tests for samples D1 to D3. The vertical axis in FIG. 23 represents the threshold voltage after the drain BT stress test. The horizontal axis shows the stress test name. Figure 23 shows the results before the stress test (initial) and after the positive gate BT stress test. After stress test (+GBT), negative gate BT After stress test (-GBT), positive gate BT After the stress test (+GBT), then after the negative gate BT stress test (-GBT). These are the results of GBT tests conducted on both.

[0427] Here, the positive gate BT stress test and the negative gate BT stress test are alternately performed. If the threshold voltage value increases and decreases alternately when the The shift in threshold voltage due to the trapping and detrapping of carriers in the associated trap levels On the other hand, if the change in threshold voltage is biased in one direction (e.g. For example, if the capacitance of the trapped capillary is gradually increasing or decreasing, It is speculated that this is due to the threshold voltage shift caused by the rear acting as a fixed charge.

[0428] From the results shown in Fig. 23, the threshold voltage of the transistor after each gate BT stress test is In comparison with sample D2, sample D3 according to one embodiment of the present invention has a smaller amount of change in threshold voltage. It can be seen that.

[0429] As described above, one embodiment of the present invention is a transistor in which the process temperature is low, like the transistor in Sample D3. However, by forming the oxide semiconductor film into a stacked structure, the reliability can be improved and the variation in electrical characteristics can be reduced. The device has excellent electrical characteristics, including suppression of on-state current, improvement of on-state current, and low S value. was shown.

[0430] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0431] In this example, a transistor corresponding to the transistor 170 shown in FIG. The ID-VG characteristics of the transistor were evaluated. Samples E1 and E2 were prepared and evaluated. Sample E1 is a comparative example of a transistor. Sample E1 is a sample having a transistor according to one embodiment of the present invention. Samples E1 and E2 each have a channel length L of 2 μm and a channel width W of 50 μm. A transistor with a channel length L=3 μm and a channel width W=50 μm. A total of three types of transistors were formed, with channel length L = 6 μm and channel width W = 50 μm. The three types of transistors are mounted on one of three substrates. 40 of them were formed on each substrate.

[0432] The sample prepared in this example will be described below. In the following description, FIG. The following description will be given using the reference numerals given to the transistor 170 shown in FIG.

[0433] <Preparation method of sample E1> First, a conductive film 104 was formed on a substrate 102. A glass substrate was used as the substrate 102. The size of the glass substrate was 600 mm x 720 mm and the thickness was 0.7 mm. The conductive film 104 was a tungsten film having a thickness of 100 nm, which was deposited by sputtering. The film was formed using a magnetron sputtering apparatus.

[0434] Next, insulating films 106 and 107 were formed on the substrate 102 and the conductive film 104. As the substrate 6, a silicon nitride film having a thickness of 400 nm was formed using a PECVD apparatus. In addition, as the insulating film 107, a silicon oxynitride film having a thickness of 50 nm was formed by using a PECVD apparatus. It was formed by

[0435] The conditions for forming the insulating film 106 were a substrate temperature of 350° C. and a flow rate of 200 sccm. Run gas, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm The pressure was set to 100 Pa, and the parallel flat plate installed in the PECVD device was A 2000W RF power was supplied between the electrodes of the plate to form a silicon nitride film with a thickness of 50nm. Next, the flow rate of ammonia gas was changed to 2000sccm, and a nitride silicon layer with a thickness of 300nm was formed. Then, the flow rate of ammonia gas was changed to 100 sccm to form a silicon film with a thickness of 50 A silicon nitride film with a thickness of nm was formed.

[0436] The conditions for forming the insulating film 107 are a substrate temperature of 350° C. and a flow rate of 20 sccm. Silane gas at a flow rate of 3000 sccm and nitrous oxide gas at a flow rate of 3000 sccm were introduced into the chamber, and the pressure The pressure was set to 40 Pa, and an RF power of 100 W was applied between the parallel plate electrodes installed in the PECVD device. A force was applied to deposit the film.

[0437] Next, the oxide semiconductor film 108 was formed over the insulating film 107. The first oxide semiconductor film 108a on the conductive film 104 side functioning as a gate electrode and the first oxide The second oxide semiconductor film 108b was formed on the oxide semiconductor film 108a. As the first oxide semiconductor film 108a, an IGZO film having a thickness of 10 nm was formed. As the nitride semiconductor film 108b, an IGZO film having a thickness of 15 nm was formed.

[0438] Note that the first oxide semiconductor film 108a was formed under the following conditions: the substrate temperature was 170° C. Argon gas with a flow rate of 140 sccm and oxygen gas with a flow rate of 60 sccm were introduced into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In:G The film was formed by applying 2500 W of AC power to a mixture of Zn and Fe (a:Zn=4:2:4.1 [atomic ratio]).

[0439] The second oxide semiconductor film 108b was formed under the following conditions: the substrate temperature was 170° C. Argon gas with a flow rate of 100 sccm and oxygen gas with a flow rate of 100 sccm were poured into the chamber. The pressure was set to 0.6 Pa, and a polycrystalline metal oxide sputtering target (In: The film was formed by applying 2500 W of AC power to a Ga:Zn film (atomic ratio: 1:1:1.2). .

[0440] Next, the first heat treatment was carried out at 450° C. for 1 hour in a nitrogen atmosphere. This was followed by a heat treatment at 450°C for 1 hour in a nitrogen and oxygen mixed gas atmosphere. Ta.

[0441] Next, the conductive films 112a and 112b are formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were a tungsten film having a thickness of 50 nm and a SiO2 film having a thickness of 400 nm. A 100 nm thick aluminum film and a 100 nm thick titanium film were deposited on the substrate using a sputtering device. The layers were formed successively in a vacuum.

[0442] Next, an insulating film was formed over the insulating film 107, the oxide semiconductor film 108, and the conductive films 112a and 112b. The insulating film 114 and the insulating film 116 were formed. The insulating film 114 was a 50 nm thick oxynitride film. The silicon film was formed using a PECVD apparatus. A silicon oxynitride film having a thickness of 1000 nm was formed using a PECVD apparatus. The insulating film 4 and the insulating film 116 were formed successively in a vacuum using a PECVD apparatus.

[0443] The conditions for forming the insulating film 114 were a substrate temperature of 220° C. and a silica gel flow rate of 50 sccm. Nitrous oxide gas at a flow rate of 2000 sccm was introduced into the chamber, and the pressure was increased to 2 The pressure was set to 0 Pa, and 100 W of RF power was applied between the parallel plate electrodes installed in the PECVD device. The insulating film 116 was formed under the conditions of a substrate temperature of 220° C. and a flow rate of 1000 μm. Silane gas at a flow rate of 160 sccm and nitrous oxide gas at a flow rate of 4000 sccm were introduced into the chamber. The pressure was set to 200 Pa, and the gas was placed between the parallel plate electrodes in the PECVD device. An RF power of 1500 W was supplied to the substrate to form the film.

[0444] Next, a second heat treatment was performed at 350° C. in a nitrogen gas atmosphere. It was set to one hour.

[0445] Next, the following three steps were carried out.

[0446] (1, ITSO film formation process) An ITSO film having a thickness of 5 nm was formed on the insulating film 116 by using a sputtering apparatus. The conditions for forming the ITSO film were: substrate temperature at room temperature, argon gas at a flow rate of 72 sccm. Gas and oxygen gas at a flow rate of 5 sccm were introduced into the chamber, and the pressure was set to 0.15 Pa. A metal oxide target (In2O3:SnO2:Si The film was formed by supplying 1000 W of DC power to a mixture of 1000 μm and 100 μm of ZnO (O2 = 85:10:5 [wt %]).

[0447] (2. Oxygen addition treatment process) Next, oxygen was introduced into the oxide semiconductor film 108 and the insulating films 114 and 116 through the ITSO film. The oxygen addition process was carried out by using an ashing device and setting the substrate temperature at 40°C. The oxygen gas was introduced into the chamber at a flow rate of 250 sccm, the pressure was set to 15 Pa, and the base A bias was applied to the plate side between the parallel plate electrodes installed in the ashing device. An RF power of 4500 W was supplied for 120 seconds.

[0448] (3, ITSO film removal process) Next, the ITSO film was removed to expose the insulating film 116. A wet etching device was used, and a 5% oxalic acid solution was used for etching. After etching for 15 seconds, the specimen was etched with 0.5% hydrofluoric acid for 15 seconds. We performed the switching.

[0449] Next, an insulating film 118 was formed on the insulating film 116. The insulating film 118 had a thickness of 100 mm. A silicon nitride film having a thickness of nm was formed using a PECVD apparatus. The substrate temperature in the PECVD apparatus was set to 350°C.

[0450] Next, an opening 142c reaching the conductive film 112b and an opening 142b reaching the conductive film 104 are formed. The openings 142a, 142b, and 142c were formed by dry etching. The film was formed using a mixing apparatus.

[0451] Next, a conductive film is formed on the insulating film 118 so as to cover the openings 142a, 142b, and 142c. The conductive film was processed to form the conductive films 120a and 120b. 120b is a 100 nm thick ITSO film formed using a sputtering device. The composition of the target used for the ITSO film was the same as that used in the ITSO film formation process described above. The composition was the same as that of the

[0452] Next, a third heat treatment was performed at 250° C. in a nitrogen gas atmosphere. It was set to one hour.

[0453] The sample E1 of this embodiment was fabricated by the above steps. The temperature was 450°C.

[0454] <How to prepare sample E2> Sample E2 differs from Sample E1 in the following steps. The same as in sample E1.

[0455] In sample E2, the first heat treatment was not performed.

[0456] The sample E2 of this example was fabricated by the above steps. The temperature was 350°C.

[0457] Next, the ID-VG characteristics of the samples E1 and E2 prepared above were measured. The ID-VG characteristic results of sample E2 are shown in Fig. 24 and Fig. 25. Note that Fig. 24 shows the ID-VG characteristic results of sample E1. FIG. 25 shows the ID-VG characteristic results of sample E1. Also, In Fig. 24 and Fig. 25, the first vertical axis represents ID (A) and the second vertical axis represents μFE (cm 2 / Vs ) and the horizontal axis represents VG(V). In addition, in FIG. 24 and FIG. 25, (A) represents ,ID-VG characteristic results of a transistor with channel length L = 2 μm and channel width W = 50 μm (B) is the I of a transistor with a channel length L = 3 μm and a channel width W = 50 μm. The D-VG characteristic results are shown in (C) for a channel length of L = 6 μm and a channel width of W = 50 μm. 24 and 25 show the ID-VG characteristics of the transistor. A total of 10 transistor characteristics are displayed overlapping each other.

[0458] In addition, the conductive film 104 serving as the first gate electrode of the transistor 170 is applied with A voltage (hereinafter also referred to as gate voltage (VG)) and a conductor functioning as a second gate electrode. The voltage (VBG) applied to the conductive film 120b is set to a value ranging from -15V to +20V in increments of 0.25V. The voltage was applied in the following steps. Only for the transistor, the voltage applied to the conductive film 104 and the conductive film 120b is changed from -15V to +15V. In addition, the voltage applied to the conductive film 112a functioning as the source electrode (hereinafter, the source voltage) The drain electrode is connected to the conductor that functions as a drain electrode. The voltage applied to the film 112b (hereinafter also referred to as drain voltage (VD)) is set to 0.1 V or The field effect mobility (μFE) was measured at VD=20 V. is.

[0459] From the results shown in Fig. 24 and Fig. 25, the maximum temperature in the process was reduced from 450℃ to 350℃. It was confirmed that there was no significant difference in the ID-VG characteristics of the transistor even when the temperature was reduced to 100

[0460] Next, the channel length L of the sample E1 and the channel width W of the sample E2 are 3 μm and 50 μm, respectively. The variation in the transistors was evaluated within the substrate surface (600 mm x 720 mm).

[0461] First, the channel length L of sample E1 and the channel width W of sample E2 are 3 μm and 50 μm, respectively. The ID-VG characteristics of the transistors were evaluated. The ID-VG characteristics of samples E1 and E2 are as follows: The results are shown in Figures 26(A) and 26(B). Note that Figure 26(A) shows the ID-VG characteristic results for sample E1. FIG. 26(B) shows the ID-VG characteristic results for sample E2. In FIG. 26(A), the vertical axis represents ID(A) and the horizontal axis represents VG(V). In each of (A) and (B), the characteristics of a total of 40 transistors are displayed in an overlapping manner. The ID-VG characteristics shown in FIGS. 26(A) and 26(B) are the same as those shown in FIGS. 24 and 25. The measurement conditions are different from those shown in Fig. 26(A) and (B). As for the gate voltage (VG) and (VBG), the range is from -15V to +20V. A voltage of 25 V was applied to the conductive film 104 and the conductive film 120b. S) was set to 0V (common), and the drain voltage (VD) was set to 10V.

[0462] Next, the threshold voltages of the transistors of the samples E1 and E2 shown in FIGS. The results of comparing the variations in (Vth) and on-current (Ion) are shown in Figures 27(A) and (B). FIG. 27(A) shows the probability of Vth within the substrate surface (600 mm x 720 mm). FIG. 27(B) is a diagram explaining the distribution of I 27B is a diagram for explaining the probability distribution of on. In FIG. 27B, Ion is VG=2 The value was taken as 0V.

[0463] From the results shown in FIG. 26 and FIG. 27, it can be seen that sample E2 has a slightly lower Ion than sample E1. However, the transistor characteristics are good with little variation within the substrate surface. was confirmed.

[0464] Next, the reliability of the samples E1 and E2 was evaluated. , the GBT test was used.

[0465] In this embodiment, the GBT test conditions are: gate voltage (VG) of ±30V; The gate voltage (VD) and source voltage (VS) are set to 0V (COMMON), and the stress temperature is set to 60 The temperature was set at ℃, the stress application time was set at 1 hour, and the measurement environment was set to a dark environment and a light irradiation environment (white L The experiment was carried out in two different environments: The source and drain electrodes of the transistor are at the same potential, and the gate electrode is connected to the source and drain electrodes. A potential different from that of the drain electrode was applied to the gate electrode for a certain period of time (here, 1 hour). When the applied potential is higher than the potential of the source electrode and the drain electrode, it is considered a positive stress. When the potential applied to the gate electrode is lower than the potentials of the source and drain electrodes, it is called negative. Therefore, in accordance with the measurement environment, plus GBT stress (dark), Negative GBT stress (dark), positive GBT stress (light exposure), and negative G Reliability evaluation was carried out under a total of four conditions, including GBT stress (light irradiation). Trace (dark) with PBTS (Positive Bias Temperature Stress) and negative GBT stress (dark) is NBTS (Nagativ e Bias Temperature Stress) and plus GBT stress ( PBITS (Positive Bias Illuminations T stress (light irradiation) and negative GBT stress (light irradiation) ITS(Nagative Bias Illuminations Temperat It may be described below as "ure Stress."

[0466] The GBT test results of the samples E1 and E2 are shown in FIG. 28. In FIG. 28, the vertical axis indicates the The change in the threshold voltage (ΔVth) and the change in the shift value (ΔShift) of the transistor are The horizontal axis indicates the sample name, process conditions, etc.

[0467] From the results shown in FIG. 28, the change in threshold voltage (Δ Vth) is slightly larger, but the negative fluctuation of the GBT is less than 1V and the positive fluctuation is less than 2V. It was confirmed that this was the case.

[0468] Next, when PBTS and NBTS were alternately repeated for samples E1 and E2, The change in threshold voltage was measured. The G characteristic was measured (initial). Then, PBTS and NBTS were alternated twice. Each GBT stress test was performed at a stress temperature of 60°C and for a stress time of 3600 In this example, the channel length L is 6 μm and the channel width W is 50 μm. The measurements were performed on the star.

[0469] The results are shown for sample E1 before the stress test (initial) and after each GBT stress test. The threshold voltage is shown in FIG. 29(A) for sample E2 before the stress test (initial) and after the stress test (initial). The threshold voltages after each GBT stress test are shown in FIG. 29(B). In 9(A) and (B), the vertical axis is the threshold voltage (Vth) when the drain voltage is 10V. The horizontal axis indicates the stress test name. Also, Fig. 29(A) and (B) show the results before and after the stress test. (initial), PBTS, NBTS, PBTS, NBTS in turn, GBT test This is the result of the above.

[0470] From the results shown in FIGS. 29(A) and 29(B), the change in threshold voltage of the transistor of sample E2 is larger than the change in threshold voltage of the transistor of sample E1, but the change is within ±4V. The amount was confirmed.

[0471] As described above, one embodiment of the present invention is a transistor that can be fabricated at a low process temperature, like the transistor of sample E2. However, by forming the oxide semiconductor film into a stacked structure, the reliability can be improved and the variation in electrical characteristics can be reduced. The device has excellent electrical characteristics, including suppression of on-state current, improvement of on-state current, and low S value. was shown.

[0472] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. EXAMPLES

[0473] In this embodiment, the transistor 100 shown in FIG. 1 and the transistor 100 shown in FIG. A transistor corresponding to No. 70 was fabricated, and a display device having the transistor was manufactured.

[0474] First, Table 1 shows the specifications of the display device produced in this example.

[0475] [Table 1]

[0476] Next, top views of the pixel portion of the display device manufactured in this embodiment are shown in Figures 30(A) and 30(B). FIG. 30A shows the upper surface of the pixel section 840A when the minimum processing dimension of the process is set to 2 μm. FIG. 30(B) is a cross-sectional view of a pixel portion when the minimum processing dimension of the process is set to 3.5 μm. 30(A) and (B) show the top view of the pixel array 840B. It represents.

[0477] In addition, the top view of the gate driver part of the display device manufactured in this embodiment is shown in FIG. FIG. 31(A) is a top view when the minimum processing dimension of the process is set to 2 μm. FIG. 31B is a top view in which the minimum processing dimension of the process is set to 3.5 μm. In FIG. 31A, region 800 is the frame width, region 801 is the dummy pixel portion, The region 802 is a protection circuit section, the region 803 is a gate driver circuit section, and the region 804 is a separation In FIG. 31B, the area 850 indicates the frame width, region 851 indicates a dummy pixel section, region 852 indicates a protection circuit section, and region 853 indicates a gate The region 852 represents the gate driver circuit portion, and the region 854 represents the margin region for separation. .

[0478] In this embodiment, the area 800 shown in FIG. 801 is 0.05 mm, area 802 is 0.08 mm, and area 803 is 0.41 mm In this embodiment, the area 804 is set to 0.16 mm. Let area 850 be 0.8 mm, area 851 be 0.05 mm, and area 852 be 0.0 7 mm, area 853 was 0.55 mm, and area 854 was 0.13 mm.

[0479] In this embodiment, as shown in FIG. 31(A)(B), the protection circuit section (area 80 2 or region 852) is provided, but the present invention is not limited to this. In this case, the protection circuit can be omitted, so the frame width can be further reduced. For example, the area 800 shown in FIG. The area 850 shown in FIG. 31(B) can be reduced to 0.7 mm.

[0480] As described above, the transistor of one embodiment of the present invention has high field-effect mobility and high reliability. Since the width of the frame (area 800 and area 801) is large, the gate driver circuit is built in. 50) is 1 mm or less, preferably 0.8 mm or less, more preferably 0.6 mm or less. Therefore, a display device with a narrow frame can be manufactured.

[0481] FIG. 32 is a cross-sectional view corresponding to the cut surface taken along the dashed line M1-N1 shown in FIG. FIG. 3A is a cross-sectional view corresponding to the cut surface between the dashed line M2-N2 shown in FIG. 2(B), respectively.

[0482] The pixel portion 840A shown in FIG. 32A includes a conductive film 904a on a substrate 902 and a An insulating film 906 on the conductive film 904, an insulating film 907 on the insulating film 906, and an insulating film 907 an oxide semiconductor film 908 on the insulating film 907; an oxide semiconductor film 909 on the insulating film 907; a conductive film 912a electrically connected to the oxide semiconductor film 908 and functioning as a source electrode; A conductive film 912b electrically connected to the insulating film 908 and functioning as a drain electrode, 7, an insulating film 914 over the oxide semiconductor films 908 and 909, and an insulating film 9 16, an insulating film 916, an insulating film 918 over the oxide semiconductor film 909, The conductive film 920a serving as a pixel electrode, the insulating film 918, and the insulating film on the conductive film 920a and a membrane 924.

[0483] Note that the oxide semiconductor film 908 includes a first oxide semiconductor film 908a and a second oxide semiconductor film 908b. The oxide semiconductor film 909 is a first oxide semiconductor film 908b. The second oxide semiconductor film 909a and the second oxide semiconductor film 909b.

[0484] The insulating film 918 is formed so as to cover the openings provided in the insulating films 914 and 916. The conductive film 920 serving as a pixel electrode is in contact with the oxide semiconductor film 909. The insulating film 914, 916, and 918 is formed so as to cover the openings. It is electrically connected to the conductive film 912b which functions as an electrode.

[0485] In addition, in Fig. 32(A) and (B), the liquid crystal element, the element on the counter substrate side, etc. are omitted. is doing.

[0486] In addition, the region 802 functioning as a protective circuit portion shown in FIG. 32(B) is a conductive layer on the substrate 902. A conductive film 904b, a conductive film 904c on the substrate 902, and an insulating film on the conductive films 904b and 904c. a film 906, an insulating film 907 over the insulating film 906, and an oxide semiconductor film 910 over the insulating film 907 a conductive film 912c electrically connected to the oxide semiconductor film 910; 0, a conductive film 912e on the insulating film 907, and an insulating film 907, the insulating film 9 over the oxide semiconductor film 910, and the conductive films 912c, 912d, and 912e 14, an insulating film 916 on the insulating film 914, an insulating film 918 on the insulating films 907 and 916, A conductive film 920b provided over the insulating film 918 and overlapping with the oxide semiconductor film 910; The conductive film 920c over the insulating film 918 and the conductive film 912e, and the insulating film 918 and the conductive film 920b , and an insulating film 924 on 920c.

[0487] The conductive film 904a, the conductive film 904b, and the conductive film 904c are formed by processing the same conductive film. In addition, the oxide semiconductor film 908, the oxide semiconductor film 909, and the oxide The oxide semiconductor film 910 was formed through the same process of processing an oxide semiconductor film. The conductive film 912a, the conductive film 912b, the conductive film 912c, the conductive film 912d, and the conductive film 91 The conductive film 920a and the conductive film 92e were formed through the same process of processing the conductive film. The conductive film 20b and the conductive film 920c were formed through the same process of processing a conductive film.

[0488] In addition, the transistor used in the region 803 functioning as the gate driver circuit portion shown in FIG. The transistor structure is the same as the transistor 170 shown in FIG. It can be used.

[0489] A glass substrate was used as the substrate 902. Conductive films 904a, 904b, and 904 As for c, a tungsten film having a thickness of 200 nm was formed by a sputtering device. As the insulating film 906, a silicon nitride film having a thickness of 400 nm is formed by a PECVD apparatus. As the insulating film 907, a silicon oxynitride film having a thickness of 50 nm was deposited by a PECVD apparatus. It was formed at.

[0490] The first oxide semiconductor films 908a, 909a, and 910a are made of 10-nm-thick oxide semiconductor films. IGZO film (In:Ga:Zn=3:1:2 [atomic ratio]) was formed using a sputtering device. The second oxide semiconductor films 908b, 909b, and 910b were formed using a 15 nm IGZO film (In:Ga:Zn=1:1:1.2 [atomic ratio]) was sputtered. It was formed in the apparatus.

[0491] The conductive films 912a, 912b, 912c, 912d, and 912e are made of a 50 nm thick tungsten film, 400 nm thick aluminum film, and 100 nm thick titanium film. A laminated film with the film was formed by a sputtering apparatus.

[0492] As the insulating film 914, a silicon oxynitride film having a thickness of 50 nm is deposited by a PECVD apparatus. The insulating film 916 was formed of a silicon oxynitride film having a thickness of 400 nm. The insulating film 918 was formed by a PECVD apparatus. The SiO2 film was formed using a PECVD apparatus.

[0493] The conductive films 920a, 920b, and 920c are made of ITSO films having a thickness of 100 nm. The film was formed using a sputtering apparatus.

[0494] In addition, in the region 802 functioning as a protection circuit portion shown in FIG. A transistor that functions as a protection circuit shown in FIG. FIG. 33 shows an example of a circuit diagram of a protection circuit that can be provided in the region 802.

[0495] The protection circuit 870 shown in FIG. 33 includes a first wiring 861 that functions as a gate line and a low potential A second wiring 862 that functions as a power supply line and a third wiring 86 that functions as a high potential power supply line 3, a transistor 871, and a transistor 872. 71 and transistor 872 have two gate electrodes, that is, a so-called dual gate structure. The two gate electrodes are supplied with the same potential.

[0496] The gate of the transistor 871 is connected to the source or drain of the transistor 871. The source of the transistor 871 is electrically connected to the first wiring 861. Or one of the drains is electrically connected to one of the source or drain of the transistor 872. The other of the source and the drain of the transistor 871 is connected to the second wiring 8 62. The other of the source and drain of the transistor 872 is The third wiring 863 is electrically connected to the gate of the transistor 872 and the third wiring 863 .

[0497] The protection circuit 870 shown in FIG. 33 is formed by dividing the area 801 and the area 803 as shown in this embodiment. By providing the insulating film between the insulating film and the insulating film, that is, in the region 802, the reliability of the display device can be improved. However, the display device of one embodiment of the present invention is not limited thereto. For example, In this case, the frame width of the display device can be further reduced. .

[0498] The configuration shown in this embodiment may be used in appropriate combination with other embodiments or embodiments. It is possible. [Explanation of symbols]

[0499] 100 transistors 102 Substrate 104 Conductive film 106 Insulating film 107 Insulating film 108 Oxide semiconductor film 108a Oxide semiconductor film 108b Oxide semiconductor film 112 Conductive film 112a Conductive film 112b Conductive film 114 Insulating film 116 Insulating film 118 Insulating film 120 Conductive Film 120a Conductive film 120b Conductive film 131 Oxide Conductive Film 138 Etching gas 139 Oxygen 140a Mask 140b Mask 142 Etchant 142a opening 142b opening 142c opening 170 Transistors 501 Pixel circuit 502 Pixel section 504 Drive circuit section 504a Gate Driver 504b source driver 506 Protection circuit 507 Terminal section 550 Transistor 552 Transistor 554 Transistor 560 Capacitive element 562 Capacitive element 570 Liquid crystal element 572 Light emitting element 700 Display device 701 Substrate 702 Pixel section 704 Source driver circuit section 705 Substrate 706 Gate driver circuit section 708 FPC terminal section 710 Signal Line 711 Wiring section 712 Sealing material 716 FPC 730 Insulating film 732 Sealing film 734 Insulating film 736 Colored film 738 Light-shielding film 750 Transistors 752 Transistor 760 Connection electrode 764 Insulating film 766 Insulating Film 767 Oxide Semiconductor Film 768 Insulating Film 770 Planarizing Insulating Film 772 Conductive Film 774 Conductive Film 775 Liquid crystal elements 776 Liquid crystal layer 778 Structure 780 Anisotropic Conductive Film 782 Light emitting element 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitive element 800 areas 801 area 802 area 803 area 804 area 840A Pixel section 840B Pixel section 850 areas 851 area 852 areas 853 areas 854 area 861 Wiring 862 Wiring 863 Wiring 870 Protection circuit 871 Transistor 872 Transistors 902 Substrate 904 Conductive film 904a Conductive film 904b Conductive film 904c conductive film 906 Insulating film 907 Insulating film 908 Oxide Semiconductor Film 908a Oxide semiconductor film 908b Oxide semiconductor film 909 Oxide semiconductor film 909a Oxide semiconductor film 909b Oxide semiconductor film 910 Oxide semiconductor film 910a Oxide semiconductor film 910b Oxide semiconductor film 912a Conductive film 912b Conductive film 912c conductive film 912d Conductive film 912e conductive film 914 Insulating film 916 Insulating film 918 Insulating film 920 Conductive Film 920a Conductive film 920b Conductive film 920c conductive film 924 Insulating film 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 PCB 5130 Target 5161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 9000 Chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Mobile Information Terminal 9101 Portable information terminal 9102 Portable information terminal 9200 Mobile Information Terminal 9201 Mobile information terminals

Claims

[Claim 1] A semiconductor device having a transistor, The transistor is A gate electrode; a gate insulating film on the gate electrode; an oxide semiconductor film on the gate insulating film; a source electrode electrically connected to the oxide semiconductor film; a drain electrode electrically connected to the oxide semiconductor film, The oxide semiconductor film is a first oxide semiconductor film on the gate electrode side; a second oxide semiconductor film over the first oxide semiconductor film, The first oxide semiconductor film is a first region in which the atomic ratio of In is greater than the atomic ratio of M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf); The second oxide semiconductor film is a second region having a smaller atomic ratio of In than the first oxide semiconductor film; The second region has a portion that is thinner than the first region.

Images