Electronic device

Abstract

To improve the performance of an electronic device.SOLUTION: The electronic device includes a wiring substrate, a memory semiconductor device arranged on the wiring substrate, and a control semiconductor device arranged on the wiring substrate. The wiring substrate has a first fixed potential wiring and a second fixed potential wiring, and a plurality of signal wirings SG arranged between the first fixed potential wiring and the second fixed potential wiring. The plurality of signal wirings SG includes a signal wiring S1 adjacent to the first fixed potential wiring, a signal wiring S2 adjacent to the signal wiring S1, and a signal wiring S3 adjacent to the signal wiring S2. A distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than a distance D2 between the signal wiring S2 and the signal wiring S3.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an electronic device, and can be suitably used, for example, in an electronic device including a plurality of semiconductor devices and a wiring board. [Background technology]

[0002] Japanese Patent Laying-Open No. 2006-237385 (Patent Document 1) describes a technique relating to a semiconductor device in which a plurality of semiconductor memory devices and a semiconductor data processing device that controls the plurality of semiconductor memory devices are mounted on a mounting board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2006-237385 A Summary of the Invention [Problem to be solved by the invention]

[0004] The present inventor considered arranging a plurality of signal wirings evenly so that crosstalk is even. Meanwhile, in recent years, there is also a demand for reducing the cost of electronic devices. Therefore, the present inventor considered reducing the number of wiring layers of the wiring board used. As a result, it is necessary to secure an area (space) for arranging other wirings provided in other wiring layers in the wiring layer in which the plurality of signal wirings are provided. As a countermeasure, the present inventor considered further reducing the interval (pitch) between adjacent wirings. However, according to the present inventor's study, when a plurality of (three or more) signal wirings are arranged evenly, it was found that a signal propagating through a certain signal wiring is easily influenced not by the signal wiring located one next to the signal wiring, but by the signal wiring located two or more adjacent to the signal wiring. In other words, there is a risk that timing fluctuation due to signal interference will become large. This leads to a decrease in the performance of the electronic device, so it is desirable to take measures against this.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, an electronic device includes a wiring board, a first semiconductor device for storage arranged on the wiring board, and a second semiconductor device arranged on the wiring board and controlling the first semiconductor device. The wiring board has a first fixed potential wiring and a second fixed potential wiring, and a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring in a plan view. The plurality of signal wirings include a first signal wiring adjacent to the first fixed potential wiring, a second signal wiring adjacent to the first signal wiring, and a third signal wiring adjacent to the second signal wiring. A first interval between the first signal wiring and the second signal wiring is smaller than a second interval between the second signal wiring and the third signal wiring. Effect of the Invention

[0007] According to one embodiment, the performance of an electronic device may be improved. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view illustrating an electronic device according to a first embodiment. [Diagram 2] 1 is a cross-sectional view of a main part of an electronic device according to a first embodiment. [Diagram 3] 2 is a partially enlarged plan view of a wiring region of a wiring board used in the electronic device of the first embodiment. FIG. [Figure 4] 2 is a partially enlarged plan view of a wiring region of a wiring board used in the electronic device of the first embodiment. FIG. [Diagram 5] 2 is a partially enlarged plan view of a wiring region of a wiring board used in the electronic device of the first embodiment. FIG. [Figure 6] 2 is a partially enlarged plan view of a wiring region of a wiring board used in the electronic device of the first embodiment. FIG. [Figure 7]FIG. 2 is a plan view of a main part of a wiring board according to a first studied example. [Figure 8] FIG. 13 is a plan view of a main part of a wiring board according to a second studied example. [Figure 9] FIG. 1 is an explanatory diagram for explaining timing fluctuations caused by crosstalk. [Figure 10] 11 is a graph showing an example of a timing margin when a write operation of a memory semiconductor device is performed by a control semiconductor device. [Figure 11] 11 is a graph showing an example of a timing margin when a control semiconductor device performs a read operation on a memory semiconductor device. [Figure 12] 11 is a partially enlarged plan view of a wiring region of a wiring board used in an electronic device according to a second embodiment. FIG. [Figure 13] 11 is a partially enlarged plan view of a wiring region of a wiring board used in an electronic device according to a second embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. In addition, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, except when specifically specified or when it is clearly limited to a specific number in principle, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, except when specifically specified or when it is clearly considered to be essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the components, etc. are mentioned, it includes those that are substantially similar to or similar to the shape, etc., except when specifically specified or when it is clearly considered not to be essential in principle. This also applies to the above numerical values ​​and ranges.

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0011] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views in order to make the drawings easier to understand, and hatching may be added even in plan views in order to make the drawings easier to understand.

[0012] (Embodiment 1) <Overall configuration of electronic device> FIG. 1 is a plan view that diagrammatically shows an electronic device DS according to the present embodiment.

[0013] 1, the electronic device DS of this embodiment includes a wiring board (mounting board) PB, a semiconductor device (semiconductor memory device) MD for memory (storage) mounted on the wiring board PB, and a semiconductor device (semiconductor control device) CD for control mounted on the wiring board PB. Other electronic components (not shown) can also be mounted on the wiring board PB.

[0014] The semiconductor device MD is a semiconductor device including a memory chip (a semiconductor chip for memory). In this embodiment, a semiconductor package in which a memory chip is packaged is applied as the semiconductor device MD. As another embodiment, a memory chip can also be applied as the semiconductor device MD.

[0015] In this embodiment, a case where two semiconductor devices MD are mounted on a wiring board PB is described. One of the two semiconductor devices MD mounted on the wiring board PB is hereinafter referred to as a semiconductor device MD1, and the other is hereinafter referred to as a semiconductor device MD2. The semiconductor devices MD1 and MD2 can be semiconductor devices of the same type (same configuration).

[0016] The semiconductor device CD is a semiconductor device that controls the semiconductor devices MD1 and MD2. In this embodiment, the semiconductor device CD is a control chip (a semiconductor chip for control) that controls the semiconductor devices MD1 and MD2. That is, in this embodiment, an unpackaged control chip (i.e., the control chip itself) is used as the semiconductor device CD. As the control chip, for example, a SoC (System On a Chip) can be used. As another form, a semiconductor package in which a control chip is packaged can also be applied as the semiconductor device CD.

[0017] The wiring board PB has a plurality of wirings electrically connecting the control semiconductor device CD and the memory semiconductor device MD1, a plurality of wirings electrically connecting the control semiconductor device CD and the memory semiconductor device MD2, and a plurality of power supply wirings PW1, PW2, PW3, and PW4.

[0018] The wiring region RG1 shown in FIG. 1 is an area in which a plurality of wirings are arranged to electrically connect the control semiconductor device CD and the memory semiconductor device MD1. A plurality (many) of signal wirings and ground wirings are arranged in the wiring region RG1. The wiring region RG2 shown in FIG. 1 is an area in which a plurality of wirings are arranged to electrically connect the control semiconductor device CD and the memory semiconductor device MD2. A plurality (many) of signal wirings and ground wirings are arranged in the wiring region RG2. In the wiring board PB, the wiring region RG1 is arranged between the semiconductor device CD and the semiconductor device MD1, and the wiring region RG2 is arranged between the semiconductor device CD and the semiconductor device MD2.

[0019] The power supply wirings PW1, PW2, PW3, and PW4 are wirings to which a power supply potential is supplied. In the wiring board PB, the power supply wirings PW1 and PW2 extend between the semiconductor device CD and the semiconductor device MD1, sandwiching the wiring area RG1. That is, in the wiring board PB, the wiring area RG1 is disposed between the power supply wirings PW1 and PW2.

[0020] In the wiring board PB, the power supply wiring PW3 and the power supply wiring PW4 extend between the semiconductor device CD and the semiconductor device MD2 so as to sandwich the wiring region RG2. That is, in the wiring board PB, the wiring region RG2 is disposed between the power supply wiring PW3 and the power supply wiring PW4.

[0021] The control semiconductor device CD is electrically connected to each of the power supply wirings PW1, PW2, PW3, and PW4. The memory semiconductor device MD1 is electrically connected to each of the power supply wirings PW1 and PW2. The memory semiconductor device MD2 is electrically connected to each of the power supply wirings PW3 and PW4. This allows a power supply potential to be supplied to the semiconductor device CD from each of the power supply wirings PW1, PW2, PW3, and PW4. A power supply potential can be supplied to the semiconductor device MD1 from each of the power supply wirings PW1 and PW2. A power supply potential can be supplied to the semiconductor device MD2 from each of the power supply wirings PW3 and PW4.

[0022] In the electronic device DS, the semiconductor device CD, which is a semiconductor chip, and multiple semiconductor devices MD1 and MD2, which include semiconductor chips (not shown), are mounted on a wiring board PB, so that the electronic device DS includes a semiconductor chip. For this reason, the electronic device DS can also be considered as a semiconductor device.

[0023] Fig. 2 is a cross-sectional view of a main part of an electronic device DS. Fig. 2 shows a cross section passing through the wiring region RG1 or the wiring region RG2 shown in Fig. 1. When Fig. 2 shows a cross section passing through the wiring region RG1, the signal wiring SG shown in Fig. 2 is the signal wiring SG arranged in the wiring region RG1. When Fig. 2 shows a cross section passing through the wiring region RG2, the signal wiring SG shown in Fig. 2 is the signal wiring SG arranged in the wiring region RG2.

[0024] 3, 4, 5 and 6 are partially enlarged views showing a part of the wiring region RG1 or the wiring region RG2 shown in FIG. 1, respectively.

[0025] Although the details will be described later, the technical idea of ​​this embodiment is to arrange three or more signal wirings SG between the ground wiring G1 and the ground wiring G2, and to arrange these three or more signal wirings SG by repeating small wiring intervals and larger wiring intervals alternately. Figures 3, 4, 5, and 6 follow this technical idea, but the number of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 differs from one another in Figures 3, 4, 5, and 6.

[0026] FIG. 3 shows two ground wirings GR and three signal wirings SG arranged between the two ground wirings GR in a plan view. FIG. 4 shows two ground wirings GR and four signal wirings SG arranged between the two ground wirings GR in a plan view. FIG. 5 shows two ground wirings GR and five signal wirings SG arranged between the two ground wirings GR in a plan view. FIG. 6 shows two ground wirings GR and six signal wirings SG arranged between the two ground wirings GR in a plan view. Many signal wirings SG and ground wirings GR are arranged in each of the wiring regions RG1 and RG2 in FIG. 1, and each of FIG. 3, FIG. 4, FIG. 5, and FIG. 6 shows some of the many signal wirings SG and ground wirings GR arranged in the wiring region RG1 or the wiring region RG2.

[0027] The semiconductor device CD has a plurality of terminals (electrodes) TE1 (see FIG. 2). The semiconductor device MD has a plurality of terminals (electrodes) TE2 (see FIG. 2).

[0028] When each of Figures 3, 4, 5, and 6 is an enlarged view of a part of the wiring region RG1, one end of each signal wiring SG shown in Figures 3, 4, 5, and 6 is electrically connected to one of the multiple terminals TE1 of the semiconductor device CD, and the other end of each signal wiring SG shown in Figures 3, 4, 5, and 6 is electrically connected to one of the multiple terminals TE2 of the semiconductor device MD1. In this case, each signal wiring SG shown in Figures 3, 4, 5, and 6 electrically connects the semiconductor device CD and the semiconductor device MD1, and functions as a signal wiring that transmits a signal between the semiconductor device CD and the semiconductor device MD1.

[0029] When each of Figures 3, 4, 5, and 6 is an enlarged view of a part of the wiring region RG2, one end of each signal wiring SG shown in Figures 3, 4, 5, and 6 is electrically connected to one of the multiple terminals TE1 of the semiconductor device CD, and the other end of each signal wiring SG shown in Figures 3, 4, 5, and 6 is electrically connected to one of the multiple terminals TE2 of the semiconductor device MD2. In this case, each signal wiring SG shown in Figures 3, 4, 5, and 6 electrically connects the semiconductor device CD and the semiconductor device MD2, and functions as a signal wiring that transmits a signal between the semiconductor device CD and the semiconductor device MD2.

[0030] A signal can be transmitted from the semiconductor device CD to the semiconductor device MD1, or from the semiconductor device MD1 to the semiconductor device CD, through a plurality of signal wirings SG provided in the wiring region RG1. A signal can be transmitted from the semiconductor device CD to the semiconductor device MD2, or from the semiconductor device MD2 to the semiconductor device CD, through a plurality of signal wirings SG provided in the wiring region RG2. Each of the signal wirings SG shown in Figures 3, 4, 5, and 6 is a single-ended signal wiring.

[0031] When the wiring board PB has multiple wiring layers, the ground wiring GR and the signal wiring SG shown in each of Figures 3, 4, 5, and 6 are formed in any one of the multiple wiring layers of the wiring board PB.

[0032] Here, in each of Fig. 3, Fig. 4, Fig. 5 and Fig. 6, one of the two ground wirings GR is hereinafter referred to as a ground wiring G1, and the other of the two ground wirings GR is hereinafter referred to as a ground wiring G2. The ground wirings G1 and G2 are spaced apart from each other in a plan view. In Fig. 3, the three signal wirings SG arranged between the ground wirings G1 and G2 are referred to as a signal wiring S1, a signal wiring S2 and a signal wiring S3 in the direction from the ground wiring G1 to the ground wiring G2. In Fig. 4, the four signal wirings SG arranged between the ground wirings G1 and G2 are referred to as a signal wiring S1, a signal wiring S2, a signal wiring S3 and a signal wiring S4 in the direction from the ground wiring G1 to the ground wiring G2. In Fig. 5, five signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are referred to as signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, and signal wiring S5 in the direction from the ground wiring G1 to the ground wiring G2. In Fig. 6, six signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are referred to as signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, signal wiring S5, and signal wiring S6 in the direction from the ground wiring G1 to the ground wiring G2.

[0033] In the case of Fig. 3, the ground wiring G1, the signal wiring S1, the signal wiring S2, the signal wiring S3, and the ground wiring G2 are formed in the same layer (same wiring layer) in the wiring board PB, and run parallel to each other in this order in a planar view. In the case of Fig. 4, the ground wiring G1, the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, and the ground wiring G2 are formed in the same layer (same wiring layer) in the wiring board PB, and run parallel to each other in this order in a planar view. In the case of Fig. 5, the ground wiring G1, the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, the signal wiring S5, and the ground wiring G2 are formed in the same layer (same wiring layer) in the wiring board PB, and run parallel to each other in this order in a planar view. In the case of Figure 6, the ground wiring G1, signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, signal wiring S5, signal wiring S6, and ground wiring G2 are formed in the same layer (same wiring layer) on the wiring board PB, and run parallel to each other in this order in a planar view.

[0034] 3, 4, 5, and 6, the ground wiring G1 and the signal wiring S1 are adjacent to each other, the signal wiring S1 and the signal wiring S2 are adjacent to each other, and the signal wiring S2 and the signal wiring S3 are adjacent to each other. In each of Fig. 3, 4, 5, and 6, the signal wiring S1 is disposed between the ground wiring G1 and the signal wiring S2, and the signal wiring S2 is disposed between the signal wiring S1 and the signal wiring S3.

[0035] In each of Figures 4, 5, and 6, the signal wiring S3 and the signal wiring S4 are adjacent to each other, and the signal wiring S3 is arranged between the signal wiring S2 and the signal wiring S4. In each of Figures 5 and 6, the signal wiring S4 and the signal wiring S5 are adjacent to each other, and the signal wiring S4 is arranged between the signal wiring S3 and the signal wiring S5. In Figure 6, the signal wiring S5 and the signal wiring S6 are adjacent to each other, and the signal wiring S5 is arranged between the signal wiring S4 and the signal wiring S6.

[0036] In Fig. 3, the signal line S3 and the ground line G2 are adjacent to each other, and the signal line S3 is disposed between the signal line S2 and the ground line G2. In Fig. 4, the signal line S4 and the ground line G2 are adjacent to each other, and the signal line S4 is disposed between the signal line S3 and the ground line G2. In Fig. 5, the signal line S5 and the ground line G2 are adjacent to each other, and the signal line S5 is disposed between the signal line S4 and the ground line G2. In Fig. 6, the signal line S6 and the ground line G2 are adjacent to each other, and the signal line S6 is disposed between the signal line S5 and the ground line G2.

[0037] It should be noted that two wires being adjacent to each other means that no other wire is disposed between the two wires.

[0038] The ground wiring GR is a wiring to which a ground potential (reference potential) is supplied. The ground wiring G1 and the ground wiring G2 have the effect of electromagnetically shielding a plurality of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 from wirings outside the ground wirings G1 and G2. In each of Figures 3, 4, 5, and 6, no ground wiring is arranged between the plurality of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2.

[0039] Next, the intervals between the signal lines SG in each of FIGS. 3, 4, 5 and 6 will be described.

[0040] Here, the interval (distance) between the signal wiring S1 and the signal wiring S2 is referred to as interval D1. The interval (distance) between the signal wiring S2 and the signal wiring S3 is referred to as interval D2. The interval (distance) between the signal wiring S3 and the signal wiring S4 is referred to as interval D3. The interval (distance) between the signal wiring S4 and the signal wiring S5 is referred to as interval D4. The interval (distance) between the signal wiring S5 and the signal wiring S6 is referred to as interval D5.

[0041] In each of FIGS. 3, 4, 5, and 6, the multiple signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are not arranged at equal intervals.

[0042] Specifically, in the case of FIG. 3, the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (that is, D2>D1).

[0043] 4, the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and the distance D3 between the signal wiring S3 and the signal wiring S4 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (i.e., D2>D1 and D2>D3). Note that it is preferable that the distance D1 between the signal wiring S1 and the signal wiring S2 and the distance D3 between the signal wiring S3 and the signal wiring S4 are the same (i.e., D1=D3).

[0044] In the case of FIG. 5, the interval D1 between the signal wiring S1 and the signal wiring S2 is smaller than the interval D2 between the signal wiring S2 and the signal wiring S3, and is smaller than the interval D4 between the signal wiring S4 and the signal wiring S5 (i.e., D2>D1 and D4>D1). The interval D3 between the signal wiring S3 and the signal wiring S4 is smaller than the interval D2 between the signal wiring S2 and the signal wiring S3, and is smaller than the interval D4 between the signal wiring S4 and the signal wiring S5 (i.e., D2>D3 and D4>D3). Note that it is preferable that the interval D1 between the signal wiring S1 and the signal wiring S2 and the interval D3 between the signal wiring S3 and the signal wiring S4 are the same (i.e., D1=D3). It is preferable that the interval D2 between the signal wiring S2 and the signal wiring S3 and the interval D4 between the signal wiring S4 and the signal wiring S5 are the same (i.e., D2=D4).

[0045] In the case of FIG. 6, the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., D2>D1 and D4>D1). The distance D3 between the signal wiring S3 and the signal wiring S4 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., D2>D3 and D4>D3). The distance D5 between the signal wiring S5 and the signal wiring S6 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., D2>D5 and D4>D5). It is preferable that the distance D1 between the signal wiring S1 and the signal wiring S2, the distance D3 between the signal wiring S3 and the signal wiring S4, and the distance D5 between the signal wiring S5 and the signal wiring S6 are the same (i.e., D1=D3=D5). It is preferable that the distance D2 between the signal wiring S2 and the signal wiring S3, and the distance D4 between the signal wiring S4 and the signal wiring S5 are the same (i.e., D2=D4).

[0046] By setting such wiring intervals for the multiple signal wirings SG arranged between the ground wiring G1 and the ground wiring G2, it is possible to reduce the area required for arranging these wirings and to reduce timing fluctuations (fluctuations in signal timing) caused by signal interference in each of the multiple signal wirings SG. The reason for this will be explained in detail later.

[0047] The ground wirings G1, G2 arranged according to the technical idea of ​​this embodiment and a plurality of (three or more) signal wirings SG between the ground wirings G1, G2 are present at one or more locations in one or both of the wiring regions RG1, RG2 shown in Fig. 1. The number of signal wirings SG between the ground wirings G1, G2 is three in Fig. 3, four in Fig. 4, five in Fig. 5, and six in Fig. 6, but it may be seven or more.

[0048] In this embodiment, the case where two memory semiconductor devices MD (MD1, MD2) and a semiconductor device CD that controls the two memory semiconductor devices MD are arranged on the wiring board PB has been described, but the number of memory semiconductor devices MD arranged on the wiring board PB is not limited to two. For example, it is also possible that the semiconductor device MD2 is not mounted on the wiring board PB, and one memory semiconductor device MD (MD1) and a semiconductor device CD that controls the memory semiconductor device MD are arranged on the wiring board PB. Alternatively, it is also possible that three or more memory semiconductor devices MD and a semiconductor device CD that controls the three or more memory semiconductor devices MD are arranged on the wiring board PB.

[0049] <Background to the review> FIG. 7 is a plan view of a main part of a wiring board of a first study example studied by the present inventors, and corresponds to FIGS. 3, 4, 5, and 6 of this embodiment.

[0050] 7, the signal wirings SG and the ground wirings GR are arranged alternately, so that each signal wiring SG is less susceptible to crosstalk from other signal wirings SG.

[0051] However, in the first example of FIG. 7, since the signal wirings SG and the ground wirings GR are arranged alternately, when the number of required signal wirings SG increases, the number of required ground wirings GR also increases accordingly. Therefore, the area of ​​the region (corresponding to the above wiring regions RG1 and RG2) required for arranging the signal wirings in the wiring board increases. This leads to an increase in the planar dimensions (planar area) of the semiconductor device to which the signal wirings are connected, and further leads to an increase in the planar dimensions of the wiring board.

[0052] FIG. 8 is a plan view of a main part of a wiring board of a second study example studied by the present inventors, and corresponds to FIGS. 3, 4, 5, and 6 of this embodiment.

[0053] In the case of the second study example of FIG. 8, a plurality of (here, six) signal wirings S11, S12, S13, S14, S15, and S16 are arranged at equal intervals between two ground wirings G11 and G12. That is, in the case of the second study example of FIG. 8, the interval D11 between the signal wirings S11 and S12, the interval D12 between the signal wirings S12 and S13, the interval D13 between the signal wirings S13 and S14, the interval D14 between the signal wirings S14 and S15, and the interval D15 between the signal wirings S15 and S16 are the same. That is, D11=D12=D13=D14=D15 holds. No ground wiring is arranged between the signal wirings S11, S12, S13, S14, S15, and S16.

[0054] 8, the signal wirings S11, S12, S13, S14, S15, and S16 are arranged between two ground wirings G11 and G12, and no ground wirings are arranged between the signal wirings S11, S12, S13, S14, S15, and S16, so that even if the number of required signal wirings SG increases, the number of required ground wirings GR can be reduced. Therefore, the area of ​​the region (corresponding to the above wiring regions RG1 and RG2) required for arranging the signal wirings on the wiring board can be reduced.

[0055] Furthermore, in the case of the second study example of Fig. 8, the signal wirings S11, S12, S13, S14, S15, and S16 are arranged at equal intervals, which makes it easier to suppress crosstalk occurring between adjacent signal wirings in the signal wirings S11, S12, S13, S14, S15, and S16. This is because the magnitude of crosstalk occurring between adjacent signal wirings depends on the interval between the adjacent signal wirings, and the smaller the interval between adjacent signal wirings, the larger the crosstalk occurring between adjacent signal wirings. If the interval between the ground wiring G11 and the ground wiring G12 is not changed, the minimum adjacent interval in the signal wirings S11, S12, S13, S14, S15, and S16 can be maximized when the intervals D11, D12, D13, D14, and D15 are the same. As a result, the magnitude of crosstalk occurring between adjacent signal wirings among the signal wirings S11, S12, S13, S14, S15, and S16 can be made uniform, and crosstalk can be prevented from increasing in a specific signal wiring.

[0056] However, according to the study by the inventors of the present invention, in the second study example of Fig. 8, it was found that while it is easy to suppress the influence of crosstalk from the signal wirings S11, S12, S13, S14, S15, and S16 arranged at equal intervals, there is a high risk of timing fluctuation (fluctuation in signal timing) occurring due to the influence of crosstalk from the signal wirings two or more adjacent to each other. This will be explained below.

[0057] The wiring arrangement of the second study example in FIG. 8 described above is considered to be a preferable wiring arrangement when all the signal wirings S11, S12, S13, S14, S15, and S16 operate asynchronously and randomly. However, in reality, the signals propagating through the signal wirings are synchronous signals synchronized with the clock. In addition, it is more important to suppress the timing fluctuations caused by crosstalk in the signal wirings than to suppress the magnitude of the crosstalk itself. In other words, if the timing fluctuations caused by crosstalk can be suppressed, there is no need to suppress the magnitude of the crosstalk itself.

[0058] Therefore, the present inventors have investigated minimizing the timing fluctuation caused by crosstalk with respect to synchronous signals, rather than minimizing the crosstalk itself.

[0059] Fig. 9 is an explanatory diagram for explaining timing fluctuations caused by crosstalk. In Fig. 9, a victim signal is indicated by a solid line, and an aggressor signal is indicated by a dashed line. In Fig. 9, symbol CC denotes an input / output circuit of a control semiconductor device, and symbol MC denotes an input / output circuit of a DRAM (memory semiconductor device).

[0060] When an aggressor signal (dashed line) makes a 0 / 1 transition relative to a victim signal (solid line), a certain percentage of the aggressor signal is added to or subtracted from the victim signal as crosstalk at the timing of the 0 / 1 transition, causing the victim signal voltage to fluctuate. At this time, if the voltage is fixed, the victim signal fluctuates in the time direction by B1 / B2, inversely proportional to the slope B2 of the victim signal. This is the timing fluctuation caused by crosstalk. Here, B1 above is the victim signal voltage fluctuation caused by crosstalk.

[0061] Since the victim signal undergoes 0 / 1 transitions, the slope of the victim signal is necessarily maximum at the 0 / 1 transition point of the victim signal, and decreases as the victim signal moves away from the 0 / 1 transition point of the victim signal. Therefore, the timing fluctuation per crosstalk voltage is minimum when the timing of the 0 / 1 transition of the victim signal and the timing of the 0 / 1 transition of the aggressor signal match. In other words, the smaller the skew between the victim signal and the aggressor signal, the smaller the timing fluctuation per crosstalk voltage.

[0062] In other words, when the timing of crosstalk from the aggressor signal coincides with the timing of the 0 / 1 transition of the victim signal, the timing fluctuation (fluctuation in the time direction) of the victim signal caused by the crosstalk is small. And the greater the difference between the timing of crosstalk from the aggressor signal and the timing of the 0 / 1 transition of the victim signal, the greater the timing fluctuation (fluctuation in the time direction) of the victim signal caused by the crosstalk. The timing of crosstalk from the aggressor signal coincides with the timing of the 0 / 1 transition of the aggressor signal. Therefore, when the skew between the victim signal and the aggressor signal is zero, the timing fluctuation (fluctuation in the time direction) of the victim signal caused by the crosstalk is small, but the greater the skew between the victim signal and the aggressor signal, the greater the timing fluctuation (fluctuation in the time direction) of the victim signal caused by the crosstalk. Therefore, it can be seen that the timing fluctuation per the same crosstalk voltage is small between signals with small skew.

[0063] Therefore, it is important to consider which signal wiring on the wiring board will transmit signals with small skew. In a wiring board, there is a high possibility that the skew of signals transmitted between adjacent signal wirings is small. The reason is as follows.

[0064] A plurality of terminals of the control semiconductor device and a plurality of terminals of the memory semiconductor device are electrically connected to each other via a plurality of signal wirings, and signals are transmitted between the control semiconductor device and the memory semiconductor device through the plurality of signal wirings. When considering the arrangement of a plurality of bus-type signal wirings, the order of the signal wirings is not determined randomly. Adjacent signal wirings are likely to be connected to adjacent terminals in the control semiconductor device and to adjacent terminals in the memory semiconductor device. In addition, adjacent signal wirings are likely to have similar characteristic impedances. Therefore, the skew of signals transmitted between adjacent signal wirings is likely to be small. On the other hand, the skew of signals transmitted between signal wirings sandwiching one or more other signal wirings between them is likely to be large.

[0065] For example, in the second study example of Fig. 8, attention is focused on the signal wiring S11. There is a high possibility that the skew between the signal transmitted through the signal wiring S11 and the signal transmitted through the signal wiring S12 is small. In comparison, there is a high possibility that the skew between the signal transmitted through the signal wiring S11 and the signal transmitted through the signal wiring S13 is large, the skew between the signal transmitted through the signal wiring S11 and the signal transmitted through the signal wiring S14 is even larger, and the skew between the signal transmitted through the signal wiring S11 and the signal transmitted through the signal wiring S15 is even larger.

[0066] In the second study example of FIG. 8, crosstalk from the signal wirings S12, S13, S14, S15, and S16 may cause timing fluctuations in the signal transmitted through the signal wiring S11. As described above, there is a high possibility that the skew of the signals transmitted between adjacent signal wirings is small, so that timing fluctuations are unlikely to occur in the signal transmitted through the signal wiring S11 due to crosstalk from the signal wiring S12. However, in the case of the second study example of FIG. 8, there is a concern that timing fluctuations may occur in the signal transmitted through the signal wiring S11 due to crosstalk from the signal wirings S13, S14, S15, and S16. On the other hand, in the second study example of FIG. 8, if we focus on the signal wiring S12, timing fluctuations are unlikely to occur in the signal transmitted through the signal wiring S12 due to crosstalk from the signal wirings S11 and S13. However, there is a concern that timing fluctuations may occur in the signal transmitted through the signal wiring S12 due to crosstalk from the signal wirings S14, S15, and S16. The same can be considered for the timing fluctuations of the signals transmitted through the other signal wirings S13, S14, S15, and S16.

[0067] Crosstalk, which causes timing fluctuations in signals transmitted through signal wiring, leads to a decrease in the performance of electronic devices and therefore must be suppressed.

[0068] <Main features and effects> The electronic device DS of this embodiment includes a wiring board PB, a semiconductor device MD for storage disposed on the wiring board PB, and a semiconductor device CD disposed on the wiring board PB and controlling the semiconductor device MD. The wiring board PB has ground wirings G1 and G2 which are fixed-potential wirings, and a plurality of signal wirings SG disposed between the ground wirings G1 and G2 in a plan view and for transmitting signals between the semiconductor device CD and the semiconductor device MD. The plurality of signal wirings SG disposed between the ground wirings G1 and G2 include a signal wiring S1 adjacent to the ground wiring G1, a signal wiring S2 adjacent to the signal wiring S1, and a signal wiring S3 adjacent to the signal wiring S2. In a plan view, the signal wiring S1 is disposed between the signal wiring S2 and the ground wiring G1, and the signal wiring S2 is disposed between the signal wiring S3 and the signal wiring S1.

[0069] One of the main features of this embodiment is that the interval D1 between the signal wiring S1 and the signal wiring S2 is smaller than the interval D2 between the signal wiring S2 and the signal wiring S3 (D1 < D2) (see FIGS. 3, 4, 5, and 6).

[0070] Assume a case where the signal wiring S1, the signal wiring S2, and the signal wiring S3 are arranged at equal intervals, which is different from this embodiment. In this case, as described in relation to the second consideration example in FIG. 8 above, it is easy to suppress crosstalk between the signal wiring S1 and the signal wiring S2 and crosstalk between the signal wiring S2 and the signal wiring S3, but there is a concern that timing fluctuations may occur in the signals transmitted through the signal wirings S1 and S3 due to crosstalk between the signal wiring S1 and the signal wiring S3.

[0071] In contrast, in the present embodiment, the distance D1 between the signal wiring S1 and the signal wiring S2 is made smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (i.e., D1 < D2). By making the distance D1 between the signal wiring S1 and the signal wiring S2 smaller, the electromagnetic coupling between the signal wiring S1 and the signal wiring S2 becomes stronger, and the pair of the signal wiring S1 and the signal wiring S2 is less likely to receive crosstalk from other signal wirings SG (S3). Therefore, it is possible to suppress the occurrence of timing variations in the signals transmitted through the signal wirings S1, S2, and S3 due to the crosstalk between the signal wiring S1 and the signal wiring S3 and the crosstalk between the signal wiring S2 and the signal wiring S3. Note that it is preferable that the signal wiring S1 and the signal wiring S2 have the same length and the same characteristic impedance as each other.

[0072] On the other hand, in the present embodiment, by making the distance D1 between the signal wiring S1 and the signal wiring S2 smaller, the crosstalk itself between the signal wiring S1 and the signal wiring S2 may increase. However, since the signal wiring S1 and the signal wiring S2 are adjacent to each other, the skew between the signal transmitted through the signal wiring S1 and the signal transmitted through the signal wiring S2 is likely to be small. Therefore, the risk of timing variations occurring in the signals transmitted through the signal wirings S1 and S2 due to the crosstalk between the signal wiring S1 and the signal wiring S2 is small.

[0073] Therefore, by making the distance D1 between the signal wiring S1 and the signal wiring S2 smaller (D1 < D2) than the distance D2 between the signal wiring S2 and the signal wiring S3, it is possible to suppress the occurrence of timing variations in the signals transmitted through the signal wirings S1, S2, and S3 due to crosstalk.

[0074] In FIGS. 4, 5, and 6, a plurality of signal wirings SG arranged between ground wirings G1 and G2 further include a signal wiring S4 adjacent to the signal wiring S3. The distance D3 between the signal wiring S3 and the signal wiring S4 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (D3 < D2). The distance D1 between the signal wiring S1 and the signal wiring S2 and the distance D3 between the signal wiring S3 and the signal wiring S4 are preferably the same as each other (D1 = D3).

[0075] By reducing the distance D3 between the signal wiring S3 and the signal wiring S4, the electromagnetic coupling between the signal wiring S3 and the signal wiring S4 becomes stronger, and the pair of the signal wiring S3 and the signal wiring S4 is less likely to receive crosstalk from other signal wirings SG (S1, S2). Therefore, it is possible to suppress the occurrence of timing variations in the signals transmitted through the signal wirings S1, S2, S3, and S4 due to crosstalk between the signal wiring S1 and the signal wiring S3, between the signal wiring S1 and the signal wiring S4, between the signal wiring S2 and the signal wiring S3, and between the signal wiring S2 and the signal wiring S4. Note that the signal wiring S3 and the signal wiring S4 preferably have the same length and the same characteristic impedance as each other.

[0076] On the other hand, by reducing the distance D3 between the signal wiring S3 and the signal wiring S4, the crosstalk between the signal wiring S3 and the signal wiring S4 itself can increase. However, since the signal wiring S3 and the signal wiring S4 are adjacent to each other, the skew between the signal transmitted through the signal wiring S3 and the signal transmitted through the signal wiring S4 is likely to be small. Therefore, the risk of timing variations occurring in the signals transmitted through the signal wirings S3 and S4 due to crosstalk between the signal wiring S3 and the signal wiring S4 is small.

[0077] Therefore, it is possible to suppress the occurrence of timing variations in the signals transmitted through the signal wirings S1, S2, S3, and S4 due to crosstalk.

[0078] In FIGS. 5 and 6, a plurality of signal wirings SG arranged between ground wirings G1 and G2 further includes a signal wiring S5 adjacent to the signal wiring S4. The distance D4 between the signal wiring S4 and the signal wiring S5 is larger than the distance D1 between the signal wiring S1 and the signal wiring S2 (D4 > D1), and is also larger than the distance D3 between the signal wiring S3 and the signal wiring S4 (D4 > D3). It is preferable that the distance D1 and the distance D3 are the same as each other (D1 = D3). It is preferable that the distance D2 and the distance D4 are the same as each other (D2 = D4).

[0079] By increasing the distance D4 between the signal wiring S4 and the signal wiring S5, the pair of the signal wiring S1 and the signal wiring S2 and the pair of the signal wiring S3 and the signal wiring S4 are less likely to receive crosstalk from the signal wiring S5. Therefore, it is possible to suppress the occurrence of timing fluctuations in the signals transmitted through the signal wirings S1, S2, S3, S4, and S5 due to the crosstalk between the signal wiring S1 and the signal wiring S5, the crosstalk between the signal wiring S2 and the signal wiring S5, the crosstalk between the signal wiring S3 and the signal wiring S5, and the crosstalk between the signal wiring S4 and the signal wiring S5.

[0080] Therefore, it is possible to suppress the occurrence of timing fluctuations in the signals transmitted through the signal wirings S1, S2, S3, S4, and S5 due to crosstalk.

[0081] In FIG. 6, in the present embodiment, a plurality of signal wirings SG arranged between ground wirings G1 and G2 further includes a signal wiring S6 adjacent to the signal wiring S5. The distance D5 between the signal wiring S5 and the signal wiring S6 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (D5 < D2), and is also smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (D5 < D4). It is preferable that the distance D1, the distance D3, and the distance D5 are the same as each other (D1 = D3 = D5). It is preferable that the distance D2 and the distance D4 are the same as each other (D2 = D4).

[0082] This strengthens the electromagnetic coupling between the signal wiring S5 and the signal wiring S6, and the pair of the signal wiring S5 and the signal wiring S6 is less susceptible to crosstalk from other signal wirings SG (S1, S2, S3, S4). This makes it possible to suppress timing fluctuations in signals transmitted through the signal wirings S1, S2, S3, S4, S5, and S6 due to crosstalk between the signal wirings S1 and S3, between the signal wirings S1 and S4, between the signal wirings S1 and S5, between the signal wirings S1 and S6, between the signal wirings S2 and S3, between the signal wirings S2 and S4, between the signal wirings S2 and S5, and between the signal wirings S2 and S6. Furthermore, it is possible to suppress timing fluctuations in signals transmitted through the signal wirings S1, S2, S3, S4, S5, and S6 due to crosstalk between the signal wirings S3 and S5, between the signal wirings S3 and S6, between the signal wirings S4 and S5, and between the signal wirings S4 and S6. It is preferable that the signal wiring S5 and the signal wiring S6 have the same length and the same characteristic impedance.

[0083] On the other hand, by reducing the distance D5 between the signal wiring S5 and the signal wiring S6, the crosstalk between the signal wiring S5 and the signal wiring S6 itself may become large. However, since the signal wiring S5 and the signal wiring S6 are adjacent to each other, the skew between the signal transmitted through the signal wiring S5 and the signal transmitted through the signal wiring S6 is likely to be small. Therefore, there is a small risk that the crosstalk between the signal wiring S5 and the signal wiring S6 will cause a timing fluctuation in the signals transmitted through the signal wirings S5 and S6.

[0084] Therefore, it is possible to suppress timing fluctuations caused by crosstalk in the signals transmitted through the signal wirings S1, S2, S3, S4, S5, and S6.

[0085] In this manner, in the present embodiment, it is possible to suppress timing fluctuations in signals transmitted through signal wiring caused by crosstalk, thereby improving the performance of electronic devices.

[0086] In this embodiment, a plurality of signal wirings SG are arranged between the ground wiring G1 and the ground wiring G2, and no ground wirings are arranged between the plurality of signal wirings SG. This makes it possible to suppress the number of required ground wirings GR even if the number of required signal wirings SG increases. This makes it possible to suppress the area of ​​the region (corresponding to the above wiring regions RG1 and RG2) required for arranging the signal wirings on the wiring board. This makes it possible to achieve both improved performance and miniaturization of the electronic device.

[0087] Each of the above intervals D1, D3, and D5 is smaller than each of the above intervals D2 and D4. Therefore, the above intervals D1, D3, and D5 can be regarded as small wiring intervals, and the above intervals D2 and D4 can be regarded as large wiring intervals. In this embodiment, a plurality of signal wirings SG are arranged between the ground wiring G1 and the ground wiring G2, with small wiring intervals and large wiring intervals being alternately repeated. Therefore, as a modification of FIG. 6, when a signal wiring S7 (not shown) is further arranged between the signal wiring S6 and the ground wiring G2, the interval between the signal wiring S7 and the signal wiring S6 may be set to a large wiring interval similar to the above intervals D2 and D4. When a signal wiring S8 (not shown) is further arranged between the signal wiring S7 and the ground wiring G2, the interval between the signal wiring S8 and the signal wiring S7 may be set to a small wiring interval similar to the above intervals D1, D3, and D5. The same can be considered when further signal wirings are added.

[0088] The signal wiring SG to which the technical concept of the present embodiment is applied is a single-ended signal wiring, but is preferably a single-ended data signal wiring. The data signal transmitted through the data signal wiring has a higher frequency than the command / address signal and the clock signal.

[0089] In this embodiment, a plurality of signal wirings SG are arranged between two fixed potential wirings to shield the plurality of signal wirings SG, and ground wirings G1 and G2 are used as the two fixed potential wirings. The ground wirings G1 and G2 are fixed potential wirings to which a ground potential is supplied, and the potential of each of the ground wirings G1 and G2 is fixed to the ground potential. As a modified example, a fixed potential wiring to which a fixed potential (power supply potential) other than the ground potential is supplied can be used instead of the ground wirings G1 and G2. That is, a plurality of signal wirings SG can be arranged between two fixed potential wirings to which a fixed potential other than the ground potential is supplied, and the interval between the plurality of signal wirings SG can be set as described above. In this case, the fixed potentials supplied to the two fixed potential wirings are the same.

[0090] Fig. 10 is a graph showing an example of a timing margin when a write operation is performed to a memory semiconductor device by a control semiconductor device. Fig. 11 is a graph showing an example of a timing margin when a read operation is performed from a memory semiconductor device by a control semiconductor device. The timing margin is one of the indices for evaluating the magnitude of timing fluctuation occurring in a signal transmitted through a signal wiring. The larger the timing margin, the smaller the timing fluctuation occurring in a signal transmitted through the signal wiring.

[0091] In each of Figures 10 and 11, the case where the wiring arrangement of this embodiment as shown in Figures 3, 4, 5 and 6 is applied is shown by solid lines, and the case where the wiring arrangement as shown in the second example of Figure 8 is applied is shown by dotted lines.

[0092] 10 and 11, the solid line graph (the present embodiment) has a larger timing margin than the dotted line graph (the second study example). This also shows that, compared to the case where a plurality of signal wirings are arranged at equal intervals between the ground wirings G11 and G12 as in the second study example of FIG. 8, the timing fluctuation occurring in the signal transmitted through the signal wirings can be suppressed by arranging a plurality of signal wirings SG between the ground wirings G1 and G2 with small wiring intervals and large wiring intervals alternately repeated as in the present embodiment.

[0093] (Embodiment 2) In the above-mentioned first embodiment, a method for setting the wiring intervals of a plurality of single-ended signal wirings SG arranged between the ground wirings G1 and G2 has been described in the case where the signal wirings SG are of the single-ended type.

[0094] In the second embodiment, a case will be described in which the signal wirings SG arranged between the ground wirings G1 and G2 are differential signal wirings, not single-ended type. In the case of differential signal wirings, the differential signal pair is regarded as one signal, and the signal wirings are arranged according to the rules of the first embodiment.

[0095] 12 and 13 are partially enlarged views showing a part of the wiring region RG1 or the wiring region RG2 shown in FIG. 1, respectively.

[0096] The technical idea of ​​the above-mentioned first embodiment is to place three or more single-ended signal wirings between the ground wiring G1 and the ground wiring G2, and to arrange these three or more single-ended signal wirings in such a way that small wiring spacing and larger wiring spacing are alternately repeated.

[0097] On the other hand, the technical idea of ​​the second embodiment is to arrange three or more differential pairs between the ground wiring G1 and the ground wiring G2, and arrange the three or more differential pairs by alternating small intervals and larger intervals. This is because a pair of two signal wirings (differential pair) functions as a signal wiring equivalent to one single-ended signal wiring. The small interval and the large interval are the intervals between two adjacent differential pairs. FIG. 12 and FIG. 13 follow this technical idea, but the number of differential pairs arranged between the ground wiring G1 and the ground wiring G2 is different between FIG. 12 and FIG. 13. In the case of FIG. 12, the number of differential pairs arranged between the ground wiring G1 and the ground wiring G2 is three, and in the case of FIG. 13, the number of differential pairs arranged between the ground wiring G1 and the ground wiring G2 is four.

[0098] Fig. 12 shows two ground wirings GR and six signal wirings SG arranged between the two ground wirings GR in a plan view. Fig. 13 shows two ground wirings GR and eight signal wirings SG arranged between the two ground wirings GR in a plan view. As in the above-mentioned first embodiment, also in the second embodiment, each signal wiring SG electrically connects the semiconductor device CD and the semiconductor device MD and functions as a signal wiring for transmitting a signal between the semiconductor device CD and the semiconductor device MD.

[0099] However, in the second embodiment, each signal wiring SG shown in FIGS. 12 and 13 is not a single-ended signal wiring but a differential signal wiring, and two adjacent signal wirings SG form a differential pair.

[0100] In the second embodiment, one of the two ground wirings GR is referred to as the ground wiring G1, and the other of the two ground wirings GR is referred to as the ground wiring G2 in each of Fig. 12 and Fig. 13. In Fig. 12, the six signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are referred to as the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, the signal wiring S5, and the signal wiring S6 in the direction from the ground wiring G1 to the ground wiring G2. In Fig. 13, the eight signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are referred to as the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, the signal wiring S5, the signal wiring S6, the signal wiring S7, and the signal wiring S8 in the direction from the ground wiring G1 to the ground wiring G2.

[0101] In the case of Fig. 12, the ground wiring G1, the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, the signal wiring S5, the signal wiring S6, and the ground wiring G2 are formed in the same layer (same wiring layer) on the wiring board PB, and run side by side in this order in a plan view. In the case of Fig. 13, the ground wiring G1, the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, the signal wiring S5, the signal wiring S6, the signal wiring S7, the signal wiring S8, and the ground wiring G2 are formed in the same layer (same wiring layer) on the wiring board PB, and run side by side in this order in a plan view.

[0102] 12 and 13, the ground wiring G1 and the signal wiring S1 are adjacent to each other, the signal wiring S1 and the signal wiring S2 are adjacent to each other, the signal wiring S2 and the signal wiring S3 are adjacent to each other, the signal wiring S3 and the signal wiring S4 are adjacent to each other, the signal wiring S4 and the signal wiring S5 are adjacent to each other, and the signal wiring S5 and the signal wiring S6 are adjacent to each other. In each of Fig. 12 and 13, the signal wiring S1 is arranged between the ground wiring G1 and the signal wiring S2, the signal wiring S2 is arranged between the signal wirings S1 and S3, the signal wiring S3 is arranged between the signal wirings S2 and S4, the signal wiring S4 is arranged between the signal wirings S3 and S5, and the signal wiring S5 is arranged between the signal wirings S4 and S6.

[0103] In FIG. 12, the signal wiring S6 and the ground wiring G2 are adjacent to each other, and the signal wiring S6 is disposed between the signal wiring S5 and the ground wiring G2.

[0104] 13, the signal wiring S6 and the signal wiring S7 are adjacent to each other, the signal wiring S7 and the signal wiring S8 are adjacent to each other, and the signal wiring S8 and the ground wiring G2 are adjacent to each other. In FIG. 13, the signal wiring S6 is disposed between the signal wirings S5 and S7, the signal wiring S7 is disposed between the signal wirings S6 and S8, and the signal wiring S8 is disposed between the signal wiring S7 and the ground wiring G2.

[0105] In each of FIGS. 12 and 13, no ground wiring is arranged between the multiple signal wirings SG arranged between the ground wiring G1 and the ground wiring G2.

[0106] In the case of FIG. 12, a differential pair P1 is formed by signal wiring S1 and signal wiring S2, a differential pair P2 is formed by signal wiring S3 and signal wiring S4, and a differential pair P3 is formed by signal wiring S5 and signal wiring S6. In the case of FIG. 13, a differential pair P1 is formed by signal wiring S1 and signal wiring S2, a differential pair P2 is formed by signal wiring S3 and signal wiring S4, a differential pair P3 is formed by signal wiring S5 and signal wiring S6, and a differential pair P4 is formed by signal wiring S7 and signal wiring S8.

[0107] In each of FIGS. 12 and 13, differential pair P1 is adjacent to ground wiring G1, differential pair P2 is adjacent to differential pair P1, and differential pair P3 is adjacent to differential pair P2. In each of FIGS. 12 and 13, differential pair P1 is disposed between differential pair P2 and ground wiring G1, and differential pair P2 is disposed between differential pair P3 and differential pair P1. In FIG. 12, ground wiring G2 is adjacent to differential pair P3, and differential pair P3 is disposed between ground wiring G2 and differential pair P2.

[0108] In FIG. 13, differential pair P4 is adjacent to differential pair P3, and ground wiring G2 is adjacent to differential pair P4. In FIG. 13, differential pair P3 is disposed between differential pair P4 and differential pair P2, and differential pair P4 is disposed between ground wiring G2 and differential pair P3.

[0109] In each of FIGS. 12 and 13, the interval D6 between differential pair P1 and differential pair P2 is smaller than the interval D7 between differential pair P2 and differential pair P3 (i.e., D6 < D7). In FIG. 13, the interval D8 between differential pair P3 and differential pair P4 is smaller than the interval D7 between differential pair P2 and differential pair P3 (i.e., D8 < D7). It is preferable that the interval D8 between differential pair P3 and differential pair P4 is the same as the interval D6 between differential pair P1 and differential pair P2 (i.e., D6 = D8).

[0110] Note that the distance D6 between the differential pair P1 and the differential pair P2 is the distance between the signal wiring S2 that constitutes the differential pair P1 and the signal wiring S3 that constitutes the differential pair P2. The distance D7 between the differential pair P2 and the differential pair P3 is the distance between the signal wiring S4 that constitutes the differential pair P2 and the signal wiring S5 that constitutes the differential pair P3. The distance D8 between the differential pair P3 and the differential pair P4 is the distance between the signal wiring S6 that constitutes the differential pair P3 and the signal wiring S7 that constitutes the differential pair P4.

[0111] When applying the technical idea of the above Embodiment 1 to this Embodiment 2, the differential pair P1 in this Embodiment 2 corresponds to the single-ended signal wiring S1 in the above Embodiment 1. The differential pair P2 in this Embodiment 2 corresponds to the single-ended signal wiring S2 in the above Embodiment 1. The differential pair P3 in this Embodiment 2 corresponds to the single-ended signal wiring S3 in the above Embodiment 1. The differential pair P4 in this Embodiment 2 corresponds to the single-ended signal wiring S4 in the above Embodiment 1.

[0112] Therefore, in the above Embodiment 1, making the distance D1 between the signal wiring S1 and the signal wiring S2 smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (D1 < D2) corresponds to making the distance D6 between the differential pair P1 and the differential pair P2 smaller than the distance D7 between the differential pair P2 and the differential pair P3 (D6 < D7) in this Embodiment 2. In the above Embodiment 1, making the distance D3 between the signal wiring S3 and the signal wiring S4 smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (D3 < D2) corresponds to making the distance D8 between the differential pair P3 and the differential pair P4 smaller than the distance D7 between the differential pair P2 and the differential pair P3 (D8 < D7) in this Embodiment 2.

[0113] Unlike the second embodiment, assume a case where the differential pairs P1, P2, and P3 are arranged at equal intervals. In this case, it is easy to suppress the crosstalk between the differential pair P1 and the differential pair P2 and the crosstalk between the differential pair P2 and the differential pair P3. However, due to the crosstalk between the differential pair P1 and the differential pair P3, there is a concern that timing variations may occur in the signals transmitted through the differential pairs P1 and P3.

[0114] On the other hand, in the second embodiment, the distance D6 between the differential pair P1 and the differential pair P2 is made smaller than the distance D7 between the differential pair P2 and the differential pair P3 (D6 < D7) (see FIGS. 12 and 13). By making the distance D6 between the differential pair P1 and the differential pair P2 smaller, the electromagnetic coupling between the differential pair P1 and the differential pair P2 becomes stronger, and the pair of the differential pair P1 and the differential pair P2 is less likely to receive crosstalk from other differential pairs (P3). Therefore, it is possible to suppress the occurrence of timing variations in the signals transmitted through the differential pairs P1, P2, and P3 due to the crosstalk between the differential pair P1 and the differential pair P3 and the crosstalk between the differential pair P2 and the differential pair P3.

[0115] On the other hand, in the second embodiment, since the distance D6 between the differential pair P1 and the differential pair P2 is made smaller, the crosstalk itself between the differential pair P1 and the differential pair P2 may increase. However, since the differential pair P1 and the differential pair P2 are adjacent to each other, the skew between the signal transmitted through the differential pair P1 and the signal transmitted through the differential pair P2 is likely to be small. Therefore, the risk of timing variations occurring in the signals transmitted through the differential pairs P1 and P2 due to the crosstalk between the differential pair P1 and the differential pair P2 is small.

[0116] Therefore, by making the distance D6 between the differential pair P1 and the differential pair P2 smaller than the distance D7 between the differential pair P2 and the differential pair P3 (D6 < D7), it is possible to suppress the occurrence of timing variations in the signals transmitted through the differential pairs P1, P2, and P3 due to crosstalk.

[0117] In FIG. 13, a differential pair P4 adjacent to the differential pair P3 is arranged between the ground wirings G1 and G2. The distance D8 between the differential pair P3 and the differential pair P4 is made smaller than the distance D7 between the differential pair P2 and the differential pair P3 (D8 < D7). Preferably, the distance D8 between the differential pair P3 and the differential pair P4 is the same as the distance D6 between the differential pair P1 and the differential pair P2 (D6 = D8).

[0118] By making the distance D8 between the differential pair P3 and the differential pair P4 smaller, the electromagnetic coupling between the differential pair P3 and the differential pair P4 becomes stronger, and the pair of the differential pair P3 and the differential pair P4 is less likely to receive crosstalk from other differential pairs (P1, P2). Therefore, it is possible to suppress the occurrence of timing variations in the signals transmitted through the differential pairs P1, P2, P3, and P4 due to the crosstalk between the differential pair P1 and the differential pair P3, the crosstalk between the differential pair P1 and the differential pair P4, the crosstalk between the differential pair P2 and the differential pair P3, and the crosstalk between the differential pair P2 and the differential pair P4.

[0119] On the other hand, by making the distance D8 between the differential pair P3 and the differential pair P4 smaller, the crosstalk between the differential pair P3 and the differential pair P4 itself may increase. However, since the differential pair P3 and the differential pair P4 are adjacent to each other, the skew between the signal transmitted through the differential pair P3 and the signal transmitted through the differential pair P4 is likely to be small. Therefore, the risk of timing variations occurring in the signals transmitted through the differential pairs P3 and P4 due to the crosstalk between the differential pair P3 and the differential pair P4 is small.

[0120] Therefore, it is possible to suppress the occurrence of timing variations in the signals transmitted through the differential pairs P1, P2, P3, and P4 due to crosstalk.

[0121] As described above, in the second embodiment, since it is possible to suppress the occurrence of timing variations in the signals transmitted through the signal wiring due to crosstalk, the performance of the electronic device can be improved.

[0122] As in the above-mentioned first embodiment, in the second embodiment, a plurality of signal wirings SG are arranged between the ground wiring G1 and the ground wiring G2, and no ground wirings are arranged between the plurality of signal wirings SG. This makes it possible to suppress the number of required ground wirings GR even if the number of required signal wirings SG increases. This makes it possible to suppress the area of ​​the region (corresponding to the above-mentioned wiring regions RG1 and RG2) required for arranging the signal wirings on the wiring board. This makes it possible to achieve both improved performance of the electronic device and miniaturization of the electronic device.

[0123] Each of the intervals D6 and D8 is smaller than the interval D7. Therefore, the intervals D6 and D8 can be regarded as small intervals, and the interval D7 can be regarded as a large interval. In the second embodiment, a plurality of differential pairs are arranged between the ground wiring G1 and the ground wiring G2, with small intervals and large intervals alternately repeated. Each of the small intervals and the large intervals is the interval between two adjacent differential pairs.

[0124] 13, when a further differential pair P5 (not shown) is arranged between the differential pair P4 and the ground wiring G2, the interval between the differential pair P5 and the differential pair P4 may be set to a large interval similar to the above-mentioned interval D7. When a further differential pair P6 (not shown) is arranged between the differential pair P5 and the ground wiring G2, the interval between the differential pair P6 and the differential pair P5 may be set to a small interval similar to the above-mentioned intervals D6 and D8. The same can be considered when further differential pairs are added.

[0125] The signal wiring SG to which the technical idea of ​​the second embodiment is applied is a differential signal wiring, and preferably a differential data signal wiring.

[0126] As in the above-described first embodiment, in the second embodiment, fixed potential wiring to which a fixed potential (power supply potential) other than the ground potential can be supplied can be used instead of the ground wirings G1 and G2.

[0127] The invention made by the inventor of the present invention has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0128] CC input / output circuit CD Semiconductor Device D1,D2,D3,D4,D5,D6,D7,D8,D11,D12,D13,D14,D15 Interval DS electronic equipment G1, G2, G11, G12, GR Ground wiring MC input / output circuit MD, MD1, MD2 Semiconductor device PB wiring board PW1, PW2, PW3, PW4 power wiring RG1,RG2 wiring area S1,S2,S3,S4,S5,S6,S7,S8,S11,S12,S13,S14,S15,S16,SG Signal wiring TE1, TE2 terminals

Claims

1. An electronic device comprising: Wiring board; a first semiconductor device for storage disposed on the wiring substrate; a second semiconductor device disposed on the wiring substrate and configured to control the first semiconductor device; Where: The wiring board includes: a first fixed potential wiring and a second fixed potential wiring; a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring in a plan view, for transmitting signals between the first semiconductor device and the second semiconductor device; having The plurality of signal wirings include a first signal wiring adjacent to the first fixed potential wiring; a second signal wiring adjacent to the first signal wiring; a third signal wiring adjacent to the second signal wiring; Including, the first signal wiring is disposed between the second signal wiring and the first fixed potential wiring; the second signal wiring is disposed between the third signal wiring and the first signal wiring; A first distance between the first signal wiring and the second signal wiring is smaller than a second distance between the second signal wiring and the third signal wiring.

2. 2. The electronic device of claim 1, The third signal wiring and the second fixed potential wiring are adjacent to each other.

3. 2. The electronic device of claim 1, the plurality of signal wirings further includes a fourth signal wiring adjacent to the third signal wiring, the third signal wiring is disposed between the fourth signal wiring and the second signal wiring; a third spacing between the third signal wiring and the fourth signal wiring is smaller than the second spacing.

4. 4. The electronic device according to claim 3, The first spacing and the third spacing are the same as each other.

5. 5. The electronic device according to claim 4, The fourth signal wiring and the second fixed potential wiring are adjacent to each other.

6. 4. The electronic device according to claim 3, the plurality of signal wirings further includes a fifth signal wiring adjacent to the fourth signal wiring, the fourth signal wiring is disposed between the fifth signal wiring and the third signal wiring; a fourth spacing between the fourth signal wiring and the fifth signal wiring is greater than the first spacing and is greater than the third spacing.

7. 7. The electronic device according to claim 6, the first interval and the third interval are equal to each other, The second spacing and the fourth spacing are the same as each other.

8. 8. The electronic device according to claim 7, The fifth signal wiring and the second fixed potential wiring are adjacent to each other.

9. 7. The electronic device according to claim 6, the plurality of signal wirings further includes a sixth signal wiring adjacent to the fifth signal wiring, the fifth signal wiring is disposed between the sixth signal wiring and the fourth signal wiring, a fifth spacing between the fifth signal wiring and the sixth signal wiring is smaller than the second spacing and smaller than the fourth spacing.

10. 10. The electronic device of claim 9, the first interval, the third interval, and the fifth interval are the same as each other, The second spacing and the fourth spacing are the same as each other.

11. 11. The electronic device of claim 10, The sixth signal wiring and the second fixed potential wiring are adjacent to each other.

12. 2. The electronic device of claim 1, An electronic device, wherein each of the plurality of signal wirings is single-ended.

13. An electronic device comprising: Wiring board; a first semiconductor device for storage disposed on the wiring substrate; a second semiconductor device disposed on the wiring substrate and configured to control the first semiconductor device; Where: The wiring board includes: a first fixed potential wiring and a second fixed potential wiring; a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring in a plan view, for transmitting signals between the first semiconductor device and the second semiconductor device; having The plurality of signal wirings include a first differential pair adjacent to the first fixed potential wiring and including a first signal wiring and a second signal wiring; a second differential pair adjacent to the first differential pair and including a third signal wiring and a fourth signal wiring; a third differential pair adjacent to the second differential pair and including fifth and sixth signal wirings; Including, the first differential pair is disposed between the second differential pair and the first fixed potential wiring; the second differential pair is disposed between the third differential pair and the first differential pair; A first spacing between the first differential pair and the second differential pair is smaller than a second spacing between the second differential pair and the third differential pair.

14. 14. The electronic device of claim 13, The third differential pair and the second fixed potential wiring are adjacent to each other.

15. 14. The electronic device of claim 13, the plurality of signal wirings further includes a fourth differential pair adjacent to the third differential pair and including seventh and eighth signal wirings; the third differential pair is disposed between the fourth differential pair and the second differential pair; A third spacing between the third differential pair and the fourth differential pair is smaller than the second spacing.

16. 16. The electronic device of claim 15, The first spacing and the third spacing are the same as each other.

17. 17. The electronic device of claim 16, The fourth differential pair and the second fixed potential wiring are adjacent to each other.

Images