Semiconductor device

Abstract

To suppress a semiconductor device from being defective.SOLUTION: A semiconductor device comprises: a pellet 60 which has a first surface where a plurality of pads 618 are provided; a first joint material provided on the first surface: and a first metal plate 20 which includes a second surface provided on the first joint material, is electrically connected to the plurality of pads 618, and opposed to the first surface, and a plurality of projection parts 211 provided on the second surface. The plurality of projection parts 211 face pads 618A at one end and pads 618B on the other end, in a direction where the plurality of pads is arrayed, respectively among the plurality of pads 618.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art A semiconductor device having a structure in which the upper and lower surfaces of a pellet are connected to conductors via a bonding material is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5807221 Specification [Patent Document 2] JP 2010-87395 A [Patent Document 3] JP 2013-89849 A [Patent Document 4] JP 2013-16603 A [Patent Document 5] Patent No. 6314433 specification Summary of the Invention [Problem to be solved by the invention]

[0004] Defects in semiconductor devices are suppressed. [Means for solving the problem]

[0005] The semiconductor device of the embodiment comprises a pellet having a first surface on which a plurality of pads are provided, a first bonding material provided on the first surface, a second surface provided on the first bonding material, electrically connected to the plurality of pads, and facing the first surface, and a plurality of protrusions provided on the second surface, wherein the plurality of protrusions respectively face one end pad and the other end pad of the plurality of pads in the direction in which the plurality of pads are arranged. [Brief description of the drawings]

[0006] [Figure 1] 1 is a bird's-eye view showing an example of an appearance of a semiconductor device according to an embodiment; [Diagram 2] FIG. 2 is an exploded view showing an example of an internal structure of the semiconductor device according to the embodiment. [Diagram 3] FIG. 2 is a plan view showing an example of a planar layout of the semiconductor device according to the embodiment; [Figure 4] 1 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device according to an embodiment; [Diagram 5] FIG. 2 is a cross-sectional view showing an example of an element structure of the semiconductor device according to the embodiment. [Figure 6] FIG. 2 is a plan view showing an example of a structure of a metal plate of the semiconductor device according to the embodiment. [Figure 7] FIG. 2 is a cross-sectional view showing an example of a structure of a metal plate of the semiconductor device according to the embodiment. [Figure 8] 5A to 5C are cross-sectional process views showing a process of a manufacturing method of a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] A semiconductor device according to an embodiment will be described with reference to Figures 1 to 8. In the following description, components having substantially the same functions and configurations are given the same reference numerals. When elements having similar configurations are to be particularly distinguished from each other, different letters or numbers may be added to the end of the same reference numerals. The dimensions and ratios of the drawings are not necessarily the same as those in reality.

[0008] (Embodiment) (a) Structure example An example of the structure of a semiconductor device according to an embodiment will be described with reference to FIGS.

[0009] FIG. 1 is a bird's-eye view showing an example of the appearance of a semiconductor device according to an embodiment.

[0010] The semiconductor device 1 of the embodiment in Fig. 1 is a power device. The semiconductor device 1 has, for example, a thin rectangular parallelepiped shape. Hereinafter, the thickness direction of the semiconductor device 1 is referred to as the up-down direction. In addition, when a component of the semiconductor device 1 has two surfaces that face each other in the up-down direction, these two surfaces are referred to as the bottom surface and the top surface, respectively.

[0011] The semiconductor device 1 includes a metal plate 10, two metal plates 20, two lead portions 30, and a sealing material 40. Each of the metal plate 10, the two metal plates 20, and the two lead portions 30 has a portion exposed outside the sealing material 40 as a terminal for electrical connection between the semiconductor device 1 and another device.

[0012] The metal plate 10 and the two metal plates 20 are provided so as to be exposed on the lower and upper surfaces of the sealing material 40. For example, the height of the exposed surface of the metal plate 10 is aligned with the height of the lower surface of the sealing material 40. For example, the height of the exposed surface of each metal plate 20 is aligned with the height of the upper surface of the sealing material 40. When viewed from a direction perpendicular to the upper surface (and lower surface) of the semiconductor device 1, the exposed surface of each metal plate 20 is included within the area of ​​the exposed surface of the metal plate 10.

[0013] In the following, the metal plate 10 on the lower surface side of the semiconductor device 1 will be referred to as a lower metal plate 10, and each of the metal plates 20 on the upper surface side of the semiconductor device 1 will be referred to as an upper metal plate 20.

[0014] The two lead portions 30 are provided so as to be exposed to the side surfaces of the sealing material 40. For example, the two lead portions 30 protrude from the side surfaces of the sealing material 40.

[0015] The sealing material 40 is an insulating member that physically and electrically protects the internal structure of the semiconductor device 1 from the outside. The sealing material 40 forms the outer shape of the semiconductor device 1.

[0016] 2 to 4 are diagrams for explaining the internal structure of the semiconductor device 1 of the present embodiment. FIG. 2 is an exploded view showing an example of the internal structure of the semiconductor device 1 of the embodiment. In FIG. 2, the internal structure of the semiconductor device 1 exploded in the thickness direction is typically shown. FIG. 3 is a plan view showing an example of a planar layout inside the semiconductor device 1 of the embodiment. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3, showing an example of a cross-sectional structure inside the semiconductor device 1 of the embodiment. In FIGS. 2, 3, and 4, the sealing material 40 is omitted.

[0017] As shown in Figures 2 to 4, the semiconductor device 1 has an internal structure that, in addition to a lower metal plate 10, two upper metal plates 20, and two lead portions 30, further includes two bonding materials 50, two pellets 60, two bonding materials 70, and two wires 80.

[0018] The lower metal plate 10 is a plate-shaped conductor. One surface of the lower metal plate 10 faces one surface (lower surface) of the pellet 60. The surface of the lower metal plate 10 facing the pellet 60 is called the upper surface of the lower metal plate 10. The other surface of the lower metal plate 10 parallel to the upper surface of the lower metal plate 10 is called the lower surface of the lower metal plate 10. The lower surface of the lower metal plate 10 corresponds to the surface of the lower metal plate 10 exposed from the sealing material 40. The upper surface and the lower surface of the lower metal plate 10 are each flat over the entire surface. A protrusion protruding toward the pellet 60 may be provided on the upper surface of the lower metal plate 10. In this case, a recess may be provided at a position on the lower surface of the lower electrode plate 10 corresponding to the protrusion provided on the upper surface of the lower electrode plate 10.

[0019] The upper metal plate 20 is a plate-shaped conductor. The upper metal plate 20 has a surface S1 facing the other surface (upper surface) of the pellet 60. The surface S1 of the upper metal plate 20 facing the pellet 60 is called the lower surface S1 of the upper metal plate 20. The other surface of the upper metal plate 20 parallel to the lower surface S1 of the upper metal plate 20 is called the upper surface of the upper metal plate 20. The upper surface of the upper metal plate 20 corresponds to the surface of the upper metal plate 20 exposed from the sealing material 40. In this embodiment, the upper metal plate 20 includes a plurality of protrusions 211 provided on the lower surface S1 side of the upper metal plate 20. The upper surface of the upper metal plate 20 may be flat over the entire surface, for example. Alternatively, a recess may be provided in a part of the upper surface of the upper metal plate 20, for example, at a position of the upper surface corresponding to the protrusions 211 provided on the lower surface S1. The structure of the upper metal plate 20 will be described in detail later.

[0020] Each of the lower metal plate 10 and the upper metal plate 20 is, for example, a copper plate. The copper plate of the lower metal plate 10 and the copper plate of the upper metal plate 20 have a thickness of about 1.5 mm.

[0021] The two bonding materials 50 are provided on the upper surface of the lower metal plate 10, spaced apart from each other. A corresponding pellet 60 is provided on the upper surface of the bonding materials 50. Each bonding material 50 is provided between the lower metal plate 10 and the corresponding pellet 60. The bonding material 50 bonds the lower metal plate 10 and the pellet 60. The bonding material 50 contacts the flat lower surface of the pellet 60. The bonding material 50 is an electrical conductor. The bonding material 50 is, for example, a plate-shaped solder layer (for example, a solder sheet).

[0022] A pellet (semiconductor chip, semiconductor substrate, semiconductor element) 60 is provided between the lower metal plate 10 and the upper metal plate 20. For example, the area of ​​the lower surface of the pellet 60 is smaller than the area of ​​the upper surface of the lower metal plate 10. For example, the area of ​​the upper surface of the pellet 60 is larger than the area of ​​the lower surface of the upper metal plate 20.

[0023] The pellet 60 is a chip including a semiconductor element such as a power semiconductor device. The power semiconductor device of the pellet 60 is, for example, a device using silicon (Si) or silicon carbide (SiC). As an example of a power semiconductor device, when silicon is used in the pellet 60, the pellet 60 is an insulated gate bipolar transistor (IGBT). As another example of a power semiconductor device, when silicon carbide is used in the pellet 60, the pellet 60 is a metal-oxide-silicon field effect transistor (MOSFET). The pellet 60 includes an element section 600. The element section 600 includes a plurality of components of a semiconductor element. In addition, a termination structure (not shown) is provided in a region between the element section 600 and an end of the pellet 60 in a direction parallel to the upper surface of the pellet 60.

[0024] A plurality of pads 618, 619 are provided on the upper surface (surface of the upper metal plate 20) of the pellet 60. Each of the pads 618, 619 is electrically connected to a component on the semiconductor substrate included in the element portion 600 and / or a component within the semiconductor substrate.

[0025] An insulating layer 629 is provided between adjacent pads 618. The insulating layer 629 is, for example, a polyimide layer. For example, the upper surfaces of the pads 618, 619 are exposed through openings provided in the insulating layer 629. The position of the upper surface of the insulating layer 629 in the third direction is higher than the position of the upper surfaces of the pads 618, 619 in the third direction. Therefore, a step 699 is generated between the upper surfaces of the pads 618, 619 and the upper surface of the insulating layer 629.

[0026] 5 is a cross-sectional view showing an example of an element structure of an IGBT as the semiconductor device 1 of this embodiment. FIG 5 shows a cross section taken along line VV in FIG 3.

[0027] 5, when the semiconductor element formed in the pellet 60 is an IGBT, a semiconductor layer 610, a semiconductor layer 611, a plurality of semiconductor layers 612, a plurality of semiconductor layers 613, a plurality of gate electrodes 614, a plurality of gate insulating layers 615, a gate wiring 616, a semiconductor layer 617, a plurality of pads (conductive patterns) 618 and 619, an electrode 650, and an insulating layer 620 are provided in the pellet 60 as components of the element section 600. A termination structure (not shown) is provided at an end of the pellet 60 in a direction parallel to the upper surface of the pellet 60.

[0028] The semiconductor layer 610 is provided on the lower surface side of the pellet 60. The semiconductor layer 610 is a diffusion layer (impurity semiconductor region) formed in the semiconductor substrate of the pellet 60. The semiconductor layer 610 is electrically connected to the lower metal plate 10 via a bonding material (solder layer) 50. The lower surface of the semiconductor layer 610 is generally flat. The semiconductor layer 610 is a semiconductor layer that serves as a collector of the IGBT.

[0029] For example, an electrode 650 is provided between the semiconductor layer 610 and the solder layer 50. The electrode 650 improves the wettability of the solder and the bonding between the solder layer 50 and the pellet 60. The electrode 650 functions as a barrier film for suppressing the penetration (diffusion) of the solder material into the pellet 60. For example, the electrode 650 is a laminated film including a titanium film (Ti film), a nickel film (Ni film), and a silver film (Ag film).

[0030] The semiconductor layer 611 is provided in a semiconductor region defined by an element isolation layer in a semiconductor substrate. The semiconductor layer 611 is, for example, a semiconductor layer serving as a drift layer of an IGBT.

[0031] A plurality of semiconductor layers 612 are provided in the semiconductor layer 611. Each of the semiconductor layers 612 is a semiconductor layer serving as the base of an IGBT.

[0032] Each of the multiple semiconductor layers 613 is provided in the semiconductor layer 612. Each of the semiconductor layers 613 is a semiconductor layer that serves as an emitter of an IGBT.

[0033] The gate electrode 614 is a trench gate. The gate electrode 614 is provided in the pellet 60 via a gate insulating layer 615. The gate insulating layer 615 is provided between the gate electrode 614 and the semiconductor layers 611, 612, and 613. The gate electrode 614 is sandwiched between the two semiconductor layers 612 and between the two semiconductor layers 613. A side surface of the gate electrode 614 faces the semiconductor layer 612 and the semiconductor layer 613 via the gate insulating layer 615. The gate electrode 614 is a conductive layer serving as the gate electrode 614 of the IGBT.

[0034] The gate wiring 616 is disposed in a region between two pads 618 adjacent to each other in the second direction. The gate wiring 616 is provided on an insulating layer 620. The semiconductor layer 617 is provided in the semiconductor region below the gate wiring 616, with the insulating layer 620 interposed therebetween.

[0035] The conductivity type of the semiconductor layers 610, 611, 612, 613, and 617 is set to N-type or P-type depending on the drive type of the IGBT. Semiconductor layers other than the semiconductor layers 610, 611, 612, 613, and 617 may be provided in the pellet 60 depending on the functions and characteristics required of the IGBT.

[0036] The pads 618 and 619 are provided on the upper surface side of the pellet 60. The pads 618 and 619 are conductors.

[0037] The pads 618 are provided on an insulating layer 620 covering the upper surface of the semiconductor substrate of the pellet 60. Each pad 618 contacts the semiconductor layers 612, 613 through an opening (contact hole) in the insulating layer 620. The pads 618 are electrically connected to the semiconductor layers 612, 613. The pads 618 are pads for electrically connecting the emitters of the IGBTs to the upper metal plate 20. Each pad 618 has, for example, a rectangular pattern. When viewed from the upper surface of the pellet 60, the pads 618 extend in a first direction parallel to the upper surface of the pellet 60. The pads 618 are arranged in a second direction that intersects with the first direction and is parallel to the upper surface of the pellet 60. Hereinafter, the pads 618 are also referred to as emitter pads 618.

[0038] The pads 618 and 619 are laminated films including an aluminum film (Al film), a nickel film (Ni film), and a gold film (Au film). The gold film prevents oxidation of the nickel film on the aluminum film of the pads 618 and 619. The nickel film ensures the bonding between the bonding material (e.g., solder layer) 70 and the pellet 60.

[0039] An insulating layer 629 is provided on the gate wiring 616. The insulating layer 629 overlaps an end of the pad 618. A step 699 is provided between the insulating layer 629 and the pad 618.

[0040] Returning to FIG. 3 and FIG. 4, for example, the multiple emitter pads 618 include emitter pads 618A, 618B, and 618C. The emitter pad 618A is disposed at the most one end side in the arrangement direction (second direction) of the multiple emitter pads 618. The emitter pad 618B is disposed at the most other end side in the arrangement direction of the multiple emitter pads 618. The emitter pad 618B is adjacent to the pad 619 in the extension direction (first direction) of the emitter pad 618. The dimension (length) LB of the emitter pad 618B in the extension direction is smaller than the dimension LA of the emitter pad 618A in the extension direction. The emitter pad 618C is disposed in a region between the emitter pads 618A and 618B. A portion of the emitter pad 618C is adjacent to the pad 619 in the arrangement direction of the emitter pads 618. The dimension of the emitter pad 618C in the extension direction is the same as the dimension LA of the emitter pad 618A in the extension direction.

[0041] A step 699 occurs between the top of the emitter pad 618 and the top of the insulating layer 620. Due to the step 699, a groove is formed above the emitter pad 618.

[0042] One pad 619 is provided on the insulating layer 620. The pad 619 is electrically connected to the gate electrode 614 via a gate wiring (not shown) in the pellet 60 and a contact plug (not shown) in the insulating layer 620. For example, the pad 619 is disposed in one corner region in the area PA in which the pads 618 and 619 are provided. The pad 619 has, for example, a square pattern. Hereinafter, the pad 619 connected to the gate electrode 614 is referred to as a gate pad 619.

[0043] Hereinafter, the area on the upper surface of the pellet 60 where the multiple emitter pads 618 and the gate pads 619 are arranged is referred to as a pad arrangement area PA.

[0044] When the pellet 60 is an IGBT, the lower metal plate 10 is a collector electrode (collector terminal), and the upper metal plate 20 is an emitter electrode (emitter terminal). When the pellet 60 is a MOSFET, for example, the lower metal plate 10 is a drain electrode, and the upper metal plate 20 is a source electrode.

[0045] The two bonding materials 70 are separated from each other. Each of the two bonding materials 70 is provided on an area of ​​the upper surface (pad arrangement area PA) of the pellet 60 including the emitter pad 618 and excluding the gate pad 619. A corresponding upper metal plate 20 is provided on the upper surface of the bonding material 70. Each bonding material 70 is provided between the corresponding upper metal plate 20 and the corresponding pellet 60. The bonding material 70 bonds the upper metal plate 20 and the pellet 60. The bonding material 70 contacts the undulating upper surface of the pellet 60. The bonding material 70 is a conductor. The bonding material 70 is, for example, a plate-shaped solder layer (solder sheet).

[0046] The bonding material 70 is provided on the upper surface of the pellet 60 so as to cover the emitter pads 618. The bonding material 70 contacts the emitter pads 618. As a result, the upper metal plate 20 is electrically connected to the multiple emitter pads 618 via the bonding material 70. The bonding material 70 does not contact the gate pad 619. For example, the bonding material 70 does not extend into the region between the end of the pad arrangement area PA and the end of the pellet 60.

[0047] One end of a wire 80 is provided on the gate pad 619 on the upper surface of the pellet 60. The wire 80 is a bonding wire. The other end of the wire 80 is connected to a corresponding lead portion 30. The lead portion 30 is a gate electrode (gate terminal).

[0048] With the above-described configuration, inside the semiconductor device 1, three terminals used for input and output of the pellet 60 are electrically connected to the collector electrode 10, the emitter electrode 20, and the gate electrode 30, respectively. The bonding materials 50 and 70 are responsible for the electrical connection between the pellet 60 and the metal plates (electrodes) 10 and 20, and also have the function of dissipating heat generated in the pellet 60 in the vertical direction.

[0049] 1 to 5, the case where two pellets 60 are provided in the semiconductor device 1 has been described, but the present invention is not limited to this. The number of pellets 60 provided in the semiconductor device 1 may be one, or three or more.

[0050] In the semiconductor device 1 of this embodiment, the upper metal plate 20 includes a plurality of protrusions 211 provided on the lower surface S1 of the upper metal plate 20.

[0051] As a result, in the semiconductor device 1 of the present embodiment, poor bonding and poor electrical connection between the upper metal plate 20 and the pellet 60 can be prevented.

[0052] <Top metal plate> 6 and 7 are diagrams for explaining a structural example of the upper metal plate 20 of the semiconductor device 1 of this embodiment. FIG. 6 is a plan view showing a structural example of the upper metal plate 20 in the semiconductor device 1 of this embodiment. FIG. 7 is a cross-sectional view showing a structural example of the upper metal plate 20 in the semiconductor device 1 of this embodiment. FIG. 7(a) is a cross-sectional view taken along line VIIa-VIIa in FIG. 6. FIG. 7(b) is a cross-sectional view taken along line VIIb-VIIb in FIG. 6. In FIG. 7, a part of the structure of the pellet 60 is shown in schematic form to show the positional relationship between the protrusion 211 of the upper metal plate 20 and the pad 618 of the pellet 60.

[0053] As described above, when the semiconductor device 1 is an IGBT, the upper metal plate 20 is an emitter electrode.

[0054] As shown in FIGS. 6 and 7, the upper metal plate 20 includes a plate portion 210 and a plurality of protrusions 211.

[0055] The plate portion 210 is a plate-shaped conductor. The plate portion 210 has two surfaces S1 and S2. The two surfaces S1 and S2 are parallel to each other. The surface S1 is the surface of the upper metal plate 20 that faces the pellet 60. The surface S2 is the surface that is exposed from the sealing material 40. The surface S1 is called the lower surface, and the surface S2 is called the upper surface.

[0056] The lower surface S1 of the upper metal plate 20 has a plurality of protrusions 211. For example, four or more protrusions 211 are provided on the plate portion 210 on the lower surface S1 of the upper metal plate 20. Note that on the lower surface S1 of the upper metal plate 20, the portion of the plate portion 210 other than the protrusions 211 is flat.

[0057] The upper surface S2 of the upper metal plate 20 (plate portion 210) is, for example, flat. However, as described above, in the upper surface S2 of the upper metal plate 20, a recess 299 may be provided at a position corresponding to the protrusion 211.

[0058] When viewed from a direction perpendicular to the lower surface S1, the protrusion 211 is provided in a region 219 near a corner of the plate portion 210. Hereinafter, the region 219 will be referred to as a corner region.

[0059] The protrusion 211 has, for example, a hemispherical or semi-ellipsoidal shape. The protrusion 211 may also have a cubic, rectangular, triangular pyramid, or quadrangular prism shape.

[0060] The multiple protrusions 211 have the same height (dimension in a direction perpendicular to the lower surface S1). For example, each protrusion 211 has a height H1. The height H1 of the protrusion 211 is the dimension in the direction perpendicular to the lower surface S1 from a flat portion of the surface S1 on the side where the protrusion 211 of the plate portion 210 is provided to the top of the protrusion 211 (the position that protrudes most from the surface S1).

[0061] The multiple protrusions 211 are laid out within the lower surface S1 of the upper metal plate 20 so as to vertically overlap the corner positions of the area in which the multiple emitter pads 618 are arranged. The protrusions 211 are provided at positions facing the emitter pads 618 on the outer periphery of the pellet 60 when viewed from a direction perpendicular to the lower surface S1. The protrusions 211 vertically overlap the ends of the emitter pads 618 in the extension direction of the pattern of the emitter pads 618 in the direction perpendicular to the lower surface S1.

[0062] For example, five protrusions 211 (211A, 211B, 211C, 211D, and 211E) are provided on the upper metal plate 20.

[0063] Two of the five protrusions 211 (211A, 211B) are provided at positions vertically overlapping with emitter pad 618A, which is the most end side of the plurality of emitter pads 618 in the direction in which the emitter pads 618 are arranged (second direction).

[0064] The other two protrusions 211 (211C, 211D) are provided at positions vertically overlapping with an emitter pad 618B that is the other end side in the arrangement direction of the emitter pads 618 among the multiple emitter pads 618. The emitter pad 618B on the other end side is adjacent to the gate pad 619 in the extension direction (first direction) of the emitter pads 618.

[0065] One (protrusion 211A, 211C) of the two protrusions 211 overlapping with one emitter pad 618 (618A, 618B) vertically overlaps one end of the emitter pad 618 in the extension direction of the emitter pad 618. The other (protrusion 211B, 211D) of the two protrusions 211 overlapping with one emitter pad 618 (618A, 618B) vertically overlaps the other end of the emitter pad 618 in the extension direction of the emitter pad 618.

[0066] The distance between two protrusions 211 facing one emitter pad 618 is smaller than the dimension (length) in the extension direction of the emitter pad 618. For example, the distance DA between the two protrusions 211A, 211B in the first direction is smaller than the length LA of the emitter pad 618A in the first direction. The distance DA is the dimension between the top of the protrusion 211A and the top of the protrusion 211B. For example, the distance DB between the two protrusions 211C, 211D in the first direction is smaller than the length LB of the emitter pad 618B in the first direction. The distance DB is the dimension between the top of the protrusion 211C and the top of the protrusion 211D.

[0067] The interval between the two protrusions 211 overlapping the different emitter pads 618 is substantially equal to the interval between the two emitter pads 618, 618 provided at one end and the other end of the outer periphery of the pad arrangement area PA. For example, the interval D1 between the protrusions 211A and 211C in the second direction is substantially equal to the interval D2 between the emitter pad 618A at one end side and the emitter pad 618B at the other end side in the second direction. For example, the interval D1 is the dimension between the top of the protrusion 211A and the top of the protrusion 211D. For example, the interval D2 is the dimension between the center line along the first direction of the emitter pad 618A at one end side and the center line along the first direction of the emitter pad 618B at the other end side.

[0068] For example, the distance D1a between the protrusion 211B and the protrusion 211D in the second direction is substantially equal to the distance D1 between the protrusion 211A and the protrusion 211C in the second direction. For example, the distance D3 between the protrusion 211B and the protrusion 211E in the second direction is smaller than the distance D1 between the protrusion 211A and the protrusion 211C in the second direction.

[0069] One of the five protrusions 211, protrusion 211E, is provided at a position vertically overlapping one end of emitter pad 618C adjacent to gate pad 619 in the arrangement direction of pads 618. Protrusion 211E is adjacent to a corner of gate pad 619. For example, protrusion 211 is not provided at a position vertically overlapping the other end of emitter pad 618C. Therefore, the other end of emitter pad 618C does not vertically overlap protrusion 211. However, protrusion 211 may be provided on lower surface S1 of upper metal plate 20 at a position vertically overlapping the other end of emitter pad 618C. Protrusion 211E does not have to be provided.

[0070] Within the area where the corners of the upper metal plate 20 are formed, another protrusion 211 may be provided on the metal plate 20 at a position facing a portion other than the end of the emitter pad 618C that is aligned with another corner portion on the side adjacent to the emitter pad 618 of the gate pad 619.

[0071] A space is formed between the plate portion 210 and the upper surface of the pellet 60 by the protrusion portion 211 having a height H1.

[0072] As described above, the solder layer 70 is provided between the upper metal plate 20 and the pellet 60. For example, the solder layer 70 is interposed between the protrusion 211 and the emitter pad 618, between the plate portion 210 and the emitter pad 618, and between the plate portion 210 and the insulating layer 620. The corner portions of the solder layer 70 vertically overlap the protrusions 211 of the upper metal plate 20 in a direction perpendicular to the upper surface of the solder layer 70 (the upper surface of the pellet 60 or the lower surface S1 of the upper metal plate 20). The protrusions 211 may be in direct contact with the emitter pad 618 without the solder layer 70 being interposed therebetween.

[0073] The protrusions 211 function as starting points for melting the solder when the solder is melted in the manufacturing process of the semiconductor device 1. The protrusions 211 can suppress curling and / or sinking of the solder layer (solder sheet) in the manufacturing process of the semiconductor device 1.

[0074] (b) Manufacturing method A method for manufacturing the semiconductor device 1 of this embodiment will be described with reference to Fig. 8. Fig. 8 is a cross-sectional process diagram showing one process of the method for manufacturing the semiconductor device 1 of this embodiment.

[0075] 8, in the manufacturing process of the semiconductor device 1 of this embodiment, a pellet 60 including a power device is laminated on a lower metal plate 10 via a solder sheet 50A. The solder sheet 50A contacts the flat lower surface of the pellet 60. The solder sheet 50A is a member for forming a solder layer (bonding material) between the lower metal plate 10 and the pellet 60.

[0076] On the upper surface of the pellet 60, a step 699 is generated between the patterns of the emitter pads 618. At the portion of the step 699, an insulating layer (e.g., a polyimide layer) 629 protrudes. On the upper surface of the pellet 60, portions of the pads 618 made of metal and portions of the insulating layer 629 are arranged alternately. A groove is formed in the space surrounded by the insulating layer 629 above the emitter pads 618.

[0077] Solder sheet 70A is laminated on the upper surface of pellet 60. Solder sheet 70A contacts the undulating upper surface of pellet 60. Solder sheet 70A is a member for forming a solder layer (bonding material) between upper metal plate 20 and pellet 60.

[0078] Upper metal plate 20 is laminated on pellet 60 via solder sheet 70A. Protrusions 211 of upper metal plate 20 are disposed above pads 618 on the outer periphery of pellet 60 in a direction perpendicular to the top surface of pellet 60 via solder sheet 70A.

[0079] After lamination of the upper metal plate 20, heat (or ultrasonic waves) 999 is supplied to the laminate including the pellet 60 sandwiched between the metal plates 10 and 20 to melt the solder sheets 50A and 70A. The supply of heat melts the solder sheets 50A and 70A. For example, the heat 999 is supplied to the pellet 60 from the lower metal plate 10 side.

[0080] In the initial stage of heat supply in the soldering process (solder reflow process), the supplied heat propagates from the protrusions 211 of the upper metal plate 20 to the solder sheet 50A. At this time, the solder sheet 70A on the upper surface of the pellet 60 melts from the multiple protrusions 211 provided on the upper metal plate 20. Thus, in this embodiment, melting of the solder sheet 70A starts from the outer periphery side within the pad arrangement area PA. Also, the protrusions 211 of the upper metal plate 20 press the ends of the solder sheet 70A against the emitter pads 618 on the periphery of the pad arrangement area PA.

[0081] Therefore, in this embodiment, curling and / or sinking of the solder on the outer periphery side of the pad arrangement area PA is suppressed. Therefore, the molten solder spreads over the entire upper surface of the pellet 60 without being adversely affected by the steps 699 between the pads 618. The pellet 60 having a plurality of emitter pads on its upper surface is joined to the upper metal plate 20 via the solder layer 70 having a relatively uniform thickness.

[0082] As described above, the upper metal plate (emitter electrode) 20 is joined to the multiple pads 618 of the pellet 60 via the solder layer formed from the solder sheet 70A. In a simultaneous process, the lower metal plate (collector electrode) 10 is also joined to the flat lower surface of the pellet 60 via a solder layer formed by melting the solder sheet 50A.

[0083] After the pellet 60 is bonded to the metal plates 10 and 20, in the pellet 60 sandwiched between the metal plates 10 and 20, the gate pad 619 is connected to the lead portion 30 via the wire 80 by wire bonding.

[0084] After the wire bonding process, the pellet 60 sandwiched between the metal plates 10 and 20 is sealed with the sealing material 40.

[0085] Through the above steps, the semiconductor device 1 of the present embodiment is completed.

[0086] (c) Summary In this embodiment, the upper metal plate 20 is joined to the upper surface of the pellet 60 on which the multiple pads 618 are arranged, by melting the solder (solder sheet).

[0087] In a manufacturing method of a general semiconductor device, when heat is supplied to the pellet from the lower metal plate side during the soldering process between the pellet and the metal plate, the temperature of the center of the pellet is likely to rise. When the solder sheet melts from the center of the pellet, the molten solder in the center of the pellet pulls the solder in the non-molten portion (e.g., the outer peripheral portion of the pellet) toward the center of the pellet. In addition, the step between the pads causes the flow of the molten solder to be hindered and / or the solder to aggregate (sink mark). As a result, the molten solder starting from the center of the pellet may not wet and spread from the center of the pellet to the pad pattern on the outer peripheral portion of the pellet.

[0088] Furthermore, if the solder sheet used to form the solder layer is deformed due to bending or other reasons, the solder sheet may not be pressed sufficiently against the pellet, which may cause solder sink marks on the outer periphery of the pellet.

[0089] For this reason, in a typical semiconductor device, defects may occur in the semiconductor device due to non-uniformity of the solder layer between the pellet and the upper metal plate.

[0090] In the semiconductor device 1 of this embodiment, the upper metal plate 20 stacked above the upper surface of the pellet 60 has a protrusion 211 in a corner region 219 of a surface S1 of the upper metal plate 20 facing the pellet 60. The protrusion 211 of the upper metal plate 20 overlaps with a pad 618 arranged on the periphery of the multiple pads 618 of the pellet 60 in a direction perpendicular to the upper surface of the pellet 60. In this embodiment, the protrusion 211 of the upper metal plate 20 faces the pattern of the pads 618 on the periphery of the pellet 60 at a corner of the upper metal plate 20 and the pad arrangement area PA.

[0091] The protrusions 211 form a space between the upper metal plate 20 and the pellet 60. The solder layer 70 is provided between the upper metal plate 20 and the pellet 60.

[0092] In this embodiment, the solder between the upper metal plate 20 and the pellet 60 melts from the protrusion 211 provided on the upper metal plate 20 as a base point. As a result, the solder melts and flows from the outer periphery toward the center of the area PA in which the pads are provided. The molten solder spreads relatively uniformly on the upper surface having undulations due to the step 699 between the pad 618 and the insulating layer 629 of the pellet 60. Therefore, the semiconductor device 1 of this embodiment can suppress the occurrence of cracks and sink marks in the solder layer 70 due to poor solder wetting.

[0093] As a result, the semiconductor device 1 of the present embodiment can form the solder layer 70 having a relatively uniform thickness and quality between the upper metal plate 20 and the pellet 60. Therefore, the semiconductor device 1 of the present embodiment can suppress defects in the semiconductor device caused by non-uniformity of the solder layer 70.

[0094] For example, in this embodiment, a solder sheet is used to form the solder layer 70. Even if the shape of the solder sheet is deformed, the semiconductor device 1 of this embodiment can press the solder sheet against the pads 618 on the outer periphery of the pellet 60 by the protrusions 211 provided on the upper metal plate 20. Therefore, the semiconductor device 1 of this embodiment can suppress curling and / or sink marks of the solder layer 70 on the pads 618 on the outer periphery in the area PA where the multiple pads 618 are provided.

[0095] As a result, the semiconductor device 1 of this embodiment can reduce poor electrical connection between the upper metal plate 20 and the pellet 60 at the pads 618 (618A, 618B, 618C) on the outer periphery of the area PA in which multiple pads 618 are arranged.

[0096] Stress tends to concentrate in areas where the solder layer is thin, which can lead to defects in the solder layer and / or breakage of the pellet.

[0097] In this embodiment, the relatively uniform formation of the solder layer 70 reduces the number of thin portions of the solder layer 70. This makes it possible for the semiconductor device 1 of this embodiment to suppress the concentration of stress caused by the thin thickness of the solder layer 70. As a result, the semiconductor device 1 of this embodiment can reduce breakage of the pellet 60.

[0098] Due to the above-mentioned effects, the semiconductor device 1 of this embodiment can improve the manufacturing yield.

[0099] As described above, the semiconductor device of this embodiment can suppress defects in the semiconductor device 1.

[0100] (d) Other The semiconductor device 1 of the embodiment is not limited to a power device as long as it is a semiconductor device having a structure in which a pellet (semiconductor chip) is sandwiched between two metal plates. For example, the semiconductor device 1 of the embodiment may be an analog circuit, a logic circuit, a processor, a communication circuit, or a memory device.

[0101] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0102] 1: semiconductor device, 10: lower metal plate, 20: upper metal plate, 30: lead portion, 40: sealing material, 50, 70: bonding material, 60: pellet, 211: protrusion portion, 618: pad.

Claims

1. a pellet having a first surface with a plurality of pads disposed thereon; A first bonding material provided on the first surface; a first metal plate provided on the first bonding material, electrically connected to the pads, and including a second surface facing the first surface, and a plurality of protrusions provided on the second surface; Equipped with the plurality of protrusions are opposed to pads at one end and pads at the other end in a direction in which the plurality of pads are arranged, Semiconductor device.

2. Each of the plurality of protrusions is disposed within a corner region of the first metal plate in the second surface. The semiconductor device according to claim 1 .

3. Each of the plurality of protrusions has a first height. The semiconductor device according to claim 1 .

4. Each of the plurality of pads extends in a first direction parallel to the first surface; the plurality of pads are arranged on an insulating layer covering the pellet along a second direction intersecting the first direction and parallel to the first surface; the plurality of pads include a first pad disposed at one end in the second direction and a second pad disposed at the other end in the second direction; one end of the first pad in the first direction faces a first protruding portion of the plurality of protruding portions, and the other end of the first pad in the first direction faces a second protruding portion of the plurality of protruding portions; one end of the second pad in the first direction faces a third protrusion of the plurality of protrusions, and the other end of the second pad in the first direction faces a fourth protrusion of the plurality of protrusions; The semiconductor device according to claim 1 .

5. the plurality of pads include a third pad provided between the first pad and the second pad, and a fourth pad adjacent to the second pad in the first direction and adjacent to the third pad in the second direction; a portion of the third pad adjacent to the fourth pad faces a fifth protrusion of the plurality of protrusions; The semiconductor device according to claim 4.

6. a distance between the first protrusion and the third protrusion in the second direction is equal to a distance between the first pad and the second pad in the second direction; The semiconductor device according to claim 4.

7. a distance between the first protrusion and the second protrusion in the first direction is smaller than a dimension of the first pad in the first direction; The semiconductor device according to claim 6.

8. The first bonding material is a solder sheet. The semiconductor device according to claim 1 .

9. a second metal plate provided on a third surface side of the pellet opposite to the first surface; a second bonding material between the pellet and the second metal plate; Further comprising: the first metal plate is an emitter electrode of an IGBT (Insulated Gate Bipolar Transistor); The second metal plate is a collector electrode of the IGBT. The semiconductor device according to claim 1 .

10. a second metal plate provided on a third surface side of the pellet opposite to the first surface; a second bonding material between the pellet and the second metal plate; Further comprising: the first metal plate is a source electrode of a metal-oxide-semiconductor field effect transistor (MOSFET); The second metal plate is a drain electrode of the MOSFET. The semiconductor device according to claim 1 .

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