Semiconductor device

Abstract

To reduce on-resistance while ensuring short-circuit resistance in a trench MOSFET having a vertical channel fin structure.SOLUTION: A semiconductor device 1 includes: a plurality of trenches 2 arranged in a second direction, each having a longitudinal direction in a first direction and having a lateral direction in the second direction in plan view; a first source region 3 of a first conductivity type, at least a portion of the first source region being divided by the plurality of trenches 2; and a channel region 5 of a second conductivity type which is in contact with the lower surface of the first source region 3 and is divided by the plurality of trenches 2. The channel region 5 is connected to a body region 9 and a channel current flows in a vertical direction in the channel region 5. The first-direction length of a gate electrode 7 disposed inside the trench 2 is greater than the first-direction length of a JFET region 8. The impurity concentration in the JFET region 8 is higher than the impurity concentration in a drift region 10. The dimensions of the body region 9 and the JFET region 8 in a depth direction from the bottom of the trench 2 are both greater than 0.5 μm.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] As one type of trench-type MOSFET, a trench MOSFET with a vertical channel fin structure has been proposed.

[0003] Fig. 17 is a perspective view showing a typical trench MOSFET having a conventional vertical channel fin structure, in which the gate electrode, gate insulating film, interlayer insulating film, source electrode, and drain electrode are omitted.

[0004] A conventional semiconductor device 1 shown in Fig. 17 has a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plan view, and has a plurality of trenches 2 arranged in the second direction. Note that the trenches 2 shown by dotted lines in the cross section at the front of Fig. 17 show positions that virtually correspond to the trenches 2 in order to explain the positional relationship between other components and the trenches 2.

[0005] The first conductivity type source region 3B includes a region having a fin structure at least partially separated by a plurality of trenches 2. A second conductivity type channel region 5 having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the source region 3B in contact with the source region 3B. A first conductivity type JFET region 8 is formed below the channel region 5, and a second conductivity type body region 9 is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. A first conductivity type drift region 10 is formed below the JFET region 8, and a first conductivity type drain region 11 is formed below the drift region 10.

[0006] 17 has a gate insulating film disposed inside the trench 2 and a gate electrode including a region at least partially disposed inside the trench 2, and a channel current flows vertically (in the depth direction) through the channel region 5. The gate electrodes embedded inside the trench 2 are connected to each other outside the trench 2.

[0007] Incidentally, an example of a patent document related to such technology is Patent Document 1. Although the names of the components and the detailed structure are different, paragraphs 0048 to 0052, FIG. 3, and FIG. 14 to FIG. 18 of Patent Document 1 describe a configuration similar to FIG. 17 described above. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2004-207289 A Summary of the Invention [Problem to be solved by the invention]

[0009] According to the structure of the conventional semiconductor device 1 shown in Fig. 17, the number of channels can be increased by reducing the trench pitch and increasing the channel density, so that the on-resistance can be reduced when viewed as a whole semiconductor chip. However, the conventional semiconductor device 1 shown in Fig. 17 has a problem that, although the on-resistance is low due to the high channel density, the short-circuit resistance is low accordingly.

[0010] Furthermore, in the conventional semiconductor device 1 shown in FIG. 17, the thickness (dimension in the depth direction) of the JFET region 8 is thin, which poses a problem of low short-circuit resistance.

[0011] Furthermore, in the conventional semiconductor device 1 shown in FIG. 17, when the impurity concentration of the JFET region 8 is the same as the impurity concentration of the drift region 10, the impurity concentration of the JFET region 8 is as low as the impurity concentration of the drift region 10, so that there is a problem that the resistance of the JFET region 8 becomes high and the on-resistance cannot be sufficiently reduced.

[0012] An object of the present invention is to provide a semiconductor device that can reduce the on-resistance while ensuring short-circuit resistance in a trench MOSFET with a vertical channel fin structure. [Means for solving the problem]

[0013] In order to achieve the above object, a semiconductor device according to the present invention includes a plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plan view, the plurality of trenches being arranged in the second direction, a first source region of a first conductivity type, at least a portion of which is separated by the plurality of trenches, a channel region of a second conductivity type in contact with a lower surface of the first source region and separated by the plurality of trenches, a gate insulating film disposed inside the trench, a gate electrode including a region at least a portion of which is disposed inside the trench, a JFET region of the first conductivity type disposed below the channel region, a body region of the second conductivity type disposed to a side of the JFET region, and a drift region of a first conductivity type disposed below the trench, and a drain region of the first conductivity type disposed below the drift region and having a higher impurity concentration than the drift region, the channel region is connected to the body region, a channel current flows vertically through the channel region, the length of the gate electrode disposed inside the trench in the first direction is longer than the length of the JFET region in the first direction, the impurity concentration of the JFET region is higher than the impurity concentration of the drift region, and the dimensions of the body region and the JFET region in the depth direction from a bottom of the trench are both greater than 0.5 μm. Effect of the Invention

[0014] According to the present invention, in a trench MOSFET having a vertical channel fin structure, it is possible to reduce the on-resistance while ensuring the short-circuit resistance. [Brief description of the drawings]

[0015] [Figure 1] FIG. 2 is a top perspective view of the semiconductor device according to the first embodiment. [Diagram 2] Cross-sectional view taken along the line X1-X1' of Figure 1. [Diagram 3] Cross-sectional view taken along the line X2-X2' of Figure 1. [Figure 4] Cross-sectional view taken along the line Y1-Y1' in FIG. [Diagram 5] FIG. 11 is a top perspective view of a semiconductor device according to a second embodiment. [Figure 6] 11A to 11C are diagrams illustrating an example of characteristics of a semiconductor device according to Example 2. [Figure 7] FIG. 11 is a top perspective view of a semiconductor device according to a third embodiment. [Figure 8] Cross-sectional view taken along the line X3-X3' in Figure 7. [Figure 9] FIG. 13 is a top perspective view of a semiconductor device according to a fourth embodiment. [Figure 10] Cross-sectional view taken along the line X4-X4' of Figure 9. [Figure 11] Cross-sectional view taken along the line Y2-Y2' of Figure 9. [Figure 12] FIG. 13 is a top perspective view of a semiconductor device according to a fifth embodiment. [Figure 13] X5-X5' sectional view of Figure 12. [Figure 14] FIG. 13 is a top perspective view of a semiconductor device according to a sixth embodiment. [Figure 15] FIG. 13 is a top perspective view of a semiconductor device according to a seventh embodiment. [Figure 16] Cross-sectional view taken along the line X6-X6' of Figure 15 . [Figure 17] FIG. 1 is a perspective view showing a schematic diagram of a conventional trench MOSFET having a vertical channel fin structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted. EXAMPLES

[0017] FIG. 1 is a top perspective view of a semiconductor device of Example 1. FIG. 2 is an X1-X1' cross-sectional view of FIG. 1. FIG. 3 is an X2-X2' cross-sectional view of FIG. 1. FIG. 4 is a Y1-Y1' cross-sectional view of FIG. 1. Note that the gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and barrier metal 16 are omitted from FIG. 1. Also, in FIG. 1, the position where a contact plug 15 is disposed is indicated by a dotted line. Note that these are the same in the subsequent top perspective views, so repeated explanation will be omitted.

[0018] The semiconductor device 1 of this embodiment has a plurality of trenches 2, a first source region 3 of a first conductivity type, a channel region 5 of a second conductivity type, a gate insulating film 6, a gate electrode 7, a JFET region 8 of a first conductivity type, a body region 9 of a second conductivity type, a drift region 10 of a first conductivity type, and a drain region 11 of a first conductivity type.

[0019] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is not limited to this, and the first conductivity type may be p-type and the second conductivity type may be n-type.

[0020] The multiple trenches 2 have a longitudinal direction in a first direction (X1-X1' direction in FIG. 1) when viewed in a plan view, and a lateral direction in a second direction (Y1-Y1' direction in FIG. 1), and are arranged in multiple in the second direction. In addition, a trench group composed of multiple trenches 2 arranged in the second direction is also arranged in multiple in the first direction. Note that the trench 2 shown by the dotted line in the cross-sectional view of FIG. 2 shows a position virtually corresponding to the trench 2 in order to explain the positional relationship between other components and the trench 2.

[0021] The first source region 3 of the first conductivity type includes a region having a fin structure at least partially separated by a plurality of trenches 2. A channel region 5 of the second conductivity type having a fin structure separated by a plurality of trenches 2 is formed on the lower surface of the first source region 3 in contact with the first source region 3. A JFET region 8 of the first conductivity type is formed below the channel region 5, and a body region 9 of the second conductivity type is formed on the side of the JFET region 8. The channel region 5 is connected to the body region 9. Therefore, the width (length in the first direction) of the channel region 5 is the width (length in the first direction) of the trench 2 minus the overlap width between the trench 2 and the body region 9.

[0022] A drift region 10 of the first conductivity type is disposed below the JFET region 8. The drift region 10 is also disposed below the body region 9. In addition, a drain region 11 of the first conductivity type having a higher impurity concentration than the drift region 10 is disposed below the drift region 10.

[0023] A gate insulating film 6 is disposed inside the trench 2. At least a portion of a gate electrode 7 is disposed inside the trench 2. The gate electrodes 7 disposed inside the trench 2 are connected to each other outside the trench 2. The gate electrodes 7 can be formed of, for example, polysilicon.

[0024] In the semiconductor device 1 of this embodiment, a channel current flows vertically (in the depth direction) in the channel region 5 of the fin structure by inputting and controlling a gate drive signal to the gate electrode 7 inside the trench 2. That is, the semiconductor device 1 is a trench MOSFET with a vertical channel fin structure. Therefore, the number of channels can be increased by reducing the trench pitch to increase the channel density, and the on-resistance of the entire semiconductor chip can be reduced.

[0025] In the semiconductor device 1 of this embodiment, as shown in FIG. 3, the width (length in the first direction) WTG of the gate electrode 7 arranged inside the trench 2 is longer than the width (length in the first direction) WJ of the JFET region 8. The width WTG of the gate electrode 7 is the width (length in the first direction) WTR of the trench 2 minus the thickness of the gate insulating film (two portions, one and the other in the first direction). Since WTG>WJ, the ends of the bottom surfaces of the trenches 2 in the first direction and the ends of the bottom surfaces of the gate electrodes 7 in the trenches 2 in the first direction are arranged in the body region 9. This results in a structure in which the three-dimensional corners of the trenches 2 and the gate electrodes 7 are present in the body region 9. Therefore, in the three-dimensional corners of the trenches 2 where the electric field is likely to concentrate and the gate insulating film 6 is likely to be destroyed, the concentration of the electric field is alleviated even when a high voltage is applied, and the destruction of the gate insulating film 6 can be suppressed.

[0026] Furthermore, in the semiconductor device 1 of this embodiment, the impurity concentration of the JFET region 8 is set higher than the impurity concentration of the drift region 10, and the thickness (dimension in the depth direction) tJ of the body region 9 and the JFET region 8 from the bottom of the trench 2 is set to a thickness greater than 0.5 μm, as shown in Fig. 3. It is desirable to set the thicknesses tJ of the body region 9 and the JFET region 8 from the bottom of the trench 2 to approximately the same thickness.

[0027] When a high voltage is applied between the drain and source, the depletion layer spreads in the JFET region 8 to ensure the breakdown voltage. Here, when the thickness tJ is small, as in the conventional structure shown in FIG. 17, the depletion layer spreads mainly in the depth direction. The depletion layer spreads more easily when the impurity concentration is low. Therefore, the concentration in the JFET region 8 cannot be increased, and it is set to the same concentration of 1×10 as that of the general drift region 10. 16 cm -3 is set to a certain extent.

[0028] In contrast, in this embodiment, by increasing the thickness tJ, when a high voltage is applied between the drain and source, the depletion layer begins to spread laterally from the body region 9 on both sides of the JFET region 8, and when a higher voltage is applied, the depletion layer closes and pinches off. As a result, the depletion layer spreads only half the width WJ of the JFET region 8, and a depletion layer with a thickness of tJ is obtained. As a result, the spread of the depletion layer required for complete depletion is small, so the impurity concentration of the JFET region 8 can be increased while maintaining the withstand voltage. And, since the impurity concentration of the JFET region 8 can be set high, the resistance of the JFET region 8 can be reduced, and the on-resistance can be reduced. In addition, although the temperature characteristic of the resistance of the JFET region 8 is positive, if the impurity concentration is high, the rate of increase in the resistance of the JFET region 8 is low even in a high-temperature environment, so that the on-resistance when viewed as a whole semiconductor chip at high temperatures can be maintained at a low state.

[0029] The thickness tJ of both the body region 9 and the JFET region 8 from the bottom of the trench 2 is preferably 0.8 μm or more and 1.3 μm or less. The larger the thickness tJ, the greater the effect described above. The width WTR of the trench 2 is preferably 1.3 μm or more and 1.6 μm or less. The width WJ of the JFET region 8 is preferably 0.3 μm or more and 1.4 μm or less. The narrower the width WJ, the greater the effect described above. The impurity concentration of the JFET region 8 is 8×10 16 cm -3 That's it, 2 x 10 17 cm -3 This is because the concentration of the drift region 10 is generally 1×10 16 cm -3 Greater than the extent.

[0030] As described above, according to this embodiment, in a trench MOSFET having a vertical channel fin structure, it is possible to realize a semiconductor device 1 capable of reducing the on-resistance while ensuring the short-circuit resistance.

[0031] In addition, the semiconductor device 1 of this embodiment also has a source electrode 12 arranged on the front side, a drain electrode 13 arranged on the back side, an interlayer insulating film 14, a second source region 4 of the second conductivity type, a contact plug 15, and a barrier metal 16.

[0032] The source electrode 12 is an electrode formed of a metal such as aluminum.

[0033] The drain electrode 13 is an electrode formed of, for example, a laminated metal film (for example, titanium / nickel / gold) and is electrically connected to the drain region 11.

[0034] The interlayer insulating film 14 is formed between the mutually connected portions of the gate electrodes 7 and the first source region 3. The interlayer insulating film 14 is also formed so as to cover the upper and side portions of the mutually connected portions of the gate electrodes 7.

[0035] In this embodiment, the gate electrodes 7 are structured to be connected to each other above the plurality of trenches 2, so that a part of the gate electrodes 7 protrudes from the other semiconductor layers to form a step.

[0036] Therefore, in this embodiment, a second source region 4 of a second conductivity type having a higher impurity concentration than the body region 9 is provided in contact with the upper surface of at least a part of the body region 9, and an interlayer insulating film 14 covers the gate electrode 7, the first source region 3, and the second source region 4, and a contact plug 15 is provided that penetrates the interlayer insulating film 14 and is connected to the first source region 3 and the second source region 4. The contact plug 15 may be made of a conductive metal such as tungsten. It is also preferable that the first source region 3 and the second source region 4 are connected to the contact plug 15 via a barrier metal 16. The barrier metal 16 may be made of, for example, TiN or Ti.

[0037] By providing the contact plug 15 as in this embodiment, the source electrode 12 can be connected to the first source region 3 and the second source region 4 via the contact plug 15, and the connection between the source electrode 12 and the first source region 3 and the second source region 4 can be stabilized. In addition, the surface of the source electrode 12 can be flattened, so that the source electrode 12 can be stabilized when connected to the outside.

[0038] Furthermore, by providing the second source region 4 of the second conductivity type, the body region 9 of the second conductivity type and the source electrode 12 can be connected with lower resistance than by connecting via the first source region 3 of the first conductivity type or by connecting directly to the body region 9.

[0039] The first source region 3, the second source region 4, and the contact plug 15 may be arranged such that the contact plug 15 has a longitudinal direction in the second direction, and the first source region 3 and the second source region 4 are arranged alternately at least in the region overlapping with the contact plug 15, as shown in Fig. 1. The second source region 4 has a longitudinal direction in the first direction and a lateral direction in the second direction, and a plurality of second source regions 4 are arranged in the second direction. The arrangement of the first source region 3, the second source region 4, and the contact plug 15 is not limited to this, and other arrangements may be used.

[0040] Regarding the impurity concentration, in this embodiment, as an example, the JFET region 8 is illustrated as n, the body region 9 and the channel region 5 as p, the drift region 10 as low concentration n-, the first source region 3 and the drain region 11 as high concentration n+, and the second source region 4 as high concentration p+, but the impurity concentration may be changed within a range in which the intended operation of this embodiment can be achieved.

[0041] The semiconductor device 1 of this embodiment can be formed using, for example, an n+-type SiC substrate, but is not limited thereto, and an Si substrate or the like may also be used. Also, for parts of the manufacturing method not specifically described in this specification, for example, an n+-type drain region 11 can be formed on an n+-type SiC substrate, and an n−-type drift region 10 can be formed by epitaxial growth. Since it can be manufactured by a general semiconductor device manufacturing method, detailed description is omitted. The same applies to the formation method of the contact plug 15 and the like.

Embodiment

[0042] FIG. 5 is a top perspective view of the semiconductor device of Example 2.

[0043] The semiconductor device 1 of Example 2, in addition to the configuration of Example 1, has a region where the width WJ of the JFET region 8 is WJ = WJ1 and a region where the width WJ of the JFET region 8 is WJ = WJ2 < WJ1 at different locations when viewed in plan.

[0044] FIG. 6 is a diagram for explaining an example of the characteristics of the semiconductor device of Example 2. In FIG. 6, the lower horizontal axis is the width WJ of the JFET region 8, the upper horizontal axis is the short-circuit withstand, the left vertical axis is the normalized on-resistance Ron·Aa, and the right vertical axis is the drain-gate capacitance Cgd.

[0045] The normalized on-resistance Ron·Aa is the on-resistance per unit area, and the smaller this value, the more current can flow per unit area. The JFET region 8 is the current path in MOSFET operation, and as the width WJ of the JFET region 8 increases, the current flows more easily, so the normalized on-resistance Ron·Aa decreases. Conversely, if it is made too narrow, the width of the current path becomes too narrow, and the normalized on-resistance Ron·Aa rises rapidly. Therefore, the point just before the normalized on-resistance Ron·Aa rises rapidly becomes the design range.

[0046] As shown in FIG. 3, the gate-drain capacitance Cgd is the capacitance formed by the lower part of the gate electrode 7 inside the trench 2 and the JFET region 8 that is in contact with it via the gate insulating film 6. The gate-drain capacitance Cgd is also called the feedback capacitance Crss, and is a parameter that greatly affects the switching speed of the MOSFET. The smaller this value is, the faster the switching speed becomes. The wider the width WJ of the JFET region 8 is, the higher the gate-drain capacitance Cgd becomes. Since the gate-drain capacitance Cgd increases as the square of the opposing area between the gate and drain, the slope increases rapidly if the width WJ of the JFET region 8 is made too wide. Therefore, the design range is just before the slope of the gate-drain capacitance Cgd increases rapidly.

[0047] As shown in FIG. 6, the increase and decrease of the normalized on-resistance Ron·Aa and the gate-drain capacitance Cgd with respect to the width WJ of the JFET region 8 are inversely related to each other.

[0048] In addition, if the width WJ of the JFET region 8 is narrow, the depletion layer is likely to close, so that if the width WJ of the JFET region 8 is narrow, the short circuit resistance is improved, and if the width WJ of the JFET region 8 is wide, the short circuit resistance is reduced.

[0049] Therefore, in the region where the width WJ of the JFET region 8 is WJ=WJ1, the width WJ of the JFET region 8 can be made wider to form a cell that actively operates as a MOSFET, and in the region where the width WJ of the JFET region 8 is WJ=WJ2, the width WJ of the JFET region 8 can be made narrower to form a cell that can limit the saturation current more than in the region where the width WJ of the JFET region 8 is WJ=WJ1, thereby improving the short-circuit resistance.

[0050] As in this embodiment, by mixing a region where the width WJ of the JFET region 8 is WJ=WJ1 and a region where the width WJ of the JFET region 8 is WJ=WJ2 and adjusting the ratio, it is possible to adjust the characteristics, thereby responding precisely to various application requirements.

[0051] In addition, among the multiple trenches 2, the JFET region 8 corresponding to the trench 2 of the terminal portion 17 in the second direction may be set to have the same impurity concentration as the drift region 10 or a lower impurity concentration than the other JFET regions 8. Since the depletion layer is easily closed in this type of cell, it can be said that the cell is capable of improving the short circuit resistance by limiting the saturation current. Since the terminal portion 17 of the cell has no cells sharing the same current path and is interrupted there, the drift resistance is lower than that inside the cell body, and the current flows easily and heat is easily generated. Also, when a drain bias is applied, the terminal portion 17 of the cell is the boundary between the cell body and the outer periphery of the chip, so the electric field is easily concentrated. By arranging a cell capable of improving the short circuit resistance by partially limiting the saturation current in such a place, it is possible to reliably ensure the short circuit resistance while maintaining as low an on-resistance as possible.

[0052] Although an example of placement at the terminal end 17 of the cell has been described here, such a structure may also be applied to the heat generating location when a heat generating location within a chip is identified for various reasons. EXAMPLES

[0053] Fig. 7 is a top perspective view of a semiconductor device according to Example 3. Fig. 8 is a cross-sectional view taken along line X3-X3' of Fig. 7.

[0054] The semiconductor device 1 of Example 3 has, in addition to the configuration of Example 1 or Example 2, a third source region 3A, at least in a portion of the first source region 3 separated by a plurality of trenches 2, which has a smaller thickness (depth dimension) and a lower impurity concentration than other portions of the first source region 3.

[0055] The third source region 3A has a smaller thickness and a lower impurity concentration than the first source region 3, and therefore has a higher resistance. At high temperatures, such as when a short circuit occurs, the resistance increases, and therefore the potential of the third source region 3A becomes higher than that of the first source region 3, and the voltage of the JFET region 8 increases accordingly. As a result, the reverse bias of the PN junction between the JFET region 8 and the body region 9 becomes stronger, and the JFET region 8 can be further depleted. As a result, the saturation current can be reduced compared to the first embodiment, and the short circuit resistance is improved.

[0056] In addition, since the third source region 3A is thinner than the first source region 3, the overlap capacitance between the gate electrode 7 extending in the depth direction of the trench 2 and the third source region 3A is reduced, and the gate capacitance can be reduced, resulting in a faster switching speed.

[0057] Therefore, according to the semiconductor device 1 of this embodiment, it is possible to improve the short-circuit resistance and reduce the gate capacitance while maintaining a high channel density, and also to increase the switching speed.

[0058] Here, in order to fully obtain the effect of improving the short circuit resistance, it is desirable that the sheet resistance of the third source region 3A is ten times or more the sheet resistance of the first source region 3.

[0059] Furthermore, in this embodiment, since the thickness of the third source region 3A is reduced, the trench 2 can be made shallower and the thickness tJ can be increased accordingly. EXAMPLES

[0060] Fig. 9 is a top perspective view of a semiconductor device of Example 4. Fig. 10 is a cross-sectional view taken along line X4-X4' in Fig. 9. Fig. 11 is a cross-sectional view taken along line Y2-Y2' in Fig. 9.

[0061] In this embodiment, an example applied to the third embodiment will be described, but the present invention is not limited to this, and may be applied to the first or second embodiment.

[0062] In this embodiment, the second source region 4 has a longitudinal direction in the second direction. The contact plugs 15 have a longitudinal direction in the first direction and are arranged in a plurality in the second direction. This allows the body region 9 and the source electrode 12 to be connected with low resistance via the second source region 4 having a longitudinal direction in the second direction. This allows the efficient operation of the built-in body diode of the MOSFET. In addition, by connecting with low resistance, the base potential of the parasitic bipolar transistor composed of the drain region 11 (n collector), the body region 9 (p base), and the first source region 3 (n emitter) can be stabilized (potential fixing effect), so that the parasitic transistor can be made less likely to operate, and element destruction due to the parasitic transistor operation can be suppressed. Furthermore, by making the second source region 4 into a continuous stripe layout, defects in which the second source region 4 is not locally connected due to pattern defects or the like are reduced, and defects in which the drain-source leakage during off-time due to this defect is large can be reduced, and the yield can be improved. EXAMPLES

[0063] Fig. 12 is a top perspective view of a semiconductor device according to the fifth embodiment. Fig. 13 is a cross-sectional view taken along line X5-X5' of Fig. 12.

[0064] In this embodiment, an example applied to the third embodiment will be described, but the present invention is not limited to this, and may be applied to the first or second embodiment.

[0065] In this embodiment, similarly to the fourth embodiment, the second source region 4 has its longitudinal direction in the second direction. The contact plugs 15 have their longitudinal direction in the first direction and are arranged in the second direction. This makes it possible to obtain the same effect as the fourth embodiment.

[0066] In addition, in this embodiment, in the region between the region in which the contact plugs 15 are arranged in the second direction and the region in which the trenches 2 are arranged in the second direction, the area of ​​the second source region 4 is larger than the area of ​​the first source region 3 on one side in the first direction of the contact plugs 15 (e.g., the left side in Figure 12), and the area of ​​the second source region 4 is smaller than the area of ​​the first source region 3 on the other side in the first direction of the contact plugs 15 (e.g., the right side in Figure 12).

[0067] For example, in the fourth embodiment, as shown in FIG. 9, the first source region 3 having a longitudinal direction in the second direction is disposed on both sides of the second source region 4 having a longitudinal direction in the second direction, so that the first source region 3 is in the form of two stripes, whereas in the fifth embodiment, as shown in FIG. 12, the first source region 3 having a longitudinal direction in the second direction is disposed only on one side of the second source region 4. This allows the interval of the trench 2 in the first direction to be shortened, and the channel density to be increased, or the size of the semiconductor chip to be reduced. In addition, the area of ​​the parasitic bipolar transistor composed of the drain region 11 (n collector), the body region 9 (p base), and the first source region 3 (n emitter) can be reduced, so that the element destruction due to the parasitic transistor operation can be suppressed. EXAMPLES

[0068] Fig. 14 is a top perspective view of a semiconductor device of Example 6. Note that in Fig. 14, the position where the contact plug 15 is disposed is not shown.

[0069] In this embodiment, an example will be described in which the present invention is applied to Example 4 based on Example 3, but the present invention is not limited to this, and may be applied to Example 4 based on Example 1 or Example 2, or may be applied to Example 5.

[0070] In this embodiment, the basic structure is the same as in embodiment 4. In this embodiment, the first source region 3 is thinned out at a terminal portion 17 in the second direction among the portion separated by the plurality of trenches 2 (when embodiment 3 is used as the base, this corresponds to a part of the third source region 3A which is a part of the first source region 3) to form a thinned out region 18. In addition, the portion between the portion separated by the plurality of trenches 2 that is the thinned out region 18 and the contact plug 15 (not shown) is also thinned out to form the thinned out region 18.

[0071] According to this embodiment, in the terminal portion 17 where an electric field is likely to concentrate, the saturation current during a short circuit can be limited, thereby improving the short circuit resistance.

[0072] Although an example in which thinning region 18 is disposed at terminal end 17 of the cell has been described here, the present invention is not limited to this, and thinning region 18 may be disposed at a location that is likely to become hot in the event of a short circuit. EXAMPLES

[0073] Fig. 15 is a top see-through view of a semiconductor device of Example 7. Fig. 16 is a cross-sectional view taken along line X6-X6' of Fig. 15. Note that Fig. 15 does not show the position where contact plug 15 is to be disposed.

[0074] In this embodiment, an example will be described in which the present invention is applied to Example 4 based on Example 3, but the present invention is not limited to this, and may be applied to Example 4 based on Example 1 or Example 2, or to Example 5 or Example 6.

[0075] In this embodiment, the basic structure is the same as in embodiment 4. In this embodiment, in a region between a region in which a plurality of contact plugs 15 are arranged in the second direction and a region in which a plurality of trenches 2 are arranged in the second direction, a first source region 3 is arranged having a longitudinal direction in the second direction, and a thinned-out region 18 in which the first source region 3 is partially thinned out is provided. In this thinned-out region 18, the body region 9 is exposed, or the second source region 4 is arranged.

[0076] According to this embodiment, the area of ​​the parasitic bipolar transistor composed of the drain region 11 (n collector), the body region 9 (p base), and the first source region 3 (n emitter) can be reduced, thereby suppressing element destruction due to the operation of the parasitic transistor.

[0077] In order to prevent an increase in the on-resistance as much as possible, it is preferable not to perform thinning out on the side opposite to thinned out region 18 via trench 2.

[0078] Furthermore, by arranging the second source region 4 in the thinning region 18, the potential fixing effect described in the fourth embodiment can be obtained, making it difficult for a parasitic transistor to operate, and thus preventing element destruction due to the parasitic transistor operation.

[0079] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0080] 1 Semiconductor device 2. Trench 3 First source region 3A Third Source Region 3B Source area 4 Second Source Region 5 Channel Area 6 Gate insulating film 7 Gate electrode 8 JFET area 9. Body Region 10 Drift Region 11 Drain region 12 Source electrode 13 Drain electrode 14 Interlayer insulating film 15 Contact plug 16 Barrier Metal 17 End 18 Thinning Area

Claims

1. A plurality of trenches having a longitudinal direction in a first direction and a lateral direction in a second direction when viewed in a plan view, the trenches being arranged in the second direction; a first source region of a first conductivity type, at least a portion of which is separated by the plurality of trenches; a second conductivity type channel region in contact with a lower surface of the first source region and separated by the plurality of trenches; a gate insulating film disposed inside the trench; a gate electrode including a region at least partially disposed within the trench; a JFET region of a first conductivity type disposed below the channel region; a body region of a second conductivity type disposed on a side of the JFET region; a drift region of a first conductivity type disposed below the JFET region; a drain region of a first conductivity type that is disposed below the drift region and has a higher impurity concentration than the drift region; the channel region is connected to the body region, and a channel current flows vertically through the channel region; a length in the first direction of the gate electrode disposed inside the trench is longer than a length in the first direction of the JFET region; an impurity concentration of the JFET region is higher than an impurity concentration of the drift region; a body region and a JFET region each having a depth dimension greater than 0.5 μm from a bottom of the trench;

2. In claim 1, a body region and a JFET region each having a depth dimension from a bottom of the trench of 0.8 μm or more and 1.3 μm or less;

3. In claim 1, The semiconductor device according to claim 1, wherein the length of the trench in the first direction is 1.3 μm or more and 1.6 μm or less.

4. In claim 1, A semiconductor device, characterized in that the length of the JFET region in the first direction is 0.3 μm or more and 1.4 μm or less.

5. In claim 1, The impurity concentration of the JFET region is 8×10 １６ cm －３ That's it, 2 x 10 １７ cm －３ A semiconductor device characterized in that:

6. In claim 1, 1. A semiconductor device comprising: a region in which a length of the JFET region in the first direction is a first length, and a region in which the length of the JFET region in the first direction is a second length that is shorter than the first length, both located at different positions when viewed in a plane.

7. In claim 1, The semiconductor device is characterized in that, among the plurality of trenches, the JFET region corresponding to the trench at the end in the second direction has an impurity concentration that is the same as that of the drift region or that is lower than the impurity concentrations of the other JFET regions.

8. In claim 1, the first source region, at least in a portion separated by the plurality of trenches, has a third source region that is smaller in dimension in a depth direction and has a lower impurity concentration than other portions of the first source region.

9. In claim 1, a second source region of a second conductivity type in contact with an upper surface of at least a portion of the body region and having an impurity concentration higher than that of the body region; an interlayer insulating film covering the gate electrode, the first source region, and the second source region; a contact plug penetrating the interlayer insulating film and connected to the first source region and the second source region.

10. In claim 9, the contact plug has a longitudinal direction in the second direction; 2. A semiconductor device comprising: a first source region and a second source region, the first source region and the second source region being alternately arranged at least in a region overlapping with the contact plug.

11. In claim 9, The second source region has a longitudinal direction in the second direction.

12. In claim 11, The semiconductor device is characterized in that the contact plug has a longitudinal direction in the first direction, and a plurality of the contact plugs are arranged in the second direction.

13. In claim 12, A semiconductor device characterized in that in a region between a region in which the contact plugs are arranged in the second direction and a region in which the trenches are arranged in the second direction, the area of ​​the second source region is larger than the area of ​​the first source region on one side of the contact plugs in the first direction, and the area of ​​the second source region is smaller than the area of ​​the first source region on the other side of the contact plugs in the first direction.

14. In claim 1, The first source region is thinned out at a terminal portion in the second direction among the portions separated by the plurality of trenches.

15. In claim 12, in a region between a region in which the contact plugs are arranged in the second direction and a region in which the trenches are arranged in the second direction, the first source region is arranged with a longitudinal direction in the second direction, and the first source region has a thinned-out region in which the first source region is partially thinned out; The semiconductor device according to claim 1, wherein the thinning region exposes the body region or has the second source region disposed therein.

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