Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of semiconductor devices capable of improving the yield by suppressing overdetection while reducing the rejection of defective products to be commercialized by executing more appropriate quality judgment.SOLUTION: After preparing a semiconductor wafer, a device formation process is carried out to form semiconductor elements (S100). Subsequently, the electrical characteristics of each semiconductor device that is to be chipped from the semiconductor wafer are measured (S110). Subsequently, at least one of the areas of any region on the graph of the electrical characteristic waveform obtained by measuring the electrical characteristics and the slope of a line connecting any two points on the graph of the electrical characteristic waveform is defined as a feature, and the feature is calculated (S120). Based on the features and the discriminant, a pass / fail determination is made for each semiconductor device (S130).SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, and is particularly suitable for a method for manufacturing a compound semiconductor device using silicon carbide (hereinafter referred to as SiC), gallium nitride (hereinafter referred to as GaN), or the like as a semiconductor material. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a semiconductor device in which a crystal defect inspection is performed before an electrical characteristic inspection is performed after a semiconductor element is formed by a semiconductor process. Specifically, an appearance inspection using a laser, that is, a crystal defect inspection by image detection, is performed at a stage where an epitaxial film is grown on a SiC substrate in advance, and crystal defects present in the epitaxial film are detected using a crystal defect inspection device. After the crystal defect inspection, an element structure is formed on the semiconductor wafer and then the wafer is diced into individual semiconductor chips. Semiconductor chips in which no crystal defects are detected by the crystal defect inspection are selected as candidates for good products. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-176696 A Summary of the Invention [Problem to be solved by the invention]

[0004] Semiconductors, especially compound semiconductors such as SiC and GaN, have a high density of crystal defects and may contain crystal defects called killer defects that have a negative impact on downstream processes and quality. It is necessary to properly detect such crystal defects and reject them before shipping to prevent them from being used in products.

[0005] However, even if crystal defects exist, some crystal defects do not cause problems in practical use, while other crystal defects, even if small, can expand and become killer defects when used in products, and so the accuracy of crystal defect inspection using image detection is insufficient. This can lead to problems such as products that should be rejected being commercialized, or overdetection, which results in rejecting products that do not need to be rejected.

[0006] The present disclosure aims to provide a manufacturing method for semiconductor devices that can perform more appropriate quality determination, prevent defective products from being rejected and commercialized, and suppress overdetection, thereby improving yield. [Means for solving the problem]

[0007] In one aspect of the present disclosure, a method for manufacturing a semiconductor device includes: After preparing a semiconductor wafer, a device formation process is performed to form a semiconductor element (S100); Measuring electrical characteristics of individual semiconductor devices to be chipped from the semiconductor wafer (S110); calculating at least one of an area of ​​an arbitrary region of a graph of an electrical characteristic waveform obtained by measuring the electrical characteristics and a slope of a line connecting any two points of the graph as a feature quantity (S120); and determining whether each of the semiconductor devices is good or bad based on the characteristic amount obtained by calculating the characteristic amount and a discriminant (S130).

[0008] In this way, at least one of the area of ​​an arbitrary region of the graph of the electrical characteristic waveform obtained by measuring the electrical characteristics and the slope of the graph of the electrical characteristic waveform is used as a feature, and a pass / fail judgment is performed based on the feature and the discriminant. Therefore, it is possible to increase the detection rate of NG products while reducing the overdetection rate. Therefore, it is possible to provide a manufacturing method for semiconductor devices that can more appropriately detect crystal defects that could become killer defects, suppress rejection and commercialization, and suppress overdetection to improve yield.

[0009] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0010] [Figure 1] 1 is a perspective cross-sectional view of a SiC semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is an explanatory diagram of a current path in a SiC semiconductor device. [Figure 3A] FIG. 4 is an explanatory diagram showing the state of holes and electrons in the vicinity of a built-in diode. [Figure 3B] FIG. 1 is an explanatory diagram of defect growth caused by BPD near a built-in diode. [Figure 4] 1 is a graph showing experimental results of electrical characteristics of drain current Id versus source-drain voltage Vds. [Diagram 5] This is a graph showing the Gini index. [Figure 6A] FIG. 13 is a diagram showing a case where three nodes are extracted from a graph of an electrical characteristic waveform. [Figure 6B] FIG. 6B is a graph showing the Gini index normalized for the three nodes extracted as in FIG. 6A. [Figure 7] FIG. 13 is a diagram showing an example of a case in which measured feature quantities of each SiC semiconductor device are plotted on a two-axis coordinate system with the two feature quantities being the x-axis and the y-axis, and a discriminant equation for determining whether a product is good or bad is set. [Figure 8] 1 is a flowchart of a manufacturing process of a SiC semiconductor device. [Figure 9] 13 is a graph showing regions defined by equal straight lines and Lorentz curves described in another embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following, including other embodiments described below, the same reference numerals will be used to denote the same or equivalent parts in each embodiment.

[0012] (First embodiment) A first embodiment of the present disclosure will be described. In this embodiment, a SiC semiconductor device using SiC as a semiconductor material will be described as an example of a semiconductor device.

[0013] [Configuration of SiC semiconductor device] The SiC semiconductor device according to this embodiment is formed with an inverted vertical MOSFET having a trench gate structure as shown in FIG. 1 as a semiconductor element. The vertical MOSFET shown in these figures is formed in a cell region of the SiC semiconductor device, and the SiC semiconductor device is configured by forming a peripheral breakdown voltage structure so as to surround the cell region, but only the vertical MOSFET is shown here. In the following, directions perpendicular to each other as shown in FIG. 1 will be described as the X direction, the Y direction, and the Z direction. Specifically, the width direction of the vertical MOSFET is the X direction, the depth direction of the vertical MOSFET intersecting the X direction is the Y direction, and the thickness direction or depth direction of the vertical MOSFET, i.e., the normal direction to the XY plane, is the Z direction.

[0014] As shown in FIG. 1, the SiC semiconductor device has n-type impurities doped therein. + A vertical SiC substrate 11 is used. The SiC substrate 11 constitutes the drain region of a vertical MOSFET. The SiC substrate 11 has an off angle of, for example, 0 to 8° with respect to the (0001) Si plane, and is doped with a high concentration of n-type impurities such as N (nitrogen) and P (phosphorus).

[0015] On the main surface of the SiC substrate 11, a n-type semiconductor layer made of SiC that constitutes a part of the drift layer is formed. -An n-type buffer layer 12 is formed on the surface of the SiC substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the SiC substrate 11, and has an n-type impurity concentration between that of the SiC substrate 11 and a low concentration layer 13 described later. In addition, an n-type impurity layer made of SiC that constitutes a part of a drift layer having a lower concentration than the SiC substrate 11 is formed on the buffer layer 12. - A low concentration layer 13 of the mold is formed.

[0016] In the cell region, an n-type JFET section 14 constituting a part of a drift layer made of SiC is formed on the low-concentration layer 13. The low-concentration layer 13 is connected to the JFET section 14 on the side opposite to the SiC substrate 11. Furthermore, on the low-concentration layer 13, in addition to the JFET section 14, a p-type deep layer 15 doped with p-type impurities such as Al (aluminum) is formed.

[0017] The JFET section 14 and the deep layer 15 constitute a saturation current suppression layer, and are both extended in the X direction as the longitudinal direction, and are arranged alternately and repeatedly in the Y direction. That is, when viewed from the normal direction to the main surface of the SiC substrate 11, at least a part of the JFET section 14 and the deep layer 15 are each formed into a plurality of lines, in other words, stripes, and are arranged alternately.

[0018] The striped deep layer 15 has linear portions of a constant width, is disposed at equal intervals, and has a constant p-type impurity concentration in the depth direction.

[0019] Furthermore, an n-type current spreading layer 16 constituting a part of the drift layer made of SiC is formed on the JFET section 14 and the deep layer 15. The current spreading layer 16 is a layer that allows the current flowing through the channel of the vertical MOSFET to be diffused in the Y direction. The current spreading layer 16 is formed in contact with the tip side in the depth direction of the gate trench 21 described later, and has a higher n-type impurity concentration than the low concentration layer 13, for example.

[0020] In this embodiment, the drift layer is composed of the buffer layer 12, the low concentration layer 13, the JFET section 14, and the current spreading layer 16. However, the configuration of the drift layer is arbitrary, and for example, the drift layer may have a structure without a buffer layer.

[0021] A p-type base region 17 made of SiC is formed on the current spreading layer 16. In addition, a n-type base region 17 made of SiC is formed on the base region 17. + A p-type source region 18 is formed in the base region 17. The base region 17 has a lower p-type impurity concentration than the deep layer 15. The source region 18 has a higher n-type impurity concentration than the current spreading layer 16.

[0022] In addition, the p-type impurity concentration is made higher than that of the base region 17 so that the p-type impurity concentration is higher from the surface of the source region 18 to the base region 17. + In the present embodiment, the contact region 19 is configured in a line shape with the Y direction as the longitudinal direction. Furthermore, below the contact region 19, a p-type coupling layer 20 that connects the base region 17 and the deep layer 15 is formed. The coupling layer 20 is formed in a line shape with the Y direction as the longitudinal direction together with the contact region 19, and is disposed on both sides of the current spreading layer 16.

[0023] The contact region 19 and the coupling layer 20 play a role in coupling the deep layer 15 and the base region 17 to a source electrode 25 described later in order to fix the deep layer 15 and the base region 17 to the source potential.

[0024] The contact regions 19 and the coupling layers 20 may be formed at any interval, but in this embodiment, they are formed on both sides of a trench gate structure, which will be described later. The width of the contact regions 19 and the coupling layers 20 may be any width, but in this embodiment, they are set to be equal to or smaller than the interval between adjacent trench gate structures.

[0025] Furthermore, a gate trench 21 is formed with a predetermined width and a predetermined depth so as to penetrate the source region 18 and the base region 17 and reach the current spreading layer 16. The above-mentioned base region 17 and source region 18 are formed so as to contact the side surface of this gate trench 21, and the contact region 19 is arranged so as to be away from the gate trench 21. The gate trench 21 is formed in a line-shaped layout with the X direction as the width direction, the direction intersecting the longitudinal direction of the JFET section 14 and the deep layer 15, the Y direction as the longitudinal direction here, and the Z direction as the depth direction. As shown in FIG. 1, the gate trench 21 is formed in a stripe shape with a plurality of gate trenches 21 arranged at equal intervals in the X direction, and the base region 17, the source region 18, the contact region 19, and the coupling layer 20 are arranged between each of them.

[0026] A portion of the base region 17 located on the side of the gate trench 21 serves as a channel region connecting the source region 18 and the current spreading layer 16 when the vertical MOSFET is in operation, and the inner wall surface of the gate trench 21 including the channel region is covered with a gate insulating film 22. A gate electrode 23 made of doped Poly-Si is formed on the surface of the gate insulating film 22, and the gate insulating film 22 and the gate electrode 23 are disposed in the gate trench 21 to form a trench gate structure. Furthermore, an interlayer insulating film 24 is formed so as to cover the gate electrode 23.

[0027] As shown in FIG. 1, a source electrode 25 and the like are formed on the surface of the source region 18 and the surface of the gate electrode 23 via an interlayer insulating film 24. The source electrode 25 is made of a plurality of metals, for example, Ni / Al. Among the plurality of metals, at least the n-type SiC, specifically the part in contact with the source region 18 and the gate electrode 23 in the case of n-type doping, is made of a metal capable of ohmic contact with the n-type SiC. Among the plurality of metals, at least the p-type SiC, specifically the part in contact with the contact region 19 is made of a metal capable of ohmic contact with the p-type SiC. The source electrode 25 is electrically insulated from the SiC part by being formed on the interlayer insulating film 24, but is electrically in contact with the source region 18 and the contact region 19 through a contact hole 24a formed in the interlayer insulating film 24.

[0028] Meanwhile, a drain electrode 26 electrically connected to the SiC substrate 11 is formed on the back surface side of the SiC substrate 11. With this structure, an n-channel type inversion type trench gate structure vertical MOSFET is formed. A cell region is formed by arranging a plurality of such vertical MOSFETs. Although not shown, a peripheral breakdown withstand structure such as a guard ring is formed to surround the periphery of the cell region, thereby forming a SiC semiconductor device.

[0029] In the SiC semiconductor device having such a configuration, a built-in diode is formed in the vertical MOSFET by a pn junction between the low concentration layer 13, the JFET portion 14, etc. and the deep layer 15, the coupling layer 20, etc.

[0030] The above is an example of the basic configuration of the SiC semiconductor device according to this embodiment. This SiC semiconductor device is used, for example, in an inverter circuit for driving a three-phase motor that uses vertical MOSFETs as switching elements.

[0031] As described above, the SiC semiconductor device has a structure in which a vertical MOSFET with a trench gate structure and an internal diode composed of a pn junction are provided in the cell region. The drift layer including the SiC substrate 11 and the buffer layer 12 contains wavy dislocations having dislocation lines on the (0001) plane, called basal plane dislocations (hereinafter referred to as BPDs). Defects caused by these BPDs may occur in the SiC semiconductor device.

[0032] As shown in FIG. 2, an equivalent circuit of the SiC semiconductor device is shown as a circuit configuration having a vertical MOSFET 30 and a built-in diode 40. When the vertical MOSFET 30 is on, an on-current I flows from the drain electrode 26 to the source electrode 25. ON 2 correspond to the source electrode 25, the drain electrode 26, and the gate electrode 23, respectively. Specifically, when a predetermined voltage, for example, 20 V, is applied to the gate electrode 23, a channel region is formed in the surface of the base region 17 that contacts the gate trench 21, and an on-current I ON flows.

[0033] Thereafter, when the SiC semiconductor device is turned off, a reverse bias is applied and the device is in a reverse conducting state, so that the built-in diode 40 functions as a freewheeling diode, and a freewheeling current I flows through the built-in diode 40 as a drain current Id. OFF flows. At this time, as shown in FIG. 3A, holes that have diffused from the p-type layer side to the n-type layer side of the pn junction that constitutes the built-in diode 40 recombine with electrons in the n-type layer. Because the recombination energy between these holes and electrons is large, the BPD50 expands and an SSF60 is generated, as shown in FIG. 3B. The SSF60 expands as the current stress on the built-in diode 40 accumulates. Since the SSF60 occupies a larger area than the BPD50, the on-current I ON and the reflux current I OFFIn addition, since the SSF 60 expands in response to the stress of current flow to the built-in diode 40, the electrical characteristics after operation are degraded compared to the electrical characteristics immediately after manufacture, that is, before the SSF 60 is generated.

[0034] Therefore, it is desirable to be able to reject, in a pass / fail judgment, a SiC semiconductor device that includes a BPD50 that can be expanded to an SSF60 such that the desired electrical characteristics of the product cannot be obtained.

[0035] However, as mentioned above, the accuracy of crystal defect inspection using image detection is insufficient, and problems can arise such as products being manufactured that should actually be rejected, or overdetection resulting in the rejection of products that do not need to be rejected.

[0036] Therefore, the detection of crystal defects by electrical property inspection was investigated, but the standard judgment that a value of leakage current etc., which is performed as a general electrical property inspection, is compared with a threshold value, and if the value does not exceed the threshold value, it is a good product, and if it exceeds the threshold value, it is a defective product, was insufficient. In other words, each value of leakage current etc. obtained by electrical property inspection is obtained as an absolute value, but the magnitude of the absolute value does not necessarily match the presence of a killer defect that adversely affects the subsequent process and quality when the SiC semiconductor device is actually used. For example, even if the leakage current exceeds the threshold value during the electrical property inspection, the leakage current may not increase much when the SiC semiconductor device is actually used, and the SiC semiconductor device may be durable for practical use. In addition, even if BPD50 exists, it may be BPD50 that does not expand to SSF60 that has adverse effects. In such a case, it is difficult to accurately detect a SiC semiconductor device having a killer defect by simply comparing the absolute value of the leakage current during the electrical property inspection with the threshold value, and it was not possible to accurately judge the quality of the SiC semiconductor device.

[0037] For this reason, further intensive research has revealed that the electrical characteristics of a SiC semiconductor device having a killer defect may be characterized by a certain specific waveform, and if the specific waveform is detected with high accuracy, it is possible to accurately detect a SiC semiconductor device having a killer defect. Although it has been confirmed that there are various specific waveform shapes, here, as an example, the electrical characteristics of the drain current Id flowing as a leakage current with respect to the source-drain voltage Vds under reverse bias will be described.

[0038] In the experiment, the electrical characteristics of the drain current Id versus the source-drain voltage Vds and the electrical characteristics of a SiC semiconductor device that had a killer defect after practical use were investigated. In order to obtain a large number of actual device data, a large number of SiC semiconductor devices manufactured using a plurality of SiC wafers were prepared, and the desired source-drain voltage Vds was applied with the gate voltage Vg=0V and the source voltage Vs=0V, and the drain current Id was measured. The source-drain voltage Vds was applied instantaneously, and a reverse bias state was instantaneously generated, and the drain current Id that flowed at that time was measured by a tester. The source-drain voltage Vds can be set arbitrarily, but here, six stages were set to 100V, 400V, 600V, 900V, 1100V, and 1200V. FIG. 4 shows the results. In the following description, each point that divides the graph of the electrical characteristics waveform shown in FIG. 4 into a plurality of regions, here the relationship of the value of the drain current Id versus each source-drain voltage Vds, is called a node. Moreover, the nodes are called nodes 1 to 6 in ascending order of the applied source-drain voltage Vds.

[0039] Furthermore, after this experiment, a durability test was conducted on the SiC semiconductor device used in the experiment, in which a source-drain voltage Vds of 1000V was applied for a long period of time, for example, a test under conditions in which BPD50 could be expanded to SSF60. Then, after the durability test, an electrical characteristic test was conducted again to check whether the electrical characteristics of the SiC semiconductor device had deteriorated compared to those immediately after manufacture, thereby determining whether a killer defect was present. For example, the on-current I that flows as the drain current Id when the vertical MOSFET 30 is turned on is ONWhen the BPD50 is less than the threshold, it is considered that the BPD50 expands to the SSF60 and the electrical characteristics deteriorate. Therefore, when the electrical characteristics of the SiC semiconductor device deteriorate compared to those immediately after manufacture, it is determined that a killer defect exists.

[0040] As shown in Figure 4, we obtained a large amount of actual device data, and the electrical characteristics basically showed that the drain current Id gradually increased as the source-drain voltage Vds increased. However, the change in the drain current Id between each node was not constant, and the slope also varied.

[0041] On the other hand, when the electrical characteristics of the SiC semiconductor device in which the killer defect existed were examined before the durability test, the line L in Figure 4 kill In the following description, the electrical characteristic waveform of the SiC semiconductor device in which it was determined that a killer defect was present is referred to as an NG waveform. kill The waveform of the electrical characteristics of a SiC semiconductor device that is not determined to have a killer defect is called a non-defective waveform. kill The rest are good waveforms.

[0042] When comparing the NG waveform with the good waveform, there was no clear relationship between the magnitude of the drain current Id at each node, and it was not possible to distinguish between the NG waveform and the good waveform based only on the magnitude of the drain current Id. This means that it is difficult to accurately detect SiC semiconductor devices with killer defects by simply comparing the absolute value of the leakage current during electrical characteristics testing with a threshold value, and it is not possible to accurately judge whether the device is good or bad.

[0043] For example, when only the magnitude of the drain current Id is considered for node 2, the drain current Id of a SiC semiconductor device that has not been determined to have a killer defect may be larger than that of a SiC semiconductor device that has been determined to have a killer defect. For this reason, simply comparing the absolute value of the leakage current with a threshold may result in overdetection, in which a killer defect is determined to exist when it does not. Conversely, a killer defect may be determined to not exist when it does exist.

[0044] Therefore, in this embodiment, a discriminant obtained from an NG waveform is calculated based on the actual device data, and when an electrical characteristic test is performed on a manufactured SiC semiconductor device, the discriminant is used to determine whether the device is good or bad. The method for calculating the discriminant is described below.

[0045] As described above, the electrical characteristic waveform is obtained as the relationship between the source-drain voltage Vds and the drain current Id. The electrical characteristic waveform can be selected by capturing the electrical characteristic waveform as the area and the slope of the line, and quantifying the area. Here, the Gini coefficient, which has been widely used in statistics, is applied to quantifying the waveform shape by interpreting it geometrically. The Gini coefficient in the following explanation is not a statistical measure, but a unique measure that has been geometrically interpreted as above to quantify the waveform shape. Furthermore, the graph of the electrical characteristic waveform is divided into regions, and the "Gini coefficient" is calculated for each region, and the "slope" of the line connecting any two points on the graph is calculated, and a specific electrical characteristic waveform is accurately selected by applying it to linear discrimination on two axes.

[0046] The "Gini coefficient" is generally a characteristic quantity that numerically represents "bias" or "inequality". Here, the Gini coefficient is used to quantify the shape information of the electrical characteristic waveform. As shown in Fig. 5, the Gini coefficient is defined as the ratio S1 / (S1 + S2) of the area S1 enclosed by the Lorenz curve drawn using two cumulative relative frequencies and the equal line, to the total area S1 + S2 of the area S2 below the equal line. The smaller the difference between the Lorenz curve and the equal line, and the closer the Gini coefficient is to 0, the smaller the "bias" or "inequality" is. Also, the larger the difference between the Lorenz curve and the equal line, and the closer the Gini coefficient is to 1, the larger the "bias" or "inequality" is.

[0047] In the case of this embodiment, the electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id becomes the Lorenz curve. Also, for the source-drain voltage Vds on the x-axis as the horizontal axis and the drain current Id on the y-axis as the vertical axis, when each maximum value is normalized to 1 and each minimum value is normalized to 0, the line y = x becomes the equal line. When the Lorenz curve is the electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id, the Lorenz curve is a curve that always has a y-coordinate value lower than the equal line, that is, a curve that satisfies the relationship y < x. And in order to quantify the waveform information of the electrical characteristic waveform, the area S1 of the crescent-shaped part between the Lorenz curve and the equal line is calculated. When normalized, since the area of the right triangle formed by the equal line and the y-axis is 1 / 2, the area S1 becomes 1 / 2 of the ratio S1 / (S1 + S2). 2×S1 obtained by doubling the area S1 represents the Gini coefficient.

[0048] The Gini coefficient is calculated by selecting at least three consecutive nodes from among the multiple nodes. Specifically, the node with the smallest absolute value of the electrical characteristics among the at least three consecutive nodes, in this case the node with the smallest source-drain voltage Vds and drain current Id, is set as the MIN node, and the node with the largest values ​​is set as the MAX node. Then, the source-drain voltage Vds and drain current Id of the MIN node are normalized to 0, and the source-drain voltage Vds and drain current Id of the MAX node are normalized to 1. This results in a Gini coefficient graph that depicts a Lorentz curve represented by the three or more consecutive selected nodes and an equal straight line where y = x.

[0049] For example, a case will be described where the Gini coefficient is calculated using all six nodes. In this case, as shown in FIG. 4, the source-drain voltage Vds of the MAX node is 1200 V, and the drain current Id at that time is 5×10 -4 A. The source-drain voltage Vds of the MIN node was 100 V, and the drain current Id was 1.5 × 10 -9 In this case, the normalized source-drain voltage Vds is calculated by subtracting 100 from the source-drain voltage Vds of each node and then multiplying it by 1 / (1200-100). Similarly, the drain current Id of each node is multiplied by 1.5×10 -9 Subtract and then 1 / (5×10 -4 -1.5×10 -9 ) is the normalized drain current Id. Note that the above conversion is performed when evaluating the waveform shape on a linear axis, and when evaluating the waveform shape on a logarithmic axis, a logarithmic function is applied before performing the normalization calculation. For example, when evaluating the drain current Id on a logarithmic axis, normalization is performed after setting the drain current of the MAX node to -3.3 and the drain current of the MIN node to -8.8.

[0050] The same applies when calculating the Gini coefficient by selecting a smaller number of nodes instead of selecting all six nodes. For example, FIG. 6A shows a case where three consecutive nodes, node 2 to node 4, are selected. In this case, node 2 is the MIN node, and node 4 is the MAX node. Then, normalization is performed by setting the source-drain voltage Vds and drain current Id of node 2, which is the MIN node, to 0, and the source-drain voltage Vds and drain current Id of node 4, which is the MAX node, to 1. As a result, a graph of the Gini coefficient is obtained in which a Lorentz curve represented by nodes 2 to 4 and an equal straight line where y=x are drawn, as shown in FIG. 6B.

[0051] When three or more nodes are selected from the six nodes from node 1 to node 6, the number of combinations is 4 when the number of nodes is three, 3 when the number of nodes is four, 2 when the number of nodes is five, and 1 when the number of nodes is six, for a total of 10 combinations. In addition, while FIG. 4 shows an electrical characteristic waveform in which the drain current Id on the vertical axis is represented on a logarithmic scale, it is also possible to use an electrical characteristic waveform represented on a linear scale in which the drain current Id on the vertical axis is represented as a linear value. Since the Gini coefficient can be calculated for each of the two patterns, the logarithmic scale and the linear scale, the Gini coefficient can be calculated for a total of 20 combinations, 10 for each pattern.

[0052] "Slope" is also used to quantify the shape information of the electrical characteristic waveform. The "slope" here means the gradient of the line connecting any two points, or two nodes in this case, on the graph of the electrical characteristic waveform, and is expressed as the change in drain current Id on the vertical axis (x-axis) relative to the change in source-drain voltage Vds on the horizontal axis (y-axis).

[0053] When any two nodes are selected from the six nodes from node 1 to node 6, the number of combinations is 6C2=15. In addition, while the electrical characteristic waveform in Fig. 4 shows the drain current Id on the vertical axis represented on a logarithmic scale, it is also possible to use an electrical characteristic waveform represented on a linear scale showing the drain current Id on the vertical axis as a linear value. Since the slope can be calculated for each of the two patterns, the logarithmic scale and the linear scale, the slope can be calculated for 15 patterns for each pattern, for a total of 30 combinations.

[0054] In this way, by calculating the "Gini coefficient" and "slope," a total of 50 feature quantities can be created, with 30 and 20 for each. Two feature quantities that can accurately determine whether a product is good or bad are selected from these 50 feature quantities, and linear discrimination is performed by setting these two feature quantities as the vertical and horizontal axes. The standard for accurate quality determination is that the detection rate of NG products is high and the overdetection rate, in which good products are mistakenly detected as NG products, is low. A discriminant equation used for linear discrimination is calculated to satisfy this. More specifically, it is preferable to set the discriminant equation so that a profit can be made by considering the expected expenses such as repair costs when NG products are mistakenly shipped and the loss when the product is not shipped due to overdetection, and looking at the difference between the expenses and losses.

[0055] Specifically, for all SiC semiconductor devices used in the experiment, 50 feature amounts, here the Gini coefficient and the slope, and data on whether the product was good or bad are stored in an electronic computer as learning data. As the electronic computer, for example, a microcomputer equipped with a CPU, ROM, RAM, I / O, etc. can be applied. Next, any two of the 50 feature amounts are selected, and a two-axis coordinate system is set with one as the x-axis and the other as the y-axis. Then, from all the feature amounts of each SiC semiconductor device that have been stored, feature amounts identical to the two feature amounts selected earlier are extracted, and points corresponding to the values ​​of each feature amount are plotted in the two-axis coordinate system. When any two feature amounts are selected from the 50 feature amounts, 50The two-axis coordinates of 1225 combinations of C2 are set, and feature quantities corresponding to the two axes are extracted from all the stored feature quantities of each SiC semiconductor device and plotted. At this time, it is made possible to determine whether each plot was a pass or fail product.

[0056] FIG. 7 is a diagram showing an example of this. Here, the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on the logarithmic scale and the slope of a line connecting two selected nodes 3 and node 5 on the linear scale are selected as two feature quantities. The former is set as the horizontal axis and the latter as the vertical axis. In this two-axis coordinate system, the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 in each SiC semiconductor device and the slope of a line connecting two selected nodes 3 and node 5 on the linear scale are plotted. Based on this, a straight line L1 with a high detection rate of NG products and a low overdetection rate of non-defective products is drawn in the two-axis coordinate system, and the following discriminant is calculated based on the equation y=-ax+b showing the straight line L1.

[0057] (Number 1) y≧-ax+b In Equation 1, "-a" indicates the slope of line L1, and "b" indicates the intercept of line L1.

[0058] That is, the feature on the horizontal axis, here the Gini coefficient calculated by selecting five consecutive nodes from node 2 to node 6 on a logarithmic scale, is denoted as x, and the feature on the vertical axis, here the slope of the line connecting the two selected nodes 3 and 5 on a linear scale is denoted as y. Then, when each feature is substituted for x and y in the discriminant, if y≧-ax+b is satisfied, the product is determined to be good and y<-ax+b, and if the discriminant is not satisfied, the product is determined to be NG.

[0059] The discriminant set in this way can be calculated only by arithmetic operations and logarithmic operations based on the actual device data. Therefore, compared with the case of performing the good / bad judgment by machine learning, the discriminant can be calculated by simple calculations and can be easily implemented. Of course, the discriminant used for the linear discrimination may be a formula showing a nonlinear curve or the like instead of a formula showing the straight line L1. However, by using a formula showing the straight line L1, it is possible to simplify the discrimination. And, by the good / bad judgment based on the discriminant, it is possible to increase the detection rate of NG products while reducing the overdetection rate. Therefore, it is possible to more appropriately detect crystal defects caused by killer defects, suppress rejection and commercialization, and manufacture a highly reliable SiC semiconductor device. It is also possible to suppress overdetection and improve the yield.

[0060] Since the discriminant can be obtained as described above, the quality of the SiC semiconductor device can be judged using the discriminant. Next, a method for manufacturing the SiC semiconductor device including such a quality judgment will be described.

[0061] The SiC semiconductor device shown in FIG. 1 is manufactured in accordance with the manufacturing process flowchart shown in FIG.

[0062] First, in step S100, a device formation process is performed to form a semiconductor element. Specifically, after preparing a SiC wafer constituting the SiC substrate 11, the buffer layer 12 and the low concentration layer 13 are formed in sequence by epitaxial growth. Then, a mask (not shown) that opens the region where the JFET section 14 is to be formed is formed on the surface of the low concentration layer 13, and then n-type impurities are ion-implanted to form the JFET section 14. In addition, a mask that opens the region where the deep layer 15 is to be formed is formed on the surfaces of the JFET section 14 and the low concentration layer 13, and then p-type impurities are ion-implanted to form the deep layer 15.

[0063] Next, a current spreading layer 16 made of SiC is epitaxially grown on the low concentration layer 13, the JFET section 14, and the deep layer 15. This forms a drift layer consisting of the buffer layer 12, the low concentration layer 13, the JFET section 14, and the current spreading layer 16. In addition, after a mask that opens in a region where a coupling layer 20 is to be formed is placed, the coupling layer 20 is formed by ion implantation of p-type impurities.

[0064] Furthermore, a p-type impurity layer is epitaxially grown on the current spreading layer 16 and the coupling layer 20 to form the base region 17, and then an n-type impurity layer is epitaxially grown on the base region 17 to form the source region 18. Next, a mask that opens the region where the contact region 19 is to be formed is placed, and then the contact region 19 is formed by ion implantation of p-type impurities. In this manner, each impurity layer is formed.

[0065] Thereafter, a trench gate structure is constructed by performing a process of forming a gate trench 21 by anisotropic etching, a process of forming a gate insulating film 22, and a process of forming a gate electrode 23. In addition, a process of forming an interlayer insulating film 24, a process of forming a contact hole 24a, a process of forming a source electrode 25 and a gate wiring, and a process of forming a drain electrode 26 on the back surface side of the SiC substrate 11 are performed, and then the substrate is divided into chip units by dicing to be individualized. In this way, chips of the SiC semiconductor device of this embodiment are manufactured.

[0066] Next, in step S110, the electrical characteristics of each chip of the SiC semiconductor device are measured. The electrical characteristics are measured using a tester or the like. In the case of this embodiment, the electrical characteristics of the drain current Id versus the source-drain voltage Vds are measured by changing the source-drain voltage Vds in multiple steps. For example, as described above, the source-drain voltage Vds is changed in six steps of 100V, 400V, 600V, 900V, 1100V, and 1200V, and the drain current Id is measured.

[0067] Furthermore, in step S120, data on the measurement results of the electrical characteristics are input to an inspection device (not shown). Then, in the inspection device, feature quantities of the electrical characteristics are calculated based on the measurement results of the electrical characteristics. In this case, it is sufficient to calculate only feature quantities used for pass / fail judgment, that is, feature quantities used for linear discrimination, as the feature quantities to be calculated.

[0068] As described above, a discriminant that can achieve a high detection rate of defective products and a low overdetection rate of non-defective products is calculated based on a combination of various feature quantities obtained in advance from a large number of actual device data. This discriminant is also stored in the inspection device. For this reason, the feature quantities used for linear discrimination are also known by the inspection device, and the feature quantities used for linear discrimination are calculated from the measurement results of electrical characteristics.

[0069] For example, if the Gini coefficient calculated by selecting five consecutive nodes, node 2 to node 6, on the logarithmic scale shown in Fig. 7 and the slope of the line connecting the two selected nodes, node 3 and node 5, on the linear scale, are features to be used in the discriminant, they are calculated. Of course, it is possible to calculate all of the 50 feature amounts described above and extract the feature amount to be used in the discriminant from among them, but since the feature amounts to be used in the discriminant are known in advance on the inspection device side, the calculation load can be reduced by calculating only the necessary feature amounts.

[0070] In the next step S130, a pass / fail judgment is performed. Specifically, for each SiC semiconductor device, the two calculated feature quantities are substituted for x and y in the discriminant y≧-ax+b as the x-axis and y-axis values ​​in a two-axis coordinate system. If the discriminant satisfies the condition, the device is judged as a pass / fail product, and if y<-ax+b and the discriminant is not satisfied, the device is judged as a fail / fail product. SiC semiconductor devices judged as fail / fail products by this pass / fail judgment are rejected and disposed of, while SiC semiconductor devices judged as pass / fail products are moved to a process of shipping them as products.

[0071] By using such a quality judgment based on the discriminant, it is possible to increase the detection rate of NG products while reducing the overdetection rate. Therefore, it is possible to perform a more appropriate quality judgment and reject defective products, which prevents products that should be rejected from being commercialized, and thus makes it possible to manufacture highly reliable SiC semiconductor devices. It is also possible to improve the yield by suppressing overdetection.

[0072] (Other embodiments) Although the present disclosure has been described based on the above-described embodiment, it is not limited to the embodiment, and includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0073] For example, in the above embodiment, an electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id when a reverse bias is applied while the vertical MOSFET is off is used to extract the feature amount, but other electrical characteristic waveforms may be used. As an example, an electrical characteristic waveform showing the relationship between the gate voltage Vg and the drain current Id when the gate voltage Vg is applied to turn on the vertical MOSFET 30 may be used. Also, an electrical characteristic waveform showing the relationship between the source-drain voltage Vds and the drain current Id when the vertical MOSFET 30 is turned on may be used.

[0074] Furthermore, in the above embodiment, the number of measurement points of the electrical characteristics is six, but it is sufficient to have three or more. Also, the Gini coefficient and the slope are used as the feature amount, but only one of them may be used, or other parameters may be used. For example, the Gini coefficient is an example of a case where the graph of the electrical characteristics waveform is divided into regions divided by nodes, and the area of ​​each divided region is used as the feature amount, but other areas divided in this way can also be used as the feature amount.

[0075] Specifically, the Gini coefficient is the area S1 of the crescent-shaped portion between the equal straight line and the Lorentz curve, i.e., the graph of the electrical characteristic waveform, between the nodes, and corresponds to the sum of the areas of the regions obtained by dividing the crescent-shaped portion into nodes. In other words, the area S1 is calculated as the sum of the differences between the areas Sa1 to Sa5 shown by solid line hatching in Fig. 9 and the areas Sb1 to Sb5 shown by dashed line hatching. In other words, the area S1 is the sum of the difference between the area Sa1 of the right-angled isosceles triangle between node 1 and node 2 and the area Sb1 of the right-angled triangle, and the difference between the areas Sa2 to Sa5 of the trapezoids between adjacent nodes among node 2 to node 6 and the areas Sb2 to Sb5 of the trapezoids.

[0076] On the other hand, instead of the total area of ​​the divided areas, the area of ​​the divided regions themselves, for example, the area of ​​the crescent-shaped portion divided for each node, for example, the difference between the area Sa1 and the area Sb1, can be used as the feature amount. Also, the areas Sb1 to Sb5 of the portions other than the crescent-shaped portion for each node can be used as the feature amount.

[0077] In the above embodiment, two of the multiple feature quantities are selected, one is set as the x-axis and the other as the y-axis, and a discriminant equation for linear discrimination of the selected two axes is set to perform quality determination. Alternatively, instead of the two-axis coordinate, three of the multiple feature quantities may be selected, one as the x-axis, the other as the y-axis, and the remaining one as the z-axis, and a discriminant equation for the selected three axes may be set to perform quality determination. In this case, points corresponding to the three feature quantities are plotted on the three-axis coordinate, and the discriminant equation in the three-axis coordinate may be calculated.

[0078] In the above embodiment, a SiC semiconductor device in which a semiconductor element is formed using SiC as a semiconductor material has been described as an example, but the present disclosure can be applied to semiconductor devices made of other semiconductor materials such as GaN, Si, etc. However, since compound semiconductors such as SiC and GaN have a particularly high crystal defect density and crystal defects can become killer defects, the present disclosure is particularly suitable for application to semiconductor devices that use compound semiconductors as semiconductor materials.

[0079] In the above embodiment, the vertical MOSFET 30 has been taken as an example of a semiconductor element formed in the semiconductor device, but the present disclosure can also be applied to a semiconductor device in which other semiconductor elements, such as an IGBT, are formed. [Explanation of symbols]

[0080] 11...SiC substrate, 12...buffer layer, 13...low-concentration layer, 14...JFET portion, 15...deep layer, 16...current spreading layer, 17...base region, 18...source region, 19...contact region, 20...connection layer, 21...gate trench, 22...gate insulating film, 23...gate electrode, 24...interlayer insulating film, 24a...contact hole, 25...source electrode, 26...drain electrode, 30...vertical MOSFET, 40...built-in diode

Claims

1. After preparing a semiconductor wafer, a device formation process is performed to form a semiconductor element (S100); Measuring electrical characteristics of individual semiconductor devices to be chipped from the semiconductor wafer (S110); calculating at least one of an area of ​​an arbitrary region of a graph of an electrical characteristic waveform obtained by measuring the electrical characteristics and a slope of a line connecting any two points of the graph as a characteristic quantity (S120); and determining whether each of the semiconductor devices is good or bad based on the characteristic amount obtained by calculating the characteristic amount and a discriminant (S130).

2. In the calculation of the feature amount, the graph is divided into a plurality of regions, and at least one of an area of ​​each divided region and a slope of a line connecting any two points on the graph is calculated as the feature amount; 2. The method of claim 1, wherein, in the pass / fail judgment, two of the feature amounts calculated in each of the regions are selected, and a formula for linearly discriminating the two selected feature amounts with respect to two axes is set as the discriminant, and the pass / fail judgment is made based on the two selected feature amounts and the discriminant.

3. 3 . The method of claim 2 , wherein the feature amount is calculated by dividing the graph into a plurality of regions and calculating an area of ​​each region as the feature amount, and the area is calculated as a Gini coefficient. 4 .

4. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the steps of: selecting three or more nodes from among the plurality of nodes, defining each point that divides the graph into a plurality of regions as a node; defining a node having the smallest absolute value of an electrical characteristic among the three or more selected nodes as a MIN node; defining a node having the largest absolute value of an electrical characteristic among the three or more selected nodes as a MAX node; normalizing the electrical characteristic at the MIN node to 0 and the electrical characteristic at the MAX node to 1; and calculating, as the characteristic amount of the area of ​​each of the regions, a value twice the area enclosed by an equal straight line where y = x on the two axes and a Lorentz curve connecting the selected three or more nodes.

5. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the discriminant is calculated as a mathematical formula for discriminating between the pass-put product and the fail-put product from actual device data obtained by calculating the feature amounts for a plurality of the semiconductor devices manufactured in advance and inspecting the semiconductor devices to determine whether the semiconductor devices are pass-put products or fail-put products.

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