Semiconductor device

Abstract

To provide a semiconductor device including a backside power delivery network (BSPDN).SOLUTION: A semiconductor device comprises: a substrate comprising a first surface and a second surface opposite to each other; a first active pattern on the first surface of the substrate; a first gate structure intersecting the first active pattern; and a first back wiring pattern and a second back wiring pattern that are disposed on the second surface of the substrate at the level equal to each other. The first back wiring pattern comprises: a first extension portion and a second extension portion each extending in a first direction; and a connection portion that extends in a second direction intersecting the first direction and connects the first extension portion with the second extension portion. The second back wiring pattern is separated from the first extension portion in the second direction, and separated from the connection portion in the first direction.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a backside power delivery network (BSPDN). [Background technology]

[0002] In the electronics industry, semiconductor devices have been gaining attention as important elements due to their characteristics such as miniaturization, multi-functionality, and / or low manufacturing cost. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include memory elements and logic elements.

[0003] As the electronics industry develops to a high level, there are increasing demands on the characteristics of semiconductor devices, such as high reliability, high speed, and / or multi-function. To meet such required characteristics, the structures within the semiconductor devices are becoming more and more complex and highly integrated. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical problem to be solved by the present invention is to provide a semiconductor device with improved design freedom and integration density.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] In order to achieve the above technical objective, a semiconductor device according to some embodiments includes a substrate having a first surface and a second surface opposite each other, a first active pattern on the first surface of the substrate, a first gate structure intersecting the first active pattern, and a first back surface wiring pattern and a second back surface wiring pattern arranged at the same level as each other on the second surface of the substrate, wherein the first back surface wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction and connecting the first extension portion and the second extension portion, and the second back surface wiring pattern is spaced apart from the first extension portion in the second direction and from the connecting portion in the first direction.

[0007] In order to achieve the above technical objective, a semiconductor device according to some embodiments includes a substrate having a first surface and a second surface opposite to each other, a first active pattern and a second active pattern extending side by side on the first surface of the substrate, a first gate structure intersecting the first active pattern and the second active pattern, first to third back surface wiring patterns disposed at the same level and spaced apart from each other on the second surface of the substrate, a first back surface source / drain contact connecting a first source / drain region of the first active pattern and the first back surface wiring pattern, and a second source / drain contact of the second active pattern. the first back surface wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction and connecting the first extension portion and the second extension portion, the connecting portion being interposed between the second back surface wiring pattern and the third back surface wiring pattern in the first direction.

[0008] In order to achieve the above technical objective, a semiconductor device according to some embodiments includes a substrate having a first surface and a second surface opposite to each other, a first active pattern on the first surface of the substrate, a first gate structure and a second gate structure extending parallel to each other and intersecting the first active pattern, a first source / drain contact between the first gate structure and the second gate structure and connected to the first active pattern, first to third back surface wiring patterns disposed at the same level and spaced apart from each other on the second surface of the substrate, and a first gate structure disposed between the first source / drain contact and connecting the first active pattern to the first back surface wiring pattern. a second gate structure is disposed between the contact and the first source / drain contact; second back surface wiring pattern connecting the first active pattern and the second back surface wiring pattern; a fourth back surface wiring pattern on a second surface of the substrate, separated from the substrate by the first to third back surface wiring patterns; and a first back surface via pattern connecting the second back surface wiring pattern and the fourth back surface wiring pattern, the first back surface wiring pattern including a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction and connecting the first extension portion and the second extension portion, the connecting portion being interposed between the second back surface wiring pattern and the third back surface wiring pattern in the first direction.

[0009] In order to achieve the above technical objective, a semiconductor device according to some embodiments includes a substrate having a first surface and a second surface opposite to each other, first to fourth active patterns extending side by side on the first surface of the substrate, a first gate structure intersecting the first active pattern and the second active pattern, a second gate structure extending side by side with the first gate structure and intersecting the first active pattern, a third gate structure spaced apart from the first gate structure and intersecting the fourth active pattern, a fourth gate structure extending side by side with the third gate structure and intersecting the third active pattern and the fourth active pattern, a first source / drain contact connecting the first active pattern and the second active pattern between the first gate structure and the second gate structure, a second source / drain contact connecting the third active pattern and the fourth active pattern between the third gate structure and the fourth gate structure, a first shared contact connecting the first gate structure and the second source / drain contact, a fourth gate structure. a second shared contact connecting the gate structure and the first source / drain contact; a first gate structure disposed between the first source / drain contact and connected to the first active pattern through the substrate; a second gate structure disposed between the second source / drain contact and connected to the fourth active pattern through the substrate; and first to third back surface wiring patterns disposed at the same level and spaced apart from each other on a second surface of the substrate, the first back surface wiring patterns including first and second extensions each extending in a first direction and a connecting portion extending in a second direction intersecting the first direction and connecting the first extensions and the second extensions, the connecting portion being interposed between the second and third back surface wiring patterns in the first direction, and the first back surface source / drain contact and the second back surface source / drain contact being connected to the first back surface wiring pattern.

[0010] Specific details of other embodiments are included in the detailed description and drawings. [Brief description of the drawings]

[0011] [Figure 1]1 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. [Diagram 2] 1 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. [Diagram 3] FIG. 3 is a schematic cross-sectional view taken along line AA in FIG. 2. [Figure 4] FIG. 3 is a schematic cross-sectional view taken along line BB in FIG. 2. [Diagram 5] FIG. 3 is a schematic cross-sectional view taken along CC in FIG. 2. [Figure 6] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 7] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 8] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 9] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 10] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 11] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 12] 1 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. [Figure 13] FIG. 13 is a schematic cross-sectional view taken along line DD in FIG. 12. [Figure 14] FIG. 13 is a schematic cross-sectional view taken along the line EE of FIG. 12. [Figure 15] FIG. 13 is a schematic cross-sectional view taken along line FF in FIG. 12. [Figure 16] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 17]1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 18] 1 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. [Figure 19] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 20] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Figure 21] 1 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. [Figure 22] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. [Diagram 23] 1A to 1C are various exemplary layout diagrams illustrating semiconductor devices according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] In this specification, the terms "first" and "second" are used to describe various elements or components, but these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another element or component. Therefore, a first element or component referred to below may be a second element or component within the technical concept of the present invention.

[0013] Hereinafter, a semiconductor device according to an exemplary embodiment will be described with reference to Figures 1 to 23. Although the embodiments disclosed below are described focusing on a static random access memory (SRAM) device as a semiconductor device, this is merely an example. Those skilled in the art will understand that the technical concept of the present invention can be applied not only to an SRAM device but also to various other semiconductor devices such as a logic device.

[0014] FIG. 1 is an exemplary circuit diagram illustrating a semiconductor device according to some embodiments.

[0015] Referring to FIG. 1, a semiconductor device according to some embodiments includes a power supply node V DD and the ground node V SS The input terminal of the first pass transistor PS1 is connected to an output node of the inverter INV2, and the output terminal of the inverter INV2 is connected to an output node of the inverter INV2.

[0016] The first pass transistor PS1 may be coupled to a bit line BL, and the second pass transistor PS2 may be coupled to a complementary bit line / BL. The gates of the first pass transistor PS1 and the second pass transistor PS2 may be coupled to a word line WL.

[0017] To configure a latch circuit, an input node of the first inverter INV1 may be connected to an output node of the second inverter INV2, and an input node of the second inverter INV2 may be connected to an output node of the first inverter INV1.

[0018] The first inverter INV1 may include a series-connected first pull-up transistor PU1 and a first pull-down transistor PD1, and the second inverter INV2 may include a series-connected second pull-up transistor PU2 and a second pull-down transistor PD2, where the first pull-up transistor PU1 and the second pull-up transistor PU2 may be PFETs, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NFETs.

[0019] Fig. 2 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. Fig. 3 is a schematic cross-sectional view taken along line AA in Fig. 2. Fig. 4 is a schematic cross-sectional view taken along line BB in Fig. 2. Fig. 5 is a schematic cross-sectional view taken along line CC in Fig. 2.

[0020] 1 to 5, a semiconductor device according to some embodiments includes a device region DR, a front region FR, and a back region BR.

[0021] The element region DR may include a substrate 100, a field insulating film 105, first to fourth active patterns AP1 to AP4, first to fourth gate structures GS1 to GS4, source / drain contacts 171 to 178, a first shared contact NC1, a second shared contact NC2, a first interlayer insulating film ID1 and a second interlayer insulating film ID2.

[0022] The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 can be a silicon substrate or can include other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 can be an epitaxial layer formed on a base substrate.

[0023] In some embodiments, the substrate 100 may be an insulating substrate including an insulating material. For example, the substrate 100 may include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon oxycarbonitride, and combinations thereof. As an example, the substrate 100 may include a silicon oxide film.

[0024] The substrate 100 may include a first surface 100a and a second surface 100b that are opposite to each other. In the following embodiments, the first surface 100a may also be referred to as the front side of the substrate 100, and the second surface 100b may also be referred to as the back side of the substrate 100.

[0025] The first to fourth active patterns AP1 to AP4 may be formed on the first surface 100a of the substrate 100. The first to fourth active patterns AP1 to AP4 may be spaced apart from each other and extend in parallel in a first direction Y. For example, the first to fourth active patterns AP1 to AP4 may each extend elongated in the first direction Y and be sequentially arranged along a second direction X intersecting the first direction Y.

[0026] The first to fourth active patterns AP1 to AP4 may each include silicon (Si) or germanium (Ge) which is an element semiconductor material. Alternatively, the first to fourth active patterns AP1 to AP4 may each include a compound semiconductor, for example, a IV-IV group compound semiconductor or a III-V group compound semiconductor. The IV-IV group compound semiconductor may be, for example, a binary compound, a ternary compound, or a compound doped with a IV group element, which includes at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). The III-V group compound semiconductor may be, for example, one of a binary compound, a ternary compound, and a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In), which are group III elements, with at least one of phosphorus (P), arsenic (As), and antimony (Sb), which are group V elements.

[0027] In some embodiments, the first active pattern AP1 and the fourth active pattern AP4 may be used as channel regions of an NFET, and the second active pattern AP2 and the third active pattern AP3 may be used as channel regions of a PFET.

[0028] In some embodiments, each of the first to fourth active patterns AP1 to AP4 may include a plurality of bridge patterns (e.g., first to third bridge patterns 111 to 113) that are stacked in sequence on the substrate 100 and spaced apart from each other. Such first to fourth active patterns AP1 to AP4 may be used as a channel region of an MBCFET (registered trademark) including a multi-bridge channel. The number of bridge patterns included in each of the first to fourth active patterns AP1 to AP4 is merely an example and is not limited to that shown in the drawings.

[0029] In some embodiments, a fin-type pattern 110F may be formed between the substrate 100 and the first bridge pattern 111. The fin-type pattern 110F may protrude from the first surface 100a of the substrate 100 and extend in a first direction Y. In some embodiments, the fin-type pattern 110F may be an insulating pattern including an insulating material.

[0030] A field insulating film 105 may be formed on the substrate 100. In some embodiments, the field insulating film 105 may cover at least a portion of the side surface of the fin-type pattern 110F. The field insulating film 105 may include, for example, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.

[0031] The first to fourth gate structures GS1 to GS4 may be formed on the substrate 100 and the field insulating film 105. The first to fourth gate structures GS1 to GS4 may be spaced apart from each other and may each extend long in the second direction X.

[0032] The first gate structure GS1 may cross the first active pattern AP1 and the second active pattern AP2. For example, bridge patterns 111-113 of the first active pattern AP1 and the second active pattern AP2 may extend in the first direction Y and pass through the first gate structure GS1. The first gate structure GS1 may serve as a gate of the first inverter INV1. For example, the first active pattern AP1 crossing the first gate structure GS1 may serve as a channel region of the first pull-down transistor PD1, and the second active pattern AP2 crossing the first gate structure GS1 may serve as a channel region of the first pull-up transistor PU1.

[0033] The second gate structure GS2 may be spaced apart from the first gate structure GS1 in the first direction Y. The second gate structure GS2 may extend parallel to the first gate structure GS1 and cross the first active pattern AP1. For example, the bridge patterns 111-113 of the first active pattern AP1 may extend in the first direction Y and pass through the second gate structure GS2. The second gate structure GS2 may serve as a gate of the first pass transistor PS1. For example, the first active pattern AP1 crossing the second gate structure GS2 may serve as a channel region of the first pass transistor PS1.

[0034] The third gate structure GS3 may be spaced apart from the first gate structure GS1 in the second direction X. The third gate structure GS3 may cross the fourth active pattern AP4. For example, the bridge patterns 111-113 of the fourth active pattern AP4 may extend in the first direction Y and penetrate the third gate structure GS3. The third gate structure GS3 may serve as a gate of the second pass transistor PS2. For example, the fourth active pattern AP4 crossing the third gate structure GS3 may serve as a channel region of the second pass transistor PS2.

[0035] The fourth gate structure GS4 may be spaced apart from the second gate structure GS2 in the second direction X. The fourth gate structure GS4 may extend parallel to the third gate structure GS3 and cross the third active pattern AP3 and the fourth active pattern AP4. For example, the bridge patterns 111-113 of the third active pattern AP3 and the fourth active pattern AP4 may extend in the first direction Y and pass through the fourth gate structure GS4. The fourth gate structure GS4 may serve as a gate of the second inverter INV2. For example, the fourth active pattern AP4 crossing the fourth gate structure GS4 may serve as a channel region of the second pull-down transistor PD2, and the third active pattern AP3 crossing the fourth gate structure GS4 may serve as a channel region of the second pull-up transistor PU2.

[0036] In some embodiments, the first to fourth gate structures GS1-GS4 may be separated by a separation pattern GC. For example, the separation pattern GC may extend in the second direction X between the third active pattern AP3 and the fourth active pattern AP4 to separate the first gate structure GS1 and the third gate structure GS3. For example, the separation pattern GC may extend in the second direction X between the first active pattern AP1 and the second active pattern AP2 to separate the second gate structure GS2 and the fourth gate structure GS4.

[0037] The separation pattern GC may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

[0038] Each of the first to fourth gate structures GS1 to GS4 may include a gate dielectric layer 120, a gate electrode 130, a gate spacer 140 and a gate capping layer 150.

[0039] The gate dielectric layer 120 may be interposed between each of the first to fourth active patterns AP1 to AP4 and the gate electrode 130. The gate dielectric layer 120 may include at least one of a dielectric material, for example, silicon oxide, silicon oxynitride, silicon nitride, or a high-k material having a dielectric constant larger than that of silicon oxide. The high-k material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is not limited thereto.

[0040] The gate electrode 130 may extend in the second direction X and cross the first to fourth active patterns AP1 to AP4. The bridge patterns 111 to 113 of the first to fourth active patterns AP1 to AP4 may extend in the first direction Y and penetrate the gate electrode 130. The gate electrode 130 may include at least one of a conductive material, for example, but is not limited to, TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and combinations thereof. The gate electrode 130 may be formed by a replacement process, but is not limited to this.

[0041] Although the gate electrode 130 is shown as a single layer, this is merely an example, and the gate electrode 130 may be a multi-layer formed by stacking a plurality of conductive layers. For example, the gate electrode 130 may include a work function adjustment layer for adjusting a work function, and a filling conductive layer for filling a space formed by the work function adjustment layer. The work function adjustment layer may include at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive layer may include W or Al, for example.

[0042] The gate spacer 140 may extend along a side surface of the gate electrode 130. The bridge patterns 111-113 of the first to fourth active patterns AP1-AP4 may extend in the first direction Y and penetrate the gate spacer 140. The gate spacer 140 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon oxycarbonitride, and combinations thereof.

[0043] In some embodiments, the gate dielectric layer 120 may include an interface layer 122 and a high dielectric layer 124 sequentially stacked on the first to fourth active patterns AP1 to AP4.

[0044] The interface film 122 may surround the periphery of each of the bridge patterns 111-113. For example, the interface film 122 may conformally extend along the periphery of each of the bridge patterns 111-113. In some embodiments, the interface film 122 may include an oxide film formed by oxidizing the surface of each of the bridge patterns 111-113. As an example, when each of the bridge patterns 111-113 includes silicon (Si), the interface film 122 may include a silicon oxide film.

[0045] The high dielectric film 124 may surround the periphery of the interface film 122. Also, a part of the high dielectric film 124 may be interposed between the gate electrode 130 and the gate spacer 140. For example, the high dielectric film 124 may conformally extend in accordance with the profile of the periphery of the interface film 122 and the inner surface of the gate spacer 140. Also, the high dielectric film 124 may further extend along the upper surface of the field insulating film 105.

[0046] In some embodiments, the high-k dielectric film 124 may include a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may be, for example, hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), strontium titanium oxide (SrTiO 3 ), lanthanum aluminum oxide (LaAlO 3 ), yttrium oxide (Y 2 O 3 ), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La 2 O x N y ), aluminum oxynitride (Al 2 O x N y ), titanium oxynitride (TiO x N y ), strontium titanium oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y 2 O x N y ) and combinations thereof, but are not limited thereto.

[0047] The gate capping layer 150 may extend along an upper surface of the gate electrode 130. The gate capping layer 150 may include an insulating material, such as, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonitride, and combinations thereof.

[0048] The first to fourth active patterns AP1 to AP4 may include first to fourth source / drain regions 161 to 164. The first to fourth source / drain regions 161 to 164 may be formed in the first to fourth active patterns AP1 to AP4 on side surfaces of the first to fourth gate structures GS1 to GS4. The bridge patterns 111 to 113 of the first to fourth active patterns AP1 to AP4 may be connected to the first to fourth source / drain regions 161 to 164 through the gate electrode 130 and the gate spacer 140. The first to fourth source / drain regions 161 to 164 may be electrically isolated from the gate electrode 130 by the gate spacer 140.

[0049] In some embodiments, the first through fourth source / drain regions 161-164 may each include an epitaxial layer doped with impurities. For example, the first through fourth source / drain regions 161-164 may each include an epitaxial pattern grown from the first through fourth active patterns AP1-AP4 by an epitaxial growth method.

[0050] The source / drain contacts 171-178 may be connected to the first to fourth active patterns AP1-AP4. For example, the source / drain contacts 171-178 may be connected to the first to fourth source / drain regions 161-164. The shapes and arrangements of the source / drain contacts 171-178 are merely examples and are not limited to those shown in the drawings.

[0051] For example, first to third source / drain contacts 171-173 may be formed, each connected to the first source / drain region 161 of the first active pattern AP1. The first to third source / drain contacts 171-173 may be sequentially arranged along the first direction Y. The second source / drain contact 172 may be interposed between the first gate structure GS1 and the second gate structure GS2. The first gate structure GS1 may be interposed between the first source / drain contact 171 and the second source / drain contact 172. The second gate structure GS2 may be interposed between the second source / drain contact 172 and the third source / drain contact 173.

[0052] For example, second and fourth source / drain contacts 172, 174 may be formed, each connected to the second source / drain region 162 of the second active pattern AP2. The second source / drain contact 172 may extend in the second direction X to connect the first source / drain region 161 of the first active pattern AP1 and the second source / drain region 162 of the second active pattern AP2. The first gate structure GS1 may be interposed between the second source / drain contact 172 and the fourth source / drain contact 174.

[0053] For example, sixth to eighth source / drain contacts 176-178 may be formed, each connected to the fourth source / drain region 164 of the fourth active pattern AP4. The sixth to eighth source / drain contacts 176-178 may be arranged in sequence along the first direction Y. The seventh source / drain contact 177 may be interposed between the third gate structure GS3 and the fourth gate structure GS4. The third gate structure GS3 may be interposed between the sixth source / drain contact 176 and the seventh source / drain contact 177. The fourth gate structure GS4 may be interposed between the seventh source / drain contact 177 and the eighth source / drain contact 178.

[0054] For example, fifth and seventh source / drain contacts 175, 177 may be formed to be connected to the third source / drain region 163 of the third active pattern AP3, respectively. The seventh source / drain contact 177 may extend in the second direction X to connect the third source / drain region 163 of the third active pattern AP3 to the fourth source / drain region 164 of the fourth active pattern AP4. A fourth gate structure GS4 may be interposed between the fifth source / drain contact 175 and the seventh source / drain contact 177.

[0055] The first shared contact NC1 may electrically connect the first gate structure GS1 and the seventh source / drain contact 177. For example, the first shared contact NC1 may extend in the first direction Y and connect the gate electrode 130 of the first gate structure GS1 and the seventh source / drain contact 177. The input node of the first inverter INV1 (i.e., the first gate structure GS1) may be connected to the output node of the second inverter INV2 (i.e., the seventh source / drain contact 177) via the first shared contact NC1.

[0056] The second shared contact NC2 may electrically connect the fourth gate structure GS4 and the second source / drain contact 172. For example, the second shared contact NC2 may extend in the first direction Y to connect the gate electrode 130 of the fourth gate structure GS4 and the second source / drain contact 172. The input node of the second inverter INV2 (i.e., the fourth gate structure GS4) may be connected to the output node of the first inverter INV1 (i.e., the second source / drain contact 172) via the second shared contact NC2.

[0057] The first interlayer insulating film ID1 may fill spaces on the side surfaces of the first to fourth gate structures GS1 to GS4. For example, the first interlayer insulating film ID1 may cover the first to fourth source / drain regions 161 to 164. The second interlayer insulating film ID2 may cover the first to fourth gate structures GS1 to GS4 and the first interlayer insulating film ID1.

[0058] The first interlayer insulating film ID1 and the second interlayer insulating film ID2 may each include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon carbonitride, silicon oxycarbonitride, and a low dielectric constant material having a dielectric constant smaller than that of silicon oxide, but are not limited thereto.

[0059] The front region FR may be formed on the first surface 100a of the substrate 100. The front region FR may include first level front wiring patterns 211-214 and a second level front wiring pattern 220. For example, a front inter-wire insulating film 200 may be formed on the second interlayer insulating film ID2. The first level front wiring patterns 211-214 and the second level front wiring pattern 220 may be formed in the front inter-wire insulating film 200 and insulated from each other.

[0060] The first level front wiring patterns 211-214 may be arranged at the same level and spaced apart from each other. The second level front wiring patterns 220 may be arranged at the same level and spaced apart from each other. In this specification, arranged at the "same level" means arranged at the same height in the third direction Z with the substrate 100 as a reference. The second level front wiring pattern 220 may be arranged at a higher level than the first level front wiring patterns 211-214. For example, the second level front wiring pattern 220 may be spaced apart from the substrate 100 in the third direction Z from the first level front wiring patterns 211-214.

[0061] In some embodiments, the first level front wiring pattern 211-214 may include a first front wiring pattern 211, a second front wiring pattern 212, a third front wiring pattern 213 and a fourth front wiring pattern 214. In some embodiments, the second level front wiring pattern 220 may include a fifth front wiring pattern 220.

[0062] The first front wiring pattern 211 may be connected to the third source / drain contact 173. For example, a first contact via 183F may be formed penetrating the second interlayer insulating film ID2 to connect the third source / drain contact 173 and the first front wiring pattern 211. The first front wiring pattern 211 may be provided as a bit line BL and connected to the first pass transistor PS1 via the third source / drain contact 173. In some embodiments, the first front wiring pattern 211 may extend long in the first direction Y.

[0063] The second front wiring pattern 212 may be connected to the sixth source / drain contact 176. For example, a second contact via 186F may be formed through the second interlayer insulating film ID2 to connect the sixth source / drain contact 176 and the second front wiring pattern 212. The second front wiring pattern 212 may be provided as a complementary bit line / BL and may be connected to the second pass transistor PS2 via the sixth source / drain contact 176. In some embodiments, the second front wiring pattern 212 may extend long in the first direction Y.

[0064] The third front wiring pattern 213 may be connected to the second gate structure GS2. For example, a first gate contact 192 may be formed through the second interlayer insulating film ID2 and the gate capping film 150 to connect the gate electrode 130 of the second gate structure GS2 to the third front wiring pattern 213.

[0065] The fourth front wiring pattern 214 may be connected to the third gate structure GS3. For example, a second gate contact 193 may be formed through the second interlayer insulating film ID2 and the gate capping film 150 to connect the gate electrode 130 of the third gate structure GS3 to the fourth front wiring pattern 214.

[0066] In some embodiments, the length over which the third front wiring pattern 213 and the fourth front wiring pattern 214 extend in the first direction Y may be smaller than the length over which the first front wiring pattern 211 and the second front wiring pattern 212 extend in the first direction Y.

[0067] The fifth front wiring pattern 220 may be connected to the third front wiring pattern 213 and the fourth front wiring pattern 214. For example, a first front via pattern 233 may be formed in the front inter-wire insulating film 200, extending in the third direction Z to connect the third front wiring pattern 213 and the fifth front wiring pattern 220. Also, for example, a second front via pattern 234 may be formed in the front inter-wire insulating film 200, extending in the third direction Z to connect the fourth front wiring pattern 214 and the fifth front wiring pattern 220. The fifth front wiring pattern 220 may be provided as a word line WL, and may be connected to the gate of the first pass transistor PS1 via the third front wiring pattern 213 and to the gate of the second pass transistor PS2 via the fourth front wiring pattern 214. In some embodiments, the fifth front wiring pattern 220 may extend long in the second direction X.

[0068] The back surface region BR may be formed on the second surface 100b of the substrate 100. The back surface region BR may include first level back surface wiring patterns 311-313 and second level back surface wiring patterns 321, 322. For example, a back surface inter-wiring insulating film 300 may be formed on the second surface 100b of the substrate 100. The first level back surface wiring patterns 311-313 and the second level back surface wiring patterns 321, 322 may be formed in the back surface inter-wiring insulating film 300 and insulated from each other.

[0069] The first level back surface wiring patterns 311-313 may be disposed at the same level and spaced apart from each other. The second level back surface wiring patterns 321, 322 may be disposed at the same level and spaced apart from each other. The second level back surface wiring patterns 321, 322 may be disposed at a higher level than the first level back surface wiring patterns 311-313. For example, the second level back surface wiring patterns 321, 322 may be spaced apart from the substrate 100 in the third direction Z from the first level back surface wiring patterns 311-313.

[0070] In some embodiments, the first level back surface wiring patterns 311-313 may include a first back surface wiring pattern 311, a second back surface wiring pattern 312, and a third back surface wiring pattern 313. In some embodiments, the second level back surface wiring patterns 321, 322 may include a fourth back surface wiring pattern 321 and a fifth back surface wiring pattern 322.

[0071] The first rear surface wiring pattern 311 may include a first extension portion 311a, a second extension portion 311b, and a connecting portion 311c. The first extension portion 311a and the second extension portion 311b may each extend in a first direction Y. The connecting portion 311c may extend in a second direction X to connect the first extension portion 311a and the second extension portion 311b.

[0072] The second back surface wiring pattern 312 may be spaced apart from the first extension portion 311a in the second direction X and from the connecting portion 311c in the first direction Y. The third back surface wiring pattern 313 may be spaced apart from the second extension portion 311b in the second direction X and from the connecting portion 311c in the first direction Y. The connecting portion 311c may be interposed between the second back surface wiring pattern 312 and the third back surface wiring pattern 313.

[0073] In some embodiments, the first extension portion 311a and the second extension portion 311b may each extend long in the first direction Y. For example, as shown, the second back surface wiring pattern 312 may be interposed between the first extension portion 311a and the second extension portion 311b in the second direction X, and the third back surface wiring pattern 313 may be interposed between the first extension portion 311a and the second extension portion 311b in the second direction X. The first extension portion 311a, the second extension portion 311b, and the connecting portion 311c may be integrally formed to provide the first back surface wiring pattern 311 having a generally "H" shape. The second back surface wiring pattern 312 and the third back surface wiring pattern 313 may each be an island-like pattern disposed in an empty area of ​​the first back surface wiring pattern 311 having a generally "H" shape.

[0074] The first backside wiring pattern 311 may be connected to the first source / drain region 161 of the first active pattern AP1, in which the first gate structure GS1 is disposed between the first backside wiring pattern 311 and the second source / drain contact 172. For example, a first backside source / drain contact 181B may be formed between the first gate structure GS1 and the second source / drain contact 172. The first backside source / drain contact 181B may penetrate the substrate 100 and connect the first source / drain region 161 of the first active pattern AP1 to the first extension portion 311a. The first backside wiring pattern 311 may be connected to a ground node V for applying a first power supply voltage to the first pull-down transistor PD1. SS It can be provided as.

[0075] In addition, the first backside wiring pattern 311 may be connected to the fourth source / drain region 164 of the fourth active pattern AP4, in which the fourth gate structure GS4 is disposed between the first backside wiring pattern 311 and the seventh source / drain contact 177. For example, a second backside source / drain contact 188B, in which the fourth gate structure GS4 is disposed between the first backside wiring pattern 311 and the seventh source / drain contact 177, may be formed. The second backside source / drain contact 188B may penetrate the substrate 100 and connect the fourth source / drain region 164 of the fourth active pattern AP4 to the second extension 311b. The first backside wiring pattern 311 may be connected to a ground node V SS It can be provided as.

[0076] The second back surface wiring pattern 312 may be connected to the second source / drain region 162 of the second active pattern AP2, in which the first gate structure GS1 is disposed between the second source / drain contact 172. For example, a third back surface source / drain contact 184B may be formed in which the first gate structure GS1 is disposed between the second source / drain contact 172. The third back surface source / drain contact 184B may penetrate the substrate 100 to connect the second source / drain region 162 of the second active pattern AP2 and the second back surface wiring pattern 312.

[0077] The third back surface wiring pattern 313 may be connected to the third source / drain region 163 of the third active pattern AP3, in which the fourth gate structure GS4 is disposed between the seventh source / drain contact 177. For example, a fourth back surface source / drain contact 185B may be formed in which the fourth gate structure GS4 is disposed between the seventh source / drain contact 177. The fourth back surface source / drain contact 185B may penetrate the substrate 100 to connect the third source / drain region 163 of the third active pattern AP3 and the third back surface wiring pattern 313.

[0078] The fourth back surface wiring pattern 321 may be connected to the second back surface wiring pattern 312. For example, a first back surface via pattern 332 may be formed in the back surface inter-wiring insulating film 300, extending in the third direction Z to connect the second back surface wiring pattern 312 and the fourth back surface wiring pattern 321. The fourth back surface wiring pattern 321 may be connected to a power supply node V DD In some embodiments, the fourth rear wiring pattern 321 may extend long in the second direction X.

[0079] The fifth back surface wiring pattern 322 may be connected to the third back surface wiring pattern 313. For example, a second back surface via pattern 333 may be formed in the back surface inter-wiring insulating film 300, extending in the third direction Z to connect the third back surface wiring pattern 313 and the fifth back surface wiring pattern 322. The fifth back surface wiring pattern 322 may be connected to a power supply node V DD In some embodiments, the fifth rear wiring pattern 322 may extend long in the second direction X.

[0080] 6 to 11 are various exemplary layout diagrams for explaining semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 5 will be briefly explained or omitted.

[0081] Referring to Figures 1 and 6, in some embodiments of a semiconductor device, the first active pattern AP1 and the fourth active pattern AP4 can be used as channel regions of a PFET, and the second active pattern AP2 and the third active pattern AP3 can be used as channel regions of an NFET.

[0082] A first active pattern AP1 intersecting the first gate structure GS1 may be provided as a channel region of the first pull-up transistor PU1, and a second active pattern AP2 intersecting the first gate structure GS1 may be provided as a channel region of the first pull-down transistor PD1.

[0083] The fourth active pattern AP4 intersecting with the fourth gate structure GS4 may be provided as a channel region of the second pull-up transistor PU2, and the third active pattern AP3 intersecting with the fourth gate structure GS4 may be provided as a channel region of the second pull-down transistor PD2.

[0084] The first back surface wiring pattern 311 is connected to a power supply node V DD It can be provided as.

[0085] The fourth back surface wiring pattern 321 is connected to a ground node V which applies the first power supply voltage to the first pull-down transistor PD1 via the second back surface wiring pattern 312. SS It can be provided as.

[0086] The fifth back surface wiring pattern 322 is connected to a ground node V SS It can be provided as.

[0087] 1 and 7, semiconductor devices according to some embodiments may include source / drain contacts 172, 173, 176, and 177.

[0088] The source / drain contacts 172, 173, 176, and 177 do not have to overlap with the back surface source / drain contacts 181B, 184B, 185B, and 188B in the third direction Z. For example, the first source / drain contact 171, the fourth source / drain contact 174, the fifth source / drain contact 175, and the eighth source / drain contact 178 in FIG. 2 are dummy source / drain contacts and can be omitted.

[0089] 1 and 8, a semiconductor device according to some embodiments may include a second level backside wiring pattern 323 including a sixth backside wiring pattern 323. As shown in FIG.

[0090] The sixth back surface wiring pattern 323 may be connected to the second back surface wiring pattern 312 and the third back surface wiring pattern 313. For example, the first back surface via pattern 332 may connect the second back surface wiring pattern 312 and the sixth back surface wiring pattern 323, and the second back surface via pattern 333 may connect the third back surface wiring pattern 313 and the sixth back surface wiring pattern 323. The sixth back surface wiring pattern 323 is connected to a power supply node V DD In some embodiments, the sixth rear wiring pattern 323 may extend long in the first direction Y.

[0091] 1 and 9, a semiconductor device according to some embodiments may include first level front wiring patterns 211-215 including a sixth front wiring pattern 215.

[0092] The sixth front wiring pattern 215 may be connected to the fourth source / drain contact 174 and the fifth source / drain contact 175. For example, a third contact via 184F may be formed to connect the fourth source / drain contact 174 and the sixth front wiring pattern 215. Also, for example, a fourth contact via 185F may be formed to connect the fifth source / drain contact 175 and the sixth front wiring pattern 215. The sixth front wiring pattern 215 is connected to a power supply node V DD In some embodiments, the sixth front wiring pattern 215 may extend long in the first direction Y.

[0093] 1 and 10, in a semiconductor device according to some embodiments, the first extension portion 311a and the second extension portion 311b may extend in opposite directions from each other about the connection portion 311c.

[0094] For example, as shown in the figure, the second back surface wiring pattern 312 may not overlap with the second extension portion 311b in the second direction X, and the third back surface wiring pattern 313 may not overlap with the first extension portion 311a in the second direction X. The first extension portion 311a, the second extension portion 311b, and the connecting portion 311c may be integrally formed to provide the first back surface wiring pattern 311 having a generally "right-angled Z" shape. The second back surface wiring pattern 312 and the third back surface wiring pattern 313 may each be an island-like pattern disposed in an empty area of ​​the first back surface wiring pattern 311 having a generally "right-angled Z" shape.

[0095] In some embodiments, a portion of the second rear wiring pattern 312 may overlap with the second extension portion 311b in the first direction Y. In some embodiments, a portion of the third rear wiring pattern 313 may overlap with the first extension portion 311a in the first direction Y.

[0096] 1 and 11, a semiconductor device according to some embodiments may include first level back surface wiring patterns 311-313 including a first back surface wiring pattern 311, and a second level back surface wiring pattern 323 including a sixth back surface wiring pattern 323. The first back surface wiring pattern 311 is similar to the content described above with reference to Fig. 10, and therefore a detailed description thereof will be omitted below. The sixth back surface wiring pattern 323 is similar to the content described above with reference to Fig. 8, and therefore a detailed description thereof will be omitted below.

[0097] Fig. 12 is an exemplary layout diagram for explaining a semiconductor device according to some embodiments. Fig. 13 is a schematic cross-sectional view taken along line DD in Fig. 12. Fig. 14 is a schematic cross-sectional view taken along line EE in Fig. 12. Fig. 15 is a schematic cross-sectional view taken along line FF in Fig. 12. For convenience of explanation, parts that overlap with the contents described above with reference to Figs. 1 to 11 will be briefly explained or omitted.

[0098] Referring to Figures 1, 12 to 15, a semiconductor device according to some embodiments may include first level front wiring patterns 213-215, a second level front wiring pattern 220, first level back wiring patterns 311-313 and second level back wiring patterns 324, 325.

[0099] The first level front wiring patterns 213-215 may include the third front wiring pattern 213, the fourth front wiring pattern 214, and the sixth front wiring pattern 215. For example, the first front wiring pattern 211 and the second front wiring pattern 212 in FIG. 2 can be omitted. By omitting the first front wiring pattern 211 and the second front wiring pattern 212, the third front wiring pattern 213 and the fourth front wiring pattern 214 can be formed relatively large in the second direction X, respectively. The sixth front wiring pattern 215 is the same as that described above with reference to FIG. 9, and therefore a detailed description thereof will be omitted below.

[0100] The first level back surface wiring patterns 311-313 may include a first back surface wiring pattern 311, a second back surface wiring pattern 312, and a third back surface wiring pattern 313. The second level back surface wiring patterns 324, 325 may include a seventh back surface wiring pattern 324 and an eighth back surface wiring pattern 325. The first back surface wiring pattern 311 is similar to the content described above with reference to FIG. 10, and therefore a detailed description thereof will be omitted below.

[0101] The second back surface wiring pattern 312 may be connected to the fourth source / drain region 164 of the fourth active pattern AP4, in which the third gate structure GS3 is disposed between the seventh source / drain contact 177. For example, a fifth back surface source / drain contact 186B may be formed, in which the third gate structure GS3 is disposed between the seventh source / drain contact 177. The fifth back surface source / drain contact 186B may penetrate the substrate 100 to connect the fourth source / drain region 164 of the fourth active pattern AP4 and the second back surface wiring pattern 312.

[0102] The third back surface wiring pattern 313 may be connected to the first source / drain region 161 of the first active pattern AP1, between which the second gate structure GS2 is disposed and the second source / drain contact 172. For example, a sixth back surface source / drain contact 183B may be formed between which the second gate structure GS2 is disposed and the second source / drain contact 172. The sixth back surface source / drain contact 183B may penetrate the substrate 100 to connect the first source / drain region 161 of the first active pattern AP1 and the third back surface wiring pattern 313.

[0103] The seventh back surface wiring pattern 324 may be connected to the third back surface wiring pattern 313. For example, the second back surface via pattern 333 may connect the third back surface wiring pattern 313 and the seventh back surface wiring pattern 324. The seventh back surface wiring pattern 324 may be provided as a bit line BL and may be connected to the first pass transistor PS1 via the third back surface wiring pattern 313. In some embodiments, the seventh back surface wiring pattern 324 may extend long in the first direction Y.

[0104] The eighth back surface wiring pattern 325 may be connected to the second back surface wiring pattern 312. For example, the first back surface via pattern 332 may connect the second back surface wiring pattern 312 and the eighth back surface wiring pattern 325. The eighth back surface wiring pattern 325 may be provided as a complementary bit line / BL and may be connected to the second pass transistor PS2 via the second back surface wiring pattern 312. In some embodiments, the eighth back surface wiring pattern 325 may extend long in the first direction Y.

[0105] 16 and 17 are various exemplary layout diagrams for explaining semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 15 will be briefly explained or omitted.

[0106] Referring to Figures 1 and 16, in some embodiments of a semiconductor device, the first active pattern AP1 and the fourth active pattern AP4 can be used as channel regions of a PFET, and the second active pattern AP2 and the third active pattern AP3 can be used as channel regions of an NFET.

[0107] A first active pattern AP1 intersecting the first gate structure GS1 may be provided as a channel region of the first pull-up transistor PU1, and a second active pattern AP2 intersecting the first gate structure GS1 may be provided as a channel region of the first pull-down transistor PD1.

[0108] The fourth active pattern AP4 intersecting with the fourth gate structure GS4 may be provided as a channel region of the second pull-up transistor PU2, and the third active pattern AP3 intersecting with the fourth gate structure GS4 may be provided as a channel region of the second pull-down transistor PD2.

[0109] The sixth front wiring pattern 215 is connected to a ground node V 1 , which applies the first power supply voltage to the first pull-down transistor PD1 and the second pull-down transistor PD2 through the fourth source / drain contact 174 and the fifth source / drain contact 175. SS It can be provided as.

[0110] The first back surface wiring pattern 311 is connected to a power supply node V DD It can be provided as.

[0111] 1 and 17, semiconductor devices according to some embodiments may include source / drain contacts 172, 174, 175, and 177.

[0112] The source / drain contacts 172, 174, 175, 177 do not need to overlap with the back surface source / drain contacts 181B, 183B, 186B, 188B in the third direction Z. For example, the first source / drain contact 171, the third source / drain contact 173, the sixth source / drain contact 176, and the eighth source / drain contact 178 in FIG. 12 are dummy source / drain contacts and can be omitted.

[0113] 18 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with the contents described above with reference to FIG. 1 will be briefly explained or omitted.

[0114] Referring to FIG. 18, a semiconductor device according to some embodiments includes a lead-out bit line RBL and a ground node V SS The second readout transistor PR2 is connected in series between the first readout transistor PR1 and the second readout transistor PR2.

[0115] The first readout transistor PR1 may be connected to a readout bit line RBL, the gate of the first readout transistor PR1 may be connected to a readout word line RWL, and the gate of the second readout transistor PR2 may be connected to an output node of the second inverter INV2.

[0116] 19 and 20 are various exemplary layout diagrams for explaining semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 18 will be briefly explained or omitted.

[0117] 18 to 20, a semiconductor device according to some embodiments may further include a fifth active pattern AP5, a fifth gate structure GS5, and ninth to eleventh source / drain contacts 571 to 573.

[0118] The fifth active pattern AP5 may extend parallel to the first to fourth active patterns AP1 to AP4. The first gate structure GS1 may intersect with the first active pattern AP1, the second active pattern AP2 and the fifth active pattern AP5. The first gate structure GS1 may serve as a gate of the second readout transistor PR2. For example, the fifth active pattern AP5 intersecting with the first gate structure GS1 may serve as a channel region of the second readout transistor PR2.

[0119] The fifth gate structure GS5 may be spaced apart from the first gate structure GS1 in the first direction Y. Also, the fifth gate structure GS5 may be spaced apart from the second gate structure GS2 in the second direction X. The fifth gate structure GS5 may extend alongside the first gate structure GS1 and intersect with the fifth active pattern AP5. The fifth gate structure GS5 may serve as a gate of the first readout transistor PR1. For example, the fifth active pattern AP5 intersecting with the fifth gate structure GS5 may serve as a channel region of the first readout transistor PR1.

[0120] The ninth to eleventh source / drain contacts 571-573 may be connected to the fifth active pattern AP5. The ninth to eleventh source / drain contacts 571-573 may be sequentially arranged along the first direction Y. The tenth source / drain contact 572 may be interposed between the first gate structure GS1 and the fifth gate structure GS5. The first gate structure GS1 may be interposed between the ninth source / drain contact 571 and the tenth source / drain contact 572. The fifth gate structure GS5 may be interposed between the tenth source / drain contact 572 and the eleventh source / drain contact 573.

[0121] 18 and 19, in a semiconductor device according to some embodiments, the first level front wiring patterns 211-214, 218, 219 in the front region FR may further include a seventh front wiring pattern 218 and an eighth front wiring pattern 219, and the first level back wiring patterns 311-313, 317, 318 in the back region BR may further include a ninth back wiring pattern 317 and a tenth back wiring pattern 318. For convenience of explanation, parts that overlap with the contents described above with reference to FIG. 2 will be briefly explained or omitted.

[0122] The seventh front wiring pattern 218 may be connected to the eleventh source / drain contact 573. For example, a fifth contact via 583F may be formed to connect the eleventh source / drain contact 573 and the seventh front wiring pattern 218. The seventh front wiring pattern 218 may be provided as a lead-out bit line RBL and may be connected to the first lead-out transistor PR1 via the eleventh source / drain contact 573. In some embodiments, the seventh front wiring pattern 218 may extend long in the first direction Y.

[0123] The eighth front wiring pattern 219 may be connected to the fifth gate structure GS5. For example, a third gate contact 590 may be formed to connect the gate electrode 130 of the third gate structure GS3 to the eighth front wiring pattern 219. The eighth front wiring pattern 219 may be provided as a readout word line RWL and may be connected to the gate of the first readout transistor PR1.

[0124] The ninth back surface wiring pattern 317 may be connected to a source / drain region of the fifth active pattern AP5, in which the first gate structure GS1 is disposed between the tenth source / drain contact 572. For example, a seventh back surface source / drain contact 581B, in which the first gate structure GS1 is disposed between the tenth source / drain contact 572, may be formed. The seventh back surface source / drain contact 581B may connect the fifth active pattern AP5 and the ninth back surface wiring pattern 317. The ninth back surface wiring pattern 317 may be connected to a ground node V 1 for applying the first power supply voltage to the second readout transistor PR2. SS In some embodiments, the ninth rear wiring pattern 317 may extend long in the first direction Y.

[0125] The tenth back wiring pattern 318 may extend in the second direction X to connect the ninth back wiring pattern 317 and the first back wiring pattern 311. In some embodiments, unlike the illustrations, the tenth back wiring pattern 318 may be omitted. That is, the ninth back wiring pattern 317 may be spaced apart from the first back wiring pattern 311 in the second direction X.

[0126] 18 and 20, in a semiconductor device according to some embodiments, the first level front wiring patterns 213-215, 219 in the front region FR may further include an eighth front wiring pattern 219, the first level back wiring patterns 311-313, 317-319 in the back region BR may further include ninth to eleventh back wiring patterns 317-319, and the second level back wiring patterns 324, 325, 329 in the back region BR may further include a twelfth back wiring pattern 329. For convenience of explanation, parts that overlap with the contents described above with reference to FIG. 12 will be briefly explained or omitted.

[0127] The eighth front wiring pattern 219, the ninth back wiring pattern 317 and the tenth back wiring pattern 318 are similar to those described above with reference to FIG. 19, and therefore will not be described in detail below.

[0128] The eleventh back surface wiring pattern 319 may be coupled to the source / drain region of the fifth active pattern AP5, in which the fifth gate structure GS5 is disposed between the tenth source / drain contact 572. For example, an eighth back surface source / drain contact 583B, in which the fifth gate structure GS5 is disposed between the tenth source / drain contact 572, may be formed. The eighth back surface source / drain contact 583B may couple the fifth active pattern AP5 and the eleventh back surface wiring pattern 319.

[0129] The twelfth back surface wiring pattern 329 may be connected to the eleventh back surface wiring pattern 319. For example, a third back surface via pattern 339 may be formed extending in the third direction Z to connect the eleventh back surface wiring pattern 319 and the twelfth back surface wiring pattern 329. The twelfth back surface wiring pattern 329 may be provided as a lead-out bit line RBL and connected to the first lead-out transistor PR1 via the eleventh back surface wiring pattern 319. In some embodiments, the twelfth back surface wiring pattern 329 may extend long in the first direction Y.

[0130] 21 is an exemplary circuit diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with the contents described above with reference to FIG. 1 will be briefly explained or omitted.

[0131] Referring to FIG. 21, a semiconductor device according to some embodiments may include first to fourth unit elements D1 to D4 adjacent to each other.

[0132] The first to fourth unit elements D1 to D4 are connected to the power supply node V DD and the ground node V SS and a first pass transistor PS1 and a second pass transistor PS2 connected to output nodes of the inverters INV1 and INV2, respectively.

[0133] In some embodiments, the first to fourth unit elements D1 to D4 may share one complementary bit line / BL. For example, two bit lines BL extending parallel to each other may be formed on both sides of one complementary bit line / BL. The first unit element D1 and the third unit element D3 may be defined between one of the two bit lines BL and the complementary bit line / BL, and the second unit element D2 and the fourth unit element D4 may be defined between the other of the two bit lines BL and the complementary bit line / BL.

[0134] In some embodiments, the first unit element D1 and the second unit element D2 may share one word line WL, and the third unit element D3 and the fourth unit element D4 may share another word line WL.

[0135] 22 and 23 are various exemplary layout diagrams for explaining semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with the contents described above with reference to FIGS. 1 to 21 will be briefly explained or omitted.

[0136] 21 to 23, in a semiconductor device according to some embodiments, each of the first to fourth unit elements D1 to D4 may include an element region DR, a front region FR, and a back region BR. The first to fourth unit elements D1 to D4 in FIG. 22 are similar to those described above with reference to FIG. 2, and therefore detailed descriptions thereof will be omitted below. Also, the first to fourth unit elements D1 to D4 in FIG. 23 are similar to those described above with reference to FIG. 12, and therefore detailed descriptions thereof will be omitted below.

[0137] The first unit element D1 and the second unit element D2 may be arranged in a plane-symmetric relationship with respect to a plane intersecting the second direction X (i.e., the YZ plane). The third unit element D3 and the fourth unit element D4 may be arranged in a plane-symmetric relationship with respect to a plane intersecting the second direction X (i.e., the YZ plane). The first unit element D1 and the third unit element D3 may be arranged in a plane-symmetric relationship with respect to a plane intersecting the first direction Y (i.e., the XZ plane). The second unit element D2 and the fourth unit element D4 may be arranged in a plane-symmetric relationship with respect to a plane intersecting the first direction Y (i.e., the XZ plane).

[0138] The first extension portion 311a and the second extension portion 311b of the first back surface wiring pattern 311 may be alternately and repeatedly arranged in the second direction X. Also, the connection portion 311c of the first back surface wiring pattern 311 may be repeatedly arranged along the first direction Y between the first extension portion 311a and the second extension portion 311b. Such a first back surface wiring pattern 311 may provide a substantially mesh-shaped wiring pattern. For example, as shown in FIG. 22, the first back surface wiring pattern 311 may provide a lattice mesh-shaped wiring pattern. Or, for example, as shown in FIG. 23, the first back surface wiring pattern 311 may provide a zigzag mesh-shaped wiring pattern.

[0139] The second back surface wiring pattern 312 and the third back surface wiring pattern 313 may be alternately and repeatedly arranged in the first direction Y. The connection portions 311c of the first back surface wiring pattern 311 may be disposed between the second back surface wiring pattern 312 and the third back surface wiring pattern 313 which are repeatedly arranged. Such second back surface wiring pattern 312 and third back surface wiring pattern 313 may be disposed within openings of the first back surface wiring pattern 311 which has a roughly net-like shape.

[0140] As semiconductor devices become more and more highly integrated, individual circuit patterns are becoming finer and finer to accommodate more semiconductor devices in the same area. For this reason, research is being conducted on a backside power delivery network (BSPDN) that places a power distribution network on the back side of the substrate.

[0141] The semiconductor device according to some embodiments can improve the design freedom and integration level of the semiconductor device by efficiently using the backside power supply network. Specifically, as described above, the first backside wiring pattern 311 in the backside region BR can be provided in a generally mesh shape over a large number of elements. Such a first backside wiring pattern 311 can reduce electrical resistance compared to a wiring pattern formed separately for each element. In addition, the second backside wiring pattern 312 and the third backside wiring pattern 313 in the backside region BR can be disposed in openings of the generally mesh-shaped first backside wiring pattern 311. Such a second backside wiring pattern 312 and the third backside wiring pattern 313 can efficiently use the backside region BR by providing a connection path between other backside wiring patterns (e.g., second-level backside wiring patterns) disposed on other levels and the elements. As a result, a semiconductor device with improved design freedom and integration level can be provided.

[0142] Although the embodiment of the present invention has been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiment, and can be manufactured in various different forms, and a person having ordinary skill in the art to which the present invention belongs can understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiment is illustrative in all respects and is not limiting.

Claims

1. a substrate including opposed first and second sides; a first active pattern on the first surface of the substrate; a first gate structure intersecting the first active pattern; and a first back surface wiring pattern and a second back surface wiring pattern disposed at the same level on the second surface of the substrate; the first rear surface wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction to connect the first extension portion and the second extension portion, the second back surface wiring pattern is spaced apart from the first extension portion in the second direction and spaced apart from the connecting portion in the first direction.

2. 2. The semiconductor device of claim 1, further comprising a first backside source / drain contact penetrating the substrate and connecting a first source / drain region of the first active pattern to the first extension.

3. a second active pattern on the first surface of the substrate, the second active pattern extending alongside the first active pattern and intersecting the first gate structure; and 3. The semiconductor device of claim 2, further comprising a second backside source / drain contact penetrating the substrate and connecting a second source / drain region of the second active pattern to the second backside wiring pattern.

4. a second active pattern on the first surface of the substrate, the second active pattern extending alongside the first active pattern; a second gate structure intersecting the second active pattern; and 3. The semiconductor device of claim 2, further comprising a second backside source / drain contact penetrating the substrate and connecting a second source / drain region of the second active pattern to the second extension.

5. a first front wiring pattern and a second front wiring pattern disposed on the first surface of the substrate at the same level; The first front wiring pattern extends in the first direction, The semiconductor device according to claim 1 , wherein the second front wiring pattern is spaced apart from the first front wiring pattern in the second direction.

6. a second gate structure extending alongside the first gate structure and intersecting the first active pattern; a first source / drain contact between the first gate structure and the second gate structure and coupled to the first active pattern; and the second gate structure is disposed between the first source / drain contacts, and the second source / drain contacts are connected to the first active patterns; the second gate structure is connected to the second front wiring pattern, 6. The semiconductor device of claim 5, wherein the second source / drain contact is connected to the first front wiring pattern.

7. The semiconductor device according to claim 1 , wherein the second back surface wiring pattern is interposed between the first extension portion and the second extension portion in the second direction.

8. The semiconductor device according to claim 1 , wherein the second extension portion does not overlap the second back surface wiring pattern in the second direction.

9. a third back surface wiring pattern disposed on the second surface of the substrate at the same level as the first back surface wiring pattern and the second back surface wiring pattern; the third rear surface wiring pattern is spaced apart from the second extension portion in the second direction and from the connection portion in the first direction; The semiconductor device according to claim 1 , wherein the connecting portion is interposed between the second back surface wiring pattern and the third back surface wiring pattern.

10. a third back surface wiring pattern on the second surface of the substrate, the third back surface wiring pattern being spaced apart from the substrate by the first back surface wiring pattern and the second back surface wiring pattern; and The semiconductor device according to claim 1 , further comprising a backside via pattern connecting the second backside wiring pattern and the third backside wiring pattern.

11. a substrate including opposed first and second sides; a first active pattern and a second active pattern extending side by side on the first surface of the substrate; a first gate structure intersecting the first active pattern and the second active pattern; first, second, and third back surface wiring patterns disposed on the second surface of the substrate at the same level and spaced apart from each other; a first back surface source / drain contact connecting a first source / drain region of the first active pattern and the first back surface wiring pattern; a second backside source / drain contact connecting a second source / drain region of the second active pattern and the second backside wiring pattern; a fourth back surface wiring pattern on the second surface of the substrate, the fourth back surface wiring pattern being spaced apart from the substrate from the first to third back surface wiring patterns; and a first back surface via pattern connecting the second back surface wiring pattern and the fourth back surface wiring pattern; the first rear surface wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction to connect the first extension portion and the second extension portion, The connecting portion is interposed between the second back surface wiring pattern and the third back surface wiring pattern in the first direction.

12. The semiconductor device according to claim 11 , wherein the second back surface wiring pattern and the third back surface wiring pattern are respectively interposed between the first extension portion and the second extension portion.

13. the second rear surface wiring pattern does not overlap with the second extension portion in the second direction; The semiconductor device according to claim 11 , wherein the third back surface wiring pattern does not overlap the first extension portion in the second direction.

14. A first power supply voltage is applied to the first rear wiring pattern, 12. The semiconductor device according to claim 11, wherein a second power supply voltage different from the first power supply voltage is applied to the fourth back surface wiring pattern.

15. the second back surface wiring pattern and the third back surface wiring pattern are alternately and repeatedly arranged along the first direction, The semiconductor device according to claim 11 , wherein the connecting portion is disposed between each of the second and third back surface wiring patterns.

16. a substrate including opposed first and second sides; a first active pattern on the first surface of the substrate; a first gate structure and a second gate structure extending alongside each other and intersecting the first active pattern respectively; a first source / drain contact between the first gate structure and the second gate structure and connected to the first active pattern; first, second, and third back surface wiring patterns disposed on the second surface of the substrate at the same level and spaced apart from each other; a first backside source / drain contact between the first gate structure and the first source / drain contact, the first gate structure being disposed between the first active pattern and the first backside wiring pattern; a second backside source / drain contact between the first source / drain contact and the second gate structure, the second gate structure being disposed between the first active pattern and the second backside wiring pattern; a fourth back surface wiring pattern on the second surface of the substrate, the fourth back surface wiring pattern being spaced apart from the substrate from the first to third back surface wiring patterns; and a first back surface via pattern connecting the second back surface wiring pattern and the fourth back surface wiring pattern; the first rear surface wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction to connect the first extension portion and the second extension portion, The connecting portion is interposed between the second back surface wiring pattern and the third back surface wiring pattern in the first direction.

17. a substrate including opposed first and second sides; first through fourth active patterns extending side by side on the first surface of the substrate; a first gate structure intersecting the first active pattern and the second active pattern; a second gate structure extending alongside the first gate structure and intersecting the first active pattern; a third gate structure spaced apart from the first gate structure and intersecting the fourth active pattern; a fourth gate structure extending alongside the third gate structure and intersecting the third active pattern and the fourth active pattern; a first source / drain contact between the first gate structure and the second gate structure, the first source / drain contact connecting the first active pattern and the second active pattern; a second source / drain contact between the third gate structure and the fourth gate structure, the second source / drain contact connecting the third active pattern and the fourth active pattern; a first shared contact connecting the first gate structure and the second source / drain contact; a second shared contact connecting the fourth gate structure and the first source / drain contact; a first backside source / drain contact between the first gate structure and the first source / drain contact, the first gate structure being disposed between the first backside source / drain contact and the first active pattern through the substrate; a second backside source / drain contact between the second source / drain contact and the fourth gate structure, the second backside source / drain contact penetrating the substrate and connected to the fourth active pattern; and a first wiring pattern, a second wiring pattern, and a third wiring pattern disposed on the second surface of the substrate and spaced apart from each other and at the same level; the first rear surface wiring pattern includes a first extension portion and a second extension portion each extending in a first direction, and a connecting portion extending in a second direction intersecting the first direction to connect the first extension portion and the second extension portion, the connecting portion is interposed between the second back surface wiring pattern and the third back surface wiring pattern in the first direction, the first back surface source / drain contact and the second back surface source / drain contact are connected to the first back surface wiring pattern.

18. a third backside source / drain contact between the first gate structure and the first source / drain contact, the third backside source / drain contact penetrating the substrate and connected to the second active pattern; and the fourth gate structure is disposed between the second source / drain contacts, and the fourth backside source / drain contacts are connected to the third active patterns through the substrate; the third back surface source / drain contact is connected to the second back surface wiring pattern; The semiconductor device of claim 17 , wherein the fourth backside source / drain contact is connected to the third backside wiring pattern.

19. a portion of the second rear surface wiring pattern overlaps with the second extension portion in the first direction; The semiconductor device according to claim 17 , wherein a portion of the third back surface wiring pattern overlaps with the first extension portion in the first direction.

20. a third backside source / drain contact between the first source / drain contact and the second gate structure, the third backside source / drain contact penetrating the substrate and connected to the first active pattern; and the third gate structure is disposed between the second source / drain contacts, and the fourth backside source / drain contacts are connected to the fourth active patterns through the substrate; the third back surface source / drain contact is connected to the third back surface wiring pattern; 20. The semiconductor device of claim 19, wherein the fourth backside source / drain contact is connected to the second backside wiring pattern.

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