Semiconductor device

Abstract

To reduce defects of an oxide semiconductor film in a semiconductor device using an oxide semiconductor film, and to improve electric characteristics in a semiconductor device using an oxide semiconductor film, and to improve reliability in a semiconductor device using an oxide semiconductor film.SOLUTION: A semiconductor device has: an oxide semiconductor layer; a metal oxide layer contacted with the oxide semiconductor layer, and composed of In-M oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf); and a conductive layer contacted with the metal oxide layer, and containing copper, aluminum, gold or silver. When an atomic ratio of In and M contained in the metal oxide layer is In:M=x:y, a value of y / (x+y) is equal to or more than 0.75 and less than 1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an article, a method, or a manufacturing method. In particular, the present invention relates to a composition of matter. One embodiment relates to a semiconductor device and a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Refers to the following in general: electro-optical devices, image display devices (also simply referred to as display devices), semiconductor circuits, A light-emitting device, a power storage device, a memory device, and an electronic device may include a semiconductor device. [Background technology]

[0003] It is used in many display devices, such as liquid crystal displays and light-emitting displays, and integrated circuits (ICs). The semiconductor material of the transistors used is amorphous silicon, single crystal silicon, or Silicon semiconductors such as polycrystalline silicon are known. Other semiconductor materials include Oxide semiconductors have been attracting attention. For example, zinc oxide or In-Ga A technology is disclosed for applying a transistor using a Zn-based oxide as a channel to a display device. Alternatively, polycrystalline In-Ga oxide is used as an oxide semiconductor for the channel (Patent Document 1). A technique for applying the transistor to a display device has been disclosed (Non-Patent Document 1).

[0004] In addition, as display devices become larger and more precise, the wiring resistance and parasitic capacitance increase. To suppress wiring delays caused by this, wiring is made using low-resistance materials such as copper, aluminum, gold, and silver. A technology for forming such a structure has been investigated (Patent Document 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-096055 A [Patent Document 2] JP 2004-133422 A [Non-patent literature]

[0006] [Non-Patent Document 1] Yasuhiro Terai et al., "A Polycrystalline Oxide TFT Driven AM-OLED Display", IDW'11, pp.61-64 Summary of the Invention [Problem to be solved by the invention]

[0007] In a transistor using an oxide semiconductor, impurities (typically Specifically, the majority of the materials are silicon, which is a component element of the insulating layer, carbon, and copper, which is a component material of the wiring. This can cause a deterioration in the electrical characteristics (for example, on-current characteristics) of the transistor.

[0008] In view of the above, one embodiment of the present invention is a semiconductor device such as a transistor including an oxide semiconductor. Another object of the present invention is to reduce the concentration of impurities in an oxide semiconductor layer. One embodiment of the present invention is to improve electrical characteristics of a semiconductor device or the like including an oxide semiconductor. Another object of one embodiment of the present invention is to provide a semiconductor device including an oxide semiconductor. Another object of the present invention is to provide a novel semiconductor device. One of the objectives is to provide a body device, etc.

[0009] The description of these problems does not preclude the description of other problems. It is not necessary for the present invention to solve all of these problems. Problems other than those mentioned above may be solved by the present invention. The above-mentioned problems are obvious from the description of the specification, etc., and the above-mentioned problems are not obvious from the description of the specification, etc. It is possible to extract the topic. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor layer including an In-M oxide (wherein M is A metal oxide layer consisting of Ti, Ga, Y, Zr, La, Ce, Nd or Hf and a gold a conductive layer containing copper, aluminum, gold or silver and in contact with the metal oxide layer; When the atomic ratio of In and M contained in is In:M=x:y, y / (x+y) is 0. The semiconductor device has a coefficient of refraction of 75 or more and less than 1.

[0011] Alternatively, one embodiment of the present invention is a gate electrode layer, a gate insulating layer in contact with the gate electrode layer, an oxide semiconductor layer facing the gate electrode layer with a gate insulating layer interposed therebetween; It consists of In-M oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf). A metal oxide layer and a pair of electrodes containing copper, aluminum, gold or silver in contact with the metal oxide layer. and the atomic ratio of In and M contained in the metal oxide layer is In:M=x:y. In this case, the semiconductor device has a structure in which y / (x+y) is equal to or greater than 0.75 and less than 1.

[0012] Alternatively, one embodiment of the present invention is a semiconductor device including a first gate electrode layer and a first gate electrode layer in contact with the first gate electrode layer. a gate insulating layer and an oxide semiconductor layer facing the first gate electrode layer via the first gate insulating layer; The In-M oxide (wherein M is Ti, Ga, Y, Zr, La, A metal oxide layer consisting of copper, aluminum, and copper (Ce, Nd, or Hf) is in contact with the metal oxide layer. a pair of electrode layers including aluminum, gold or silver; and a second gate insulating layer in contact with the pair of electrode layers; a second gate electrode layer facing the oxide semiconductor layer via a second gate insulating layer; When the atomic ratio of In and M contained in the metal oxide layer is In:M=x:y, y / (x +y) is 0.75 or more and less than 1, and the first gate electrode layer and the second gate electrode layer are The first gate insulating layer and the second gate insulating layer are electrically connected to each other through an opening provided in the first gate insulating layer and the second gate insulating layer. It is a semiconductor device.

[0013] In the semiconductor device, the oxide semiconductor layer has first sides in contact with the pair of electrode layers. a third side surface facing the first gate electrode layer or the second gate electrode layer; and a fourth side.

[0014] Alternatively, in the above semiconductor device, it is preferable that the element M contains gallium. .

[0015] Alternatively, in the above semiconductor device, the oxide semiconductor layer includes a first oxide semiconductor layer and a first a second oxide semiconductor layer located between the first oxide semiconductor layer and the metal oxide layer; In this case, the electron affinity of the second oxide semiconductor layer may be larger than that of the first oxide semiconductor layer. It is preferable that the electron affinity of the metal oxide layer is smaller than that of the inorganic layer and larger than that of the metal oxide layer. It is nice.

[0016] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0017] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. . Effect of the Invention

[0018] According to one embodiment of the present invention, the concentration of impurities in an oxide semiconductor layer can be reduced. According to one embodiment of the present invention, in a semiconductor device including an oxide semiconductor, According to one embodiment of the present invention, the characteristics of the semiconductor device using an oxide semiconductor can be improved. The reliability of a semiconductor device or the like can be improved. It is to be noted that the description of these effects may include other effects. However, it is not necessary for one embodiment of the present invention to have all of these effects. It is not necessary for the invention to have the above effects. Effects other than these can be understood from the description in the specification, drawings, claims, etc. It is obvious that there are other effects than these from the description, drawings, claims, etc. It is possible to extract the results. [Brief description of the drawings]

[0019] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 2]1A and 1B are a plan view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 3] 1A and 1B are a plan view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 4] 1A and 1B are a plan view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Diagram 5] 1A to 1C illustrate a manufacturing process of a transistor according to one embodiment of the present invention. [Figure 6] 1A to 1C illustrate a manufacturing process of a transistor according to one embodiment of the present invention. [Figure 7] 1A to 1C are a plan view, a cross-sectional view, and a band diagram illustrating a transistor according to one embodiment of the present invention. [Figure 8] Cs-corrected high-resolution TEM image of a cross section of CAAC-OS, and a schematic cross-sectional diagram of CAAC-OS. [Figure 9] 1A and 1B are a nanobeam electron diffraction pattern of an oxide semiconductor film and a diagram showing an example of a transmission electron diffraction measurement apparatus. [Figure 10] An example of structural analysis using transmission electron diffraction measurements and a planar TEM image. [Figure 11] 13A to 13C are diagrams illustrating Id-Vg characteristics, band diagrams, and SIMS analysis results of a transistor. [Figure 12] Id-Vg characteristics and band diagram of a transistor. [Figure 13] 13A to 13C are diagrams illustrating Id-Vg characteristics, band diagrams, and SIMS analysis results of a transistor. [Figure 14] 13A to 13C are diagrams illustrating Id-Vg characteristics, band diagrams, and SIMS analysis results of a transistor. [Figure 15] 13A to 13C are diagrams illustrating Id-Vg characteristics, band diagrams, and SIMS analysis results of a transistor. [Figure 16] FIG. 1 is a diagram illustrating the results of XRD measurement. [Figure 17] FIG. 1 is a diagram for explaining a band diagram. [Figure 18] 1A and 1B are a diagram and a circuit diagram illustrating a structure of a display device according to one embodiment of the present invention. [Figure 19]1A and 1B are diagrams illustrating a display module according to one embodiment of the present invention. [Figure 20] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 21] 1A and 1B are a cross-sectional view and a band diagram illustrating a transistor according to one embodiment of the present invention. [Figure 22] 1A and 1B are a plan view and a cross-sectional view illustrating a transistor according to one embodiment of the present invention. [Figure 23] Cs-corrected high-resolution TEM image of the CAAC-OS in the plane. [Figure 24] 13A to 13C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. [Diagram 25] Electron diffraction pattern of CAAC-OS. [Figure 26] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. [Figure 27] Schematic diagram explaining the film formation model of CAAC-OS and nc-OS. [Figure 28] A diagram explaining InGaZnO4 crystals and pellets. [Figure 29] Schematic diagram explaining a film formation model of CAAC-OS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiment. In the embodiments described below, the same parts or parts having similar functions are designated by the same reference numerals or symbols. The same hatch patterns are used in common among different drawings and will not be described repeatedly.

[0021] In each figure described in this specification, the size, thickness, or area of ​​each component is not clearly indicated. The figures may be exaggerated for illustrative purposes and are not necessarily limited to scale.

[0022] In addition, ordinal numbers such as 1st, 2nd, etc., used in this specification are used to avoid confusion of components. Therefore, for example, "the first" can be changed to "the second " or "third," etc., as appropriate.

[0023] In addition, the function of the "source" and "drain" is to change the direction of the current during circuit operation. For this reason, in this specification and other documents, the terms "source" and " The terms "drain" and "insulator" can be used interchangeably.

[0024] In addition, in this specification, the terms "above" and "below" mean that the positional relationship of the components is "directly above" or "below". For example, "gate electrode on a gate insulating layer" is not limited to "directly under". If the term "layer" is used, it means that other components are included between the gate insulating layer and the gate electrode layer. The same applies to "below."

[0025] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Straight" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, this also includes cases where the angle is between 85° and 95°.

[0026] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0027] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention and a manufacturing method thereof will be described. The description will be given with reference to FIG.

[0028] <Transistor configuration example 1> 1A and 1B show a plan view of a transistor 200 included in the semiconductor device of this embodiment. The transistor 200 shown in FIG. 1 is a channel-etched transistor. FIG. 1A is a plan view of a transistor 200, and FIG. 1B is a schematic diagram of a transistor 200. 1A) is a cross-sectional view taken along dashed lines A1-A2 and B1-B2. For clarity, the substrate 100 and some of the components of the transistor 200 (e.g., the gate insulating layer ) are omitted in the illustration.

[0029] The transistor 200 shown in FIG. 1(A) and FIG. 1(B) is a gate insulating film formed on a substrate 100. a gate electrode layer 102; a gate insulating layer 104 in contact with the gate electrode layer 102; and a gate insulating layer 1 The oxide semiconductor layer 106 faces the gate electrode layer 102 through the oxide semiconductor layer 104. A metal oxide layer 108 on the substrate 106 and a pair of electrode layers 110a and 110b in contact with the metal oxide layer 108. A pair of electrode layers 110a and 110b and a metal An oxide insulating layer 112, an oxide insulating layer 114 and a nitride insulating layer are formed on the oxide layer 108. Layer 116 may be included as a component of transistor 200 .

[0030] In the transistor 200, a layer in contact with the top surface of the oxide semiconductor layer 106 in which a channel is formed is The metal oxide layer 108 is formed by oxidizing the constituent elements of the pair of electrode layers 110a and 110b. It functions as a barrier layer that suppresses diffusion into the metal oxide semiconductor layer 106. By providing the layer 108, the oxide insulating layer 112 provided over the oxide semiconductor layer 106 is It is also possible to prevent the constituent elements such as ZnO from being mixed into the oxide semiconductor layer 106. By suppressing the intrusion of impurities into the oxide semiconductor layer 106 in which the junction is formed, The deterioration of the electrical properties of 200 can be suppressed.

[0031] The metal oxide layer 108 is made of In-M oxide (wherein M is Ti, Ga, Y, Zr, La, Ce, The metal oxide layer 1 may be formed of a metal oxide represented by Nd or Hf. The conductivity is low enough to prevent 08 from acting as part of the channel-forming region. Alternatively, the metal oxide layer 108 may be made of a material having a high electron affinity (vacuum level and conductivity). The energy difference between the conduction band minimum and the conduction band minimum of the oxide semiconductor layer 106 is smaller than that of the oxide semiconductor layer 106. has a difference (band offset) with respect to the conduction band minimum energy of the oxide semiconductor layer 106. In addition, the difference in threshold voltage depends on the magnitude of the drain voltage. In order to suppress this, the energy of the conduction band minimum of the metal oxide layer 108 is set to be equal to or lower than that of the oxide A material having an energy level closer to the vacuum level than the conduction band minimum of the semiconductor layer 106 by 0.2 eV or more is preferable. It is preferable to use a material having a vacuum level of 0.5 eV or more.

[0032] In addition, by increasing the atomic ratio of element M to In, the energy of the metal oxide layer 108 is The gap can be increased and the electron affinity can be decreased. 06, a band offset of the conduction band is formed, and a channel is formed in the metal oxide layer 108. In order to suppress this, the metal oxide layer 108 has an atomic ratio of In:M=x:y. Then, y / (x+y) is 0.75 or more and less than 1, preferably 0.78 or more and less than 1. More preferably, it is set to 0.80 or more and less than 1. However, the metal oxide layer 108 may contain elements other than the main components indium, M, and oxygen as impurities. In this case, the ratio of impurities is preferably 0.1% or less. The measurements were performed using inductively coupled plasma mass spectrometry. This is done using ICP-MS (Inductively Coupled Plasma Mass Spectrometry) For example, when the atomic ratio is In:M=x:y, In:M=x:y is the This does not refer to the composition of the target, but to the composition of the metal oxide film obtained by the sputtering method. Therefore, y / (x+y) is greater than or equal to 0.75 and less than 1.

[0033] In addition, when the metal oxide layer 108 is formed by a sputtering method, the element for In is By increasing the atomic ratio of M, it is possible to reduce the number of particles during film formation. In order to reduce the number of particles, if In:M=x:y [atomic ratio], then y / ( x+y) is preferably 0.90 or more, for example, 0.93. However, the metal oxide layer 108 When forming a thin film by sputtering, if the atomic ratio of M to In is too high, the thickness of the thin film may be reduced. - The target has high insulating properties, making it difficult to form a film using DC discharge, and it is necessary to apply RF discharge. Therefore, in order to perform film formation using DC discharge that can be used on large-area substrates, y / (x+y) is set to 0.96 or less, preferably 0.95 or less, for example 0.93. By applying a deposition method suitable for large-area substrates, the productivity of semiconductor devices can be improved. can.

[0034] Note that in the transistor 200, the oxide semiconductor layer 106 in which a channel is formed has a side A pair of electrode layers 110a and 110b functioning as a source electrode layer and a drain electrode layer on the 0b, and a source region and a drain region are formed in the contact region. Therefore, the metal oxide layer 108 may have insulating properties.

[0035] It is preferable that the metal oxide layer 108 does not contain a spinel type crystal structure in the film. When the metal oxide layer 108 contains a spinel crystal structure, the spinel crystal Due to the structure, the constituent elements of the pair of electrode layers 110a and 110b diffuse into the oxide semiconductor layer 106. For example, the metal oxide layer 108 may be an In-M oxide. By applying the above formula, the composition does not contain a divalent metal atom (e.g., zinc) as M, This is preferred because it allows the formation of a metal oxide layer 108 that does not contain a spinel type crystal structure. It is.

[0036] The thickness of the metal oxide layer 108 is determined by determining whether the constituent elements of the pair of electrode layers 110a and 110b are oxide semiconductors. The thickness of the oxide insulating layer 11 is equal to or larger than the thickness at which diffusion into the oxide insulating layer 106 can be suppressed. The thickness of the metal oxide semiconductor layer 106 is set to be less than the thickness that prevents oxygen from being supplied from the metal oxide semiconductor layer 2 to the oxide semiconductor layer 106. When the thickness of the oxide layer 108 is 10 nm or more, the elemental composition of the pair of electrode layers 110a and 110b is The diffusion of the metal oxide into the metal oxide semiconductor layer 106 can be suppressed. When the thickness of the oxide insulating layers 112 and 114 is set to 100 nm or less, the oxide semiconductor layer 10 6.

[0037] In the transistor 200 described in this embodiment, the source electrode layer and the drain electrode The pair of electrode layers 110a and 110b functioning as the layers may be made of copper, aluminum, gold, or is a low-resistance metal such as silver, or an alloy, or a compound whose main component is one of these It is preferable that the pair of electrode layers 110a and 110b have a single layer structure or a laminate structure. Since the electrode layer also functions as wiring, the electrode layer is made of a low resistance material such as copper, aluminum, gold, or silver. By forming the substrate 100 including the wiring delay It is possible to manufacture a semiconductor device in which the above-mentioned problems are suppressed.

[0038] When the pair of electrode layers 110a and 110b have a two-layer structure, the thickness of the second conductive layer is made large. And low-resistance metals such as copper, aluminum, gold, and silver, or alloys. or a conductive layer containing a compound having these as its main component, The first conductive layer in contact with the side and top surfaces of the metal oxide layer 108 is made of the above-mentioned second conductive layer. It is preferable to form the insulating layer using a conductor that functions as a barrier layer against the Metals or alloys of titanium, tantalum, molybdenum, and tungsten, or titanium nitride, A conductive layer containing tantalum nitride, molybdenum nitride, tungsten nitride, or the like is used as a barrier layer. In addition, when the pair of electrode layers 110a and 110b have a three-layer structure, A conductor is used that is in contact with the first and second layers and functions as a barrier layer against the second layer conductor. It is preferable to form a third conductive layer on the substrate.

[0039] For example, when the pair of electrode layers 110a and 110b have a two-layer structure, an aluminum film is formed on a titanium film. A structure with a tungsten film on top of a copper film, a structure with a tungsten film on top of a copper film, A structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film. The structure has a copper film laminated on a titanium film, a copper film laminated on a tungsten film, etc. In addition, when the pair of electrode layers 110a and 110b has a three-layer structure, The first and third layers are made of titanium, titanium nitride, molybdenum, or molybdenum nitride. and on the second layer, a film made of a low resistance material such as copper, aluminum, gold or silver is formed. It is preferable.

[0040] The transistor 200 described in this embodiment functions as a source electrode layer and a drain electrode layer. As a pair of electrode layers, electrode layers containing a low resistance material such as copper, aluminum, gold, or silver are used. By using the above, a semiconductor device in which wiring delay is suppressed can be manufactured. By providing the metal oxide layer 108 that functions as a barrier layer in contact with the electrode layer, the electrical characteristics It is possible to provide a semiconductor device having good electrical characteristics by suppressing the decrease in the electrical conductivity.

[0041] The electrode layer 110a and the electrode layer 110b are formed, and the oxide semiconductor layer 106 and The formation of the metal oxide layer 108 is performed using a half-tone mask (or a gray-tone mask, By forming the mask using a phase contrast mask, the number of masks can be reduced and the number of process steps can be reduced. In this case, the pattern may be reduced by ashing the resist. Therefore, under the electrode layer 110a and the electrode layer 110b, An oxide semiconductor layer 106 and a metal oxide layer 108 are provided. The plan view and cross-sectional view of the halftone are shown in FIG. .

[0042] Other components included in the semiconductor device of this embodiment will be described in detail below. do.

[0043] (substrate) There is no particular restriction on the material of the substrate 100, but it should be at least strong enough to withstand the subsequent heat treatment. It is necessary to have heat resistance. For example, glass substrate, ceramic substrate, quartz substrate, surface treatment substrate, etc. A fiber substrate or the like may be used as the substrate 100. Also, a material such as silicon or silicon carbide may be used. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, S It is also possible to use OI substrates, etc., on which semiconductor elements are provided. may be used as the substrate 100. In addition, when a glass substrate is used as the substrate 100, , 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2200mm) , 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2800mm) By using large-area substrates such as the 10th generation (2950mm x 3400mm), it is possible to produce large-sized displays. It is possible to create a display device.

[0044] In addition, a flexible substrate is used as the substrate 100, and the transistor 200 is directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 100 and the transistor 200. The release layer is used to separate the semiconductor device from the substrate 100 after a part or whole of the semiconductor device is completed thereon. The transistor 200 can be separated and transferred to another substrate. It can also be transferred to less rigid or flexible substrates.

[0045] (gate electrode layer) The gate electrode layer 102 may be made of any of a variety of materials, including chromium, copper, aluminum, gold, silver, zinc, molybdenum, and tantalum. Metal elements selected from the group consisting of titanium, tungsten, and arsenic, or metal elements selected from the group consisting of the above-mentioned metal elements. The metal layer can be formed by using an alloy or an alloy of the above-mentioned metal elements. Alternatively, one or more metal elements selected from manganese, zirconium, etc. may be used. The gate electrode layer 102 may have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, or a titanium film laminated on an aluminum film, Two-layer structure: a titanium film laminated on a titanium nitride film; a tungsten film laminated on a titanium nitride film A two-layer structure in which a tantalum nitride film is laminated, a tungsten film on a tantalum nitride film or a tungsten nitride film A two-layer structure in which a titanium film is laminated, an aluminum film is laminated on the titanium film, and then There are three-layer structures, such as a titanium film on top of aluminum. tungsten, molybdenum, chromium, neodymium, and scandium. An alloy film or a nitride film having a combination of the above may also be used.

[0046] The gate electrode layer 102 may be formed of indium tin oxide or indium containing tungsten oxide. Oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium zinc oxide, silicon oxide, etc. A light-transmitting conductive material such as doped indium tin oxide can also be used. Alternatively, the conductive material having light-transmitting properties and the metal element may be laminated together.

[0047] In addition, an In-Ga-Zn-based oxynitride is formed between the gate electrode layer 102 and the gate insulating layer 104. Semiconductor film, In-Sn-based oxynitride semiconductor film, In-Ga-based oxynitride semiconductor film, In-Zn Sn-based oxynitride semiconductor film, In-based oxynitride semiconductor film, metal nitride film ( InN, ZnN, etc.) may be provided. These films have a thermal conductivity of 5 eV, preferably 5.5 eV or more. Since the electron affinity of the oxide semiconductor is larger than that of the oxide semiconductor, The threshold voltage of the transistor using the above-mentioned can be shifted to the positive side. It is possible to realize a switching element with off characteristics. For example, In-Ga-Zn-based oxynitride semiconductor In the case of using a film, the nitrogen concentration is at least higher than that of the oxide semiconductor layer 106, specifically, 7 atomic % or more of an In-Ga-Zn-based oxynitride semiconductor film is used.

[0048] (Gate insulation layer) The gate insulating layer 104 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. Silicon oxide, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn metal An oxide or the like may be used, and the insulating film is provided as a laminated layer or a single layer.

[0049] The gate insulating layer 104 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium Silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminium minate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high- The use of k-materials can reduce the gate leakage of transistors.

[0050] The thickness of the gate insulating layer 104 is 5 nm or more and 400 nm or less, and more preferably 10 nm or more. It is preferably 300 nm or less, and more preferably 50 nm or more and 250 nm or less.

[0051] (Oxide semiconductor layer) The oxide semiconductor layer 106 is typically made of In-Ga oxide, In-Zn oxide, In-M -Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf).

[0052] The oxide semiconductor layer 106 is an In-M-Zn oxide (wherein M is Ti, Ga, Y, Zr, La, or C e, Nd or Hf), the sputtering method used to deposit the In-M-Zn oxide film The atomic ratio of the metal elements in the annealing target preferably satisfies In≧M and Zn>M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn=1 :1:1, In:M:Zn=1:1:1.2, and In:M:Zn=3:1:2 are preferred. The atomic ratio of the oxide semiconductor layer 106 to be formed may be calculated by subtracting the above-mentioned sputtering time from the atomic ratio of the oxide semiconductor layer 106 as an error. The atomic ratio of metal elements contained in the target varies by ±40%. .

[0053] When the oxide semiconductor layer 106 is an In-M-Zn oxide, the components other than Zn and O are The atomic ratio of In to M is preferably such that In is higher than 25 atomic % and M is 75 atomic % or higher. More preferably, In is less than 34 atomic % and M is 66 atomic %. The concentration must be less than mic%.

[0054] The oxide semiconductor layer 106 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, the energy gap is 3 eV or more. By using such a body, the off-state current of the transistor 200 can be reduced.

[0055] The thickness of the oxide semiconductor layer 106 is 3 nm to 200 nm, preferably 3 nm to 10 0 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0056] As the oxide semiconductor layer 106, an oxide semiconductor layer with low carrier density is used. For example, The oxide semiconductor layer 106 has a carrier density of 1×10 17 pieces / cm 3 Below, preferably 1x 10 15 pieces / cm 3 Less than 1×10, more preferably 13 pieces / cm 3 The following is more preferable: is 1×10 11 pieces / cm 3 The following applies.

[0057] In addition, the semiconductor characteristics and electrical characteristics (field effect The appropriate composition should be used depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density and impurities of the oxide semiconductor layer 106 are By appropriately adjusting the concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. is preferred.

[0058] Note that the oxide semiconductor layer 106 is formed of an oxide semiconductor having a low impurity concentration and a low density of defect states. By using a dielectric layer, it is possible to fabricate transistors with even better electrical properties. Here, it is preferable that the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). High purity authentic or substantially high purity authentic. High purity authentic or substantially high purity authentic Some oxide semiconductors have a small number of carrier generation sources, so the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor layer has a threshold voltage The electrical characteristics where the voltage is negative (also called normally-on) are rare. Since a highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor layer has a low density of defect states, Therefore, the trap level density may be low. The oxide semiconductor layer, which is a thin film transistor, has a remarkably small off-state current and a channel width of 1×10 6 μm Even if the channel length L of the element is 10 μm, the voltage between the source electrode and the drain electrode (drain When the voltage (voltage) is in the range of 1V to 10V, the off-state current is measured by a semiconductor parameter analyzer. Below the limit, i.e. 1×10 -13 It is possible to obtain a characteristic of A or less.

[0059] Therefore, a channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor layer. The transistors to be fabricated have small variations in electrical characteristics and are highly reliable. Note that it takes a long time for charges trapped in the trap states of the oxide semiconductor film to disappear. It takes a long time for the charge to be trapped, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor layer with high density of states has excellent electrical characteristics. Impurities include hydrogen, nitrogen, alkali metals, or alkali metals. Earth metals, etc.

[0060] Hydrogen contained in the oxide semiconductor layer reacts with oxygen that is bonded to metal atoms to form water, and the hydrogen is then released into the oxide semiconductor layer. Oxygen vacancies are formed in the lattice from which the atoms have been removed (or in the area from which the oxygen has been removed). When hydrogen enters, electrons, which act as carriers, may be generated. Also, some of the hydrogen may be converted to gold. It can combine with oxygen, which is a carrier of electrons, to produce a A transistor using an oxide semiconductor containing hydrogen tends to be normally-on. For this reason, it is preferable that the amount of hydrogen in the oxide semiconductor layer 106 be reduced as much as possible. Specifically, the oxide semiconductor layer 106 was analyzed by secondary ion mass spectrometry (SIMS:Se Hydrogen concentration obtained by condary ion mass spectrometry Degrees, 2 x 10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 Less than or equal to 5×1, more preferably 0 17 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 below Let us assume that.

[0061] When the oxide semiconductor layer 106 contains silicon or carbon, which is one of the Group 14 elements, As a result, oxygen vacancies increase in the oxide semiconductor layer 106, causing the oxide semiconductor layer 106 to become n-type. The concentration of silicon or carbon in the metal semiconductor layer 106, or the concentration of the metal oxide layer 108 and the oxide The concentration of silicon and carbon near the interface with the semiconductor layer 106 (obtained by secondary ion mass spectrometry) The concentration of 18 atoms / cm 3 Less than or equal to 2 x 10 17 atom s / cm 3 The following applies.

[0062] In addition, in the oxide semiconductor layer 106, an alkali metal oxide was obtained by secondary ion mass spectrometry. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Hereinafter, preferably 2×10 16 atoms / cm 3 The alkali metals and alkaline earth metals are When they bond with oxide semiconductors, carriers may be generated, increasing the off-state current of the transistor. For this reason, the alkali metal or alkali metal in the oxide semiconductor layer 106 may It is preferable to reduce the concentration of earth metals.

[0063] In addition, when the oxide semiconductor layer 106 contains nitrogen, electrons that serve as carriers are generated. The rear density increases and it becomes easier to make it n-type. As a result, A transistor having such an oxide semiconductor film tends to be normally on. It is preferable that the nitrogen content is reduced as much as possible. For example, in the secondary ion mass spectrometry, The resulting nitrogen concentration is 5×10 18 atoms / cm 3 It is preferable to do the following:

[0064] The oxide semiconductor layer 106 may have a non-single crystal structure, for example. , CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure (described below), or Among non-single crystal structures, the amorphous structure has the highest defect level density and CA AC-OS has the lowest defect state density.

[0065] The oxide semiconductor layer 106 may have, for example, an amorphous structure. For example, the atomic arrangement is disordered and does not have crystalline components. Or, the oxide film has an amorphous structure. For example, it has a completely amorphous structure and does not have any crystalline parts.

[0066] Note that the oxide semiconductor layer 106 may have an amorphous structure, a microcrystalline structure, or a polycrystalline structure. The film may be a mixed film having two or more of the following structures: a Cd-Al-Cu-O-S region, a Cd-Al-Cu-O-S region, and a single crystal structure. The film may have regions of amorphous structure, regions of microcrystalline structure, regions of polycrystalline structure, CAAC-O In some cases, the material may have two or more regions, either the S region or the single crystal structure region. The film may have regions of amorphous structure, regions of microcrystalline structure, regions of polycrystalline structure, CAAC-O The semiconductor device may have a laminated structure of two or more regions of either an S region or a single crystal structure region. The metal oxide layer 108 in contact with the oxide semiconductor layer 106 may have an amorphous structure or a microcrystalline structure. The structure may be a polycrystalline structure, a polycrystalline structure, etc.

[0067] In addition, a constituent element (e.g., silicon) different from the oxide semiconductor is in contact with the oxide semiconductor layer 106. In the case where an insulating layer having the above structure is provided, a heterojunction is formed at the interface between the oxide semiconductor layer 106 and the insulating layer. In this case, an interface state may be formed due to the incorporation of impurities. In the photodiode 200, the oxide semiconductor layer 106 and the oxide semiconductor layer 107 are formed of a material having a different constituent element (e.g., silicon). A gold layer having the same constituent elements as the oxide semiconductor is placed between the oxide insulating layer 112, which may have a metal oxide semiconductor. Therefore, the metal oxide layer 108 and the oxide insulating layer 11 Even if a trap level is formed by impurities and defects between the two, the trap level There is a gap between the oxide semiconductor layer 106 and the oxide semiconductor layer 106. The electrons that are released from the semiconductor layer are less likely to be captured by the trap level, which increases the on-state current of the transistor. In addition, the field effect mobility can be increased. When trapped, the electrons become a fixed negative charge. However, the oxide semiconductor layer 106 and the trap states Since there is a gap between the trap levels, it is possible to reduce the capture of electrons at the trap levels. Therefore, the variation in the threshold voltage can be reduced.

[0068] In addition, the element M contained in the metal oxide layer 108 has a strong bond with oxygen. The metal oxide layer 108 having a high molecular weight ratio is less likely to form oxygen vacancies. In this case, the amount of oxygen vacancies in the oxide semiconductor layer 106 in contact with the insulating film 8 can be reduced.

[0069] (Oxide insulating layer) The oxide insulating layer 112 is an oxide insulating film that transmits oxygen. This is to prevent the metal oxide layer 108 and the oxide semiconductor layer 112 from being damaged when the oxide insulating layer 114 is formed later. It also functions as a film for reducing damage to the conductor layer 106 .

[0070] The oxide insulating layer 112 has a thickness of 5 nm or more and 150 nm or less, preferably 5 nm or more. Silicon oxide, silicon oxynitride, etc., having a thickness of 50 nm or less can be used. In the present specification, a silicon oxynitride film is a film having a composition in which oxygen is more abundant than nitrogen. The term silicon nitride oxide refers to a film that contains more nitrogen than oxygen. Refers to the membrane.

[0071] In addition, the oxide insulating layer 112 preferably has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 3×10 17 spins / cm 3 This is because the oxide insulation If the layer 112 contains a large density of defects, oxygen is bound to the defects, resulting in the formation of an oxide insulating layer. This is because the amount of oxygen permeating through 112 decreases.

[0072] In addition, the amount of defects at the interface between the oxide insulating layer 112 and the metal oxide layer 108 is small. Preferably, typically, the ESR measurement shows that the metal oxide layer 108 has a defect-derived g=1 The spin density of the signal appearing between .89 and 1.96 is 1×10 17 spins / cm 3 Below It is preferable that the concentration is below the lower limit of detection.

[0073] Note that in the oxide insulating layer 112, all of the oxygen that has entered the oxide insulating layer 112 from the outside is Some oxygen does not move outside the oxide insulating layer 112 and remains in the oxide insulating layer 112. At the same time, oxygen enters the oxide insulating layer 112, and the oxygen contained in the oxide insulating layer 112 is converted into an oxide The movement of oxygen to the outside of the insulating layer 112 occurs in the oxide insulating layer 112. When an oxide insulating film that transmits oxygen is formed as the oxide insulating layer 112, the oxide insulating layer 112 may be oxidized. The oxide insulating layer 114 is provided on the oxide insulating layer 112. The oxide insulating layer 114 is formed of a SiO 2 . The oxide semiconductor layer 106 can be transferred through the oxide semiconductor layer 112 .

[0074] An oxide insulating layer 114 is formed in contact with the oxide insulating layer 112. 114 is formed using an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than the stoichiometric composition is heated. A part of the oxygen is released. The amount of oxygen released from the coating, calculated as oxygen atoms, was 1.0 x 10 18 ato ms / cm 3 More than 3.0×10 20 atoms / cm 3 The oxide insulator is The substrate temperature during the TDS analysis was 100°C to 700°C. or in the range of 100° C. to 500° C.

[0075] The oxide insulating layer 114 has a thickness of 30 nm to 500 nm, preferably 50 nm. Silicon oxide, silicon oxynitride, etc., having a thickness of 400 nm or more and 400 nm or less can be used.

[0076] In addition, the oxide insulating layer 114 preferably has a small amount of defects. Therefore, the spin of the signal at g=2.001 originating from the silicon dangling bond Density is 1.5×10 18 spins / cm 3 Less than or even 1×10 18 spins / cm 3 Note that the oxide insulating layer 114 is preferably 0.1 to 1.0 μm in thickness compared to the oxide insulating layer 112. Since the oxide insulating layer 112 is farther away from the oxide semiconductor layer 106, the oxide insulating layer 112 has a higher defect density. It would be good.

[0077] (Nitride insulating layer) On the oxide insulating layer 114, a block of oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, or the like is formed. By providing the nitride insulating layer 116 having the insulating effect, the oxide semiconductor layer 106 can be prevented from being oxidized. In order to prevent the diffusion of elements to the outside and the intrusion of hydrogen, water, and the like into the oxide semiconductor layer 106 from the outside, The nitride insulating layer can be made of silicon nitride, silicon oxynitride, aluminum nitride, Aluminum oxide nitride, etc. In addition, oxygen, hydrogen, water, alkali metals, alkaline earth metals Instead of a nitride insulating layer having a blocking effect on metals, etc., a blocking layer for oxygen, hydrogen, water, etc. An oxide insulating layer having a blocking effect against oxygen, hydrogen, water, etc. may be provided. The oxide insulating layer may be formed of aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride and the like.

[0078] <Transistor configuration example 2> 2A and 2B show a plan view of a transistor 210 included in the semiconductor device of this embodiment. FIG. 2A is a plan view of a transistor 210, and FIG. 2(A) is a cross-sectional view taken along dashed lines A3-A4 and B3-B4 in FIG. In A), for clarity, the substrate 100 and some of the components of the transistor 210 (e.g., the gate In the figure, the insulating layer (and other parts) are omitted.

[0079] The transistor 210 shown in FIG. 2(A) and FIG. 2(B) is a gate insulating film formed on a substrate 100. a gate electrode layer 102; a gate insulating layer 104 in contact with the gate electrode layer 102; and a gate insulating layer 1 The oxide semiconductor layer 206 faces the gate electrode layer 102 through the oxide semiconductor layer 204. A metal oxide layer 108 on the substrate 106 and a pair of electrode layers 110a and 110b in contact with the metal oxide layer 108. 10b, a pair of electrode layers 110a and 110b, and a metal oxide layer 108. The oxide insulating layer 112, the oxide insulating layer 114, and the nitride insulating layer 116 are 16 and an electrode layer 118 disposed thereon.

[0080] In the transistor 210, the electrode layer 118 functions as a backgate electrode. The oxide insulating layer 112 is provided between the electrode layer 118 and the oxide semiconductor layer 206. The stack including the border layer 114 and the nitride insulating layer 116 provides a gate electrode for the back gate electrode. The electrode layer 118 functions as an insulating layer. 2. Openings 117a and 117b provided in the oxide insulating layer 114 and the nitride insulating layer 116 1, the electrode layer 118 is connected to the gate electrode layer 102. 2 is given the same potential.

[0081] The transistor 210 shown in FIG. 2 has a nitride insulating layer 116 on it that functions as a backgate electrode. The transistor 200 differs from the transistor 200 in FIG. The configuration is similar to that of the transistor 200, and the same effects can be obtained. The transistor 210 includes a pair of electrode layers 110a and 110b made of a low resistance material and a channel A metal oxide layer 100 serving as a barrier layer is formed between the oxide semiconductor layer 206 and the metal oxide layer 100. 8. This suppresses the intrusion and diffusion of impurities into the oxide semiconductor layer 206. Therefore, the transistor 210 is a transistor in which the deterioration of electrical characteristics is suppressed. The details of each component of transistor 210 are shown in The explanation can be taken into consideration.

[0082] The oxide semiconductor layer 206 included in the transistor 210 illustrated in FIG. The oxide semiconductor layer 106 is formed of the same material as that of the oxide semiconductor layer 106 included in 200 and has a thickness of 100 nm. m or more, for example, 100 nm or more and 1000 nm or less, preferably 200 nm or more and 1000 nm or less. m or less. In addition, the channel length of the transistor 210 (the pair of electrode layers 110a and 110 The distance between the first and second electrodes (b) is preferably 0.5 μm or more and 2 μm or less, and more preferably 0.5 μm or more and 1 μm or less. It is more preferable that the length is set to m or less.

[0083] As shown in the cross-sectional view of FIG. 2B, the oxide semiconductor layer 206 is The two gate electrodes are positioned so as to face each of the pole layers 118 (back gate electrodes). The length of the electrode layer 118 functioning as a back gate electrode in the channel length direction is The length in the channel length direction and the length in the channel width direction of the oxide semiconductor layer 206 are The oxide semiconductor layer 206 is entirely made of an insulating layer (oxide The insulating layer 112, the oxide insulating layer 114, and the nitride insulating layer 116 are interposed between the electrode layer 118. The electrode layer 118 and the gate electrode layer 102 are connected to a gate insulating layer 104 and an oxide layer 106. An opening 117 is provided in the oxide insulating layer 112, the oxide insulating layer 114, and the nitride insulating layer 116. a and 117b are connected. , through the insulating layers (the oxide insulating layer 112, the oxide insulating layer 114, and the nitride insulating layer 116) It faces the back gate electrode (electrode layer 118).

[0084] With such a structure, the oxide semiconductor layer 206 included in the transistor 210 The transistor can be electrically surrounded by the electric field of the gate electrode layer 102 and the electrode layer 118. As in the transistor 210, the electric field in the gate electrode layer and the back gate electrode layer causes a channel The device structure of the transistor that electrically surrounds the oxide semiconductor layer on which the conductor is formed is called surro This can be called an unded channel (s-channel) structure.

[0085] Since the transistor 210 has an s-channel structure, the gate electrode layer 102 As a result, an electric field for inducing a channel can be effectively applied to the oxide semiconductor layer 206. Therefore, the current driving capability of the transistor 210 is improved, and high on-current characteristics can be obtained. In addition, since the on-state current can be increased, the transistor 210 can be In addition, the transistor 210 has a channel formed on the gate electrode layer 1. Since the transistor 210 has a structure surrounded by the electrode layer 118 and the Strength can be increased.

[0086] In the structure of the transistor 210, either one of the openings 117a and 117b is The electrode layer 118 and the gate electrode layer 102 are connected to each other through the opening. This is also fine.

[0087] The pair of electrode layers 110a and 110b included in the transistor 210 are the first conductive layer. The first conductive layer 109a, 109b and the second conductive layer 111a, 111b are laminated together. The conductive layers 109a and 109b are the same as the first layer in the above description of the electrode layers 110a and 110b. The materials exemplified above can be used as appropriate. The material exemplified for the second layer in the previous description of the electrode layers 110a and 110b is appropriately used. The pair of electrode layers 110a and 110b included in the transistor 210 can be As long as the material is made of copper, aluminum, gold or silver, it is not limited to the configuration shown in FIG. Instead, it may have a single layer structure or a laminated structure of three or more layers.

[0088] <Transistor configuration example 3> 3A and 3B show a plan view of a transistor 220 included in the semiconductor device of this embodiment. 2. Transistor 220 is a variation of transistor 210 in FIG. FIG. 3A is a plan view of the transistor 220, and FIG. 3B is a schematic diagram of the transistor 220 shown in FIG. 3A is a cross-sectional view taken along dashed lines A5-A6 and B5-B6. Therefore, the substrate 100 and some of the components of the transistor 220 (for example, the gate insulating layer) are omitted. It is illustrated in an abbreviated form.

[0089] The transistor 220 shown in FIG. 3(A) and FIG. 3(B) is a gate insulating film formed on a substrate 100. a gate electrode layer 102; a gate insulating layer 104 in contact with the gate electrode layer 102; and a gate insulating layer 1 The oxide semiconductor layer 206 faces the gate electrode layer 102 through the oxide semiconductor layer 204. A metal oxide layer 108 that functions as a barrier layer on the SiO 6 and a layer adjacent to the metal oxide layer 108 A pair of electrode layers 110a and 110b, and a pair of electrode layers 110a and 110b and a metal oxide The oxide insulating layer 112, the oxide insulating layer 114 and the nitride insulating layer 115 are formed on the nitride layer 108. 16, electrode layers 119a, 119b, 119c having a nitride insulating layer 116 thereon, has.

[0090] In the transistor 220, the metal oxide layer 108 and the insulating layer (the oxide insulating layer 112, the oxide An electrode overlapping the oxide semiconductor layer 206 via the nitride insulating layer 114 and the nitride insulating layer 116. The layer 119b functions as a back gate electrode. The electrode layers 119a and 119c are formed by the gate insulating layer 104, the oxide insulating layer 112, and the oxide In the openings 117a and 117b provided in the insulating layer 114 and the nitride insulating layer 116, Each of the electrode layers 119a and 119c is connected to the gate electrode layer 102. It functions as a part of the electrode layer 102 .

[0091] The transistor 220 functions as a backgate electrode of the transistor 210. The difference is that the electrode layer 118 has a separate structure. The details of the configuration of the transistor 220 can be the same as those of the transistor 210. For further details, please refer to the explanation for controller 210.

[0092] The electrode layers 119a and 119c included in the transistor 220 are formed of an oxide semiconductor in the top view. The oxide semiconductor layer 2 is formed in the openings 117a and 117b. Therefore, like the transistor 210, the transistor 220 also has an oxide The compound semiconductor layer 206 is formed by the gate electrode layer 102 and the electrode layers 119a, 119b, and 119c. Since the MOSFET has an s-channel structure electrically surrounded by the gate electrode layer 102, An electric field for inducing a channel can be effectively applied to the oxide semiconductor layer 206. As a result, the current driving capability of the transistor 220 is improved, and high on-current characteristics can be obtained. This becomes possible.

[0093] In the transistor 220, the electrode layer 119b functioning as a back gate electrode is Since the gate electrode layer 102 is not electrically connected to the gate electrode layer 102, the gate electrode layer 102 and the electrode layer 119 A different potential or signal can be input to b. Therefore, it functions as a back gate electrode. The threshold voltage of the transistor 220 is controlled by an input signal or an input potential to the electrode layer 119b. The transistor 220 can be shifted in the positive or negative direction. By appropriately controlling the threshold voltage, the transistor 220 is turned on during operation of the semiconductor device. It is possible to appropriately change to a suppression type or a depression type.

[0094] <Transistor configuration example 4> 4A and 4B show a plan view of a transistor 230 included in the semiconductor device of this embodiment. The transistor 230 is the same as the transistor 210 in FIG. FIG. 4A is a plan view of the transistor 230. 4(B) is a cross-sectional view taken along dashed lines A7-A8 and B7-B8 in FIG. For clarity, in FIG. 4A, the substrate 100 and some of the components of the transistor 230 (e.g. For example, the gate insulating layer and the like are omitted in the drawing.

[0095] The transistor 230 shown in FIG. 4(A) and FIG. 4(B) is a gate insulating film formed on the substrate 100. a gate electrode layer 102; a gate insulating layer 104 in contact with the gate electrode layer 102; and a gate insulating layer 1 The oxide semiconductor layer 106 faces the gate electrode layer 102 through the oxide semiconductor layer 104. A metal oxide layer 108 that functions as a barrier layer on the SiO 6 and a layer adjacent to the metal oxide layer 108 A pair of electrode layers 110a and 110b, and a pair of electrode layers 110a and 110b and a metal oxide The oxide insulating layer 112, the oxide insulating layer 114 and the nitride insulating layer 115 are formed on the nitride layer 108. 16 and electrode layers 119a, 119c having a nitride insulating layer 116 disposed thereon.

[0096] The transistor 230 is formed by a metal oxide layer 108 and an insulating layer (oxide insulating layer 112, oxide insulating layer 113). The insulating layer 114 and the nitride insulating layer 116 overlap with the oxide semiconductor layer 106. The electrode layers 119a and 119c are gate insulating layers. The insulating layer 104, the oxide insulating layer 112, the oxide insulating layer 114, and the nitride insulating layer 116 are provided with a The gate electrodes 102 are connected to the gate electrode layer 102 at the openings 117a and 117b. That is, the transistor 230 functions as a part of the polar layer 102. 0, the electrode layer 119b functioning as a back gate electrode is omitted. In the transistor 220 or the transistor 230, either the electrode layer 119a or the electrode layer 119c A configuration having only one of the two may be used.

[0097] As with the transistors 210 and 220, the transistor 230 also The gate electrode layers (gate Since the oxide semiconductor layer 206 has the electrode layer 102, the electrode layers 119a and 119c, Therefore, the transistor 230 can have an s-channel structure that surrounds the This improves the current driving capability, making it possible to produce a transistor with high on-current characteristics. For details of each component of the transistor 230, see the above description of the transistors 210 and 220. The explanation given in the above paragraph can be taken into consideration.

[0098] The transistor according to the present embodiment can be formed by freely combining the above structures. It is possible.

[0099] <How to fabricate a transistor> A method for manufacturing a transistor of this embodiment will be described below with reference to FIGS. A method for manufacturing the transistor 210 will be described as a representative example.

[0100] First, a conductive film is formed on a substrate 100, and the conductive film is processed using a photolithography process. Then, a gate insulating layer 1 is formed on the gate electrode layer 102. 04 (see Figure 5(A)).

[0101] The conductive film constituting the gate electrode layer 102 is formed by a method such as sputtering or chemical vapor deposition (CVD). , vacuum evaporation, pulsed laser deposition (PLD), or The film can be formed by a coating method or a printing method. The most representative method is the plasma-enhanced chemical vapor deposition (PECVD) method, but the most common is metal-organic chemical vapor deposition (MOCVD) Alternatively, a thermal CVD method such as a CVD method or an atomic layer deposition (ALD) method may be used.

[0102] In the thermal CVD method, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and the source gas and the oxidizing agent are simultaneously The film is formed by feeding the gas into the chamber, reacting it near or on the substrate, and depositing it on the substrate. The thermal CVD method is a film formation method that does not use plasma. This has the advantage that defects due to masonry damage are not generated.

[0103] In addition, in the ALD method, the pressure inside the chamber is set to atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially The gas may then be introduced into the chamber, and the gas introduction sequence may be repeated to form a film. For example, by switching between two or more switching valves (also called high-speed valves), The source gases are sequentially supplied to the chamber, and the first source gas is supplied to the chamber so as not to mix the source gases. Inert gas (argon, nitrogen, etc.) is introduced simultaneously with or after the feed gas. In addition, when an inert gas is introduced at the same time, the inert gas is The second source gas may be introduced simultaneously with the introduction of the inert gas. Also, instead of introducing an inert gas, the first source gas is discharged by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first single source gas. The second monoatomic layer is formed on the first monoatomic layer by reacting with the second source gas introduced later. A thin film is formed by stacking atomic layers. The order of gas introduction is controlled to obtain the desired thickness. By repeating this process several times until the thin film is completely removed, a thin film with excellent step coverage can be formed. The thickness can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing precise film thickness adjustment. This allows for cutting, making it suitable for producing fine transistors.

[0104] In this embodiment, a glass substrate is used as the substrate 100, and a gate electrode layer 102 is made of a A 100 nm tungsten layer is formed by sputtering.

[0105] For example, when a tungsten layer is formed using a deposition apparatus that uses ALD, W F6 gas and B2H6 gas are introduced in sequence to form an initial tungsten layer, and then The tungsten layer is formed by simultaneously introducing WF6 gas and H2 gas. Note that B2H6 gas Alternatively, SiH4 gas may be used.

[0106] The gate insulating layer 104 can be formed by sputtering, PECVD, thermal CVD, vacuum deposition, or P The gate insulating layer can be formed by the LD method or the like. A silicon nitride film having a thickness of 400 nm and a silicon oxynitride film having a thickness of 50 nm are stacked as 104. Form in layers.

[0107] Alternatively, a film constituting the gate insulating layer 104 may be formed by a thermal CVD method. To form a hafnium film, a liquid containing a solvent and a hafnium precursor compound (hafnium Alkoxide solution, typically tetrakisdimethylamidohafnium (TDMAH) Two types of gases are used: vaporized raw gas and ozone (O3) as an oxidizing agent. The chemical formula for trachysdimethylamidohafnium is Hf[N(CH3)2]4. Other liquid materials include tetrakis(ethylmethylamido)hafnium.

[0108] For example, when forming an aluminum oxide film, a solvent and an aluminum precursor compound are used. Two types of gases are used: the raw gas is a vaporized liquid containing TMA, and H2O is used as an oxidizing agent. The chemical formula for trimethylaluminum is Al(CH3)3. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate) There are some.

[0109] For example, when forming a silicon oxide film, hexachlorodisilane is adsorbed on the film formation surface. This removes the chlorine contained in the adsorbed matter and provides radicals of oxidizing gases (O2, nitrous oxide). is fed to react with the adsorbate.

[0110] Next, an oxide semiconductor film 106a which will become the oxide semiconductor layer 106 is formed on the gate insulating layer 104. Then, a laminated film of the metal oxide film 108a which becomes the metal oxide layer 108 is formed (see FIG. 5B). ).

[0111] In this embodiment, an In-Ga-Zn oxide target (In:Ga:Zn=1:1:1) is used. The oxide semiconductor film 106a was formed by sputtering using In-Ga-Zn oxide. In addition, an In-Ga oxide target (In:Ga=7:93) was used. Then, an In-Ga oxide film is formed as the metal oxide film 108a by a sputtering method. The metal oxide film 108a is formed as an oxide semiconductor film or an insulating film. Note that the constituent elements and compositions applicable to the oxide semiconductor film 106a and the metal oxide film 108a However, the present invention is not limited to this.

[0112] When the oxide semiconductor film 106a and the metal oxide film 108a are formed by a sputtering method, The power supply for generating plasma can be an RF power supply, an AC power supply, a DC power supply, etc. However, it is recommended to use DC discharge to form the film, which is suitable for large-area substrates. It is preferable to perform the above-mentioned step because it is possible to increase the productivity of the semiconductor device. In order to deposit a film of In by sputtering using DC discharge, the ratio of In:M=x:y [atomic number When the ratio is 0.96 or less, preferably 0.95 or less, for example 0. A good choice would be .93.

[0113] The sputtering gas is a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen. In the case of mixed gas, it is preferable to increase the ratio of oxygen to rare gas. I wish.

[0114] Note that the chamber of the sputtering apparatus is designed to prevent impurities from being generated in the oxide semiconductor film 106a. In order to remove as much water as possible, a vacuum pump of the adsorption type like a cryopump is used. High vacuum pumping (5×10 -7 Pa~1×10 -4 It is preferable to use a temperature of up to about 10 Pa. Alternatively, a turbomolecular pump and cold trap can be combined to circulate the gas from the exhaust system to the chamber. It is preferable to prevent gases, especially gases containing carbon or hydrogen, from flowing back. In addition, impurities such as water contained in the metal oxide film 108a in contact with the oxide semiconductor film 106a may also be present. It is preferable to remove as much as possible, so the chamber for forming the metal oxide film 108a It is also desirable that the chamber is evacuated to a high vacuum.

[0115] In order to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film, Not only is it necessary to evacuate the inside of the device to a high vacuum, but it is also necessary to highly purify the sputtering gas. The oxygen gas and argon gas used in the present invention have a dew point of -40°C or less, preferably -80°C or less, and Preferably, the gas is purified to a temperature of -100°C or lower, more preferably -120°C or lower. By using the above-mentioned, moisture and the like are taken into the oxide semiconductor film 106a and the metal oxide film 108a. This can be prevented as much as possible.

[0116] In addition, instead of the sputtering method, the oxide semiconductor film 10 may be formed by a film formation apparatus using ALD. 6a and / or metal oxide film 108a. For example, In-Ga-Z When forming an n-oxide film, In(CH3)3 gas and O3 gas are introduced in sequence. Then, Ga(CH3)3 gas and O3 gas are introduced simultaneously to form an InO2 layer. An O layer is formed, and then Zn(CH3)2 and O3 gas are introduced simultaneously to form a ZnO layer. The order of these layers is not limited to this example. Mixed compounds such as aO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Alternatively, a layer of H may be formed by bubbling inert gas such as Ar instead of O gas. Although O gas may be used, it is preferable to use O gas that does not contain H. Instead of the gas, In(C2H5)3 may be used. Instead of In(CH3)3 gas, Ga(C2H5)3 gas may be used. Instead of gas, In(C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used. It's fine.

[0117] Next, a photolithography process using a photoresist mask is performed on the metal oxide film 108a. After forming a resist mask by the process, the metal oxide film 108a is The oxide semiconductor film 106a is etched to separate elements, and the oxide semiconductor layer 106 and the gold A metal oxide layer 108 is formed (see FIG. 5(C)). However, a dry etching method may also be used. Alternatively, both may be used in combination.

[0118] After the oxide semiconductor layer 106 is formed, the substrate is heated at 150° C. or higher and lower than the distortion point of the substrate, preferably at 200° C. or higher. A heat treatment at a temperature of 300° C. to 450° C. may be performed. The heat treatment here is one of the purification treatments for the oxide semiconductor layer. It is possible to reduce hydrogen, water, etc. contained in 06. The heat treatment may be performed before the oxide semiconductor layer 106 is processed into an island shape. After the deposition of the organic semiconductor film 106a and before the deposition of the metal oxide film 108a, a heat treatment is performed. In this case, the deposition temperature of the metal oxide film 108a may be room temperature.

[0119] The heat treatment on the oxide semiconductor layer 106 can be performed using an electric furnace, an RTA apparatus, or the like. By using the TA device, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. This makes it possible to shorten the heating time.

[0120] Note that the heat treatment on the oxide semiconductor layer 106 was performed using nitrogen, oxygen, or ultra-dry air (containing 2 0 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less) or The process may be carried out under a gas (argon, helium, etc.) atmosphere. It is preferable that the air or rare gas does not contain hydrogen, water, etc. Also, nitrogen or rare gas After the heat treatment in the atmosphere, it may be heated in an oxygen or ultra-dry air atmosphere. Hydrogen, water, etc. contained in the oxide semiconductor layer are eliminated, and oxygen is supplied to the oxide semiconductor layer. As a result, the amount of oxygen vacancies in the oxide semiconductor layer can be reduced. can be done.

[0121] Next, a metal oxide layer 108 is formed on the side surface of the oxide semiconductor layer 106 and the side surface and the top surface of the metal oxide layer 108. A pair of electrode layers 110a and 110b are formed (see FIG. 5(D)).

[0122] Here, the first conductive layers 109a and 109b are formed by sputtering. A tungsten film having a thickness of 300 nm and a copper film having a thickness of 300 nm that will become the second conductive layers 111a and 111b are then formed. Then, a photolithography process is performed on the copper film using a photoresist mask. After forming a resist mask, the tungsten film and the copper film are processed using the resist mask. As a result, a pair of electrode layers 110a and 110b are formed. Conductive films such as a tin film and a copper film may be formed by the ALD method or the thermal CVD method. A conductive film can be formed without causing plasma damage to the conductor layer 106 and the metal oxide layer 108. This can be done.

[0123] For example, a wet etching method is used to etch a copper film, and a wet etching method is used to etch a tungsten film. When dry etching using SF6 is applied to the etching, fluoride is formed on the surface of the copper film. The fluoride prevents copper from diffusing from the copper film into the oxide semiconductor layer 106. In addition, the metal oxide layer 108 can provide etching protection to the oxide semiconductor layer 106. It can also function as a protective film.

[0124] Next, the oxide insulating layer 112 is formed on the pair of electrode layers 110a and 110b. The oxide insulating layer 114 is formed over the oxide insulating layer 112 (see FIG. 6A).

[0125] After the oxide insulating layer 112 is formed, the oxide insulating layer 1 is successively formed without being exposed to the air. After the oxide insulating layer 112 is formed, the source gas The oxide insulating layer 114 is continuously formed by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature. By forming the oxide insulating layer 112 and the oxide insulating layer 114 in a non-uniform manner, the oxide insulating layer 112 and the oxide insulating layer 114 are prevented from being oxidized. In addition, the concentration of impurities derived from oxygen in the oxide insulating layer 114 can be reduced. can be moved to the oxide semiconductor layer 106, and oxygen vacancies in the oxide semiconductor layer 106 can be reduced. It is possible to reduce the amount of

[0126] For example, a substrate placed in a vacuum-evacuated processing chamber of a plasma CVD device is heated to 180° C. or higher. The temperature is kept at 400° C. or less, more preferably 200° C. to 370° C., and the raw material gas is introduced into the processing chamber. By introducing the gas, the pressure in the processing chamber is adjusted to 20 Pa or more and 250 Pa or less, more preferably 10 The pressure is between 0 Pa and 250 Pa, and high-frequency power is supplied to the electrode installed in the processing chamber. As a result, a silicon oxide film or a silicon oxynitride film is formed as the oxide insulating layer 112. It is possible.

[0127] By using the above deposition conditions, an oxide insulating layer through which oxygen can pass can be formed as the oxide insulating layer 112. In addition, the metal oxide layer 108 and the oxide insulating layer 112 can be formed. In the subsequent process of forming the oxide insulating layer 114, the oxide semiconductor layer 106 is Image reduction is possible.

[0128] In the above film formation conditions, the substrate temperature is set to 300° C. or higher and 400° C. or lower, and more preferably By setting the temperature to 320°C or higher and 370°C or lower, the bonding strength between silicon and oxygen becomes stronger. As a result, the oxide insulating layer 112 is an oxide insulating layer that is oxygen permeable, dense, and hard. Generally speaking, the etching rate when using 0.5% by weight hydrofluoric acid at 25°C is 10n A silicon oxide film or a silicon oxynitride film having a speed of 8 nm / min or less, preferably 8 nm / min or less. can be formed.

[0129] In addition, in the process of forming the oxide insulating layer 112, the oxide insulating layer 112 is formed while heating. The water contained in the oxide semiconductor layer 106 and the metal oxide layer 108 in contact with the oxide semiconductor layer 106 is The hydrogen contained in the oxide semiconductor layer 106 is effectively removed by the plasma. The oxide insulating layer 112 is formed on the substrate by the deposition process. Since the oxide semiconductor layer 106 is heated, water generated by the combination of oxygen and hydrogen flows into the oxide semiconductor layer 106. That is, the oxide insulating layer 112 is formed by the plasma CVD method. Thus, the amount of water, hydrogen, and the like contained in the oxide semiconductor layer 106 can be reduced.

[0130] Furthermore, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulating layer 1 The water content in the 12 is reduced, so the electrical characteristics of the transistor 210 are less variable. It is possible to reduce the threshold voltage and suppress the fluctuation of the threshold voltage.

[0131] Note that when the oxide insulating layer 112 is formed, the oxide semiconductor layer 106 is not damaged as much as possible. It is preferable to suppress the oxide film formed later to improve the reliability of the transistor. When the oxide insulating layer 114 is formed under conditions that reduce defects in the film, the oxide insulating layer Therefore, the amount of oxygen desorbed from the oxide semiconductor layer 114 can be easily reduced, and defects in the oxide semiconductor layer 106 can be sufficiently reduced. Therefore, when the oxide insulating layer 112 is formed, It is preferable to set the pressure to 100 Pa or more and 250 Pa or less. By this, damage to the oxide semiconductor layer 106 can be reduced.

[0132] In addition, by increasing the amount of oxidizing gas to 100 times the amount of silicon-containing deposition gas, It is possible to reduce the hydrogen content in the oxide insulating layer 112. Since the amount of hydrogen mixed into the semiconductor layer 106 can be reduced, the threshold voltage of the transistor can be reduced. The negative shift can be suppressed.

[0133] The oxide insulating layer 114 is made of a silicon oxide film placed in a vacuum-evacuated processing chamber of a plasma CVD apparatus. The substrate is kept at a temperature of 180° C. or higher and 280° C. or lower, more preferably 200° C. or higher and 240° C. or lower. The raw material gas is introduced into the processing chamber to set the pressure in the processing chamber at 100 Pa or more and 250 Pa or less. More preferably, the pressure is set to 100 Pa or more and 200 Pa or less. .17W / cm 2 More than 0.5W / cm 2 Less than or equal to 0.25 W / cm 2 End 0.35W / cm 2 Under the following conditions of high frequency power supply, silicon oxide film or oxide A silicon nitride film is formed.

[0134] The oxide insulating layer 114 was formed under the conditions of high frequency irradiation at the above power density in a reaction chamber at the above pressure. Supplying microwave power increases the efficiency of decomposing the source gas in the plasma, and oxygen radicals are increased. As the oxidation of the source gas proceeds, the oxygen content in the oxide insulating layer 114 becomes stoichiometric. On the other hand, in the film formed at the above substrate temperature, the ratio of silicon and oxygen is Because the bonding strength is weak, some of the oxygen in the film is released during the heat treatment in the subsequent process. It contains more oxygen than is required for the stoichiometric composition, and some of the oxygen is released when heated. An oxide insulating layer can be formed.

[0135] In the step of forming the oxide insulating layer 114, the oxide insulating layer 112 is The metal oxide layer 108 serves as a protective film for the oxide semiconductor layer 8. In addition, the metal oxide layer 108 serves as a protective film for the oxide semiconductor layer 106. As a result, damage to the oxide semiconductor layer 106 can be reduced, and high-frequency power density can be achieved. The oxide insulating layer 114 can be formed using wave power.

[0136] In addition, in the deposition conditions of the oxide insulating layer 114, a deposition gas containing silicon is used in the oxidizing gas. By increasing the flow rate of the reactive gas, the amount of defects in the oxide insulating layer 114 can be reduced. Typically, ESR measurements reveal that the g value is 2. The spin density of the signal appearing in 001 is 6×10 17 spins / cm 3 Less than 3, preferably ×10 17 spins / cm 3 Less than or equal to 1.5×10 17 spins / cm 3 Below As a result, an oxide insulating layer with a low defect amount can be formed. Reliability can be improved.

[0137] After the oxide insulating layers 112 and 114 are formed, heat treatment is performed. A part of the oxygen contained in the insulating layer 114 is transferred to the oxide semiconductor layer 106, and the oxide semiconductor The amount of oxygen vacancies in the layer 106 can be further reduced. An edge layer 116 is formed.

[0138] When the oxide insulating layers 112 and 114 contain water, hydrogen, or the like, the oxide insulating layers 112 and 114 are provided with a function of blocking the water, hydrogen, or the like. When heat treatment is performed after the formation of the nitride insulating layer 116 having a function of insulating the oxide insulating layer 112, Water, hydrogen, and the like contained in 114 move to the oxide semiconductor layer 106. Therefore, by performing heat treatment before the formation of the nitride insulating layer 116, the oxide This effectively reduces the amount of water and hydrogen contained in the oxide insulating layers 112 and 114.

[0139] Note that the oxide insulating layer 114 is formed over the oxide insulating layer 112 while being heated. Oxygen is transferred to the oxide semiconductor layer 106, and oxygen vacancies in the oxide semiconductor layer 106 are reduced. Therefore, this heat treatment may not be necessary.

[0140] The temperature of the heat treatment on the oxide insulating layers 112 and 114 is typically 150° C. or higher and 400° C. Preferably, the temperature is 300° C. or higher and 400° C. or lower, and more preferably, the temperature is 320° C. or higher and 370° C. or lower. Heat treatment should be carried out in an atmosphere of nitrogen, oxygen, or ultra-dry air (water content of 20 ppm or less, preferably or air at less than 1 ppm, preferably less than 10 ppb), or rare gases (argon, helium The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas atmosphere may be used. It is preferable that the heating process does not contain hydrogen, water, etc. An electric furnace, RTA device, etc. is used. It is possible.

[0141] Here, the heat treatment is performed at 350°C for 1 hour in a nitrogen and oxygen atmosphere. An insulating layer 116 is formed (see FIG. 6(A)).

[0142] When the nitride insulating layer 116 is formed by the plasma CVD method, the substrate temperature is set to 300° C. or higher and 400° C. or lower. By setting the temperature at 320°C or lower, preferably at 370°C or higher, a dense film can be formed. This is preferable.

[0143] For example, when a silicon nitride film is formed as the nitride insulating layer 116 by the plasma CVD method, In this case, it is preferable to use a deposition gas containing silicon, nitrogen, and ammonia as the source gas. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma. The active species react with silicon and the like contained in the silicon-containing deposition gas. This breaks the bonds between silicon and hydrogen and the triple bond between nitrogen. This promotes the bonding of silicon and nitrogen. This leads to fewer bonds between silicon and hydrogen, fewer defects, and a dense silicon nitride film. On the other hand, if the amount of ammonia relative to nitrogen is high, the deposition properties including silicon are increased. The decomposition of gas and nitrogen did not proceed, silicon and hydrogen bonds remained, and defects increased. In addition, a rough silicon nitride film is formed. It is preferable that the flow rate ratio of nitrogen to monoxide is 5 or more and 50 or less, and more preferably 10 or more and 50 or less. .

[0144] Here, the nitride insulating layer 116 is formed by using a plasma CVD apparatus and a mixture of silane, nitrogen, and A silicon nitride film with a thickness of 50 nm is formed from the raw material gases of silicon dioxide and ammonia. The gas is 50 sccm of acetylene, 5000 sccm of nitrogen, and 100 sccm of ammonia. The pressure in the processing chamber was set to 100 Pa, the substrate temperature to 350°C, and a high-frequency power source of 27.12 MHz was used. The PECVD device supplies 1000W of high-frequency power to the parallel plate electrodes. 6000cm2 This is a parallel plate type plasma CVD device, and the power supplied is divided into This is converted to power per unit area (power density) of 1.7 x 10 -1 W / cm 2 It is.

[0145] After the nitride insulating layer 116 is formed, heat treatment may be performed. The temperature of the heat treatment is typically The temperature is 150° C. or higher and 400° C. or lower, preferably 300° C. or higher and 400° C. or lower, more preferably 3 The temperature is 20° C. or higher and 370° C. or lower. Since hydrogen and water in the oxide semiconductor layer 106 are reduced, the above-described defects in the oxide semiconductor layer 106 are reduced. The incidence is suppressed.

[0146] Next, a photolithography process is performed on the nitride insulating layer 116 using a photoresist mask. A resist mask is formed by using the resist mask. The insulating layers 112 and 114 and the gate insulating layer 104 are etched to form openings 117a, 117b is formed (see FIG. 6(B)).

[0147] After removing the resist mask, a conductive film is formed over the nitride insulating layer 116 and then processed. Then, an electrode layer 118 functioning as a back gate electrode is formed (see FIG. 6C).

[0148] Through the above steps, the transistor 210 according to this embodiment can be formed. The other transistors according to this embodiment can be fabricated in the same manner as the transistor 210. is possible.

[0149] As described above, the transistor described in this embodiment has a source electrode layer and a drain electrode layer. A pair of electrode layers that function as a low resistance material such as copper, aluminum, gold, or silver is used. By using an electrode layer including the above-mentioned, a semiconductor device in which wiring delay is suppressed can be manufactured. By providing a metal oxide layer that functions as a barrier layer in contact with the pair of electrode layers, It is possible to provide a semiconductor device having good electrical characteristics by suppressing deterioration of the characteristics.

[0150] In addition, the oxide semiconductor layer including the channel formation region can be formed by the manufacturing process according to this embodiment. To manufacture a highly reliable transistor in which oxygen defects are reduced and the concentration of impurities is reduced. It is possible.

[0151] Furthermore, the transistor according to the present embodiment is a channel-etch type transistor. The metal oxide layer 108, which functions as a barrier layer for preventing impurities from being mixed in, is formed by Since the same mask as the conductor layer 106 is used for processing, a channel protection type transistor is formed. It is therefore possible to reduce the number of masks used in the manufacture of a semiconductor device, as compared to the case where the number of masks used is reduced. Costs can be reduced.

[0152] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0153] (Embodiment 2) In this embodiment, a structure of an oxide semiconductor layer included in a transistor of one embodiment of the present invention will be described. This will be explained in detail below.

[0154] Possible structures of the oxide semiconductor layer will be described below.

[0155] The oxide semiconductor layer is divided into, for example, a non-single crystal oxide semiconductor layer and a single crystal oxide semiconductor layer. Alternatively, the oxide semiconductor layer may be, for example, a crystalline oxide semiconductor layer and an amorphous oxide semiconductor layer. It can be divided into:

[0156] As the non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors made of crystalline oxides include semiconductors made of microcrystalline oxides and amorphous oxides. The materials include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0157] First, we will explain the CAAC-OS film.

[0158] The CAAC-OS film is an oxide film having multiple crystal parts (also called pellets) aligned along the c-axis. It is one of the semiconductor layers.

[0159] Transmission Electron Microscope (TEM) A bright-field image and a combined diffraction pattern of CAAC-OS were obtained by using a high-resolution microscope. By observing the TEM image, multiple pellets can be confirmed. On the other hand, the high-resolution TEM image also clearly shows the boundaries between pellets, i.e., grain boundaries. Therefore, CAAC-OS cannot check the boundary between the It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0160] For example, as shown in FIG. 8(A), the cross section of the CAAC-OS is A high-resolution TEM image is observed. Here, spherical aberration correction is used. The TEM image is observed using the Spherical Aberration Corrector function. Hereinafter, the high-resolution TEM image using the correction function will be specifically referred to as the Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM images were obtained using, for example, an atomic resolution analyzer manufactured by JEOL Ltd. This can be done using a deposition electron microscope such as the JEM-ARM200F.

[0161] An enlarged Cs-corrected high-resolution TEM image of region (1) in Figure 8(A) is shown in Figure 8(B). From (B), it can be seen that the metal atoms are arranged in layers in the pellet. Each layer of atoms is a concave surface of the CAAC-OS film-forming surface (also called a surface on which the film is to be formed) or a concave surface of the top surface. The shape reflects a convexity and is arranged parallel to the surface on which the CAAC-OS is formed or the upper surface.

[0162] In FIG. 8(B), CAAC-OS has a characteristic atomic arrangement. The atomic arrangement of the Pellet is shown by auxiliary lines. The size of each pellet is about 1 nm to 3 nm, and the size varies depending on the inclination of the pellets. It can be seen that the size of the gap that occurs is about 0.8 nm. They can also be called nanocrystals (nc).

[0163] Here, from the Cs-corrected high-resolution TEM image, the pellet 5 of CAAC-OS on the substrate 5120 was A schematic diagram of the arrangement of 100 would resemble a pile of bricks or blocks. (See Figure 8(D)). The pellets in Figure 8(C) are tilted. The portion corresponds to the region 5161 shown in FIG.

[0164] For example, as shown in FIG. 23(A), the CAAC-OS Observe the Cs-corrected high-resolution TEM images of the planes of regions (1) and (2) in Figure 23(A). The Cs-corrected high-resolution TEM images of the enlarged areas (a) and (b) are shown in Fig. 23(B) and Fig. 2 3(C) and 23(D). The pellets were then inspected to ensure that the metal atoms were arranged in triangular, quadrangular or hexagonal shapes. However, no regularity is observed in the arrangement of metal atoms among different pellets.

[0165] For example, X-ray diffraction (XRD) of CAAC-OS with InGaZnO4 crystals Using the out-of-plane method with a 3D ray diffraction (RF) device, When structural analysis was performed, a peak appeared at a diffraction angle (2θ) of approximately 31°, as shown in Figure 24(A). This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the CAAC-OS crystal has a c-axis orientation, and the c-axis is approximately perpendicular to the surface on which the CAAC-OS is formed or the upper surface. You can see that it is pointing in the right direction.

[0166] In addition, the out-of-plane method of CAAC-OS with InGaZnO4 crystals In the structural analysis by NMR, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ around 36° may be due to the c-axis orientation in some CAAC-OS. This indicates that the CAAC-OS contains crystals that do not have a peak at 2θ of around 31°. It is preferable that the compound exhibits a peak at 2θ of about 36° and does not exhibit a peak at 2θ of about 36°.

[0167] On the other hand, in-plan X-ray irradiation is performed on CAAC-OS in a direction perpendicular to the c-axis. When the structure is analyzed by the δ method, a peak appears at 2θ of about 56°. This peak is due to In It is assigned to the (110) plane of the GaZnO4 crystal. In the case of CAAC-OS, 2θ is set to 56 The sample was rotated around the normal vector of the sample surface as the axis (φ axis) while performing the analysis. Even if a φ scan is performed, no clear peak appears as shown in FIG. However, in the case of a single crystal oxide semiconductor such as InGaZnO4, 2θ is fixed at around 56° and φ shift is When scanning was performed, the peaks attributable to the crystal plane equivalent to the (110) plane were as shown in FIG. Therefore, from the structural analysis using XRD, CAAC-OS has the following structure: It can be seen that the orientation of the a-axis and b-axis is irregular.

[0168] Next, the In-Ga-Zn oxide CAAC-OS was subjected to a plasmon resonance in a direction parallel to the sample surface. Diffraction pattern when an electron beam with a lobe diameter of 300 nm is incident (selected area transmission electron diffraction The pattern is shown in FIG. 25(A). The spots due to the (009) plane of the O4 crystal are confirmed. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the On the other hand, the same sample had a surface perpendicular to the sample surface. The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident from the direction is shown in Fig. 25(B ) is shown. From FIG. 25(B), a ring-shaped diffraction pattern is confirmed. Therefore, Diffraction analysis also revealed that the a-axis and b-axis of the pellets contained in CAAC-OS do not have any orientation. It can be seen that the first ring in FIG. 25(B) is a crystal of InGaZnO4. This is thought to be due to the (010) and (100) planes. The second ring is thought to be due to the (110) plane.

[0169] In this way, the c-axis of each pellet (nanocrystal) is approximately perpendicular to the surface on which the pellet is formed or the top surface. Because of the direction, CAAC-OS is aligned with CANC (C-Axis Aligned The oxide semiconductor may also be referred to as an oxide semiconductor having nanocrystals.

[0170] CAAC-OS is an oxide semiconductor with a low concentration of impurities. The impurities are hydrogen, carbon, and silicon. Elements other than the main components of oxide semiconductors, such as silicon and transition metal elements. The elements that bond with oxygen more strongly than the metal elements that make up the oxide semiconductor are The removal of oxygen from the oxide semiconductor disrupts the atomic arrangement of the oxide semiconductor, which is a factor in reducing the crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have atomic radii (or molecular radii). Since the radius of the oxide semiconductor is large, when the oxide semiconductor is contained in the oxide semiconductor, the atomic arrangement of the oxide semiconductor is disturbed. Impurities contained in an oxide semiconductor can cause carrier transport and lead to a decrease in crystallinity. These may be sources of tripping or carrier generation.

[0171] In addition, the CAAC-OS is an oxide semiconductor with a low density of defect states. Oxygen deficiencies in the body act as carrier traps or capture hydrogen to reduce the amount of carriers. It can be a source of pollution.

[0172] In addition, transistors using CAAC-OS show changes in their electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0173] Next, a microcrystalline oxide semiconductor layer will be described.

[0174] Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. A region in which no clear crystal part can be confirmed is also included. The crystal part contained in the crystal is 1 nm to 100 nm or 1 nm to 10 nm in size. In particular, microcrystals with a size of 1 nm to 10 nm or 1 nm to 3 nm are often found. The oxide semiconductor having nanocrystals is called nc-OS (nanocrystalline- In addition, nc-OS is a In high-resolution TEM images, the grain boundaries may not be clearly visible. It is possible that the pellets in AAC-OS have the same origin. Therefore, in the following, The crystalline part of c-OS is sometimes called a pellet.

[0175] The nc-OS is a nano-sized area (e.g., an area of ​​1 nm to 10 nm, especially 1 nm to 3 nm). The nc-OS has periodic atomic arrangement in the sub-nm region. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD apparatus that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peaks were detected. Also, for nc-OS, the probe diameter (e.g. When electron diffraction (also called selected area electron diffraction) is performed using an electron beam with a diameter of 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size. When the electron diffraction pattern is applied to the nc-OS, a spot is observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. When nanobeam electron diffraction was performed on the OS, multiple spots were observed within the ring-shaped region. There may be cases where this occurs.

[0176] In this way, the crystal orientation of each pellet (nanocrystal) is not regular. nc-OS has NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0177] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. Therefore, nc-OS is The defect level density is higher than that of AC-OS.

[0178] Next, the amorphous oxide semiconductor will be described.

[0179] Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystal parts. An example is an oxide semiconductor that has an amorphous state, such as quartz.

[0180] In the case of an amorphous oxide semiconductor, no crystalline parts can be confirmed in a high-resolution TEM image.

[0181] When the structure of amorphous oxide semiconductors is analyzed using an XRD device, out-of-plane In the analysis by the ane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on the amorphous oxide semiconductor, a halo pattern is observed. In contrast, when nanobeam electron diffraction is performed, no spots are observed, but a halo pattern is observed. can be.

[0182] There are various views on amorphous structures. For example, A structure that does not have a completely amorphous structure is called a completely amorphous structure. In addition, the distance between the nearest neighbors or the second nearest neighbors is called the A structure that has order but no long-range order is sometimes called an amorphous structure. According to the strictest definition, an oxide semiconductor that has even a slight degree of order in its atomic arrangement is called an amorphous semiconductor. In addition, oxides with at least long-range order cannot be called solid oxide semiconductors. The semiconductor cannot be called an amorphous oxide semiconductor. For example, the CAAC-OS and nc-OS are It cannot be called a compound semiconductor.

[0183] Note that the oxide semiconductor has a structure that exhibits physical properties between the nc-OS and the amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor. (a-like OS:amorphous-like Oxide Semiconductor It is called a uctor.

[0184] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. and regions where no crystalline portion can be identified.

[0185] The following describes how the effect of electron irradiation differs depending on the structure of the oxide semiconductor.

[0186] We prepared a-like OS, nc-OS and CAAC-OS. -Ga-Zn oxide.

[0187] First, high-resolution cross-sectional TEM images of each sample are obtained. It can be seen that each of the samples has a crystalline portion.

[0188] In addition, the size of the crystal part of each sample is measured. Figure 26 shows the crystal part of each sample (from 22 points). This is an example of investigating the change in the average size of the 45 locations. It can be seen that the crystal part grows larger according to the cumulative dose of electron irradiation. As shown in (1) in 26, the size of the particles was about 1.2 nm in the initial stage of TEM observation. The crystal part was exposed to a cumulative irradiation dose of 4.2 × 10 8 e - / nm 2 In the case of On the other hand, the nc-OS and CAAC-OS have grown to a size of 100 nm. The cumulative electron dose from the start of irradiation was 4.2×10 8 e - / nm 2 The range of It can be seen that there is no change in the size of the crystals regardless of the cumulative dose of irradiation. As shown in (2) in Figure 26, the size of the crystals was 1.0 mm regardless of the TEM observation. As shown in (3) in Figure 26, the TEM Regardless of the observation time, the size of the crystals is found to be approximately 2.1 nm.

[0189] In this way, a-like OS can be observed by irradiating it with a small amount of electrons, which is the same level as observed by TEM. Crystallization may occur and the growth of crystals may be observed. On the other hand, good quality nc-OS and In the case of CAAC-OS, crystallization due to minute electron irradiation, which is comparable to that observed with a TEM, is hardly observed. You can see that it cannot be seen.

[0190] The size of the crystalline parts of the a-like OS and nc-OS was measured using high-resolution TEM. For example, InGaZnO4 crystals have a layered structure, and In The unit cell of the InGaZnO4 crystal is: It has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. The spacing between adjacent layers is determined by the lattice of the (009) plane. This is approximately the same as the interplanar spacing (also called the d value), and the value was determined to be 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and investigated the In the area where the thickness is between 0.28 nm and 0.30 nm, each lattice fringe is InGaZ It corresponds to the ab plane of the nO4 crystal.

[0191] In addition, the density of an oxide semiconductor may differ depending on the structure. For example, If the composition of is known, the density of the single crystal of the same composition can be compared to that of the said composition. The structure of the oxide semiconductor can be estimated. For example, the density of a single crystal is e The density of OS is 78.6% or more and less than 92.3%. For example, the density of a single crystal is In contrast, the density of the nc-OS and CAAC-OS was 92.3% or more and less than 100%. Note that an oxide semiconductor having a density of less than 78% of that of a single crystal can be formed by film formation. The body is difficult.

[0192] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor that satisfies the [number ratio], the single crystal InGaZnO4 with a rhombohedral crystal structure Density is 6.357g / cm 3 Therefore, for example, In:Ga:Zn=1:1:1[ In the case of an oxide semiconductor that satisfies the atomic ratio, the density of the a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1:1 [ In the oxide semiconductor that satisfies the [atomic ratio], the density of the nc-OS and the density of the CAAC-OS are is 5.9g / cm 3 More than 6.3g / cm 3 It will be less than.

[0193] In addition, there are cases where single crystals with the same composition do not exist. In such cases, the composition may differ in any ratio. By combining single crystals, it is possible to calculate the density equivalent to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions. However, the density should be calculated using as few types of single crystals as possible. It is preferable to perform the calculation in combination.

[0194] The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, or a microcrystalline oxide semiconductor. The layer may be a laminated film having two or more of a compound semiconductor and a CAAC-OS.

[0195] Oxide semiconductors, which have low impurity concentrations and low defect state densities (few oxygen vacancies), have carrier Therefore, such an oxide semiconductor can be used as a high-purity intrinsic or The a-type oxide semiconductor is essentially a highly pure intrinsic oxide semiconductor. The impurity concentration is lower than that of OS-like and amorphous oxide semiconductors, and the density of defect states is lower. That is, a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor is likely to be obtained. In the case of a transistor using the CAAC-OS or nc-OS, the threshold voltage is negative. In addition, the high purity intrinsic or In reality, high-purity intrinsic oxide semiconductors have few carrier traps. Transistors using C-OS or nc-OS have small fluctuations in electrical characteristics and are highly reliable. The charge trapped in the carrier traps in the oxide semiconductor is It takes a long time for the charge to be released, and it can behave as if it were a fixed charge. Therefore, a transistor using an oxide semiconductor with a high impurity concentration and a high density of defect states has a low current density. The electrical characteristics may become unstable. <Film formation model> An example of a film formation model for CAAC-OS and nc-OS will be described below.

[0196] FIG. 27A shows how a CAAC-OS film is formed by a sputtering method. FIG.

[0197] The target 5130 is attached to a backing plate. A plurality of magnets are disposed at positions facing the target 5130. The magnetic field is generated by the magnets. The arrangement and configuration of the magnets are described above. Please refer to the description of the deposition chamber. The sputtering method is called magnetron sputtering.

[0198] The target 5130 has a polycrystalline structure, with each grain including a cleavage plane.

[0199] As an example, the cleavage surface of a target 5130 having an In-Ga-Zn oxide is described. FIG. 28(A) shows the crystal structure of InGaZnO4 contained in the target 5130. In FIG. 28(A), the c-axis is oriented upward, and the InGaZnO This is the structure of the crystal of 4.

[0200] As shown in FIG. 28(A), the oxide in each of the two adjacent Ga-Zn-O layers is It can be seen that the atomic groups are arranged close to each other. And the oxygen atom has a negative charge. As a result, the two adjacent Ga-Zn-O layers repel each other. A ZnO4 crystal has a cleavage plane between two adjacent Ga-Zn-O layers.

[0201] The substrate 5120 is disposed so as to face the target 5130, and the distance therebetween is d ( The target-substrate distance (TS distance) is preferably 0.01 m or more and 1 m or less. The thickness of the deposition chamber is set to 0.02m or more and 0.5m or less. Most of the deposition gas (e.g., oxygen) is The chamber is filled with a gas mixture containing 5% or more by volume of nitrogen, argon, or oxygen. The pressure is controlled to be 0.1 Pa or more and 100 Pa or less, preferably 0.1 Pa or more and 10 Pa or less. By applying a certain voltage to the target 5130, discharge begins and plasma is generated. It is noted that a high-density plasma region is formed near the target 5130 by the magnetic field. In the high density plasma region, the deposition gas is ionized, and ions 5101 are generated. The ions 5101 are, for example, positive oxygen ions (O + ) and argon cations (A r + ) etc.

[0202] The ions 5101 are accelerated toward the target 5130 by the electric field, and eventually reach the target 5130. At this time, flat or pellet-shaped sputter particles are ejected from the cleavage plane. The pellets 5100a and 5100b are peeled off and knocked out. 5100a and pellet 5100b are structured by the impact of the collision of ion 5101. Distortion may occur.

[0203] The pellet 5100a is a flat or pellet-shaped pellet having a triangular, for example equilateral, plane. The pellet 5100b has a hexagonal, for example, regular hexagonal, planar surface. The sputtered particles are in the form of a plate or pellet. Pellet 5100b and other flat or pellet-shaped sputter particles are collectively referred to as pellet 5 The planar shape of the pellet 5100 is not limited to a triangle or a hexagon. For example, a triangle (e.g., an equilateral triangle) may have a shape that is made up of multiple triangles. In some cases, the shape may be two squares (e.g., a diamond).

[0204] The thickness of the pellet 5100 is determined according to the type of deposition gas. The reason for this will be described later. It is preferable that the thickness of the pellet 5100 is uniform. Thin pellets are preferred over thick cubes. The thickness of the 5100 is 0.4 nm or more and 1 nm or less, preferably 0.6 nm or more and 0.8 nm or less. For example, the pellet 5100 has a width of 1 nm or more and 3 nm or less, preferably The diameter of the pellet 5100 is 1.2 nm or more and 2.5 nm or less. For example, the target 51 having In-Ga-Zn oxide corresponds to the initial nucleus described in . When ions 5101 are bombarded onto the Ga-Zn-O layer 30, as shown in FIG. A pellet 5100 having three layers, an In-O layer, a Ga-Zn-O layer, and a Ga-Zn-O layer, is ejected. FIG. 28(C) shows the structure of the pellet 5100 when observed from a direction parallel to the c-axis. Therefore, the pellet 5100 is composed of two Ga-Zn-O layers (pans) and an In- It can also be called a nano-sized sandwich structure having a layer (filling) and a layer (filling).

[0205] The pellet 5100 receives an electrical charge as it passes through the plasma, causing the sides to become negative or positive. The pellet 5100 has oxygen atoms on the side, and the oxygen atoms are negatively charged. In this way, the sides can be charged with the same polarity, The repulsion between the particles occurs, allowing the particles to maintain their flat shape. However, in the case of In-Ga-Zn oxide, the oxygen atom bonded to the indium atom is negatively charged. Or, an acid bonded to an indium atom, a gallium atom, or a zinc atom may The elementary atoms may become negatively charged. Also, the pellet 5100 may become charged as it passes through the plasma. It grows by bonding with indium atoms, gallium atoms, zinc atoms, oxygen atoms, etc. This corresponds to the difference in size between (2) and (1) in Figure 26 above. When the substrate 5120 is at room temperature, the pellet 5100 does not grow any more. The film is formed at room temperature. Even if the substrate 5120 has a large area, the nc-OS film can be formed. In order to grow 100 in plasma, the film formation power in the sputtering method must be increased. It is effective to increase the deposition power to stabilize the structure of the pellet 5100. It is possible.

[0206] As shown in FIG. 27(A) and FIG. 27(B), for example, a pellet 5100 is It flies like a kite through the air and flutters up to the top of the substrate 5120. Pellet 51 Since the 00 is electrically charged, it approaches an area where other pellets 5100 are already deposited. Here, on the upper surface of the substrate 5120, a repulsive force is generated in a direction parallel to the upper surface of the substrate 5120. In addition, the substrate 5120 and the target 51 Since a potential difference is applied between the substrate 5120 and the target 5130, Therefore, the pellet 5100 is disposed on the upper surface of the substrate 5120. The magnetic field and the electric current act on the object, resulting in a force (Lorentz force). This is what Fleming This can be understood by the left-hand rule.

[0207] The pellet 5100 has a large mass compared to a single atom. In order to move the object, it is important to apply some kind of force from the outside. It is possible that the force is generated by the action of a field and an electric current. In order to increase the size of the substrate 5120, the substrate 5120 is The magnetic field is 10 G or more, preferably 20 G or more, more preferably 30 G or more, and more preferably It is preferable to provide an area where the resistance is 50 G or more. The magnetic field parallel to the top surface of the substrate 5120 is 1.5 times that of the magnetic field perpendicular to the top surface of the substrate 5120. fold or more, preferably 2 times or more, more preferably 3 times or more, and even more preferably 5 times or more. It is a good idea to provide an area for this purpose.

[0208] At this time, the magnet unit and / or the substrate 5120 move relatively. By rotating the substrate 5120, the direction of the horizontal magnetic field on the upper surface of the substrate 5120 continues to change. Therefore, on the upper surface of the substrate 5120, the pellet 5100 exerts forces in various directions. It can receive and move in various directions.

[0209] Also, when the substrate 5120 is heated as shown in FIG. 27(A), the pellet 5100 The resistance due to friction between the substrate 5120 and the substrate 5120 is small. The pellet 5100 glides over the upper surface of the substrate 5120. The movement occurs with the flat surface facing the substrate 5120. When the pellet 5100 reaches the side of the pellet, the sides of the pellet 5100 are joined together. The oxygen atom on the side of 0 is removed. The removed oxygen atom causes the acid in CAAC-OS to be Since the electron vacancies may be filled, the CAAC-OS has a low defect level density. The temperature of the upper surface of 5120 is, for example, 100°C or more and less than 500°C, 150°C or more and less than 450°C. or 170° C. or more and less than 400° C. That is, when the substrate 5120 has a large area, In this case, it is possible to form a CAAC-OS film.

[0210] In addition, when the pellet 5100 is heated on the substrate 5120, the atoms are rearranged and the The structural distortion caused by the collision of the pellet 5101 is relaxed. Pellet 5100 becomes almost a single crystal, so pellet 5 Even if the 100 are heated after bonding, the pellet 5100 itself hardly expands or contracts. This is not possible. Therefore, the gaps between the pellets 5100 may widen, causing defects such as grain boundaries. It does not form depressions or crevasses.

[0211] In addition, the CAAC-OS is not made of a single crystal oxide semiconductor. The aggregates of Pellet 5100 (nano crystals) are arranged like piles of bricks or blocks. In addition, there are no grain boundaries between them. Even if CAAC-OS is deformed, such as shrinking, by heating or bending, the local stress Therefore, it is possible to reduce the strain or release the distortion. The structure of nc-OS is suitable for biological devices. The arrangement is like something stacked in order.

[0212] When the target is sputtered with ions, not only pellets but also zinc oxide and other substances fly out. Since zinc oxide is lighter than the pellets, it may reach the top surface of the substrate 5120 first. And, 0.1 nm to 10 nm, 0.2 nm to 5 nm, or 0.5 nm A zinc oxide layer 5102 having a thickness of 2 nm or less is formed. A schematic cross-sectional view is shown in FIG.

[0213] As shown in FIG. 29(A), a pellet 5105a and a pellet Here, the pellets 5105a and 5105b are piled up. The pellets 5105c are arranged so that their sides are in contact with each other. After being deposited on pellet 5105b, the pellet 5105b slides on the pellet 5105b. In another aspect of 5a, a plurality of particles 510 ejected from the target along with zinc oxide. The substrate 5120 is heated to crystallize the region 5105a1. The element 5103 may include oxygen, zinc, indium, gallium, and the like.

[0214] Then, as shown in FIG. 29(B), the region 5105a1 is assimilated with the pellet 5105a. The pellet 5105c is formed by cutting the pellet 5105a1 at its side. Place it so that it touches the other side of 05b.

[0215] Next, as shown in FIG. 29(C), a pellet 5105d is further formed on the pellet 5105a2. and pellet 5105b, and then pellet 5105a2 and pellet 51 It slides on the pellet 5105b. It also slides towards the other side of the pellet 5105c. The pellet 5105 e slides on the zinc oxide layer 5102 .

[0216] As shown in FIG. 29(D), the pellet 5105d has a side surface similar to that of the pellet 510. The pellet 5105e is arranged so that its side surface is in contact with the pellet 5105a. Also, the other side of the pellet 5105d is arranged so as to contact the other side of the pellet 5105c. In the process, a plurality of particles 5103 that fly out of the target together with zinc oxide are deposited on the substrate 512. Heating at 0 causes crystallization, forming region 5105d1.

[0217] As described above, the piled up pellets are arranged so that they come into contact with each other, and the pellets are bonded on their sides. As a result of the crystal growth, a CAAC-OS is formed on the substrate 5120. The individual pellets of AAC-OS are larger than those of nc-OS. This corresponds to the difference in size between (3) and (2) in 26.

[0218] In addition, the gaps between the pellets 5100 are extremely small, so it feels like one large pellet. Large pellets may form. Large pellets have a single crystal structure. The size of the ret is 10 nm to 200 nm, 15 nm to 100 nm when viewed from the top. The thickness of the transistor may be less than 20 nm or less than 50 nm. If the channel-forming region is smaller than the large pellet, a single crystal is used as the channel-forming region. A region having a structure can be used. Also, by making the pellet larger, A region having a single crystal structure as a channel forming region, a source region, and a drain region of the sta may be used.

[0219] In this way, the channel formation region of the transistor and the like are formed in a region having a single crystal structure. By doing so, it may be possible to improve the frequency characteristics of the transistor.

[0220] Based on the above model, it is considered that the pellet 5100 accumulates on the substrate 5120. Therefore, unlike epitaxial growth, if the surface on which the film is to be formed does not have a crystal structure, For example, the CAAC-OS film can be formed on the substrate 5120. Even if the structure of the upper surface (the surface to be formed) is amorphous (e.g., amorphous silicon oxide), It is possible to form a film of C-OS.

[0221] In addition, the CAAC-OS can be used even if the upper surface of the substrate 5120 on which the formation is to be performed is uneven. For example, the pellets 5100 are arranged along the shape of the upper surface of the substrate 5120. If the surface is atomically flat, the pellet 5100 will be placed with the flat surface, which is parallel to the ab plane, facing down. Since the layers are arranged facing each other, a layer having a uniform thickness, flatness, and high crystallinity is formed. By stacking the layers n times (n is a natural number), CAAC-OS can be obtained. do.

[0222] On the other hand, even if the upper surface of the substrate 5120 has unevenness, the CAAC-OS can be easily formed by the pellet 510. The structure is made up of n layers (n is a natural number) of 0s arranged side by side along the convex surface. Since the surface of the CAAC-OS is uneven, gaps may easily occur between the pellets. However, there are cases where intermolecular forces act between the pellets, and even if there are irregularities, the The gaps are arranged to be as small as possible. Therefore, even if there are irregularities, high crystallinity is maintained. It can be called CAAC-OS.

[0223] Therefore, CAAC-OS does not require laser crystallization and can be used on large-area glass substrates. Even if there is any, a uniform film can be formed.

[0224] Since the CAAC-OS film is formed by such a model, the sputtered particles have a thin film thickness. It is preferable that the sputtered particles are in the form of pellets. However, the surface facing the substrate 5120 may not be uniform, and the thickness and crystal orientation may not be uniform. be.

[0225] The film formation model shown above shows that a highly crystalline film can be formed even on a substrate surface with an amorphous structure. It is possible to obtain a CAAC-OS having the formula:

[0226] FIG. 9C shows the electron gun chamber 10, the optical system 12 below the electron gun chamber 10, and the test specimen below the optical system 12. A sample chamber 14, an optical system 16 below the sample chamber 14, an observation chamber 20 below the optical system 16, and an observation chamber 2 0 and a film chamber 22 below the observation chamber 20. The folding measurement device is shown. The camera 18 is installed facing the inside of the observation room 20. The chamber 22 may not be provided.

[0227] FIG. 9(D) shows the internal structure of the transmission electron diffraction measurement device shown in FIG. Inside the electron diffraction measurement device, electrons emitted from an electron gun installed in the electron gun chamber 10 are incident on a light source. The electrons are irradiated onto a substance 28 placed in the sample chamber 14 via the optical system 12. The electrons are incident on a fluorescent screen 32 installed inside the observation room 20 via the optical system 16. In 2, a transmission electron diffraction pattern is measured by measuring a pattern that appears according to the intensity of the incident electrons. It can be determined.

[0228] The camera 18 is set facing the fluorescent screen 32 and captures the pattern appearing on the fluorescent screen 32. It is possible to set the distance between the center of the camera lens and the top surface of the fluorescent screen 32 and The angle between the upper surface of the fluorescent screen 32 and the light source 31 is, for example, 15° to 80°, or 30° to 75°. The smaller the angle, the more difficult it is to capture the image captured by the camera 18. However, if the angle is known in advance, the transmission electron diffraction pattern will be significantly distorted. It is also possible to correct distortions in the obtained transmission electron diffraction pattern by using a camera. In some cases, it may be acceptable to install the camera 18 in the film chamber 22. 22 so as to face the direction of incidence of the electrons 24. In this case, the fluorescent screen 32 It is possible to capture a transmission electron diffraction pattern with little distortion from the backside.

[0229] A holder for fixing a substance 28, which is a sample, is installed in the sample chamber 14. The holder is structured to be transparent to electrons passing through the material 28. The holder may have a function of moving the holder 28 along the X-axis, Y-axis, Z-axis, etc. For example, 1 nm or more and 10 nm or less, 5 nm or more and 50 nm or less, 10 nm or more and 100 nm or less The range is 50 nm to 500 nm, 100 nm to 1 μm, etc. These ranges can be set optimally depending on the structure of the substance 28. good.

[0230] Next, the transmission electron diffraction pattern of the material is measured using the above-mentioned transmission electron diffraction measurement device. The method will be explained.

[0231] For example, as shown in FIG. 9(D), the irradiation position of the electron 24, which is a nanobeam, on the material is changed. By scanning the material, it is possible to observe how the structure of the material changes. In this case, if the material 28 is a CAAC-OS film, the diffraction pattern shown in FIG. Alternatively, if the material 28 is an nc-OS film, a turn is observed as shown in FIG. Such a diffraction pattern is observed.

[0232] By the way, even if material 28 is a CAAC-OS film, it may be partially composed of an nc-OS film, etc. The same diffraction pattern may be observed. Therefore, the quality of the CAAC-OS film can be judged by The ratio of the area where the diffraction pattern of the CAAC-OS film is observed in a certain range (CAAC For example, a good quality CAAC-OS film can be expressed as In this case, the CAAC ratio is 60% or more, preferably 80% or more, and more preferably 90% or more. The diffraction pattern of the CAAC-OS film is different from that of the CAAC-OS film. The observed area is denoted as the non-CAAC rate.

[0233] As an example, immediately after film formation (denoted as-sputtered) or in an atmosphere containing oxygen The top surface of each sample with CAAC-OS film after the 450°C heat treatment was scanned. Transmission electron diffraction patterns were obtained while scanning at a speed of 5 nm / sec for 60 sec. The diffraction pattern was observed while scanning, and the observed diffraction pattern was converted to a still image every 0.5 seconds. The CAAC rate was calculated by converting the electron beam into the ion beam. A nano-electron beam was used. The same measurements were performed on six samples. The rate was calculated using the average value of six samples.

[0234] The CAAC ratio in each sample is shown in Fig. 10(A). The AC ratio was 75.7% (non-CAAC ratio was 24.3%). The CAAC content of the treated CAAC-OS film was 85.3% (non-CAAC content was 14.7%). It can be seen that the CAAC conversion rate is higher after the 450°C heat treatment than immediately after the film formation. In other words, the non-CAAC ratio is low due to heat treatment at high temperatures (e.g., 400°C or higher). In addition, in the case of heat treatment at temperatures below 500°C, It can be seen that a CAAC-OS membrane with a high CAAC content can be obtained.

[0235] Here, most of the diffraction patterns different from those of the CAAC-OS film are similar to those of the nc-OS film. In addition, the amorphous oxide semiconductor film was not observed in the measurement area. Therefore, it is possible that the heat treatment produces a region with a structure similar to that of the nc-OS film. It is suggested that the CAAC domain is rearranged due to the influence of the structure of the neighboring domain.

[0236] 10(B) and 10(C) show the CAAC-O immediately after deposition and after heat treatment at 450° C. 10(B) and 10(C) are planar TEM images of the S film. It can be seen that the CAAC-OS film after the 0°C heat treatment has a more homogeneous film quality. It can be seen that the film quality of the CAAC-OS film is improved by the heat treatment at high temperature.

[0237] By using such a measurement method, it is possible to analyze the structure of an oxide semiconductor layer having multiple structures. This may be the case.

[0238] A transistor according to one embodiment of the present invention can be formed using an oxide semiconductor layer having any of the above structures. The data can be configured.

[0239] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0240] (Embodiment 3) In this embodiment, a semiconductor device including a transistor having a different configuration from that in the first embodiment is The transistor described in this embodiment is the same as that described in the embodiment. 1, it is different in that it has a multilayer film having multiple oxide semiconductor layers. The details of a transistor will be described using the semiconductor device of the first embodiment shown in FIG.

[0241] 7A and 7B show a plan view of a transistor 310 included in the semiconductor device of this embodiment. 7A is a plan view of a transistor 310, and FIG. 7A is a cross-sectional view taken along dashed lines A9-A10 and B9-B10 in FIG. 7(A), for clarity, the substrate 100 and some of the components of the transistor 310 (e.g. 7C, the transistor 310 is shown with the gate insulating layer and the like omitted. FIG. 1 shows a band diagram of the stacked structure included in

[0242] The transistor 310 included in the semiconductor device shown in FIG. The oxide semiconductor layer provided between the oxide semiconductor layer 306a and the oxide semiconductor layer 108 is The transistor 210 shown in FIG. 2 differs from the transistor 210 shown in FIG. Other configurations are the same as those in FIG. 2, and the above explanation can be referred to.

[0243] In the transistor 310, the oxide semiconductor layers 306a and 306b are The GaN-GaN-GaN is formed of a metal oxide containing at least In or Zn. A typical example is In-GaN. a oxide, In-Zn oxide, In-M-Zn oxide (M is Ti, Ga, Y, Zr, La , Ce, Nd or Hf). The oxide semiconductor layer 306b is The energy of the bottom of the conduction band is closer to the vacuum level than that of 06a. The energy of the bottom of the conduction band of the oxide semiconductor layer 306b is The difference in energy is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, 0.15 eV or more, or 0.5 eV or more and 2 eV or less, or 1 eV or less. That is, the oxide semiconductor The difference between the electron affinity of the oxide semiconductor layer 306b and the electron affinity of the oxide semiconductor layer 306a is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, 0.15 eV or more, or 0.5 eV or more , and is 2 eV or less, or 1 eV or less.

[0244] With such a structure, when a voltage is applied to the transistor 310, the oxide semiconductor The layer 306a becomes the main path for current and functions as a channel region. The layer 306b is a kind of metal element included in the oxide semiconductor layer 306a in which a channel is formed. Since the oxide semiconductor layer is composed of the above, the oxide semiconductor layer 306a and the oxide semiconductor At the interface with the layer 306b, interfacial scattering is unlikely to occur. Since the rear movement is not hindered, the field effect mobility of the transistor is increased.

[0245] When the oxide semiconductor layer 306b is an In-M-Zn oxide, the element M is Ti, Ga, By having Y, Zr, La, Ce, Nd or Hf in a higher atomic ratio than In, The energy gap of the semiconductor layer 306b can be increased and the electron affinity can be decreased. The difference in electron affinity with the oxide semiconductor layer 306a can be controlled by the composition of element M. In addition, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf may become oxygen. Since these elements have a stronger bond with In, it is necessary to have a higher atomic ratio of these elements than In. This makes it difficult for oxygen deficiency to occur.

[0246] When the oxide semiconductor layer 306b is an In-M-Zn oxide, I other than Zn and O The atomic ratio of n to M is preferably such that In is less than 50 atomic % and M is less than 50 atomic %. ic% or more, more preferably, In is less than 25 atomic % and M is 75 atomic %. % or more.

[0247] In addition, the oxide semiconductor layer 306a and the oxide semiconductor layer 306b are made of In-M-Zn oxide ( In the case where M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf, the oxide semiconductor layer 30 In comparison with 6a, M (Ti, Ga, Y, Zr, La, The atomic ratio of Ce, Nd, or Hf is large, and is typically contained in the oxide semiconductor layer 306a. Compared with the above atoms contained in the This is a high atomic ratio.

[0248] In addition, the oxide semiconductor layer 306a and the oxide semiconductor layer 306b are made of In-M-Zn oxide ( In the case where M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf, the oxide semiconductor layer 30 The oxide semiconductor layer 6a is In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 306b is In :M:Zn=x2:y2:z2 [atomic ratio], y2 / x2 is greater than y1 / x1. Preferably, y2 / x2 is 1.5 times or more larger than y1 / x1. More preferably, , y2 / x2 is more than twice as large as y1 / x1, and more preferably, y2 / x2 is more than y1 / x1. In this case, in the oxide semiconductor layer, y1 is 3 or more times or 4 or more times larger than When x is 1 or more, a transistor including the oxide semiconductor layer can have stable electrical characteristics. However, when y1 is three times or more of x1, the oxide semiconductor layer is not used. Because the field effect mobility of the transistor would be reduced, y1 is less than three times x1. The composition of the oxide semiconductor layer is preferably determined by inductively coupled plasma mass spectrometry (ICP-MS analysis). For example, the thickness of a tube with In2O3:Ga2O3:ZnO=1:1:1 can be measured by the Using a target (In:Ga:Zn=1:1:0.5), the sputtering method was performed with an argon gas flow. The metal oxide film obtained at a flow rate of 40 sccm was InGa 0.95 Zinc 0.41 O 3.33 The measurement method is Rutherford backscattering spectrometry. d Backscattering Spectrometry (RBS analysis method) It can also be quantified.

[0249] The oxide semiconductor layer 306a is an In-M-Zn oxide (wherein M is Ti, Ga, Y, Zr, La, In the case of the oxide semiconductor layer 306a, the target used for depositing the oxide semiconductor layer 306a is In this case, if the atomic ratio of metal elements is In:M:Zn=x1:y1:z1, 、 x1 / y1 is 1 / 3 or more and 6 or less, further 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and It is preferable that z1 / y1 is 1 or more and 6 or less, and more preferably 1 or more and 6 or less. In this case, a CAAC-OS film is easily formed as the oxide semiconductor layer 306a. A typical example of the atomic ratio of the target metal elements is In:M:Zn=1:1:1, I Examples include n:M:Zn=1:1:1.2, In:M:Zn=3:1:2, etc.

[0250] Note that a target for depositing the oxide semiconductor layer 306a was In:M:Zn=1 : 1: z 10 When using a target that is z 10 it is preferable that z be 1 or more and 1.4 or less, more preferably z 10 be 1 or more and 1.3 or less. For example, when In:M:Zn = 1:1:1.5, the target becomes cloudy, and sputtering film formation using a DC power supply or an AC power supply may become difficult. For such a target, film formation using an RF power supply is applicable, but considering the productivity of semiconductor devices, it is desirable to use a target for which sputtering film formation using a DC power supply or an AC power supply is possible.

[0251] When the oxide semiconductor layer 306b is an In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf), in the target used to form the oxide semiconductor layer 306b, when the atomic ratio of the metal elements is In:M:Zn = x2:y2:z2, then 、 x2 / y2 < x1 / y1, and z2 / y2 is preferably 1 / 3 or more and 6 or less, and further preferably 1 or more and 6 or less. Also, by increasing the atomic ratio of M to indium, it is possible to increase the energy gap of the oxide semiconductor layer 306b and decrease the electron affinity, so it is preferable that y2 / x2 be 3 or more, or 4 or more. Representative examples of the atomic ratio of the metal elements of the target include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:5, In:M:Zn = 1:3:6, In:M:Z n = 1:4:2, In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, etc. n = 1:4:2, In:M:Zn = 1:4:4, In:M:Zn = 1:4:5, etc.

[0252] ​​​For example, a target for depositing the oxide semiconductor layer 306b may be In:M:Zn= 1:3:z 20 When using a target where z 20 It is preferable to set the value to 2 or more and 5 or less. Alternatively, the oxide semiconductor layer 306b may be formed using a target containing In:M:Z n=1:4:z 30 When using a target where z 30 It is preferable to set the value to 2 or more and 5 or less. I wish.

[0253] Note that the atomic ratios of the oxide semiconductor layer 306a and the oxide semiconductor layer 306b are each determined with an error of The atomic ratios above may vary by ±40%.

[0254] The oxide semiconductor layer 306a and the oxide semiconductor layer 306b preferably have a crystalline part. It is more preferable that the oxide semiconductor layer 306a and the oxide semiconductor layer 306b have the same crystal structure. When the layer 306b has a different crystal structure from the layer 306a, the interface between the two layers becomes a hetero-crystal structure portion and defects are formed. The hetero-crystalline structure may have defects such as grain boundaries. It can also be considered.

[0255] The oxide semiconductor layer 306a has a low impurity concentration and a low density of defect states (few oxygen vacancies). It is more preferable to use a CAAC-OS film, which is an oxide semiconductor layer. A low concentration of impurities and a low density of defect states is called high purity intrinsic or substantially high purity intrinsic. A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor layer has a small carrier generation source. Therefore, the carrier density can be reduced. The transistor used in this study has electrical characteristics in which the threshold voltage is negative (also called normally-on). In addition, the oxide is highly pure or substantially highly pure. The semiconductor layer has few carrier traps. Therefore, the oxide semiconductor layer is used as a channel. The transistor thus obtained has a small fluctuation in electrical characteristics and is highly reliable. In the case of a transistor using a CAAC-OS film, the electrical characteristics change when irradiated with visible light or ultraviolet light. The movement is small.

[0256] The oxide semiconductor layer 306a was formed using a target of In:M:Zn=1: When 1:1.2 is used, a spinel structure is formed in the oxide semiconductor layer 306a. This is preferable because it is less likely to be damaged and the CAAC conversion rate can be increased.

[0257] In addition, when the oxide semiconductor layer 306a is a CAAC-OS film, When the oxide semiconductor layer 306b formed in contact with the oxide semiconductor layer 306b has a different crystal structure, Grain boundaries may be formed, which may cause defects in the oxide semiconductor layer. It is preferable to use a CAAC-OS film for 306b as well.

[0258] On the other hand, as a barrier layer for preventing impurities from being mixed into the oxide semiconductor layers 306a and 306b, When forming, for example, an In-Ga oxide layer as the metal oxide layer 108 functioning as a metal oxide layer, the I The n-Ga oxide layer forms an amorphous structure, a crystalline structure similar to the nc-OS film, or a monoclinic structure. However, it is difficult to obtain a crystal structure similar to that of the CAAC-OS film. Therefore, the oxide semiconductor layer 306a in which the channel is formed is in contact with the metal oxide layer 108. In this embodiment, a heterostructure may be formed at the interface between the two layers. In the transistor 310 shown in the embodiment, the oxide semiconductor layer 306a in which a channel is formed By providing the oxide semiconductor layer 306b between the metal oxide layer 108, a heterostructure can be bonded. The region where the carriers flow can be separated from the oxide semiconductor layer 306a through which carriers flow. However, the oxide semiconductor layer 306b may have a spinel structure in the film. By providing the layer 108, the constituent elements of the pair of electrode layers 110a and 110b are Since the diffusion of the spin-doped oxide into the oxide semiconductor layer 306b can be suppressed, the spin-doped oxide Even if a spinel structure exists, the channeling of metallic elements such as copper due to the spinel structure is This is to prevent diffusion into the

[0259] FIG. 7C shows a gate insulating layer 104, an oxide semiconductor layer 306a, and an oxide semiconductor layer 306b. 1. Band structure in the thickness direction of the laminated structure having the metal oxide layer 108 and the oxide insulating layer 112 In order to facilitate understanding, the band structure is shown by taking the gate insulating layer 104, the oxide semiconductor The conductive layer 306a, the oxide semiconductor layer 306b, the metal oxide layer 108 and the oxide insulating layer 112. The energy at the bottom of the conductive band (Ec) is shown.

[0260] As shown in FIG. 7C, in the oxide semiconductor layer 306a and the oxide semiconductor layer 306b, In this case, the energy at the bottom of the conduction band changes smoothly without any barrier (also called a continuous junction). In this case, it can be said that the band structure changes continuously. At the interface between the oxide semiconductor layer 306a and the oxide semiconductor layer 306b, a trap center It is preferable that there are no impurities that may form defect levels such as vacancies or recombination centers. In addition, if impurities are present between the stacked oxide semiconductor layers, the continuity of the energy bands is This is because the conductivity is lost and carriers are trapped or recombined at the interface and disappear. It is.

[0261] In order to form a continuous junction between the oxide semiconductor layer 306a and the oxide semiconductor layer 306b, Using a multi-chamber deposition system (sputtering system) equipped with a lock chamber, It is necessary to laminate each film in succession without exposing them to the air.

[0262] In the structure of FIG. 7C, the oxide semiconductor layer 306a serves as a well, and the In the transistor having a layer structure, a channel region is formed in the oxide semiconductor layer 306a. It can be seen that this is possible.

[0263] As shown in FIG. 8A, near the interface between the metal oxide layer 108 and the oxide insulating layer 112, Although trap levels due to impurities or defects may be formed nearby, the metal oxide layer 10 By providing the insulating film 8, the oxide semiconductor layers 306a and 306b are separated from the trap levels. In addition, a heterojunction between the metal oxide layer 108 and the oxide semiconductor layer 306b can be formed. Even if the oxide semiconductor layer 306b has defects due to the crystal structure, This can suppress the effect of the defects on the oxide semiconductor layer 306a. The energy difference between the conduction band minimums of the oxide semiconductor layer 306a and the oxide semiconductor layer 306b is small. In this case, electrons in the oxide semiconductor layer 306a exceed the energy difference and reach the trap level. When electrons are captured in the trap level, a negative fixed charge is generated at the interface of the insulating film. This generates a charge, and the threshold voltage of the transistor shifts in the positive direction. The energy difference between the conduction band minimums of the oxide semiconductor layer 306a and the oxide semiconductor layer 306b is set to 0 If the capacitance is set to 0.1 eV or more, preferably 0.15 eV or more, the change in the threshold voltage of the transistor is This is preferable because it reduces the vibration and provides stable electrical characteristics.

[0264] In addition, the energy difference between the conduction band minimums of the oxide semiconductor layers 306a and 306b is When the potential difference is set to 0.1 eV or more, preferably 0.15 eV or more, the metal oxide layer 108 and the oxide The trap states that may exist near the interface with the oxide semiconductor layer 306b and the oxide insulating layer 112 are This is preferable because the oxide semiconductor layer 306a in contact with the oxide semiconductor layer 306a can be prevented from being affected. It is nice.

[0265] Note that the transistor having a stacked structure described in this embodiment is not limited to the structure in FIG. For example, a transistor 300 shown in FIG. 21A is a transistor according to the first embodiment. In the structure shown by 200, a gate insulating layer 104 and a metal oxide layer 108 are provided. The oxide semiconductor layer has a stacked structure of an oxide semiconductor layer 316a and an oxide semiconductor layer 316b. In FIG. 21A, the channel length of the transistor 300 may be 2, a cross section in the direction of the gate electrode layer 202a, an electrode layer 202b formed in the same layer as the gate electrode layer 202a, and a pair of electrodes 1 shows a cross section of a connection between the electrode layers 110a and 110b and the electrode layer 110c formed in the same layer. is.

[0266] In the transistor 300 illustrated in FIG. 21A, the gate electrode layer 202a and the gate The electrode layer 202b is formed in the same layer as the electrode layer 202a. The first conductive layer 101a, the second conductive layer 103a, and the second conductive layer 103b are laminated together. 101b includes a pair of electrode layers 110a and 110b, and first conductive layers 109a and 109b. The second conductive layers 103a and 103b may be made of the same material. The same material as the second conductive layers 111a and 111b of the pair of electrode layers 110a and 110b is used. It can be used.

[0267] The gate electrode layer 202a and the electrode layer 202b are made of a low resistance material such as copper, aluminum, gold, or silver. By forming the substrate 100 containing the material, wiring can be performed easily even when a large-area substrate is used as the substrate 100. It is possible to manufacture a semiconductor device in which delay is suppressed. When the electrode layer 202b is formed of the above-mentioned low resistance material, the gate insulating layer 1 04 includes a stacked structure of a nitride insulating layer 104a and an oxide insulating layer 104b, It is preferable that the insulating layer 104b be in contact with the oxide semiconductor layer 316a. The nitride insulating layer 104a included in the gate insulating layer 104 is used to prevent the diffusion of the above-mentioned low resistance material. The oxide insulating layer 104b can be used as a barrier layer for preventing the formation of a nitride insulating layer. The diffusion of nitrogen from the oxide semiconductor layer 104a to the oxide semiconductor layers 316a and 316b is prevented, and the oxygen The oxide semiconductor layers 316a and 316b can function as a source of oxygen.

[0268] The oxide semiconductor layer 316a included in the transistor 300 has the same structure as that of the above-described transistor 3 The oxide semiconductor layer 306a in the embodiment 10 can be formed in the same manner as described above. The oxide semiconductor layer 316b has the same structure as the oxide semiconductor layer 316 of the transistor 310. The conductor layer 306b may be the same as the conductor layer 306b, and the above description may be taken into consideration. , the gate insulating layer 104, the oxide semiconductor layer 316a, and the oxide The thickness of the stacked structure including the semiconductor layer 316b, the metal oxide layer 108, and the oxide insulating layer 112 As shown in FIG. 21B, the band structure in the direction of the oxide semiconductor layer 316a is a well. In the transistor using the stacked structure, a channel region is formed in an oxide semiconductor layer. 316a.

[0269] In the transistor 300, the electrode layer 202b and the electrode layer 110c are connected by a gold After processing the metal oxide film and the oxide semiconductor film into an island shape, an opening is formed in the gate insulating layer 104. Then, the pair of electrode layers 110a and 110b and the electrode A conductive film for forming the layer 110c is formed, and the conductive film is processed to form the electrode layer 202. b and electrode layer 110c can be connected.

[0270] With the structure described in this embodiment, impurities in the oxide semiconductor layer including the channel formation region can be prevented from being It is possible to obtain a highly reliable transistor with a reduced concentration. The structure is less susceptible to the effects of interface states, and the on-current caused by the interface states is reduced. Therefore, it is possible to make a transistor with a high on-state current and a low S value. In addition, the electrical characteristics are less likely to change due to the interface state, making it possible to produce highly reliable transistors. It becomes Jista.

[0271] The configuration and method described in this embodiment may be appropriately combined with the configuration and method described in other embodiment. It can be used in combination.

[0272] (Embodiment 4) In this embodiment, a structural example of a display panel will be described as a semiconductor device according to one embodiment of the present invention. do.

[0273] <Display panel> A display panel including a semiconductor device such as the above-described transistor will be described below.

[0274] FIG. 18A is a top view of a display panel according to one embodiment of the present invention, and FIG. A pixel circuit that can be used when a liquid crystal element is applied to a pixel of a display panel according to one embodiment of the present invention. FIG. 18C is a circuit diagram for explaining a display panel of one embodiment of the present invention. A circuit diagram for explaining a pixel circuit that can be used when an organic EL element is used as a substrate. It is.

[0275] The transistor arranged in the pixel portion has the structure described in Embodiment 1 or 3. A transistor can be used. The transistor is an n-channel type. Since it is easy to configure the driver circuit using n-channel transistors, Part of the circuit is formed on the same substrate as the transistors in the pixel section. By using the transistor described in Embodiment 1 or 3 in a circuit, reliability can be improved. It is possible to provide a high-quality display device.

[0276] An example of a block diagram of an active matrix display device is shown in FIG. On a substrate 700, a pixel section 701, a first scanning line driving circuit 702, a second scanning line driving circuit The pixel portion 701 includes a signal line driver circuit 703 and a signal line driver circuit 704. A first scanning line driving circuit 702 extends from the first scanning line driving circuit 704. The scanning line driver circuit 703 is arranged to extend from the scanning line driver circuit 703. In each region, pixels each having a display element are arranged in a matrix. The substrate 700 is a connection board for FPC (Flexible Printed Circuit) etc. It is connected to a timing control circuit (also called a controller or control IC) via .

[0277] In FIG. 18A, a first scanning line driver circuit 702, a second scanning line driver circuit 703, a signal line The driver circuit 704 is formed on the same substrate 700 as the pixel portion 701. The number of components, such as the drive circuits, that are required can be reduced, leading to cost reduction. 00When an external driver circuit is provided, it becomes necessary to extend the wiring, and the number of connections between the wiring increases. When a driving circuit is provided on the same substrate 700, the number of connections between the wirings can be reduced. Therefore, it is possible to improve reliability or yield.

[0278] [Liquid crystal panel] As one mode of a display panel, an example of a circuit configuration of a pixel of a liquid crystal panel is shown in FIG. Here, a pixel circuit that can be applied to the pixels of a VA type liquid crystal display panel is shown.

[0279] This pixel circuit can be applied to a configuration in which one pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. This allows individual pixels of a multi-domain pixel to be The signals applied to the electrode layers can be controlled independently.

[0280] The gate wiring 712 of the transistor 716 and the gate wiring 713 of the transistor 717 are , are separated so that different gate signals can be applied. On the other hand, The functioning source or drain electrode layer 714 is a transistor 716 and a transistor The transistors 716 and 717 are used in common. The transistors described in Section 3 can be used appropriately. This makes it possible to realize a highly reliable liquid crystal display. A display panel can be provided.

[0281] A first pixel electrode layer electrically connected to the transistor 716 and a second pixel electrode layer electrically connected to the transistor 717 The shape of the second pixel electrode layer that is electrically connected to the first pixel electrode layer will be described. The shape of the electrode layer is separated by slits. The first pixel electrode layer spreads in a V-shape. The second pixel electrode layer is formed so as to surround the outside of the first pixel electrode layer.

[0282] The gate electrode of the transistor 716 is connected to the gate wiring 712. The gate electrode is connected to the gate wiring 713. By applying different gate signals to the transistors 716 and 717, the operation timing of the transistors 716 and 717 is By varying the polarity, the alignment of the liquid crystal can be controlled.

[0283] In addition, a capacitance wiring 710, a gate insulating layer functioning as a dielectric, and a first pixel electrode layer or A storage capacitor may be formed by a capacitor electrode electrically connected to the second pixel electrode layer.

[0284] The multi-domain structure includes a first liquid crystal element 718 and a second liquid crystal element 719 in one pixel. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. do.

[0285] Note that the pixel circuit shown in FIG. 18(B) is not limited to this. The pixels are now equipped with new switches, resistors, capacitors, transistors, sensors, logic circuits, etc. Any of the above may be added.

[0286] [Organic EL Panel] As another embodiment of the display panel, an example of the circuit configuration of a pixel of an organic EL panel is shown in FIG. As shown in.

[0287] In an organic EL element, when a voltage is applied to the light-emitting element, electrons are emitted from one of a pair of electrodes. Holes are injected from the other side into the layer containing the light-emitting organic compound, causing a current to flow. When the electrons and holes recombine, the light-emitting organic compound forms an excited state, and Light is emitted when the excited state returns to the ground state. Such a device is called a current-excited light-emitting device.

[0288] FIG. 18C is a diagram showing an example of an applicable pixel circuit. An example in which two transistors are used in one pixel is shown. The film can be used for the channel formation region of an n-channel transistor. The pixel circuit can apply digital time gray scale driving.

[0289] Regarding the configuration of an applicable pixel circuit and the operation of a pixel when digital time gray scale driving is applied, He explains.

[0290] The pixel 720 includes a switching transistor 721, a driving transistor 722, and a light-emitting element The switching transistor 721 has a gate electrode 724 and a capacitance element 723. The first electrode layer is connected to the scan line 726, and the second electrode (one of the source and drain electrode layers) is connected to the scan line 726. ) is connected to a signal line 725, and the second electrode (the other of the source electrode layer and the drain electrode layer) is The driving transistor 722 is connected to the gate electrode layer of the driving transistor 722. The gate electrode layer is connected to a power supply line 727 via a capacitance element 723, and the first electrode is connected to the power supply line 7 27, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 724. The second electrode of the light emitting element 724 corresponds to a common electrode 728. The common electrode 728 is formed on the same substrate. The common potential line is electrically connected to the common potential line formed in the

[0291] The switching transistor 721 and the driving transistor 722 are the same as those described in the third embodiment. This allows the use of transistors that can achieve high reliability in organic EL display panels. A panel can be provided.

[0292] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to a low power supply potential. The power supply potential is a potential lower than the high power supply potential set on the power supply line 727, for example, GND , 0V, etc. can be set as the low power supply potential. The high power supply potential and the low power supply potential are set so that the potential difference is equal to or greater than the threshold voltage. By applying a voltage to the light emitting element 724, a current flows through the light emitting element 724, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and must be at least the forward threshold. Includes low-value voltages.

[0293] The capacitance element 723 can be omitted by substituting the gate capacitance of the driving transistor 722. The gate capacitance of the driving transistor 722 can be omitted. A capacitance may be formed between the first electrode layer and the second electrode layer.

[0294] Next, a signal to be input to the driving transistor 722 will be described. In this case, the driving transistor 722 is in two states: fully on or fully off. A video signal such as the above is input to the driving transistor 722. In order to operate the driving transistor 722 in a linear region, a voltage higher than the voltage of the power supply line 727 is applied to the driving transistor 722. A signal line 725 is connected to the gate electrode layer of the transistor 722. A voltage equal to or greater than the threshold voltage Vth of the input transistor 722 is applied.

[0295] When analog gradation driving is performed, the gate electrode layer of the driving transistor 722 is connected to the light emitting element 72 A voltage equal to or greater than the forward voltage of the driving transistor 722 plus the threshold voltage Vth of the driving transistor 722. Note that a video signal is input so that the driving transistor 722 operates in the saturation region. A current flows through the light emitting element 724. In addition, the driving transistor 722 is operated in a saturation region. In order to achieve this, the potential of the power supply line 727 is set higher than the gate potential of the driving transistor 722. By converting the video signal into an analog signal, a current corresponding to the video signal is applied to the light emitting element 724. It is possible to perform analog gray scale driving.

[0296] Note that the configuration of the pixel circuit is not limited to the pixel configuration shown in FIG. (C) A switch, a resistive element, a capacitive element, a sensor, a transistor or a logic Circuits etc. may be added.

[0297] In the case where the transistor illustrated in the first or third embodiment is applied to the circuit illustrated in FIG. In this case, the source electrode layer is electrically connected to the low potential side and the drain electrode layer is electrically connected to the high potential side. The configuration will be as follows.

[0298] For example, in this specification and the like, the term "display element," "display device having a display element," "light-emitting element," A light-emitting device, which is a device having a light-emitting element, can be used in various forms or in various Examples of a display element, a display device, a light-emitting element, or a light-emitting device include , EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) ), transistors (transistors that emit light according to electric current), electron-emitting devices, liquid crystal devices, Dye ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), MEMS (Micro Electro Mechanical Systems), Digital Ma Micromirror Device (DMD), DMS (Digital Micro Shutter), IMO D (Interference Modulation) element, electrowetting element, Piezoelectric ceramic displays, carbon nanotubes, etc., are made by electromagnetic interactions. Some have display media that change contrast, brightness, reflectance, transmittance, etc. An example of a display device using electron-emitting devices is an EL display. An example of such a display device is a field emission display (FED) or SED. Type Flat Panel Display (SED: Surface-conduction Elect A type of display device that uses liquid crystal elements. Examples include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, There are various types of LCD displays, such as reflective LCD displays, direct-view LCD displays, and projection LCD displays. An example of a display device using electronic ink or electrophoretic elements is electronic paper. be.

[0299] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done.

[0300] (Embodiment 5) In this embodiment, a display module to which a semiconductor device of one embodiment of the present invention is applied will be described. In addition, examples of the structure of an electronic device to which the semiconductor device of one embodiment of the present invention is applied will be described. do.

[0301] The display module 8000 shown in FIG. 19 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 is connected to FPC8003, and touch panel 8005 is connected to FPC8005. Display panel 8006, backlight unit 8007, frame 8009, printed circuit board 8010 and a battery 8011. In some cases, the read / write head 8011, the touch panel 8004, etc. may not be provided.

[0302] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0303] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel 8 The shape and dimensions can be changed appropriately to match the size of 006.

[0304] The touch panel 8004 is a resistive or capacitive touch panel, and the display panel 8 8006. In addition, the opposing substrate (sealing substrate) of the display panel 8006 It is also possible to provide the display panel 8 with a touch panel function. It is also possible to provide an optical sensor in each pixel of the touch panel to make it an optical touch panel. Alternatively, a touch sensor electrode is provided in each pixel of the display panel 8006 to form a capacitive touch panel. It is also possible to use a channel.

[0305] The backlight unit 8007 includes a light source 8008. It may be provided at the end of the unit 8007 and may be configured to use a light diffusion plate.

[0306] The frame 8009 protects the display panel 8006 and also prevents the operation of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The plate 8009 may function as a heat sink.

[0307] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal, and a clock signal. The power supply circuit is supplied with power from an external commercial power source. Alternatively, the power source may be a battery 8011 provided separately. This can be omitted if a commercial power source is used.

[0308] In addition, the display module 8000 includes components such as a polarizing plate, a retardation plate, and a prism sheet. It may be added.

[0309] FIG. 20 is an external view of an electronic device including a semiconductor device of one embodiment of the present invention.

[0310] Examples of electronic devices include television sets (also known as televisions or television receivers). (hereinafter referred to as "computer monitors"), digital cameras, digital video cameras, and other cameras digital photo frames; mobile phones (also called mobile phones or mobile phone devices); Examples include game machines, mobile information terminals, audio playback devices, and large game machines such as pachinko machines. do.

[0311] FIG. 20A shows a portable information terminal, which includes a main body 1001, a housing 1002, a display unit 100 The display unit 1003b is a touch panel. The screen can be operated by touching keyboard buttons 1004 displayed on the display unit 1003b. Of course, the display unit 1003a can be configured as a touch panel. The transistor described in the above embodiment may be used as a switching element in a liquid crystal panel. By fabricating an organic light-emitting panel and applying it to the display units 1003a and 1003b, It is possible to provide a highly useful portable information terminal.

[0312] The portable information terminal shown in FIG. 20(A) displays various information (still images, videos, text images, etc.). ), calendar, date or time display function, The ability to manipulate or edit the information displayed, and to process it using various software (programs) In addition, the rear and side of the housing can have external connection terminals ( It may also be configured to include an earphone jack, a USB terminal, a recording medium insertion portion, etc.

[0313] The portable information terminal shown in FIG. 20(A) can also be configured to transmit and receive information wirelessly. You can wirelessly purchase and download the desired book data from the electronic book server. It is also possible to configure it in this way.

[0314] FIG. 20B shows a portable music player. The main body 1021 has a display unit 1023 and a A fixing part 1022 for mounting, a speaker, an operation button 1024, and an external memory slot The transistor shown in the above embodiment is used as a switching element. By manufacturing a liquid crystal panel or an organic light-emitting panel as a display unit 1023, This makes the portable music player more reliable.

[0315] Furthermore, the portable music player shown in FIG. 20(B) has an antenna, a microphone function, and a wireless function. In addition, by linking it with a mobile phone, you can enjoy wireless hands-free driving while driving a passenger car. Conversation by telephone is also possible.

[0316] FIG. 20C shows a mobile phone, which is composed of two housings, a housing 1030 and a housing 1031. The housing 1031 includes a display panel 1032, a speaker 1033, a microphone, and a 1034, a pointing device 1036, a camera 1037, and an external connection terminal 1038 The housing 1030 also includes a solar cell 1040 for charging the mobile phone, The external memory slot 1041 is also provided. The antenna is internally mounted inside the housing 1031. The transistor described in the above embodiment is applied to the display panel 1032. This makes it possible to provide a highly reliable mobile phone.

[0317] The display panel 1032 is equipped with a touch panel, and the image displayed on the display panel 1032 is shown in FIG. A plurality of operation keys 1035 are shown by dotted lines. It also includes a boost circuit to boost the voltage required for each circuit.

[0318] The display direction of the display panel 1032 changes appropriately depending on the usage mode. A camera 1037 is provided on the same surface as the camera 1032, so video calls are possible. The speaker 1033 and microphone 1034 are not limited to voice calls, but can also be used for video calls, recording, playback, etc. Furthermore, the housing 1030 and the housing 1031 can be slid to each other, as shown in FIG. ) can be folded up into a compact size suitable for carrying around. It is possible to achieve this.

[0319] The external connection terminal 1038 can be connected to various cables such as AC adapters and USB cables. It is possible to charge the battery and to communicate data with a personal computer, etc. A recording medium can be inserted into the memory slot 1041 to accommodate the storage and transfer of larger amounts of data. do.

[0320] In addition to the above functions, even if the device has infrared communication function, TV reception function, etc. good.

[0321] FIG. 20D shows an example of a television device. The television device 1050 includes: A display unit 1053 is built into the housing 1051. The display unit 1053 displays images. In addition, the CPU is built into the stand 1055 that supports the housing 1051. The transistor described in the above embodiment is applied to the display portion 1053 and the CPU. By using this, a highly reliable television device 1050 can be obtained.

[0322] The television device 1050 can be operated using an operation switch provided on the housing 1051 or a separate remote control. The remote control can be operated by a remote controller. A display unit for displaying information output from the device may be provided.

[0323] The television device 1050 is configured to include a receiver, a modem, and the like. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0324] The television device 1050 also includes an external connection terminal 1054 and a storage medium playback / recording unit 10 52, an external memory slot. An external connection terminal 1054 is provided for connecting a USB cable, etc. It can be connected to various cables, enabling data communication with a personal computer, etc. In the storage medium playback / recording unit 1052, a disk-shaped recording medium is inserted and recorded on the recording medium. It is possible to read data stored in the external memory and write data to the recording medium. Displays images and videos stored in the external memory 1056 inserted in the slot. It is also possible to display it on the display unit 1053.

[0325] In addition, when the off-leak current of the transistor described in the above embodiment is extremely small, By applying this transistor to the external memory 1056 and the CPU, power consumption is sufficiently reduced. This results in a highly reliable television apparatus 1050 with reduced noise.

[0326] This embodiment may be implemented in appropriate combination with other embodiments described in this specification. can be done. EXAMPLES

[0327] In this example, a transistor of one embodiment of the present invention was manufactured, and its initial characteristics were measured. Measure the band diagram of the oxide semiconductor layer and the metal oxide layer included in the transistor. They also evaluated the diffusion of copper in metal oxide layers in transistors. These results will be explained.

[0328] First, a method for manufacturing a transistor used in this embodiment will be described below. A transistor having a structure similar to that of the transistor 200 shown in FIG.

[0329] (Sample A1) A method for preparing the sample A1 will be described.

[0330] A glass substrate was used as the substrate 100, and a 150 nm thick tin film was formed on the substrate 100 as a conductive film. A tungsten film was formed by sputtering. Then, a photolithography method was used to The conductive film was selectively processed using the formed mask to form a gate electrode layer 102.

[0331] Next, a gate insulating layer 104 was formed on the substrate 100 and the gate electrode layer 102. The gate insulating layer 104 is a silicon nitride film having a thickness of 400 nm and a nitriding oxide film having a thickness of 50 nm. The silicon nitride films were formed by the CVD method.

[0332] Next, on the gate insulating layer 104, an oxide semiconductor film of In:Ga:Zn=1:1:1[ The In- was deposited with a thickness of 35 nm by sputtering using an oxide target with a [atomic ratio] of 1.0 to 1.5 nm. A Ga-Zn oxide film (hereinafter referred to as IGZO (1:1:1)) was formed. Film formation conditions was performed under an atmosphere of argon and oxygen (argon:oxygen=20sccm:10sccm) at pressure The conditions were 0.4 Pa, power supply power (DC) 200 kW, and substrate temperature 300°C.

[0333] After the oxide semiconductor film was formed, a metal oxide film was successively formed without exposure to the atmosphere. The oxide film was prepared by sputtering using an oxide target with an In:Ga atomic ratio of 7:93. A 20 nm thick In-Ga oxide film (hereafter referred to as IGO (1:1)) was prepared by the ion beam sputtering method. The deposition conditions were argon and oxygen (argon:oxygen=20sccm: 10sccm) atmosphere, pressure 0.4Pa, power supply (DC) 200kW, substrate temperature 30 The temperature was set to 0°C.

[0334] The oxide semiconductor film and the oxide semiconductor film after the heat treatment were formed using a mask formed by photolithography. The metal oxide film is processed into an island shape to form an oxide semiconductor layer 106 and a metal oxide layer 108. Ta.

[0335] Next, heat treatment was performed at 450°C for 1 hour in a nitrogen atmosphere, and then the same treatment chamber was used for The atmosphere was a mixture of oxygen and nitrogen gas, and heat treatment was performed at 450°C for 1 hour.

[0336] A conductive film having a thickness of 30 nm was formed on the island-shaped oxide semiconductor layer 106 and the metal oxide layer 108. A tungsten film having a thickness of 100 nm and a copper film having a thickness of 200 nm were formed by sputtering.

[0337] Next, a tungsten film and a copper film are formed by using a mask formed by photolithography. A pair of electrode layers 110a and 110b were formed by selectively etching.

[0338] Next, the gate insulating layer 104, the metal oxide layer 108, and the pair of electrode layers 110a, 110b are On the top of the insulating layer 112, a silicon oxynitride film having a thickness of 50 nm is formed by a CVD method. Next, without exposing to the atmosphere, a 40 mm thick oxide insulating layer was formed. A 0 nm silicon oxynitride film was formed by CVD.

[0339] Next, a heat treatment was carried out at 350° C. for 1 hour in an atmosphere of a mixed gas of oxygen and nitrogen.

[0340] Next, a 100 nm thick silicon nitride film is formed on the oxide insulating layer 114 as a nitride insulating layer 116. The SiO2 film was formed by CVD.

[0341] Next, although not shown, an oxide insulating layer is formed using a mask formed by photolithography. Etch away a portion of each of the edge layer 112, the oxide insulating layer 114, and the nitride insulating layer 116. Thus, an opening was formed to expose one of the pair of electrode layers 110a, 110b.

[0342] Next, a 100 nm thick oxide film containing silicon oxide is formed on the nitride insulating layer 116 as a conductive film. An indium-tin oxide compound (ITO-SiO2) film was formed by sputtering. Next, a part of the conductive film is etched using a mask formed by photolithography. A conductive layer was formed by etching to contact one of the pair of electrode layers 110a and 110b. Heat treatment was carried out at 250° C. for 1 hour in a nitrogen atmosphere.

[0343] Next, a planarization layer (not shown) was formed on the nitride insulating layer 116 and the conductive layer. A polyimide layer having a thickness of 1 μm was formed. Here, after applying the composition onto the nitride insulating layer 116, After exposure and development, the film is heated at 300°C for 1 hour in a nitrogen atmosphere. A planarizing layer having openings that expose parts of the pair of electrode layers 110a and 110b was formed.

[0344] Through the above steps, sample A1 was produced.

[0345] (Sample A2) The sample A2, which is a comparative example, has a structure in which the metal oxide layer 108 in the sample A1 is not provided. The other configurations and fabrication conditions were the same as those of sample A1.

[0346] (Sample A3) The comparative sample A3 has an oxide semiconductor layer instead of the metal oxide layer 108 in the sample A1. The other structures and preparation conditions were the same as those of sample A1. Specifically, a sample in which an oxide semiconductor film to be an oxide semiconductor layer was formed under the following conditions was prepared. , and was prepared as sample A3.

[0347] The oxide semiconductor film was prepared by using an oxide target with an atomic ratio of In:Ga:Zn=1:3:6. The sputtering method used here produced a 20 nm thick In-Ga-Zn oxide film (hereinafter referred to as IG The deposition conditions were argon and oxygen (argon : Oxygen = 20sccm: 10sccm) atmosphere, pressure 0.4Pa, power supply (DC) 2 The power consumption was 100 kW and the substrate temperature was 200°C.

[0348] (Sample A4) The comparative sample A4 has an oxide semiconductor layer instead of the metal oxide layer 108 in the sample A1. The other structures and preparation conditions were the same as those of sample A1. Specifically, a sample in which an oxide semiconductor film to be an oxide semiconductor layer was formed under the following conditions was prepared. , and was prepared as sample A4.

[0349] The oxide semiconductor film was prepared by using an oxide target with an atomic ratio of In:Ga:Zn=1:6:4. The sputtering method used here produced a 20 nm thick In-Ga-Zn oxide film (IGZO( The deposition conditions were argon and oxygen (argon:oxygen 1:6:4). =20sccm:10sccm) atmosphere, pressure 0.4Pa, power supply (DC) 200k The substrate temperature was 200°C.

[0350] (Sample A5) The comparative sample A5 has an indium oxide layer instead of the metal oxide layer 108 in the sample A1. The structure is a metal oxide layer having a different atomic ratio of gallium and gallium. The preparation conditions were the same as those for sample A1. Specifically, the metal oxide layer and A sample having a metal oxide film formed thereon was prepared as sample A5.

[0351] The metal oxide layer was prepared by sputtering using an oxide target with an atomic ratio of In:Ga of 2:1. A 20 nm thick In-Ga oxide film (also referred to as IGO (2:1)) was prepared by the deposition method. The deposition conditions were argon and oxygen (argon:oxygen=20sccm:10sc The experiment was carried out under an atmosphere of 100 cm, pressure of 0.4 Pa, power supply (DC) of 200 kW, and substrate temperature of 300°C. Ta.

[0352] (Vg-Id characteristics) Next, the Vg-Id characteristics of the transistors included in Samples A1 to A5 were measured. The substrate temperature is set to 25°C, and the potential difference between the source and drain electrode layers (hereafter referred to as drain voltage) is The potential difference between the source and gate electrode layers (hereinafter referred to as gate The source-drain The change in the current flowing between the electrode layers (hereinafter referred to as the drain current, Id), i.e., V The g-Id characteristics were measured. In each sample, the channel length L of the transistor was 6 μm. The channel width W was 50 μm. Each sample had four transistors. do.

[0353] FIG. 11A shows the Vg-Id characteristics of the transistor included in the sample A1, and FIG. 13A shows the Vg-Id characteristics of the transistor included in Sample A2, and FIG. FIG. 14(A) shows the Vg-Id characteristics of the transistor included in sample A3, and FIG. FIG. 15(A) shows the Vg-Id characteristics of the transistor included in sample A5. 11(A) to 15(A), the horizontal axis The first vertical axis represents the gate voltage Vg, the second vertical axis represents the drain current Id, and the third vertical axis represents the field effect mobility Here, the field effect mobility is expressed as Vd=10 to show the value in the saturation region. The field-effect mobility calculated in V is shown.

[0354] As shown in FIG. 11A, sample A1 has a high on-state current and excellent Vg-Id characteristics. It was discovered that a transistor could be fabricated.

[0355] On the other hand, as shown in FIG. 12A, the Vg-Id characteristics of the transistor included in the sample A2 are One of the reasons for the decrease in on-current is the difference between the pair of electrode layers. Cu contained in 110a and 110b migrates to the surface or inside of the oxide semiconductor layer 106, The Cu forms shallow trap levels in the oxide semiconductor layer, trapping conduction electrons. It is possible that...

[0356] In addition, as shown in FIG. 13A, the Vg-Id characteristics of the transistor included in the sample A3 are The threshold voltage is different when the gate voltage is 1V and 10V.

[0357] In addition, as shown in FIG. 14A, the Vg-Id characteristics of the transistor included in the sample A4 are The threshold voltage is different when the gate voltage is 1V and 10V. It was found that the device does not have switching characteristics.

[0358] On the other hand, as shown in FIG. 15A, the Vg-Id characteristics of the transistor included in the sample A5 are The flow was found to be decreasing.

[0359] (Band diagram) Next, the oxide semiconductor layer and the metal oxide layer in Sample A1 and Sample A5, and the oxide semiconductor layer in Sample A2 the stacked oxide semiconductor layers in Sample A3 and Sample A4, The energy difference between the electric conduction band edge Ec and the valence band edge Ev, that is, the energy gap Eg, is The measurements were performed using a spectroscopic ellipsometer. Violet Photoelectron Spectroscopy (VPS) was performed. The energy difference between the vacuum level Evac and the top of the valence band Ev, i.e., the ionization potential Ip Next, the difference between the ionization potential Ip and the energy gap Eg was calculated. By this, the energy difference between the vacuum level Evac and the bottom edge of the electric conduction band Ec, that is, the electron affinity χ, is calculated. By performing the above analysis, a band diagram was obtained for each sample.

[0360] FIG. 11(B) shows the band diagram of sample A1, and FIG. 12(B) shows the band diagram of sample A2. FIG. 13(B) shows a band diagram of sample A3, and FIG. FIG. 4(B) shows the band diagram of sample A4, and FIG. 15(B) shows the band diagram of sample A5. Diagram shown.

[0361] As shown in FIG. 11B, in the sample A1, the oxide semiconductor layer (IGZO(1:1:1 The difference in electron affinity χ between the IGO layer and the metal oxide layer (IGO(7:93)) is as large as 0.5 eV. In addition, as shown in FIG. 14B, in the sample A4, the stacked oxide semiconductor layer (I The difference in electron affinity χ between GZO (1:1:1) and IGZO (1:6:4) is 0.5 eV. big.

[0362] On the other hand, as shown in FIG. 13B, in the sample A3, the stacked oxide semiconductor layer (IG The difference in electron affinity χ between ZO (1:1:1) and IGZO (1:3:6) is small at 0.2 eV. In addition, as shown in FIG. 15B, in sample A5, the oxide semiconductor layer (IGZO The difference in electron affinity χ between the IGO (1:1:1) and metal oxide layer (IGO (2:1)) is 0.2e V and small.

[0363] From this, as shown in sample A1, a gold layer provided between the oxide semiconductor layer and the pair of electrode layers By using the metal oxide layer as shown in the first embodiment, it is possible to obtain an oxide semiconductor. A band offset of the conduction band edge Ec can be formed between the metal layer and the metal oxide layer. .

[0364] On the other hand, as shown in sample A3, the difference in the conduction band minimum Ec of the stacked oxide semiconductor layers is small. and oxide semiconductor layer (IGZO(1:1:1)) and oxide semiconductor layer (IGZO(1:6: 4)) and the band offset of the conduction band minimum Ec between the oxide semiconductor layer (IGZO (1:6:4)) also experiences carrier leakage.

[0365] (Analysis of Cu concentration by SIMS) Next, in each of the samples A1, A3 to A5, the pair of electrode layers 110a and 110b were connected to each other. The diffusion of Cu in a metal oxide layer or an oxide semiconductor layer is discussed. The concentration of was measured.

[0366] Here, the samples were prepared by laminating a metal oxide film and a copper film on a substrate. The process for preparing the material will be explained.

[0367] (Sample A6) Sample A6 is a 100 nm thick In-Ga oxide film on a glass substrate. A film of (IGO(7:93)) was formed.

[0368] Next, a copper film having a thickness of 60 nm was formed on the metal oxide film. After forming the silicon nitride film, it was heated at 350°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen. Heat treatment was carried out.

[0369] The metal oxide film (IGO(7:93)) was the same as the metal oxide film (IGO( 7:93)) were prepared using similar conditions.

[0370] Through the above steps, sample A6 was produced.

[0371] (Sample A7) In sample A7, instead of the metal oxide film in sample A6, an oxide semiconductor film (IGZO(1 The other structures and fabrication conditions were the same as those of sample A6. The oxide semiconductor film (IGZO(1:3:6)) was the same as that of the oxide semiconductor film shown in Sample A3. The film was deposited under the same conditions as the solid film (IGZO (1:3:6)).

[0372] (Sample A8) In sample A8, instead of the metal oxide film in sample A6, an oxide semiconductor film (IGZO(1 The other structures and fabrication conditions were the same as those of sample A6. The oxide semiconductor film (IGZO (1:6:4)) was the same as the oxide semiconductor film shown in Sample A4. The film was deposited under the same conditions as the solid film (IGZO (1:6:4)).

[0373] (Sample A9) Sample A9 is a metal oxide film made of indium and gallium atoms instead of the metal oxide film in sample A6. The structure is provided with a metal oxide film with a different ratio (IGO (2:1)), and other structures and The formation conditions were the same as for sample A6. The metal oxide film (IGO(2:1)) was The film was formed under the same conditions as the metal oxide film (IGO (2:1)) shown in Sample A5.

[0374] Next, the Cu concentration of samples A6 to A9 was measured. The copper (Cu) concentration was measured using secondary ion Secondary Ion Mass Spectromet (SIMS) The Cu concentration was measured from the substrate side.

[0375] FIG. 11(C) shows the analysis result of the Cu concentration of sample A6, and FIG. 13(C) shows the analysis result of the Cu concentration of sample A7. The analysis results of the copper (Cu) concentration are shown in FIG. 14(C). FIG. 15(C) shows the analysis result of the copper (Cu) concentration of sample A9.

[0376] Here, the concentration of copper (Cu) in the channel region of a transistor, which affects the electrical characteristics, Degree is 1×10 18 atoms / cm 3 That's all.

[0377] As shown in FIG. 11C, in sample A6, the copper (Cu) concentration is 1×10 18 ato ms / cm 3 The area is located approximately 10 cm from the interface between the copper film and the metal oxide film (IGO(7:93)). It was found that the region was on the nm substrate side.

[0378] As shown in FIG. 13C, in sample A7, the copper (Cu) concentration is 1×10 18 atoms / cm 3 The area is the boundary between the copper film and the oxide semiconductor film (IGZO (1:3:6)). It was found that the area was approximately 10 nm from the surface toward the substrate.

[0379] On the other hand, as shown in FIG. 14C, in sample A8, the copper (Cu) concentration is 1×10 18 atoms / cm 3 The area is the boundary between the copper film and the oxide semiconductor film (IGZO (1:6:4)). It was found that the area was approximately 16 nm from the surface toward the substrate.

[0380] As shown in FIG. 15C, in the sample A9, the concentration of copper (Cu) was 1×10 18 atoms / cm 3 The region is located approximately 100 nm from the interface between the copper film and the metal oxide film (IGO(2:1)). It was found to be in the 15nm substrate side region.

[0381] A comparison of Sample A6 and Sample A9 shows that the metal oxide film with a high atomic ratio of Ga to In is It was found that the diffusion length of copper (Cu) can be reduced.

[0382] Comparing Sample A7 and Sample A8, the oxide semiconductor film with a high atomic ratio of Zn to Ga is It was found that the diffusion length of copper (Cu) can be reduced by the The high atomic ratio of Zn makes it possible to reduce the content of the spinel-type crystal structure. This is the case.

[0383] From the above, it is easy to form a band offset with the oxide semiconductor layer, and the copper (Cu) A metal oxide layer capable of reducing the diffusion length is provided between the oxide semiconductor layer and the pair of electrode layers. By providing the gate insulating film, a transistor having a high on-state current and excellent Vg-Id characteristics can be manufactured. It is possible. EXAMPLES

[0384] In this embodiment, the crystal structure of the metal oxide film, the number of particles during film formation, and the band diameter The results of these measurements are explained below.

[0385] (Sample preparation method) In this embodiment, a 100 nm thick In-Ga oxide film was formed on a quartz substrate as a metal oxide film. The above was deposited by sputtering to prepare a sample.

[0386] The deposition conditions for the In-Ga oxide film were In:Ga=22:78 [atomic ratio]. In:Ga=7:93 [atomic ratio] oxide target, or In: Each sample was prepared using an oxide target with an atomic ratio of Ga=2:98. The oxide target had an atomic ratio of n:Ga=22:78, and the In:Ga target had an atomic ratio of 7:93. When using an oxide target with a molecular weight ratio of 1.0 to 1.0, the power supply (DC) was set to 200 kW. When using an oxide target with In:Ga=2:98 [atomic ratio], the power supply (RF) The power output was set at 400kW.

[0387] The deposition atmosphere was argon:oxygen=20sccm:10sccm, or The oxygen flow rate was 30 sccm.

[0388] As the substrate temperature condition, the substrate temperature was set to 200° C. or 300° C.

[0389] The pressure in the chamber was set to 0.4 Pa for each sample.

[0390] (XRD measurement) Here, the substrate temperature was set at 300°C, and metal oxide films were formed using each oxide target. Next, the crystal structure of the metal oxide film of each sample was measured by XRD. The results of the XRD measurements are shown in FIG.

[0391] As shown in FIG. 16, the oxide target with In:Ga=22:78 [atomic ratio] and In:Ga The metal oxide film formed using an oxide target with an atomic ratio of 7:93 has low crystallinity. It was a thin membrane.

[0392] On the other hand, an oxide target with an In:Ga atomic ratio of 2:98 was used, and the deposition atmosphere was The metal oxide film formed under the condition of oxygen 30sccm had a peak indicating Ga2O3 crystals. This indicates that the atomic ratio of Ga to In is high and the condition is oxygen atmosphere. It was found that the metal oxide film formed in the above process contained Ga2O3 crystals.

[0393] (Number of particles during deposition) Next, the relationship between the atomic ratio of metals contained in the oxide target and the number of particles generated was examined. The measurement results will be explained below.

[0394] In the samples used for the measurements, a glass substrate was used instead of a quartz substrate. The conditions were argon:oxygen=20sccm:10sccm, and the substrate temperature was set at 3 00° C., and a metal oxide film was formed using each oxide target.

[0395] Next, the number of particles on the glass substrate before and after the formation of the metal oxide film was counted using a laser. The results are shown in Table 1.

[0396] [Table 1]

[0397] From Table 1, when the atomic ratio of In and Ga is In:M=x:y, y / (x+y) is 0. By forming a metal oxide film using an oxide target with a surface roughness of 9 or more, From this, it can be seen that the number of In atoms and Ga atoms can be reduced by setting the atomic ratio of In to Ga as follows: When x:y, a metal oxide is produced by using an oxide target where y / (x+y) is 0.9 or more. By forming the film, transistors can be manufactured with high yield.

[0398] (Band diagram) Next, in the same manner as in Example 1, a spectroscopic ellipsometer and an ultraviolet photoelectron Using spectroscopic analysis, the energy gap Eg, ionization potential Ip, and electron affinity The force χ was calculated and a band diagram was obtained for each metal oxide film.

[0399] In addition, the sample used for the measurement was deposited under the following atmospheric conditions: argon:oxygen=20scc The substrate temperature was set at 300°C, and each oxide target was used for gold. A metal oxide film was formed.

[0400] Figure 17 shows a metal oxide film formed using an oxide target with an In:Ga atomic ratio of 1:1. In:Ga=22:78 [atomic ratio] oxide target Metal oxide film (IGO(22:78)) formed using In:Ga=7:93 [atomic Metal oxide film (IGO(7:93)) formed using an oxide target with a ratio of 1:1, In Metal oxide film (IG) formed using an oxide target with an atomic ratio of 2:98 O(2:98)) are shown. An oxide semiconductor film formed using an oxide target with an atomic ratio of a:Zn=1:1:1 (IGZO(1:1:1) band diagram shown.

[0401] As shown in Fig. 17, in the oxide target, as the atomic ratio of Ga to In increases, , the difference in electron affinity χ between the oxide semiconductor film and the metal oxide film becomes large.

[0402] For this reason, the metal oxide layer provided between the oxide semiconductor layer and the pair of electrode layers is The metal oxide layer shown in Form 1 is typically formed by forming a metal oxide layer having an atomic ratio of In and Ga of In:M=x: When y is used, y / (x+y) is 0.75 or more and less than 1, preferably 0.78 or more and less than 1. More preferably, the metal oxide layer has a refractive index of 0.80 or more and less than 1. A band offset of the conduction band minimum Ec can be formed between the layer and the metal oxide layer. [Explanation of symbols]

[0403] 10 Electron Gun Room 12 Optical system 14 Sample Room 16 Optical system 18 Camera 20 Observation Room 22 Film Room 24 electronic 28 Substance 32 Fluorescent Screen 100 Substrates 101a first conductive layer 101b First conductive layer 102 Gate electrode layer 103a second conductive layer 103b second conductive layer 104 Gate insulation layer 104a Nitride insulating layer 104b Oxide insulating layer 106 Oxide semiconductor layer 106a Oxide semiconductor film 108 Metal oxide layer 108a Metal oxide film 109a first conductive layer 109b first conductive layer 110a Electrode layer 110b Electrode layer 110c electrode layer 111a Second conductive layer 111b Second conductive layer 112 Oxide insulating layer 114 Oxide insulating layer 116 Nitride insulating layer 117a opening 117b opening 118 Electrode layer 119a Electrode layer 119b Electrode layer 119c electrode layer 200 Transistors 202a Gate electrode layer 202b Electrode layer 206 Oxide semiconductor layer 210 Transistor 220 Transistor 230 Transistor 300 Transistors 306a Oxide semiconductor layer 306b Oxide semiconductor layer 316a Oxide semiconductor layer 316b Oxide semiconductor layer 310 Transistor 700 Substrates 701 Pixel section 702 Scanning line driver circuit 703 Scanning line driver circuit 704 Signal line driver circuit 710 Capacitance wiring 712 Gate wiring 713 Gate wiring 714 Drain electrode layer 716 Transistor 717 Transistor 718 Liquid crystal element 719 Liquid crystal element 720 pixels 721 Switching Transistors 722 Driving Transistor 723 Capacitive element 724 Light emitting element 725 Signal Line 726 scan lines 727 Power line 728 Common electrode 1001 Main unit 1002 Case 1003a Display section 1003b Display section 1004 Keyboard Buttons 1021 Main unit 1022 Fixed part 1023 Display section 1024 operation buttons 1025 external memory slot 1030 Case 1031 Case 1032 Display Panel 1033 Speaker 1034 Microphone 1035 Operation Key 1036 Pointing Device 1037 Camera 1038 External connection terminal 1040 Solar Cell 1041 External memory slot 1050 Television Equipment 1051 Case 1052 Storage media playback and recording unit 1053 Display section 1054 External connection terminal 1055 Stand 1056 External Memory 5100 pellets 5100a Pellet 5100b Pellets 5101 AEON 5102 Zinc oxide layer 5103 particles 5105a Pellet 5105a1 area 5105a2 Pellet 5105b Pellet 5105c Pellet 5105d Pellet 5105d1 area 5105e Pellet 5120 PCB 5130 Target 5161 area 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

[Claim 1] an oxide semiconductor layer; a metal oxide layer in contact with the oxide semiconductor layer and made of an In-M oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf); a conductive layer in contact with the metal oxide layer and containing copper, aluminum, gold or silver; The semiconductor device according to the present invention is characterized in that, when the atomic ratio of In to M contained in the metal oxide layer is In:M=x:y, y / (x+y) is 0.75 or more and less than 1.

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