Semiconductor device

Abstract

To provide a semiconductor device with a JBS structure in which an electric characteristic is improved.SOLUTION: A JBS structure in which a Schottky junction of an n- type drift region 2 and a Schottky electrode 11 and a pn junction of a p+type region 3 and the n- type drift region 2 are mixed on a front surface side of a semiconductor substrate 10 is provided. Also, on a front surface of the semiconductor substrate 10, a first trench 4 subsidiarily formed at the time of forming the p+type region 3 and a second trench 5 intentionally formed are provided. The second trench 5 is provided in a stripe shape crossing the p+type region 3 at a depth that is shallower than the p+type region 3, and crosses a pn junction diode by the pn junction with an SBD by the Schottky junction. By repeatedly arranging steps 41, 42, 51, and 52 having different heights on the front surface of the semiconductor substrate 10 by the first and second trenches 4 and 5 with a predetermined pattern, an exposure surface of the n- type drift region 2 on the front surface side of the semiconductor substrate 10 is increased.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, Schottky barrier diodes (SBDs) used as power devices have adopted a JBS (Junction Barrier Schottky) structure in which a Schottky junction and a pn junction are mixed on the front surface side of a semiconductor substrate, and the p + An apparatus in which a mold region is formed on the surface region of the inner wall of an anode trench is known (see, for example, Patent Documents 1 to 3 listed below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-116471 A [Patent Document 2] JP 2018-101668 A [Patent Document 3] JP 2011-009797 A Summary of the Invention [Problem to be solved by the invention]

[0004] The conduction loss of an SBD is n - The larger the contact area between the semiconductor substrate and the Schottky electrode (the area of ​​the Schottky junction), the greater the conduction loss. However, in an SBD with a JBS structure, a Schottky junction and a pn junction are mixed on the front surface side of the semiconductor substrate, and the area of ​​the Schottky junction is reduced by the area of ​​the pn junction diode formed by the pn junction, resulting in greater conduction loss than an SBD with only a Schottky junction of the same chip size.

[0005] SUMMARY OF THE PRESENT DISCLOSURE In order to solve the above-mentioned problems associated with the prior art, an object of the present invention is to provide a semiconductor device having a JBS structure with improved electrical characteristics. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features. A second conductivity type region is selectively provided on a first main surface of a first conductivity type semiconductor substrate, and extends in a direction parallel to the first main surface. The first conductivity type region is a portion of the semiconductor substrate excluding the second conductivity type region, and extends along the second conductivity type region in a direction parallel to the first main surface. A first electrode is provided on the first main surface, forms a Schottky junction with the first conductivity type region, and contacts the second conductivity type region at the first main surface. A second electrode is provided on the second main surface of the semiconductor substrate.

[0007] A first step, a second step, and a third step are formed on the first main surface. The first step makes the height position of a contact surface between the first electrode and the second conductivity type region lower than the height position of a contact surface between the first electrode and the first conductivity type region. The second step intersects with the first step and has a height difference in the longitudinal direction of the first conductivity type region to partially lower a height position of a contact surface between the first electrode and the first conductivity type region. The third step intersects the first step and is continuous with the second step, and has a height difference in the longitudinal direction of the second conductivity type region to partially lower the height position of the contact surface between the first electrode and the second conductivity type region.

[0008] The semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, a first trench is provided in the first main surface, extends along the second conductivity type region in a direction parallel to the first main surface, and has a bottom surface surrounded by the second conductivity type region. A second trench is provided in the first main surface intersecting the first conductivity type region and the second conductivity type region, and has a bottom surface selectively surrounded by the first conductivity type region and the second conductivity type region, respectively. The first step is formed by the first trench. The second step and the third step are formed by the second trench.

[0009] In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A first trench is provided in a first main surface of a semiconductor substrate of a first conductivity type, and extends in a direction parallel to the first main surface. A second conductivity type region is selectively provided in the semiconductor substrate, extends along the first trench in a direction parallel to the first main surface, and surrounds a bottom surface of the first trench. The first conductivity type region is a portion of the semiconductor substrate excluding the second conductivity type region, and extends along the second conductivity type region in a direction parallel to the first main surface in the first main surface. A second trench is provided in the first main surface so as to intersect with the first conductivity type region and the second conductivity type region, and has a bottom surface selectively surrounded by the first conductivity type region and the second conductivity type region, respectively. A first electrode is provided on the first main surface, is embedded in the first trench and the second trench, is Schottky junctioned with the first conductivity type region, and is in contact with the second conductivity type region. A second electrode is provided on the second main surface of the semiconductor substrate.

[0010] In addition, the semiconductor device of the present invention is characterized in that, in the above-mentioned invention, the second conductivity type region is deeper toward the second main surface than the bottom surface of the second trench, at least in the portion that faces the second trench in the depth direction.

[0011] In addition, in the semiconductor device according to the present invention, the depth of the second conductivity type region from the first main surface is uniform.

[0012] In addition, in the semiconductor device according to the present invention, a bottom surface of the second trench is located deeper toward the second main surface than a bottom surface of the first trench.

[0013] In the semiconductor device according to the present invention, in the above-mentioned invention, the second conductivity type regions extend in a stripe pattern in a direction parallel to the first main surface, the second trenches extend in a stripe pattern intersecting the first conductivity type regions and the second conductivity type regions, and a width of the second trenches is narrower than an arrangement interval of the second conductivity type regions.

[0014] In addition, in the semiconductor device according to the present invention described above, the second conductivity type region surrounds the entire inner wall of the first trench.

[0015] In the semiconductor device according to the present invention, in the above-mentioned invention, the first electrode has a first metal layer and a second metal layer. The first metal layer is provided along the first main surface, an inner wall of the first trench, and an inner wall of the second trench, forms a Schottky junction with the first conductivity type region, and contacts the second conductivity type region. The second metal layer is provided on the first metal layer inside the first trench and inside the second trench, and fills the first trench and the second trench.

[0016] In addition, in the semiconductor device according to the present invention, the second metal layer is made of titanium nitride or tungsten.

[0017] According to the above-mentioned invention, the exposed area of ​​the first conductivity type region or the second conductivity type region on the first main surface side of the semiconductor substrate is increased, and therefore the contact area between the first conductivity type region or the second conductivity type region on the first main surface side of the semiconductor substrate and the Schottky electrode is increased. When the contact area between the first conductivity type region and the Schottky electrode is increased, the internal resistance of the SBD is lowered and the conduction loss of the SBD is reduced. When the contact area between the second conductivity type region and the Schottky electrode is increased, the allowable current amount of the pn junction diode formed by the pn junction between the second conductivity type region and the first conductivity type region is increased, and the withstand capability against a large current exceeding the rated current is improved. Effect of the Invention

[0018] According to the semiconductor device of the present invention, it is possible to provide a semiconductor device having a JBS structure with improved electrical characteristics. [Brief description of the drawings]

[0019] [Figure 1] 1 is a perspective view showing a structure of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view showing a cross-sectional structure taken along line AA' in FIG. [Diagram 3] 2 is a cross-sectional view showing a cross-sectional structure taken along line BB' in FIG. [Figure 4] 2 is a cross-sectional view showing a cross-sectional structure taken along line CC' in FIG. [Diagram 5] 2 is a cross-sectional view showing a cross-sectional structure taken along line DD' in FIG. [Figure 6] 1. FIG. 4 is a cross-sectional view showing another example of the cross-sectional structure taken along the line DD' in FIG. [Figure 7] 4 is a plan view showing another example of the layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. FIG. [Figure 8] 1 is a cross-sectional view (part 1) showing a state during the manufacture of the semiconductor device according to the first embodiment; [Figure 9] 4 is a cross-sectional view (part 2) showing a state during the manufacture of the semiconductor device according to the first embodiment. FIG. [Figure 10] 4 is a cross-sectional view (part 3) showing a state during the manufacture of the semiconductor device according to the first embodiment. FIG. [Figure 11] 4 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment (part 4). FIG. [Figure 12] 5 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment (part 5). FIG. [Figure 13] 6 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment (part 6). FIG. [Figure 14] FIG. 7 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; [Figure 15] FIG. 8 is a cross-sectional view showing a state during the manufacture of the semiconductor device according to the first embodiment; [Figure 16] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. [Figure 17] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. [Figure 18] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. [Figure 19] FIG. 11 is a cross-sectional view showing a structure of a semiconductor device according to a second embodiment. [Figure 20] 11 is a cross-sectional view (part 1) showing a state during the manufacture of a semiconductor device according to a second embodiment. FIG. [Figure 21] FIG. 2 is a cross-sectional view (part 2) showing a state during the manufacture of the semiconductor device according to the second embodiment. [Figure 22] FIG. 1 is a perspective view showing a structure of a semiconductor device according to a reference example. [Diagram 23] 23 is a cross-sectional view showing a cross-sectional structure taken along line AA-AA' in FIG. 22. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, in layers and regions prefixed with n or p, electrons or holes are the majority carriers, respectively. In addition, + and - appended to n or p respectively mean that the impurity concentration is higher and lower than that of layers and regions not prefixed with them. In the following description of the embodiments and the accompanying drawings, the same reference numerals are assigned to similar configurations, and duplicated explanations will be omitted.

[0021] (overview) As a result of intensive research, the present inventor has found the following. The structure of a semiconductor device of a reference example will be described. FIG. 22 is a perspective view showing the structure of a semiconductor device of a reference example. In FIG. 22, an anode electrode 114 is omitted in order to clarify the layout of the JBS structure and the trench 104. FIG. 23 is a cross-sectional view showing the cross-sectional structure taken along the cutting line AA-AA' in FIG. 22. A semiconductor device 120 of a reference example shown in FIGS. 22 and 23 is a SiC-SBD of a JBS structure in which a Schottky junction and a pn junction are mixed on the front surface side of a semiconductor substrate (semiconductor chip) 110 made of silicon carbide (SiC), and has Schottky junction regions 121 and pn junction regions 122 alternately and repeatedly arranged in a first direction X parallel to the front surface of the semiconductor substrate 110.

[0022] The Schottky junction region 121 has n - An SBD is formed by a Schottky junction between the type drift region 102 and the Schottky electrode 111 at the bottom of the anode electrode 114. + Type region 103 and n - A pn junction diode is formed by a pn junction with the type drift region 102. The SBD of the Schottky junction region 121 and the pn junction diode of the pn junction region 122 are connected in parallel by a Schottky electrode 111 and a cathode electrode 115. The Schottky junction region 121 and the pn junction region 122 extend in a stripe shape in a second direction Y that is parallel to the front surface of the semiconductor substrate 110 and perpendicular to the first direction X.

[0023] p + The n-type region 103 is connected to the trench 104. - The p-type drift region 102 is provided between the p-type drift region 102 and the p-type drift region 102. + The mold regions 103 are provided in a plurality of locations spaced apart from each other in the first direction X and extend in stripes in the second direction Y. + Between the mold regions 103, n - The drift region 102 reaches the front surface of the semiconductor substrate 110. + The portion where the type region 103 is provided is a pn junction region 122. + The portion sandwiched between the p-type regions 103 is a Schottky junction region 121. The trench 104 is + In order to reliably form openings in the ion implantation mask used to form mold region 103, over-etching is performed to form a second opening on the front surface of semiconductor substrate 110 in the same pattern as the mask opening pattern.

[0024] Impurities in SiC have a small diffusion coefficient and hardly diffuse at all. + The Schottky region 103 is formed by ion implanting p-type impurities into the bottom surface of the trench 104 through an ion implantation mask, has approximately the same width as the bottom surface of the trench 104, and surrounds only the bottom surface of the trench 104. The Schottky electrode 111 is provided along the front surface of the semiconductor substrate 110 and the inner wall of the trench 104 in the active region. The Schottky electrode 111 is n-type on the front surface of the semiconductor substrate 110 and the sidewall of the trench 104. - The bottom surface of the trench 104 is p + The semiconductor substrate 110 is in contact with the n-type region 103. + A mold cathode region 101 and a cathode electrode 115 are provided.

[0025] Generally, the conduction loss of an SBD is -The larger the contact area (area of ​​the Schottky junction) between the n-type semiconductor substrate and the Schottky electrode, the lower the wiring resistance. The reason for this is that, just as the larger the diameter (cross-sectional area) of the wiring, the larger the area of ​​the Schottky junction, the larger the cross-sectional area of ​​the path of the forward current in the SBD, and the lower the internal resistance of the SBD. In the semiconductor device 120 (SiC-SBD with a JBS structure) of the reference example described above, the n-type semiconductor substrate 110 is located from the front surface of the semiconductor substrate 110 to the sidewall of the trench 104. - Since the type drift region 102 and the Schottky electrode 111 form a Schottky junction, the area of ​​the Schottky junction is increased by the trench 104, thereby reducing the conduction loss.

[0026] On the other hand, impurities in silicon (Si) have a large diffusion coefficient and are easily diffused. When the semiconductor device 120 of the above-mentioned reference example is applied to a Si-SBD (not shown) having a JBS structure using Si as a semiconductor material, the pn junction of the JBS structure is formed. + The p-type region is formed by diffusing p-type impurities ion-implanted into the bottom surface of the trench by over-etching during the formation of the ion implantation mask, so that the p-type region surrounds the entire inner wall of the trench. + The contact area between the type region and the Schottky electrode is increased. This increases the allowable current of the pn junction diode, improving its resistance to large currents (surge currents and inrush currents) that exceed the rated current. In addition, the increased area of ​​the pn junction improves the effect of suppressing leakage currents during reverse bias.

[0027] However, trench 104 is p + The p-type region 103 is formed by over-etching during the formation of an ion implantation mask. + The trenches 104 are formed to have the same width as the mold region 103. Therefore, the number of trenches 104 that can be formed in the active region is p +The effect of increasing the contact area with Schottky electrode 111 by trench 104 is limited due to the constraints imposed by the pattern of mold region 103. In addition, trench 104 is not intentionally formed with a view to achieving a specific effect, and therefore contributes little to improving the electrical characteristics of the JBS SBD (e.g., reducing conduction loss and improving breakdown voltage). Therefore, one of the problems to be solved in this embodiment is how to improve the electrical characteristics of the JBS SBD.

[0028] (Embodiment 1) The structure of the semiconductor device according to the first embodiment will be described. FIG. 1 is a perspective view showing the structure of the semiconductor device according to the first embodiment. In FIG. 1, the anode electrode 14 is omitted. FIGS. 2 to 5 are cross-sectional views showing the cross-sectional structures along the lines A-A', B-B', C-C', and D-D' in FIG. 1, respectively. FIG. 6 is a cross-sectional view showing another example of the cross-sectional structure along the line D-D' in FIG. 1. In FIGS. 2, 5, and 6, the height position of the first n-type surface 2a on the front surface of the semiconductor substrate 10 is indicated by a broken line. FIG. 7 is a plan view showing another example of the layout of the semiconductor device according to the first embodiment as viewed from the front surface side of the semiconductor substrate. FIG. 7 shows another example of the layout of the second trenches 5 (5a, 5b).

[0029] 1 to 5, a semiconductor device 20 according to a first embodiment is a SiC-SBD with a JBS structure in which a Schottky junction and a pn junction are mixed on the front surface side of a semiconductor substrate (semiconductor chip) 10 made of SiC, and has a Schottky junction region 21 and a pn junction region 22 in an active region. The Schottky junction regions 21 and the pn junction regions 22 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 10, and extend in a stripe shape in a second direction Y parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X. A pair of adjacent Schottky junction regions 21 and pn junction regions 22 may extend linearly in the second direction Y. The active region is a region through which a forward current flows when the SBD is conductive.

[0030] The entire front surface of the semiconductor substrate 10 in the edge termination region (not shown) is covered with an interlayer insulating film, and the entire active region is exposed at an opening in the interlayer insulating film. The edge termination region is a region between the active region and the side surface of the semiconductor substrate 10, and surrounds the periphery of the active region. The edge termination region has the function of maintaining a breakdown voltage by mitigating the electric field on the front surface side of the semiconductor substrate 10. The breakdown voltage is the maximum voltage at which an element does not malfunction or break down. In the edge termination region, a predetermined breakdown voltage structure such as a field limiting ring (FLR) or a junction termination extension (JTE) structure is disposed.

[0031] The Schottky junction region 21 has n - An SBD is formed utilizing the rectification of a Schottky barrier formed at the junction (Schottky junction) between the first-conductivity-type drift region (first conductivity-type region) 2 and the Schottky electrode (first metal layer) 11. + type region (second conductivity type region) 3 and n - A pn junction diode is formed by a pn junction with the type drift region 2. The SBD of the Schottky junction region 21 and the pn junction diode of the pn junction region 22 are connected in parallel by an anode electrode (first electrode) 14 and a cathode electrode (second electrode) 15.

[0032] The SBD in the Schottky junction region 21 conducts at a rated current when forward biased. The pn junction diode in the pn junction region 22 has the function of conducting and suppressing an increase in forward voltage when a large current (surge current or inrush current) exceeding the rated current flows when the power supply is turned on or off or the load is shorted. The timing at which a forward current flows into the pn junction diode in the pn junction region 22 is determined by the relationship between the Schottky electrode 11 and the p + It is determined by the contact resistance with the p-type region 3. + Type regions 3 and n - The leakage current is suppressed by a depletion layer extending from the pn junction with the type drift region 2.

[0033] The semiconductor substrate 10 is made of SiC. + On the front surface of the starting substrate 31, - n type drift region 2 - The semiconductor substrate 10 is formed by stacking an n-type epitaxial layer 32. - The first main surface on the n-type epitaxial layer 32 side is the front surface, + The second main surface (n + The back side of the starting substrate 31 is referred to as the back side. + The starting substrate 31 is n + This is the type cathode region 1. - Of the p-type epitaxial layer 32, + The part excluding the type region 3 is n - type drift region 2. + The n-type region 3 is connected to the bottom surface of the first trench 4. - Between the n-type drift region 2, - The first trench 4 is formed in contact with the first drift region 2 and surrounds the bottom surface of the first trench 4. + A plurality of mold regions 3 are provided spaced apart from each other in the first direction X and extend in the second direction Y in a striped pattern.

[0034] p + The width of the mold region 3 (width in the first direction X) is, for example, about 2.3 μm or more and 3 μm or less. + The pitch of the mold regions 3 (the arrangement interval in the first direction X (the interval between the stripes)) is, for example, about 2.3 μm or more and 3 μm or less. + Between the type regions 3, n - The drift region 2 reaches the front surface of the semiconductor substrate 10 and is exposed on the front surface of the semiconductor substrate 10. - Type 2 drift region and p + The type regions 3 are arranged alternately and repeatedly adjacent to each other in a first direction X in a portion exposed on the front surface side of the semiconductor substrate 10, and extend in a stripe shape in a second direction Y. The exposure on the front surface side of the semiconductor substrate 10 means that the type regions 3 are exposed on the front surface of the semiconductor substrate 10 or on the inner walls (side walls and bottom surfaces) of the first and second trenches 4 and 5 described later, and are in contact with a Schottky electrode 11 described later. + The portion where the type region 3 is provided is a pn junction region 22.+ The portion sandwiched between the mold regions 3 is a Schottky junction region 21 .

[0035] First and second trenches 4 and 5 are provided in the front surface of the semiconductor substrate 10 in the active region, and intersect with each other. The first and second trenches 4 and 5 form three or more steps (steps 41, 42, 51, and 52 in FIG. 1) with different heights that are repeatedly arranged in a predetermined pattern on the front surface of the semiconductor substrate 10. The bottom surfaces of the first and second trenches 4 and 5 are p + The lower surface (n + The first and second trenches 4 and 5 are located at a shallower depth on the front surface side of the semiconductor substrate 10 than the surface on the side of the n-type cathode region 1. The first and second trenches 4 and 5 may be substantially rectangular or may be trapezoidal in shape with a width in the first direction X narrowing toward the bottom. The first and second trenches 4 and 5 form an n-type - Since the exposed surface of the n-type drift region 2 increases, - The contact area between the type drift region 2 and the Schottky electrode 11 (the area of ​​the Schottky junction) becomes large.

[0036] Specifically, the first trench 4 is p + The first trench 4 is formed in the same pattern as the mask opening pattern by overetching during the formation of the ion implantation mask used to form the mold region 3. + It has a width (bottom width) approximately the same as the width of the mold region 3, and p + p in the same position as type 3 + The first trench 4 is formed in the same pattern as the mold region 3. + The type region 3 is exposed, and the entire side wall of the first trench 4 is doped with n - The first trenches 4 expose the n-type drift region 2. - Type 2 drift region and p + Between the n-type region 3, - The upper surfaces (hereinafter referred to as the first and second n-type surfaces) 2a and 2b of the n-type drift region 2 are p + The upper surfaces 3a and 3b of the mold region 3 (hereinafter referred to as the first and second p-type surfaces) are +Lowered steps (first steps) 41 and 42 are formed on the side of the mold cathode region 1 (FIG. 3, 2).

[0037] The first n-type surface 2a and the first p-type surface 3a are alternately and repeatedly arranged with steps 41 interposed therebetween in the longitudinal direction of the second trench 5. A fourth n-type surface 2d (a sidewall of the first trench 4) connecting the first n-type surface 2a and the first p-type surface 3a has an n - The second n-type drift region 2 is exposed. The second n-type surface 2b and the second p-type surface 3b are alternately and repeatedly arranged with steps 42 interposed therebetween in the longitudinal direction of the second trench 5. A fifth n-type surface 2e (a side wall of the first trench 4) connecting the second n-type surface 2b and the second p-type surface 3b has an n - The first drift region 2 is exposed. The steps 41, 42 are formed simultaneously by the first trench 4 and have the same height difference. The steps 41, 42 intersect with the steps 51, 52 and are continuous in the second direction Y. The steps 51, 52 are formed by the second trench 5 between the first and second n-type faces 2a, 2b and between the first and second p-type faces 3a, 3b, respectively.

[0038] The second trench 5 is p + The second trenches 5 are provided in a stripe shape intersecting the type region 3 and intersect with the SBD of the Schottky junction region 21 and the pn junction diode of the pn junction region 22. + It may be perpendicular to the mold region 3 (i.e. extend in the first direction X) (see FIG. 1), + The second trench 5 may be formed so as to intersect obliquely with the type region 3 (see FIG. 7). - The p-type drift region 2 (i.e., the first n-type surface 2a) is partially left. + It is sufficient that the p + In this case, the p + By forming the second trenches 5 intersecting the type region 3 at different depths, - Type drift region 2 and p + The height difference between steps 51 and 52, which will be described later, at the intersection between the mold region 3 and the second trench 5 can be further increased. +Parts of second trenches 5 (5a, 5b) that diagonally intersect with mold region 3 and extend in two different directions XY1, XY2 are indicated by thick lines.

[0039] Each of the second trenches 5 provides a second n-type surface 2b that is closer to the first n-type surface 2a on the front surface of the semiconductor substrate 10. + A plurality of steps (second steps) 51 are formed on the side of the n-type cathode region 1 (FIG. 4). The first n-type surface 2a and the second n-type surface 2b are aligned in a second direction Y (the n-type surface of the front surface of the semiconductor substrate 10). - The first n-type surface 2a and the second n-type surface 2b are connected to a third n-type surface 2c (the side wall of the second trench 5) by a step 51. - The n-type drift region 2 is exposed. In addition, the n-type drift region 2 is exposed on the front surface of the semiconductor substrate 10 by the second trenches 5. + A plurality of steps (third steps) 52 are formed on the side of the p-type cathode region 1 (FIGS. 5 and 6). The first p-type surface 3a and the second p-type surface 3b are arranged in a second direction Y(p + The first p-type surface 3a and the second p-type surface 3b are connected to each other via a step 52 in a longitudinal direction of the p-type region 3. A third p-type surface 3c (a side wall of the second trench 5) connecting the first p-type surface 3a and the second p-type surface 3b has a p + The mold region 3 is exposed. The steps 51, 52 are formed simultaneously by the second trench 5 and have the same height difference. The steps 51, 52 intersect the steps 41, 42 and are continuous with each other in the longitudinal direction of the second trench 5 (the first direction X in FIGS. 1 to 6).

[0040] On the front surface side of the semiconductor substrate 10, the first n-type surface 2a where neither the first nor the second trenches 4, 5 exist is at the highest (most protruding) height position. The second p-type surface 3b (bottom surface of the first and second trenches 4, 5) at each intersection of the first trench 4 and the second trench 5 is lower by the total depth of the first and second trenches 4, 5 formed at different times, and is therefore at the lowest (most protruding) height position. +The second n-type surface 2b, which is the bottom surface of the second trench 5, and the first p-type surface 3a, which is the bottom surface of the first trench 4, may be at the same height (height difference between the steps 41 and 51). At the intersection of the Schottky junction region 21 and the second trench 5, the inner wall of the second trench 5 has an n - The pn-type drift region 2 is exposed. At the intersection of the pn junction region 22 and the second trench 5, a p + The mold area 3 is exposed.

[0041] The width of the bottom surface of the second trench 5 in the short direction is preferably as narrow as possible. For example, + The pitch of the second trenches 5 is narrower than the pitch of the n-type regions 3. Preferably, the width of the short side of the bottom surface of the second trenches 5 is the minimum width of the etching processing limit. The narrower the width of the short side of the bottom surface of the second trenches 5, the more the number of second trenches 5 that can be arranged in the active region can be increased. This allows the n-type region 3 on the front surface side of the semiconductor substrate 10 to be - Since the exposed surface of the drift region 2 can be increased, the area of ​​the Schottky junction is increased. + Since the exposed surface of the p-type region 3 is increased, the Schottky electrode 11 and + The contact area with the mold region 3 is also increased. The bottom surface of the second trench 5 is n-type, which is larger than the bottom surface of the first trench 4. + The second trench 5 may be located deeper on the side of the n-type cathode region 1. As the second trench 5 becomes deeper, the n-type cathode region 1 on the front surface side of the semiconductor substrate 10 - Type drift region 2 and p + The exposed surface area of ​​the mold area 3 can be increased.

[0042] The second trench 5 is intentionally formed at any timing after the start of the manufacturing process of the semiconductor device 20 and before the formation of the Schottky electrode 11. For example, the second trench 5 may be formed simultaneously with an alignment mark (a recess serving as a mark for aligning a mask when forming each part of the element structure). By forming the second trench 5 simultaneously with the alignment mark, an increase in the number of steps in the manufacturing process can be suppressed, and therefore the manufacturing process can be simplified. When the second trench 5 is formed simultaneously with the alignment mark, for example, the second trench 5 is formed at a pitch of about 0.5 μm to a depth of about 0.4 μm (or a depth of about 0.8 μm). The depth of the alignment mark may be set according to the depth of the second trench 5.

[0043] The second trench 5 is p + When the p-type region 3 (first trench 4) is formed before the formation of the p-type region 3 (first trench 4), + In the ion implantation 65 (see FIG. 13) to form the p-type region 3, which will be described later, p-type impurities are ion-implanted into the bottom surfaces of the first and second trenches 4 and 5. + The depth of the mold region 3 is n in the portion facing the second trench 5 in the depth direction Z. + The second trench 5 is protruding toward the cathode region 1 and is deeper (FIG. 5). + When the p-type region 3 is formed after the p-type region 3, the p-type impurity is ion-implanted 65 into the bottom surface of the first trench 4. + After the formation of the type region 3, p + The second trench 5 is formed to a depth that does not penetrate the mold region 3. + The depth of the p-type region 3 from the front surface of the semiconductor substrate 10 is approximately uniform. + The lower surface of the mold region 3 is a substantially flat surface parallel to the front surface of the semiconductor substrate 10 (FIG. 6).

[0044] The anode electrode 14 is formed by sequentially stacking a Schottky electrode 11, a buried electrode (second metal layer) 12, and a surface electrode 13 on the front surface of the semiconductor substrate 10 in the active region. The Schottky electrode 11 is formed along the unevenness due to steps 41, 42, 51, 52 formed by the first and second trenches 4, 5 on the front surface of the semiconductor wafer 60. The Schottky electrode 11 is formed on the first to fifth n-type surfaces 2a to 2e. - The first to third p-type surfaces 3a to 3c are connected to a Schottky junction with the p-type drift region 2. + The Schottky electrode 11 is in contact with the n-type region 3. - The Schottky barrier height is large relative to the p-type drift region 2, and + It is a metal having a small Schottky barrier height with respect to the type region 3, and specifically, for example, titanium (Ti) or molybdenum (Mo) can be used.

[0045] The buried electrode 12 is provided on the Schottky electrode 11 so as to fill the first and second trenches 4 and 5. The buried electrode 12 has a function of suppressing the occurrence of unevenness on the surface of the anode electrode 14 due to the first and second trenches 4 and 5, and flattening the surface of the anode electrode 14. The buried electrode 12 may be made of, for example, titanium nitride (TiN) or tungsten (W). By flattening the surface of the anode electrode 14, it is possible to suppress a decrease in adhesion between the anode electrode 14 and the bonding wire. If the flatness of the surface of the anode electrode 14 is not required, the buried electrode 12 may not be provided. The front surface electrode 13 is, for example, an aluminum (Al) film or an aluminum alloy film containing silicon (Si) or copper (Cu). A cathode electrode 15 common to the SBD of the Schottky junction region 21 and the pn junction diode of the pn junction region 22 is provided on the entire back surface of the semiconductor substrate 10. The cathode electrode 15 is an n + The cathode region 1 is in ohmic contact with the semiconductor substrate 1 .

[0046] The operation of the semiconductor device 20 (SiC-SBD with JBS structure) according to the first embodiment will be described. When the forward current flowing through the semiconductor device 20 according to the first embodiment is equal to or less than the rated current value, the anode electrode 14 and the Schottky electrode 11 are connected to the n-type MOSFET 10. - A forward current flows through a path (the current path of the SBD in the Schottky junction region 21) toward the cathode electrode 15 through the Schottky junction with the type drift region 2. When the forward current flowing through the semiconductor device 20 is equal to or less than the rated current value, no forward current flows through the pn junction diode in the pn junction region 22.

[0047] By forming the steps 41, 42, 51, 52 due to the first and second trenches 4, 5 on the front surface of the semiconductor substrate 10, the n-type semiconductor substrate 10 has a larger n-type ... - The exposed surface area of ​​the type drift region 2 is increased, and the area of ​​the Schottky junction is increased. As a result, the internal resistance of the SBD in the Schottky junction region 21 is reduced, and the conduction loss of the SBD is reduced.

[0048] When the power supply of a circuit in which the semiconductor device 20 is mounted is turned on and off or when a load is shorted, the forward current flowing through the semiconductor device 20 becomes a large current (surge current or inrush current) that exceeds the rated current value. - The entire current cannot be borne by the path through the Schottky junction with the type drift region 2 alone, and the current flows from the anode electrode 14 to the p + Current also flows into the pn junction region 3, and a forward current also flows into the pn junction diode of the pn junction region 22. This makes it possible to prevent the semiconductor device 20 from being destroyed by a large current.

[0049] On the other hand, when a positive voltage (reverse voltage) is applied to the cathode electrode 15 with respect to the anode electrode 14, p + Type regions 3 and n - Each pn junction with the drift region 2 + Type regions 3 and n- The depletion layer spreads in the p-type drift region 2. When the reverse voltage increases, the p + The depletion layers between the doped regions 3 are connected to each other and punched through. As a result, the maximum electric field point is located on the p + Since the electric field applied to the front surface of the semiconductor substrate 10 decreases, leakage current is suppressed.

[0050] A method for manufacturing the semiconductor device 20 according to the first embodiment will be described. FIGS. 8 to 15 are cross-sectional views showing the semiconductor device according to the first embodiment in the process of being manufactured. FIGS. 8 to 15 show cross sections corresponding to FIG. 3. First, as shown in FIG. 8, a starting wafer made of SiC (n after dicing) is + On the front surface of the mold (the portion that will become the starting substrate 31) - n type drift region 2 - The n-type epitaxial layer 32 is epitaxially grown to produce a semiconductor wafer 60 made of SiC. - The first main surface on the mold epitaxial layer 32 side is referred to as the front surface, and the second main surface on the starting wafer side is referred to as the back surface.

[0051] Next, by photolithography and etching, an alignment mark (not shown) is formed in the invalid area on the front surface of the semiconductor wafer 60, and a second trench 5 (see FIG. 1) is formed in the valid area on the front surface of the semiconductor wafer 60. The valid area of ​​the semiconductor wafer 60 is an area that will be separated into semiconductor chips (semiconductor substrate 10) after dicing. The invalid area of ​​the semiconductor wafer 60 is an area that is not included in the semiconductor chip, such as a dicing line. Next, an oxide film (SiO2 film) 61 is formed on the front surface of the semiconductor wafer 60.

[0052] 9, a resist film 62 is formed on the oxide film 61. Next, as shown in FIG. 10, p +A mask (reticle) 63 having a pattern of the mold region 3 is aligned. Next, light 64 from a predetermined light source is irradiated onto the resist film 62 through the mask 63, and the pattern of the mask 63 is projected and transferred onto the resist film 62 (exposure). Next, as shown in Fig. 11, the exposed portion of the resist film 62 is dissolved (developed) to form openings 62a in the resist film 62 having the same pattern as the pattern of the mask 63.

[0053] Next, as shown in FIG. 12, the oxide film 61 is etched and partially removed using the resist film 62 as a mask, and p is formed on the oxide film 61. + An opening 61a is formed exposing a portion corresponding to a region for forming the mold region 3. The oxide film 61 is over-etched so that the opening 61a reliably penetrates the oxide film 61 in the depth direction Z. This over-etching removes the surface region (SiC portion) of the front surface of the semiconductor wafer 60 at the portion of the oxide film 61 exposed at the opening 61a, and secondarily forms a first trench 4 in the front surface of the semiconductor wafer 60.

[0054] During this overetching, etching of the SiC portion also progresses in a direction parallel to the front surface of the semiconductor wafer 60 (lateral direction), so the width of the opening side of the first trench 4 becomes slightly wider than the width of the opening 61a of the oxide film 61. By forming the first trench 4, steps 41, 42, 51, 52 with different height differences due to the first and second trenches 4, 5 are formed on the front surface of the semiconductor wafer 60 (see FIG. 1). The overetching time may be intentionally lengthened to deepen the depth of the first trench 4. Then, the resist film 62 is removed.

[0055] Next, as shown in FIG. 13, p-type impurities are ion-implanted 65 using the remaining portion of the oxide film 61 as a mask, so that p-type impurities are implanted into the surface region of the bottom surface (first p-type surfaces 3a to 3c) of the first trench 4. + The p-type region 3 is formed. The p-type impurity ions 65 are not implanted into the sidewalls (fourth and fifth n-type surfaces 2d and 2e) of the first trench 4. Therefore, the portions (first to third n-type surfaces 2a to 2c) covered with the oxide film 61 and the sidewalls of the first trench 4 are not implanted with the p-type impurity ions 65. - Type epitaxial layer 32(n- The drift region 2) is maintained.

[0056] The second trench 5 is p + Even when the n-type regions 3 are formed after the n-type regions 3 are formed, the n-type regions 3 are formed on the first to fifth n-type surfaces 2a to 2e. - The second n-type drift region 2 is exposed. - 2) and the second p-type surface 3b (p + The step 42 formed by the first trench 4 due to the height difference with the upper surface of the mold region 3 is entirely n by the second trench 5. + The cathode region 1 is moved to a lower position, and the n - p type drift region 2 + This is because the contact surface (interface) with the type region 3 is exposed as a fifth n-type surface 2e that connects the second n-type surface 2b and the second p-type surface 3b.

[0057] The second trench 5 is p + Even when the first to third p-type surfaces 3a to 3c are formed after the formation of the p-type region 3, + The mold region 3 is exposed. + A step 52 is formed on the upper surface of the p-type region 3 (the bottom surface of the first trench 4) due to the difference in height between the first and second p-type surfaces 3a and 3b by the second trench 5. The bottom surface of the second trench 5 (the second p-type surface 3b) is p + Since the depth position is shallower on the front surface side of the semiconductor wafer 60 than the lower surface of the mold region 3, p + The side wall (third p-type surface 3c) of the second trench 5 on the upper surface of the p-type region 3 + This is because the mold area 3 is exposed.

[0058] Next, as shown in Fig. 14, the remaining portion of the oxide film 61 is removed. Then, as shown in Fig. 15, a Schottky electrode 11 is formed on the front surface of the semiconductor wafer 60 by a general method through a silicide reaction with the semiconductor wafer 60. The Schottky electrode 11 is a nickel silicide (NixSiy, where x and y are positive numbers) film formed by reacting, for example, Ni in a nickel (Ni) film formed on the front surface of the semiconductor wafer 60 and along the inner walls of the first and second trenches 4 and 5 with SiC in the semiconductor wafer 60 through heat treatment.

[0059] The heat treatment for silicidation of the Schottky electrode 11 also serves as a heat treatment for activating the p-type impurity ions implanted 65 into the semiconductor wafer 60. The heat treatment for activating the impurity ions implanted into the semiconductor wafer 60 (activation annealing) may be performed at a different time from the heat treatment for silicidation of the Schottky electrode 11. The impurity in SiC has a small diffusion coefficient and hardly diffuses. Therefore, even after activation annealing, the p + The depth of the type region 3 becomes slightly deeper, and the sidewall of the first trench 4 remains n-type.

[0060] Next, buried electrode 12 is formed on Schottky electrode 11 so as to fill the first and second trenches 4, 5, and surface electrode 13 is formed on buried electrode 12, thereby forming anode electrode 14 which is formed by sequentially stacking Schottky electrode 11, buried electrode 12, and surface electrode 13. Cathode electrode 15 is formed on the back surface of semiconductor wafer 60. Thereafter, the effective region of semiconductor wafer 60 is diced (cut) to separate it into individual semiconductor chips (semiconductor substrates 10), thereby completing the SiC-SBD with the JBS structure shown in FIGS. 1 to 5.

[0061] As described above, according to the first embodiment, a JBS structure in which a Schottky junction and a pn junction are mixed and a pn junction forming a pn junction of the JBS structure are provided on the front surface side of a semiconductor substrate. + The semiconductor device includes a first trench formed by overetching during the formation of an ion implantation mask for forming a type region, and a second trench formed intentionally. The SBD formed by the Schottky junction and the pn junction diode formed by the pn junction are disposed adjacent to each other and extend in a direction parallel to the front surface of the semiconductor substrate. The second trench is a pn junction that forms the pn junction of the JBS structure. + The p at a depth shallower than the type region + The first and second trenches are provided in a stripe shape intersecting the mold region and intersecting the SBD and the pn junction diode. The first and second trenches form three or more steps having different height differences that are repeatedly arranged in a predetermined pattern on the front surface of the semiconductor substrate.

[0062] The step caused by the first and second trenches causes the n - The exposed surface area of ​​the n-type drift region increases. - The contact area between the type drift region and the Schottky electrode (area of ​​the Schottky junction) is increased. For example, when forming second trenches with a depth and bottom width of 0.4 μm and 0.5 μm at a pitch of 0.5 μm, the area of ​​the Schottky junction is expanded by 1.8 times or more compared to the case where there is no unevenness due to the trenches on the front surface of the semiconductor substrate. This reduces the internal resistance of the SBD, and therefore reduces the conduction loss of the SBD if the chip size is maintained. If the conduction loss of the SBD is maintained, the chip size can be reduced, and the number of semiconductor chips that can be produced from one semiconductor wafer increases, resulting in cost reduction.

[0063] (Embodiment 2) The structure of the semiconductor device according to the second embodiment will be described. Figures 16 to 19 are cross-sectional views showing the structure of the semiconductor device according to the second embodiment. The reference characters 1, 2, 2a to 2e, 3, 3a to 3c, 4, 5, and 10 to 15 in Figure 1 are replaced with the reference characters 81, 82, 82a to 82e, 83, 83a to 83c, 84, 85, and 70 to 75, respectively, and + 16 to 19 respectively show cross-sectional structures along cut lines A-A', B-B', C-C', and D-D' in a structure in which the width of mold region 83 is wider than the width of first trench 84. In Figures 16 and 19, the height position of first surface 82a on the front surface of semiconductor substrate 70 is indicated by a dashed line.

[0064] A semiconductor device 80 according to the second embodiment is a semiconductor device 20 (see FIGS. 1 to 5) according to the first embodiment applied to a Si-SBD having a JBS structure using silicon (Si) as a semiconductor material. In the second embodiment, the diffusion coefficient of impurities in Si is larger than that in SiC, so that the p + The width of the mold region 83 is +The width of the first trench 84 is wider than the width of the first trench 84 which is formed secondarily by overetching during the formation of the mold region 83 .

[0065] The semiconductor substrate 70 is made of Si. - The semiconductor substrate 70 is a bulk single crystal substrate of the type. The front surface side of the semiconductor substrate 70 is provided with p + The semiconductor substrate 70 is provided with a type region 83, first and second trenches 84 and 85 that form steps 41, 42, 51 and 52 on the front surface side of the semiconductor substrate 70, and a Schottky electrode 71, a buried electrode 72 and a front surface electrode 73 that constitute an anode electrode 74. + A mold cathode region 81 and a cathode electrode 75 are provided.

[0066] n + The cathode region 81 is connected to the rear surface of the semiconductor substrate 70 and - The n-type drift region 82 is provided between the n-type drift region 82 and the n-type drift region 82. + The structure of the n-type cathode region 81 is the same as that of the first embodiment, except that it is a diffusion region formed by ion implantation. + The structure of the anode electrode 74 (Schottky electrode 71, buried electrode 72, and surface electrode 73) and the structure of the cathode electrode 75 are similar to those of the anode electrode 14 (Schottky electrode 11, buried electrode 12, and surface electrode 13) and the cathode electrode 15 of the first embodiment, respectively.

[0067] n - Of the n-type semiconductor substrate 70, + type cathode region 81 and p + The part excluding the mold region 83 is n - The drift region 82 is a p + The type region 83 is connected to the inner wall (side wall and bottom surface) of the first trench 84 and the n-type region 84. - Between the n-type drift region 82, - The first trench 84 is provided on the entire inner wall of the first trench 84. + The mold area 83 is exposed. +The structure of the mold region 83 is the same as that of the first embodiment except that it is exposed to the entire inner wall of the first trench 84. + Similar to type region 3.

[0068] The first and second trenches 84 and 85 are formed in the same manner as the first and second trenches 4 and 5 in the first embodiment. The configurations of the steps 41, 42, 51, and 52 on the front surface of the semiconductor substrate 70 formed by the first and second trenches 84 and 85 are similar to the steps 41, 42, 51, and 52 on the front surface of the semiconductor substrate 10 in the first embodiment. In the second embodiment, the steps 41, 42, 51, and 52 form p + The exposed surface of the p-type region 83 is increased to form a Schottky electrode 71 and + The contact area with the mold region 83 is increased.

[0069] Specifically, the first trench 84 is p + The pattern is the same as the mask opening pattern due to overetching during the formation of the ion implantation mask used to form the mold region 83. + It is formed in the same pattern as the mold region 83. + The width of the mold region 83 is increased by impurity diffusion during the subsequent activation annealing, and the width of the mold region 83 is increased by first to third surfaces 82a to 82c (described later) along the inner wall of the first trench 84 (the second trench 85). + If it is formed after the formation of the mold region 83, it will reach the front surface of the semiconductor substrate 70. + The mold region 83 covers the entire inner wall of the first trench 84. - The mold drift region 82 is not exposed.

[0070] Each of the first trenches 84 provides n - The upper surfaces (hereinafter referred to as first and second surfaces) 82a and 82b of the drift region 82 are + The upper surfaces (first and second p-type surfaces) 83a and 83b of the type region 83 are n + A plurality of lowered steps 41, 42 are formed on the side of the mold cathode region 81 (FIGS. 17 and 16). +The mold region 83 extends to the first and second faces 82a and 82b via the steps 41 and 42. - A step 51 is formed between the first and second faces 82a and 82b adjacent to each other in the second direction Y (the longitudinal direction of the mold drift region 82). + A step 52 is formed between the first and second p-type surfaces 83a and 83b adjacent to each other in the longitudinal direction of the mold region 83.

[0071] The first surface 82a and the first p-type surface 83a are alternately and repeatedly arranged with steps 41 interposed therebetween in the longitudinal direction of the second trench 85. A fourth p-type surface 83d (a sidewall of the first trench 4) connecting the first surface 82a and the first p-type surface 83a has a p + The second surface 82b and the second p-type surface 83b are alternately and repeatedly arranged with steps 42 interposed therebetween in the longitudinal direction of the second trench 85. A fifth p-type surface 83e (a sidewall of the first trench 4) connecting the second surface 82b and the second p-type surface 83b has a p + The mold region 83 is exposed. The steps 41 and 42 are simultaneously formed by the first trench 84 and have the same height difference. The steps 41 and 42 are continuous with each other in the second direction Y.

[0072] The second trench 85 is a p-type trench that configures a JBS structure, similar to the second trench 5 of the first embodiment. + The second trenches 85 are provided in a stripe shape intersecting the mold region 83. The second trenches 85 form a n-type trench on the front surface of the semiconductor substrate 70, with the second surface 82b closer to the n-type trench than the first surface 82a. + A plurality of steps 51 are formed on the side of the cathode region 81 (FIG. 18). The first surface 82a and the second surface 82b are alternately and repeatedly arranged with the steps 51 interposed therebetween in the second direction Y. The first and second surfaces 82a and 82b and the third surface 82c (the sidewall of the second trench 85) connecting the first surface 82a and the second surface 82b are provided with n - The p-type drift region 82 is exposed. + The mold area 83 is exposed.

[0073] In addition, the second trenches 85 form a second p-type surface 83b closer to the front surface of the semiconductor substrate 70 than the first p-type surface 83a. +A plurality of steps 52 are formed on the side of the p-type cathode region 81 (FIG. 19). The first p-type surface 83a and the second p-type surface 83b are alternately and repeatedly arranged in the second direction Y with the steps 52 interposed therebetween. The third p-type surface 83c (the side wall of the second trench 5) connecting the first p-type surface 83a and the second p-type surface 83b has a p + The mold region 83 is exposed. The steps 51, 52 are formed at the same time and have the same height difference. The steps 51, 52 intersect the steps 41, 42 and are continuous with each other in the longitudinal direction of the second trench 85 (the first direction X in FIGS. 16 to 19).

[0074] In this manner, the first and second trenches 84 and 85 form a p + The exposed surface of the p-type region 83 increases. On the front surface side of the semiconductor substrate 70, the first surface 82a where neither the first nor the second trenches 84, 85 exist is at the highest height position. The second p-type surfaces 83b at the intersections of the first trench 84 and the second trench 85 are lower by the total depth of the first and second trenches 84, 85 formed at different times, and are at the lowest height position. The second surface 82b at the bottom surface of the second trench 85 and the first p-type surface 83a at the bottom surface of the first trench 84 may be at the same height position.

[0075] The method for manufacturing the semiconductor device 80 according to the second embodiment is to - The method is the same as that for manufacturing the semiconductor device 20 according to the first embodiment (see Figs. 8 to 12), except that the mold bulk single crystal wafer itself is used as the semiconductor wafer 60 which becomes the semiconductor substrate 70, and that the impurity diffusion in the activation annealing is wider. Figs. 20 and 21 are cross-sectional views showing the semiconductor device according to the second embodiment in the middle of its manufacture. Figs. 20 and 21 show a cross section corresponding to Fig. 17.

[0076] First, similarly to the first embodiment, an alignment mark (not shown) and a second trench 85 (see FIGS. 18 and 19) are formed on the front surface of a semiconductor wafer 60 made of Si by photolithography and etching. + Bulk single crystal wafers of type (n +The front surface of the cathode region 81) is - Type epitaxial layer (n - The semiconductor wafer may have a type drift region 82) epitaxially grown thereon.

[0077] Next, as shown in FIG. 20, similarly to the first embodiment, p + An oxide film 61 is formed with an opening in a portion corresponding to a region for forming a mold region 83. Over-etching during the formation of the oxide film 61 forms steps 41, 42, 51, 52 with different height differences due to the first and second trenches 84, 85 on the front surface of the semiconductor wafer 60.

[0078] Next, in the same manner as in the first embodiment, p-type impurities are ion-implanted 65 using the remaining portion of the oxide film 61 as a mask, so that p-type impurities are implanted into the surface region of the bottom surface (first to third p-type surfaces 83a to 83c) of the first trench 84. + 21, after removing the remaining portion of the oxide film 61, a Schottky electrode 71 is formed on the front surface of the semiconductor wafer 60 by a silicide reaction with the semiconductor wafer 60, similarly to the first embodiment.

[0079] The heat treatment for silicidation of the Schottky electrode 71 also serves as a heat treatment for activating the p-type impurity ion-implanted 65 into the semiconductor wafer 60, as in the first embodiment. Impurities in Si are more likely to diffuse than in SiC, and this heat treatment causes the impurities to diffuse radially from the bottom surface of the first trench 84 into the semiconductor wafer 60, activating the p + The inner wall of the first trench 4 is entirely covered with the type region 83 (the fourth and fifth p-type surfaces 83d and 83e).

[0080] Next, in the same manner as in the first embodiment, a buried electrode 72 and a surface electrode 73 are formed on the Schottky electrode 71, thereby forming an anode electrode 74. +A mold cathode region 81 and a cathode electrode 75 are formed. Thereafter, the effective region of the semiconductor wafer 60 is diced into individual semiconductor chips (semiconductor substrates 70), thereby completing the SiC-SBD with the JBS structure shown in FIGS.

[0081] As described above, according to the second embodiment, by applying the first embodiment to an SBD having a JBS structure in which Si is used as a semiconductor material, it is possible to obtain a p + Since the exposed surface area of ​​the type region is increased, the p + The contact area between the type region and the Schottky electrode is increased. Therefore, if the chip size is maintained, the allowable current of the pn junction diode is increased, and the withstand current against a large current exceeding the rated current is improved. If the allowable current of the pn junction diode is maintained, the chip size can be reduced, and the number of semiconductor chips that can be manufactured from one semiconductor wafer increases, resulting in cost reduction. Furthermore, according to the second embodiment, the pn junction forming the pn junction of the JBS structure is + Since the type region surrounds the entire inner wall of the first trench, the area of ​​the pn junction increases, thereby enhancing the effect of suppressing leakage current during reverse bias.

[0082] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0083] INDUSTRIAL APPLICABILITY As described above, the semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines, and is particularly suitable when SiC is used as the semiconductor material. [Explanation of symbols]

[0084] 1,81,101 n + Type cathode area 2,82,102 n - Type Drift Region 2a, 2b, 2c, 2d, 2e 1st to 5th n-type surfaces of the front surface of the semiconductor substrate 3,83,103 p + type area 3a, 3b, 3c: first to third p-type surfaces on the front surface of a semiconductor substrate 4,84 First Trench 5,85 Second Trench 10,70,110 Semiconductor substrate 11,71,111 Schottky electrode 12,72 Buried electrodes 13,73 surface electrode 14,74,114 Anode electrode 15,75,115 Cathode electrode 20,80,120 Semiconductor devices 21,121 Schottky junction area 22,122 pn junction area 31 n + Starting substrate 32n - Type epitaxial layer 41, 42, 51, 52 Steps on the front surface of the semiconductor substrate 60 Semiconductor Wafers 61 Oxide Film 61a Opening in oxide film 62 Resist film 62a Opening in resist film 63 Mask (reticle) 64 Light from a specified light source of an exposure device 65 Ion Implantation 82a, 82b, 82c: first to third surfaces of the front surface of the semiconductor substrate 83a, 83b, 83c, 83d, 83e First to fifth p-type surfaces of the front surface of the semiconductor substrate 104 Trench X: A first direction parallel to the front surface of the semiconductor substrate XY1,XY2 p + Diagonal crossing direction to the mold area Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction X. Z depth direction

Claims

1. a semiconductor substrate of a first conductivity type; a second conductivity type region selectively provided on a first main surface of the semiconductor substrate and extending in a direction parallel to the first main surface; a first conductivity type region that is a portion of the semiconductor substrate excluding the second conductivity type region and that extends along the second conductivity type region in a direction parallel to the first main surface; a first electrode provided on the first main surface, forming a Schottky junction with the first conductivity type region and contacting the second conductivity type region at the first main surface; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with On the first main surface, a first step that makes a height position of a contact surface between the first electrode and the second conductivity type region lower than a height position of a contact surface between the first electrode and the first conductivity type region; a second step that intersects with the first step and has a height difference in a longitudinal direction of the first conductivity type region to partially lower a height position of a contact surface between the first electrode and the first conductivity type region; a third step that intersects the first step, is continuous with the second step, and has a height difference in the longitudinal direction of the second conductivity type region to partially lower the height position of the contact surface between the first electrode and the second conductivity type region.

2. a first trench provided in the first main surface, extending along the second conductivity type region in a direction parallel to the first main surface, and having a bottom surface surrounded by the second conductivity type region; a second trench provided in the first main surface so as to intersect with the first conductivity type region and the second conductivity type region, the second trench having a bottom surface selectively surrounded by the first conductivity type region and the second conductivity type region, Equipped with The first step is formed by the first trench.

2. The semiconductor device according to claim 1, wherein the second step and the third step are formed by the second trench.

3. a semiconductor substrate of a first conductivity type; a first trench provided in a first main surface of the semiconductor substrate and extending in a direction parallel to the first main surface; a second conductivity type region selectively provided in the semiconductor substrate, extending along the first trench in a direction parallel to the first main surface, and surrounding a bottom surface of the first trench; a first conductivity type region that is a portion of the semiconductor substrate excluding the second conductivity type region and that extends along the second conductivity type region in a direction parallel to the first main surface; a second trench provided in the first main surface so as to intersect with the first conductivity type region and the second conductivity type region, the second trench having a bottom surface selectively surrounded by the first conductivity type region and the second conductivity type region, a first electrode provided on the first main surface, embedded in the first trench and the second trench, forming a Schottky junction with the first conductivity type region, and in contact with the second conductivity type region; a second electrode provided on a second main surface of the semiconductor substrate; A semiconductor device comprising:

4. 4. The semiconductor device according to claim 2, wherein the second conductivity type region is deeper toward the second main surface than the bottom surface of the second trench at least in a portion facing the second trench in the depth direction.

5. 5. The semiconductor device according to claim 4, wherein the second conductivity type region has a uniform depth from the first main surface.

6. 4. The semiconductor device according to claim 2, wherein a bottom surface of the second trench is located deeper toward the second main surface than a bottom surface of the first trench.

7. the second conductivity type region extends in a stripe shape in a direction parallel to the first main surface, the second trench extends in a stripe shape intersecting the first conductivity type region and the second conductivity type region; 4. The semiconductor device according to claim 2, wherein the width of the second trench is narrower than an interval between the second conductivity type regions.

8. 4. The semiconductor device according to claim 2, wherein the second conductivity type region surrounds an entire inner wall of the first trench.

9. The first electrode is a first metal layer provided along the first main surface, an inner wall of the first trench, and an inner wall of the second trench, forming a Schottky junction with the first conductivity type region, and in contact with the second conductivity type region; 4. The semiconductor device according to claim 2, further comprising: a second metal layer provided on the first metal layer inside the first trench and inside the second trench, and filling the first trench and the second trench.

10. 10. The semiconductor device according to claim 9, wherein the second metal layer is made of titanium nitride or tungsten.

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