Single chamber flowable film formation and processing

Abstract

To provide an improved semiconductor system and processing method that can be used to manufacture a high quality device and structure.SOLUTION: In a semiconductor processing system, a process chamber 200 includes a chamber body 205, a pedestal (substrate support 210) that supports a semiconductor substrate, a face 215 that defines a processing volume together with the chamber body and the pedestal, a high frequency plasma source (first plasma power source 220) connected to the faceplate, and a low frequency plasma source (second plasma power source 230) connected to the pedestal, and the low frequency plasma source operates at a pulse frequency of about 1 kHz or less.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 17 / 014,224, entitled "SINGLE CHAMBER FLOWABLE FILM FORMATION AND TREATMENTS," filed Sep. 8, 2020, the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology is related to the following applications, all filed simultaneously on September 8, 2020, entitled "SEMICONDUCTOR PROCESSING CHAMBERS FOR DEPOSITION AND ETCH," Attorney Docket No. 44018254US01 (1192137), and "SEMICONDUCTOR PROCESSING CHAMBERS FOR DEPOSITION AND ETCH," Attorney Docket No. 44018155US01 (1190407), each of which is incorporated by reference in its entirety for all purposes. [Background technology]

[0003]

[0003] The present technology relates to semiconductor processing, and more particularly, to systems and methods for depositing and processing materials, including flowable films.

[0004]

[0004] Integrated circuits are made possible by processes that produce intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods of forming and removing exposed materials. As devices become smaller, material formation can impact subsequent operations. For example, in gap-fill operations, material can be formed or deposited to fill trenches or other features formed on a semiconductor substrate. These fill operations can be challenging because the features can be characterized by high aspect ratios and reduced critical dimensions. For example, deposition can occur on top of and along the sidewalls of the features, so continued deposition can pinch off the feature, including between the sidewalls within the feature, creating voids within the feature. This can impact device performance and subsequent processing operations.

[0005]

[0005] Thus, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. These and other needs are addressed by the present technique. Summary of the Invention

[0006] An exemplary processing method may include forming a plasma of a silicon-containing precursor. The method may include depositing a flowable film on a semiconductor substrate using plasma effluents of the silicon-containing precursor. The semiconductor substrate may be contained in a processing region of a semiconductor processing chamber. The semiconductor substrate may define features in the semiconductor substrate. The processing region may be defined at least in part between a faceplate and a substrate support on which the semiconductor substrate rests. The method may include forming a processing plasma within the processing region of the semiconductor processing chamber. The processing plasma may be formed at a first power level from a first power source. A second power may be applied to the substrate support from a second power source at a second power level. The method may include densifying the flowable film within features defined within the semiconductor substrate using plasma effluents of the processing plasma.

[0007] In some embodiments, the semiconductor processing chamber can be part of a semiconductor processing system. The system can include a chamber body. The system can include a pedestal configured to support a semiconductor substrate. The system can include a faceplate. The chamber body, pedestal, and faceplate can define a processing region. The system can include a high frequency plasma source coupled to the faceplate. The high frequency plasma source can be a first power source. The system can include a low frequency plasma source coupled to the pedestal. The low frequency plasma source can be a second power source. The system can include a first LC filter coupled to the pedestal and configured to virtually ground the high frequency plasma source through the pedestal. The system can include a second LC filter coupled to the faceplate and configured to virtually ground the low frequency plasma source to the chamber body.

[0008] The second power supply may be operated in a pulsed mode at a pulse frequency of about 1 kHz or less. The first power supply may be operated in a continuous wave mode during the treatment plasma, while the second power supply is operated in a pulsed mode. The second power supply may be operated at a duty cycle of about 50% or less. The first power supply may be operated to generate a power spike within a first period during deposition. Following the first period, the first power supply may be operated for a second period during deposition. The first period may be about 1 second or less, and the second period may be about 1 second or more. The first power supply may be operated at a pulse frequency of about 200 kHz or less at a duty cycle of about 20% or less to generate an effective plasma power of about 10 W or less. The method may be repeated for a second cycle. The temperature of the semiconductor substrate may be maintained at a temperature of about 0° C. or less during the method.

[0009] Some embodiments of the present technology may include a semiconductor processing system. The system may include a chamber body. The system may include a pedestal configured to support a semiconductor substrate. The system may include a faceplate. The chamber body, the pedestal, and the faceplate may define a processing region. The system may include a high frequency plasma source coupled to the faceplate. The system may include a low frequency plasma source coupled to the pedestal.

[0010] In some embodiments, the pedestal may include an electrostatic chuck. The semiconductor processing system may include a DC power source connected to the pedestal. The low frequency plasma source may be configured to operate at about 2 MHz or less. The high frequency plasma source may be configured to operate at about 13.56 MHz or greater at a pulsed frequency of about 200 kHz or less. The high frequency plasma source may be configured to operate at about 20 kHz or less or a pulsed frequency at a duty cycle of about 20% or less. The high frequency plasma source may be configured to generate plasma at an effective power of about 5 W or less. The system may include a first LC filter connected to the pedestal and configured to substantially ground the high frequency plasma source through the pedestal. The system may include a second LC filter connected to the faceplate and configured to substantially ground the low frequency plasma source to the chamber body.

[0011]

[0011] Such techniques may provide numerous advantages over conventional systems and techniques. For example, by performing a curing or treatment step inside the deposition chamber, throughput may be increased while limiting or controlling sidewall coverage and limiting void formation in small features. In addition, by performing deposition according to embodiments of the present technique, repeatable plasma generation may be achieved during the deposition process. These and other embodiments, together with their many advantages and features, are described in more detail in conjunction with the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed techniques may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 2]

[0014] 1 shows a schematic partial cross-sectional view of a chamber in accordance with some embodiments of the present technique; [Diagram 3]

[0015] 1 illustrates exemplary steps in a processing method according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014]

[0016] Some figures are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0015]

[0017] In the accompanying drawings, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished according to the reference numbers, with a letter distinguishing between the similar components. If only a first reference number is used in this specification, the description is applicable to any one of the similar components having the same first reference number, regardless of the letter.

[0016]

[0018] Amorphous silicon may be used in semiconductor device fabrication for many structures and processes, including as a sacrificial material, e.g., as a dummy gate material, or as a trench fill material. In gap-filling steps, some processes utilize a flowable film formed under process conditions to limit the conformality of the deposition, allowing the deposited material to better fill features on the substrate. Flowable silicon materials may be characterized by a relatively high amount of hydrogen and may be less dense than other formed films. As a result, subsequent processing steps may be performed to harden the resulting film. Conventional techniques may utilize a UV curing process to remove hydrogen and treat the film. However, UV curing may cause significant film shrinkage, which may create voids in the structure as well as stress the features. In addition, the processing is performed in a separate chamber from the deposition chamber, which increases processing time and reduces throughput.

[0017]

[0019] As feature sizes continue to shrink, flowable films can be a challenge for narrow features that may be further characterized by higher aspect ratios. For example, deposition on the sidewalls of the feature may more easily result in pinching of the feature, and smaller feature sizes may further restrict further flow into the feature, resulting in voids. Some conventional flowable film formation may be performed by generating radicals in a remote capacitively coupled plasma region or a remote plasma source unit connected to the chamber. However, for cyclical formation of high aspect ratio features, this process may provide unreliable deposition. For example, as radicals pass through chamber parts such as the faceplate, recombination may cause problems with consistent delivery of radical effluent. In addition, remote plasma sources may not be able to limit the amount of deposition in small pitch features. This may result in excessive deposition in the feature, limiting or preventing complete penetration of processing effluent. This may cause damage during subsequent processing and may result in scrapping of the substrate.

[0018]

[0020] The present technology overcomes these limitations by separating high and low frequency power sources and utilizing triggering sequences that can perform short periods of repeatable plasma generation at low power. This can limit deposition during trench filling to tightly controlled amounts as well as ensure complete processing during subsequent processing steps. After describing general aspects of chambers according to some embodiments of the present technology in which the plasma processing steps described below may be performed, specific chamber configurations and methods may be described. It is understood that the technology is not intended to be limited to the specific films, chambers, or processes described, as the techniques described may be used to improve numerous film formation processes for any number of materials and may be applicable to a variety of processing chambers and steps.

[0019]

[0021] FIG. 1 illustrates a cross-sectional view of an exemplary processing chamber 100 according to some embodiments of the present technique. The diagram may provide an overview of a system incorporating one or more aspects of the present technique and / or that may perform one or more deposition or other processing steps according to embodiments of the present technique. Additional details of the chamber 100 or the method performed may be further described below. Although the chamber 100 may be utilized to form a film layer according to some embodiments of the present technique, it should be understood that the method may similarly be performed in any chamber in which film formation may occur. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and confining the substrate support 104 within a processing space 120. A substrate 103 may be provided to the processing space 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may be located on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by arrow 145, along an axis 147 about which the shaft 144 of the substrate support 104 may lie. Alternatively, the substrate support 104 may be elevated for rotation as needed during the deposition process.

[0020]

[0022] A plasma profile modulator 111 may be disposed in the process chamber 100 to control plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile modulator 111 includes a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop along the periphery of the process chamber 100 surrounding the process space 120 or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as a secondary gas distributor, for example.

[0021]

[0023] The one or more isolators 110a, 110b may be a dielectric material such as ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be connected to a processing chamber. In some embodiments, the first power source 142 may be an RF power source.

[0022]

[0024] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive, but the face plate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be connected to ground in some embodiments.

[0023]

[0025] The first electrode 108 may be connected to a first tuned circuit 128 that may control a ground path of the process chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or may include a variable capacitor or other circuit element. The first tuned circuit 128 may be or may include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under plasma conditions present in the process space 120 during processing. In some illustrated embodiments, the first tuned circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. The second inductor 132B can be disposed between the first electronic controller 134 and a node coupling both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 can be a voltage sensor or a current sensor and can be connected to the first electronic controller 134 to allow some closed-loop control of the plasma conditions inside the process space 120.

[0024]

[0026] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be incorporated into the substrate support 104 or may be connected to a surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed configuration of conductive elements. The second electrode 122 may be a tuning electrode and may be connected to a second tuning circuit 136, for example, by a conduit 146 (e.g., a cable having a selected resistance, such as 50 ohms) disposed in a shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138, a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the process space 120.

[0025]

[0027] A third electrode 124, which may be a bias electrode and / or an electrostatic chucking electrode, may be connected to the substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, a pulsed RF source or bias power, or a combination of these or other sources. In some embodiments, the second power source 150 may be RF bias power.

[0026]

[0028] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber 100 may perform real-time control of plasma conditions within the processing space 120. The substrate 103 may be placed on the substrate support 104, and process gases may flow through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may be exhausted from the processing chamber 100 through the outlet 152. Power may be connected to the gas distributor 112 to establish a plasma within the processing space 120. In some embodiments, the substrate may be subjected to an electrical bias using the third electrode 124.

[0027]

[0029] Upon exciting a plasma in the process space 120, a potential difference may be established between the plasma and the first electrode 108. A potential difference may also be established between the plasma and the second electrode 122. The electronic controllers 134 and 140 may then be used to adjust the flow characteristics of the ground paths represented by the two tuned circuits 128 and 136. Set points may be provided to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of the deposition rate and center-to-edge plasma density uniformity. In an embodiment in which both electronic controllers may be variable capacitors, the electronic sensors may independently adjust the variable capacitors to maximize the deposition rate and minimize the thickness non-uniformity.

[0028]

[0030] Each of the tuning circuits 128 and 136 may have a variable impedance that may be adjusted using the respective electronic controllers 134 and 140. If the electronic controllers 134, 140 are variable capacitors, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum, the impedance of the first tuning circuit 128 may be high. This results in a plasma shape that has a minimum aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 reaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum, thus effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls, reducing the aerial coverage of the substrate support. The second electronic controller 140 may have a similar effect, so that as the capacitance of the second electronic controller 140 changes, the aerial coverage of the plasma above the substrate support increases or decreases.

[0029]

[0031] Electronic sensors 130 and 138 may be used to tune the respective circuits 128, 136 in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be attached to each sensor. The sensors may be provided with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the shape of the plasma may be selected and dynamically controlled during processing. Although the above description is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic components having adjustable characteristics may be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0030]

[0032] 2 illustrates a schematic partial cross-sectional view of a processing chamber 200 in accordance with some embodiments of the present technique. The chamber 200 may include any of the features, components, or characteristics of the processing chamber 100 described above, and may exhibit additional features of the chamber, including certain power sources in communication with the chamber. For example, the chamber 200 may include a chamber body 205. The chamber may include a substrate support 210, which may be configured to support a substrate during semiconductor processing. The chamber may include a faceplate 215, which, together with a pedestal and the chamber body, may define a processing region above a substrate during processing.

[0031]

[0033] Some conventional processing systems may generate a plasma within the processing region by applying power to the faceplate while grounding the pedestal, or by applying source power to the pedestal and grounding the faceplate. In some systems, an additional bias power may be connected to the pedestal to enhance directionality of the plasma effluents. It should be understood that a separate DC power supply for electrostatic chucking may be connected to the pedestal and operated to further bias the plasma generated within the processing chamber in addition to chucking the substrate, as described above with respect to the processing chamber 100. The present technique may differ from conventional configurations by connecting two separate plasma power sources to the showerhead and pedestal as shown. For example, a first plasma power source 220 may be connected to the showerhead and a second plasma power source 230 may be connected to the pedestal. In some embodiments, the first plasma power source 220 may be a high frequency plasma power source and the second plasma power source 230 may be a low frequency plasma power source. In some embodiments, the low frequency plasma power supply 230 is separate from the DC power supply, which may be used to electrostatically couple the substrate to the pedestal.

[0032]

[0034] The low frequency plasma power source operates at a first frequency that is about 2 MHz or less, and may operate at about 1.5 MHz or less, about 1.0 MHz or less, about 800 kHz or less, about 600 kHz or less, about 500 kHz or less, about 400 kHz or less, about 350 kHz or less, about 300 kHz or less, about 250 kHz or less, about 200 kHz or less, or less. The high frequency plasma power source operates at a second frequency that is about 2 MHz or more, and may be about 10 MHz or more, about 13 MHz or more (such as about 13.56 MHz), about 15 MHz or more, about 20 MHz or more, about 40 MHz or more, or more.

[0033]

[0035] Additional aspects of the plasma source may be used to further tailor the plasma generated within the processing region. For example, chambers according to embodiments of the present technology may be used to fill high aspect ratio features, where a discreet amount of deposition may be produced to limit void formation within the features being filled. Conventional chambers may be limited in reducing plasma power based on an inability to generate repeatable low power plasma for a limited period of time. The present technology may be used to produce material layers characterized by thicknesses of about 10 nm or less per cycle. To achieve this limited deposition, either the deposition period may be limited or the power used during deposition may be reduced. Conventional systems may not be able to reduce plasma power to about 100 W or less, which increases the amount of deposited material, and shortening the formation period to accommodate this higher power may limit the ability to generate reproducible plasma during multiple cycles of deposition.

[0034]

[0036] The present technology overcomes these problems by generating a low power deposition plasma, which is characterized by an effective plasma power of about 20 W or less, and may be characterized by an effective plasma power of about 15 W or less, about 10 W or less, about 8 W or less, about 6 W or less, about 5 W or less, about 4 W or less, about 3 W or less, or less. To generate this low power plasma during the deposition process, the system may operate a high frequency plasma power at a pulse frequency of about 200 kHz or less, and operate the plasma power at a pulse frequency of about 150 kHz or less, about 100 kHz or less, about 80 kHz or less, about 70 kHz or less, about 60 kHz or less, about 50 kHz or less, about 40 kHz or less, about 30 kHz or less, about 20 kHz or less, about 10 kHz or less, or less. Additionally, at any of the listed pulse frequencies, the radio frequency plasma power source can be operated at a reduced duty cycle of about 50% or less, about 45% or less, about 40% or less, about 35% or less, about 30% or less, about 25% or less, about 20% or less, about 15% or less, about 10% or less, about 5% or less, or less than this.

[0035]

[0037] In some embodiments, the pulse frequency and duty cycle may be reduced to address plasma generation in a consistent manner. A low power plasma, once generated, may generate a slow deposition rate to limit deposition per cycle, but ignition may be problematic. Thus, in some embodiments, the plasma power may be operated in a trigger sequence to facilitate plasma generation during deposition. For example, as described above, in some embodiments, the deposition process may be performed without a low frequency plasma power source. However, in some embodiments, the low frequency plasma power source may be operated during the deposition process to facilitate ignition. In addition, the low frequency plasma power source may not be operated, and a power spike may be applied with the high frequency plasma power source to facilitate ignition. The power spike may be applied directly by the power management or through level-by-level operation of the high frequency plasma power source.

[0036]

[0038] The low frequency plasma power source may also operate to control the plasma formation and ion directionality during processing. By supplying low frequency plasma power through the pedestal, the plasma sheath formed by this powered electrode may benefit the directionality of ions to the features being densified. Although the low frequency plasma power source may operate at any of the power levels or pulse frequencies described above, in some embodiments, the second power source 230 may operate at a plasma power greater than the first power source 220 during processing steps. For example, the plasma power supplied by the second power source during processing may be about 50 W or more, about 100 W or more, about 200 W or more, about 300 W or more, about 400 W, about 500 W or more, about 600 W or more, about 700 W or more, about 800 W or more, or more. By increasing the plasma power of the low frequency power source during processing plasma formation, a greater amount of plasma effluent may be generated. By applying more low frequency power from the pedestal, the directionality of the supply perpendicular to the plane across the substrate may be increased.

[0037]

[0039] Additional adjustments can be made to further increase etching of the deposited material along the sidewalls of the feature by adjusting one or more characteristics of the supplied plasma power or bias power. For example, in some embodiments, both the plasma power source and the bias power source can be operated in a continuous wave mode. In addition, one or both of the power sources can be operated in a pulsed mode. In some embodiments, during processing, the high frequency source power can be operated in a continuous wave mode or a pulsed mode, while the low frequency power can be operated in a pulsed mode. The pulse frequency of the low frequency plasma power source can be about 1,000 Hz or less, and can be about 900 Hz or less, about 800 Hz or less, about 700 Hz or less, about 600 Hz or less, about 500 Hz or less, about 400 Hz or less, about 300 Hz or less, about 200 Hz or less, about 100 Hz or less, or less. The duty cycle of the second power source is about 50% or less, and the low frequency plasma power may be operated at a duty cycle of about 45% or less, about 40% or less, about 35% or less, about 30% or less, about 25% or less, about 20% or less, about 15% or less, about 10% or less, about 5%, or less. By operating the low frequency power at a reduced duty cycle, such as an on-time duty of about 50% or less, the longer time per cycle may result in a more isotropic etch in the feature based on the operation of the high frequency power source, which may allow for better removal of material from the sidewalls during the densification operation.

[0038]

[0040] The first plasma power source 220 may be connected to ground substantially through the pedestal. For example, as shown, a first LC filter 225 may be connected to the pedestal to substantially ground the high frequency plasma source through the pedestal. Similarly, the second plasma power source 230 may be connected to ground through the chamber. For example, a second LC filter may be connected to the faceplate, which may substantially ground the low frequency plasma source, such as the chamber body or an external ground. By separating the high frequency and low frequency power sources, improved plasma generation and operation may be provided.

[0039]

[0041] The processing chamber 100 and / or the processing chamber 200 may be utilized in some embodiments of the present technology for processing methods that may include forming, etching, or curing materials for semiconductor structures. The described chambers should not be considered limiting, and it should be understood that any chamber that may be configured to perform the operations as described may be used as well. FIG. 3 illustrates exemplary steps in a processing method 300 according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including the processing chamber 100 or the processing chamber 200 described above, and in one or more mainframes or tools. The method 300 may include several optional steps. These steps may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader scope of structure formation, but are not critical to the present technology or may be performed by alternative methodologies that will be readily understood.

[0040]

[0042] Method 300 may include additional steps prior to the initiation of the recited steps. For example, the additional processing steps may include forming structures on the semiconductor substrate, which may include both the formation and removal of materials. For example, transistor structures, memory structures, or any other structures may be formed. The prior processing steps may be performed in the chamber in which method 300 may be performed, or processing may be performed in one or more other processing chambers prior to providing a substrate to one or more semiconductor processing chambers in which method 300 may be performed. Nevertheless, method 300 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 200 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support, which may be a pedestal, such as substrate support 210, and may be present in a processing region of a chamber, such as processing space 120 described above.

[0041]

[0043] The substrate being processed may be or include any number of materials used in semiconductor processing. The substrate material may be or include silicon, germanium, a dielectric material including silicon oxide or silicon nitride, a metallic material, or any number of combinations of these materials, and may be a substrate or a material formed on a substrate. The features may be characterized by any shape or configuration according to the present technology. In some embodiments, the features may be or include trench structures or openings formed within the substrate. The features may be characterized by any shape or size, but in some embodiments, the features may be characterized by a higher aspect ratio, or the ratio of the depth of the feature to the width across the feature. For example, in some embodiments, the features may be characterized by an aspect ratio of about 5:1 or greater, and may be characterized by an aspect ratio of about 10:1 or greater, about 15:1 or greater, about 20:1 or greater, about 25:1 or greater, about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, or greater. Additionally, the feature may be characterized by a narrow width or diameter across the feature, including between two sidewalls, such as a dimension of about 20 nm or less, and may be characterized by a width across the feature of about 15 nm or less, about 12 nm or less, about 10 nm or less, about 9 nm or less, about 8 nm or less, about 7 nm or less, about 6 nm or less, less than about 5 nm or less, or less.

[0042]

[0044] In some embodiments, the method 300 may include optional processing steps, such as pre-processing, that may be performed to prepare the surface of the substrate for deposition. Once prepared, the method 300 may include supplying one or more precursors to a processing region of a semiconductor processing chamber that houses the structure. The precursors may include one or more silicon-containing precursors, as well as one or more diluents or carrier gases, such as inert gases or other gases, that are supplied with the silicon-containing precursors. Although the method is described in the context of producing a flowable silicon film, it should be understood that the described method and / or chamber may be used to produce any number of materials in accordance with embodiments of the present technology. At step 305, a plasma may be formed from the deposition precursors, including the silicon-containing precursors. The plasma may be formed in the processing region, which may allow a deposited material to be deposited on the substrate. For example, in some embodiments, a capacitively coupled plasma may be formed in the processing region by applying plasma power to a face plate as described above. For example, the radio frequency power source described above may be operated at a reduced effective plasma power to deposit material within features on the substrate.

[0043]

[0045] At step 310, a silicon-containing material may be deposited on the substrate from the plasma effluent of the silicon-containing precursor. The material may be a flowable silicon-containing material, in some embodiments, and may be or include amorphous silicon. The deposited material may at least partially flow into a feature on the substrate to provide bottom-up gap filling. As shown, the deposited material may flow to the bottom of the feature, although an amount of material may remain on the sidewalls of the substrate. Although the amount deposited may be relatively small, the material remaining on the sidewalls may limit subsequent flow.

[0044]

[0046] The power applied during deposition may be a low power plasma to limit dissociation and maintain hydrogen incorporation into the deposited material. This incorporation of hydrogen may contribute to the flowability of the deposited material. Thus, in some embodiments, the plasma power source may provide a plasma power of about 100 W or less to the faceplate, and may provide a power of about 90 W or less, about 80 W or less, about 70 W or less, about 60 W or less, about 50 W or less, or less. This power may be further attenuated by operating the high frequency power source at a pulse frequency and duty cycle as previously described to produce an effective power of about 10 W or less, or about 5 W or less, as described above.

[0045]

[0047] Following the deposition amount, in some embodiments of the present technology, a treatment or curing process configured to densify the formed material may be formed, advantageously cleaning or re-etching the material on the sidewalls of the feature. This process may be performed in the same chamber as the deposition and may be performed in a cyclic process to fill the feature. In some embodiments, the flow of the silicon-containing precursor may be stopped and the processing region may be purged. Following the purge, a processing precursor may be flowed into the processing region of the processing chamber. The processing precursor may be or may include hydrogen, helium, argon, or another inert material that may not chemically react with the film. In step 315, a processing plasma may be formed, which may also be a capacitively coupled plasma formed inside the processing region. The deposition plasma may be formed by applying a high frequency plasma power to a faceplate or showerhead, but in some embodiments may not include a separate power source engaged. The processing may utilize both a high frequency power source and a low frequency power source connected to the substrate support as described above. During processing, the high frequency power source may operate at a first power level and the low frequency power source may operate at a second power level. In embodiments of the present technology, the two power levels may be similar or different.

[0046]

[0048] The high frequency power source may be operated at a pulsed low effective power during deposition plasma, but in a continuous wave configuration during processing. This may be done at any of the plasma powers previously described. The low frequency power source may be operated in a pulsed mode during processing. This may be done at any of the pulse frequencies and / or duty cycles previously described.

[0047]

[0049] During the deposition steps, the low frequency power supply may not be operated. As described above, to allow repeatable plasma generation at low power, a trigger sequence may be utilized to ensure plasma generation during each deposition step. The trigger sequence may include a first period and a second period, which together form a deposition period. In some embodiments, to limit deposition, the deposition period may be about 30 seconds or less, about 20 seconds or less, about 15 seconds or less, about 10 seconds or less, about 8 seconds or less, about 6 seconds or less, about 5 seconds or less, about 4 seconds or less, or less. The first period may be shorter than the second period, and the first period may be used to ensure plasma generation while limiting the impact on the deposition process. Thus, in some embodiments, the first period of time is about 2 seconds or less, and can be about 1 second or less, about 0.5 seconds or less, about 0.4 seconds or less, about 0.3 seconds or less, about 0.2 seconds or less, about 0.1 seconds or less, about 0.09 seconds or less, about 0.08 seconds or less, about 0.07 seconds or less, about 0.06 seconds or less, about 0.05 seconds or less, or less.

[0048]

[0050] In some embodiments, a first power is applied by the high frequency power source during a first period, which can be higher than a second power applied by the high frequency power source during a second period. For example, during the first period, the first power can be about 50 W or more, about 80 W or more, about 100 W or more, about 120 W or more, about 140 W, about 160 W or more, about 180 W or more, about 200 W or more, or more. The high frequency power source can then apply power during a second period at any of the above-mentioned effective powers for the remainder of the deposition time. In addition, the high frequency power source can operate consistently during the deposition time, but during the first period, a low frequency power source can be applied at any of the power levels above to ensure ignition. In another example, the high frequency power source can operate in a multi-level pulse configuration during the first period before switching to the desired effective power during the second period. A multi-level pulse may include several pulses, each of which may be less than 0.1 seconds, and may occur during a first period of time, such as, for example, about 50 microseconds or less, about 40 microseconds or less, about 30 microseconds or less, about 20 microseconds or less, or less. The pulse may include a first pulse that is higher in a first fraction of the pulse, followed by a second pulse that is lower in a second fraction of the pulse. The two portions of the pulse may occur at any of the power levels discussed above.

[0049]

[0051] During the processing steps, the plasma effluents may optionally at least partially etch the flowable film and remove it from the sidewalls of the trench in step 320. Simultaneously, or in addition, the more directionally delivered plasma effluents may penetrate the remaining film formed at the bottom of the feature and reduce hydrogen uptake to densify the film in step 325.

[0050]

[0052] Although the deposits can be formed to a few nanometers or more, by performing the etching process as described above, the thickness of the densified material can be controlled to a thickness of about 100 Å or less, and can be about 90 Å or less, about 80 Å or less, about 70 Å or less, about 60 Å or less, about 50 Å or less, about 40 Å or less, about 30 Å or less, about 20 Å or less, about 10 Å or less, or less. By controlling the thickness of the deposited material, conversion through the entire thickness can be more easily performed and can solve penetration issues common to conventional processes. This process can then be repeated in any number of complete cycles to continue to generate densified material down to the feature.

[0051]

[0053] With regard to the deposition precursors used during any of the formation steps, any number of precursors may be used in the present technology. Silicon-containing precursors that may be used may include, but are not limited to, silane (SiH4), disilane (Si2H6), or other organosilanes, including cyclohexasilane, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), and other silicon-containing precursors that may be used for silicon-containing film formation. Silicon-containing materials may be nitrogen-free, oxygen-free, and / or carbon-free in some embodiments. One or more additional precursors may be included in any of the steps, such as inert precursors that may include Ar, diatomic hydrogen, He, or other materials such as nitrogen, ammonia, or other precursors.

[0052]

[0054] Temperature and pressure can also affect the operation of the technique. For example, in some embodiments, the process is performed at a temperature of about 20° C. or less to facilitate film flow, and may be performed at a temperature of about 10° C. or less, about 0° C. or less, about −10° C. or less, about −20° C. or less, about −30° C. or less, or less. The temperature may be maintained in any of these ranges throughout the method, including during processing and densification. The pressure inside the chamber is kept relatively low, such as a chamber pressure of about 10 Torr or less, for any of the processes, and the pressure may be maintained at about 8 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. Additionally, in some embodiments, the pressure may be maintained at different levels during deposition and processing. For example, the pressure may be maintained at about 1 Torr or more (such as about 2 Torr or more, about 3 Torr or more, or more) during deposition, and the pressure may be maintained at about 1 Torr or less (such as about 0.8 Torr or less, about 0.5 Torr or less, about 0.1 Torr or less, or less) during deposition. By performing processes according to some embodiments of the present technique, improved filling of narrow features utilizing silicon-containing or other flowable materials may be produced.

[0053]

[0055] In the preceding description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one of ordinary skill in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0054]

[0056] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be interpreted as limiting the scope of the present technology. Furthermore, although a method or process may be described sequentially or stepwise, it should be understood that the steps may be performed simultaneously or in a different order than that listed.

[0055]

[0057] Where a range of values ​​is given, each intervening value between the upper and lower limit of that range is specifically disclosed to the smallest unit of the lower limit, unless the context clearly indicates otherwise. Any smaller ranges between any stated or unstated intervening value in a stated range, as well as any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may be individually included or excluded from the range. Each range in which either or both limits are included in the narrower range, or neither is included in the narrower range, is also encompassed by this technology and covers any specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0056]

[0058] As used in the specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the layer" includes reference to one or more layers and equivalents known to those skilled in the art, and so forth.

[0057]

[0059] Additionally, the terms "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, operations, or groups.

Claims

1. forming a plasma of a silicon-containing precursor; depositing a flowable film on a semiconductor substrate using plasma effluents of the silicon-containing precursor, the semiconductor substrate being contained within a processing region of a semiconductor processing chamber, the semiconductor substrate defining features therein, the processing region being defined at least in part between a faceplate and a substrate support upon which the semiconductor substrate rests; forming a processing plasma within the processing region of the semiconductor processing chamber, the processing plasma being formed at a first power level from a first power source and a second power level being applied to the substrate support from a second power source; densifying the flowable film within the feature defined within the semiconductor substrate using plasma effluents of the treatment plasma; A processing method comprising:

2. The semiconductor chamber is part of a semiconductor processing system, the semiconductor processing system comprising: A chamber body; a pedestal configured to support a semiconductor substrate; a faceplate, the chamber body, the pedestal, and the faceplate defining the processing region; and a radio frequency plasma source connected to the face plate, the radio frequency plasma source being the first power source; a low frequency plasma source connected to the pedestal, the low frequency plasma source being the second power source; The method of claim 1 , comprising:

3. a first LC filter connected to the pedestal and configured to substantially ground the RF plasma source through the pedestal; a second LC filter connected to the faceplate and configured to substantially ground the low frequency plasma source to the chamber body; The method of claim 2 further comprising:

4. 10. The method of claim 1, wherein the second power source operates in a pulsed mode with a pulse frequency of about 1 kHz or less.

5. 5. The processing method of claim 4, wherein the first power source operates in a continuous wave mode during the processing plasma while the second power source operates in the pulsed mode.

6. 5. The method of claim 4, wherein the second power supply operates at a duty cycle of about 50% or less.

7. 10. The method of claim 1, wherein the first power supply is operative to generate a power spike within a first period during the deposition.

8. 8. The method of claim 7, wherein following the first time period, the first power supply operates for a second time period during the deposition.

9. 9. The method of claim 8, wherein the first period of time is less than or equal to about 1 second and the second period of time is greater than or equal to about 1 second.

10. 10. The method of claim 9, wherein the first power supply operates at a pulse frequency of about 200 kHz or less with a duty cycle of about 20% or less to generate an effective plasma power of about 10 W or less.

11. The method of claim 1 , wherein the method is repeated a second cycle.

12. 10. The method of claim 1, wherein the temperature of the semiconductor substrate is maintained at a temperature of about 0[deg.] C. or less during the method.

13. A chamber body; a pedestal configured to support a semiconductor substrate; a faceplate, wherein the chamber body, the pedestal, and the faceplate define a processing region; and a radio frequency plasma source connected to the face plate; a low frequency plasma source connected to the pedestal; A semiconductor processing system comprising:

14. the pedestal comprises an electrostatic chuck, and the semiconductor processing system comprises: A DC power supply connected to the pedestal The semiconductor processing system of claim 13 further comprising:

15. 14. The semiconductor processing system of claim 13, wherein said low frequency plasma source is configured to operate at less than about 2 MHz.

16. 14. The semiconductor processing system of claim 13, wherein said radio frequency plasma source is configured to operate at about 13.56 MHz or greater, with a pulse frequency of about 200 kHz or less.

17. 20. The semiconductor processing system of claim 16, wherein said radio frequency plasma source is configured to operate at a pulse frequency of about 20 kHz or less with a duty cycle of about 20% or less.

18. 20. The semiconductor processing system of claim 17, wherein the radio frequency plasma source is configured to generate a plasma with an effective power of about 5 W or less.

19. a first LC filter connected to the pedestal and configured to substantially ground the high frequency plasma source through the pedestal; The semiconductor processing system of claim 13 further comprising:

20. a second LC filter connected to the faceplate and configured to substantially ground the low frequency plasma source to the chamber body; 20. The semiconductor processing system of claim 19 further comprising:

Images