Semiconductor device

Abstract

To provide a semiconductor device which prevents write failure of a signal to a transistor, which is caused by voltage drop or signal delay, which is associated with wiring resistance; and provide a display device which prevents gradation failure caused by write failure to a transistor provided for a pixel of the display device and has high display quality.SOLUTION: In a semiconductor device, it is favorable that a transistor is manufactured by connecting an oxide semiconductor which has wide band gap and a low carrier concentration and achieves high purity to wiring containing copper having low wiring resistance. Not only reducing off-state current of the transistor by using the oxide semiconductor having a wide band gap, but by using the oxide semiconductor which has the low carrier concentration and achieves the high purity, a ratio of an off-state current to an on-state current can be increased as a so-called normally-off transistor having a positive threshold voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device using a semiconductor element and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This generally refers to semiconductor elements such as transistors, semiconductor circuits using semiconductor elements, and electro-optical equipment. All semiconductor devices include industrial equipment and electronic devices. [Background technology]

[0003] In recent years, transistors have been manufactured using oxide semiconductors as semiconductor materials. This technology is attracting attention for its application to semiconductor circuits, ICs, electro-optical devices, and electronic equipment.

[0004] For example, zinc oxide, In-Ga-Zn-O oxide semiconductor, etc. are formed on a substrate having an insulating surface. Thin film transistors (TFTs) are made using semiconductor thin films (thickness: several to several hundred nm). We will create a switching element for image display devices. Technologies for use in children and the like are disclosed in Patent Documents 1 and 2.

[0005] Conventional transistors are mainly made of amorphous silicon or polycrystalline silicon. Amorphous silicon TFTs are made using field effect transfer (FED) technology. Although the degree of adhesion is low, it is relatively easy to accommodate larger areas of substrates such as glass substrates. On the other hand, TFTs using polycrystalline silicon have high field effect mobility, but they are difficult to anneal due to laser or other factors. Since a crystallization process is required, it is not necessarily suitable for making large-area substrates such as glass substrates. It has the following characteristics:

[0006] In contrast, a TFT in which a channel formation region (also called a channel region) is provided in an oxide semiconductor The field effect mobility is higher than that of amorphous silicon TFTs. In addition, the oxide semiconductor film can be formed by a sputtering method or the like, and polycrystalline silicon The manufacturing process is simpler than that of TFTs using polysilicon, and it is easier to manufacture on larger substrates.

[0007] In this way, we have developed an oxidizing process that can form high-performance transistors on glass and plastic substrates. Semiconductors include liquid crystal displays, electroluminescence displays (EL displays), It is expected that these materials will be used in display devices such as LCDs (also known as LCD panels) or electronic paper.

[0008] In particular, in active matrix type semiconductor devices such as liquid crystal display devices, There is a trend for TVs to become larger, with diagonal sizes of 60 inches or more, and even 120 inches or more. The development is also taking into consideration the screen size. In addition, the screen resolution is also high definition. Image quality (HD, 1366 x 768), Full HD image quality (FHD, 1920 x 1080 ) and the trend is toward higher definition, with resolutions of 3840 x 2048 or 4096 x 2180. The development of so-called 4K digital cinema display devices is also underway.

[0009] As display devices become larger and more precise, the number of pixels required is increasing dramatically. The write time per pixel is shortened, and the transistors arranged in the pixels have operating characteristics On the other hand, there is a problem of energy depletion in recent years. Therefore, there is a demand for display devices with reduced power consumption, such as display devices with low off-state current and suppressed wasteful leakage current. There is a demand for transistors with this feature.

[0010] Thus, a transistor with a large ratio of on-current to off-current is desired. In the case of transistors using semiconductors, the ratio of on-current to off-current is set to 10 3 Tiger with improved level A technique relating to transistors is disclosed in Patent Document 3.

[0011] Furthermore, larger screen sizes and higher definitions tend to increase the wiring resistance within the display unit. Increased wiring resistance can cause delays in signal transmission to the end of the signal line and voltage drops in the power line. As a result, display quality may deteriorate, resulting in uneven display and poor gradation, and power consumption may increase. It ends up like this.

[0012] As a result, in order to suppress the increase in wiring resistance, copper (Cu) is used to form a low-resistance wiring layer. Technologies for achieving this are being investigated (see, for example, Patent Documents 4 and 5). [Prior art documents] [Patent documents]

[0013] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2007-134496 A [Patent Document 4] JP 2004-133422 A [Patent Document 5] JP 2004-163901 A Summary of the Invention [Problem to be solved by the invention]

[0014] In semiconductor devices where delay resistance is an issue, such as large display devices, the reduction of wiring resistance is essential. For example, a method using copper wiring is being considered. The oxide semiconductor has high field-effect mobility and is easy to adapt to changes in temperature. The copper wiring has low wiring resistance. The ratio of the on-current to the off-current of the connected transistor is 10 3 It is only to a certain extent, but not enough. There was a problem.

[0015] In addition, impurities may enter the inside of a transistor after a long period of use, causing changes in transistor threshold and other transistor characteristics. However, there was a problem that the transistor characteristics changed.

[0016] One aspect of the present invention is to reduce the voltage drop and signal delay caused by wiring resistance in a transistor. It is an object of the present invention to provide a semiconductor device that prevents a write failure of a signal. This prevents poor gradation caused by poor writing to transistors in the pixels of a display device. It is an object of the present invention to provide a display device with high display quality.

[0017] Another object of one embodiment of the present invention is to achieve high-speed operation of a semiconductor device.

[0018] Another object of one embodiment of the present invention is to achieve power saving in a semiconductor device.

[0019] Another embodiment of the present invention is a transistor which operates stably and a semiconductor device including the transistor. One of our goals is to provide

[0020] Another object of one embodiment of the present invention is to realize a semiconductor device with excellent productivity. .

[0021] Another object of one embodiment of the present invention is to realize a semiconductor device with excellent reliability. . [Means for solving the problem]

[0022] For wiring containing copper with low wiring resistance, high purity copper with wide band gap and low carrier concentration A transistor can be fabricated by connecting a fluorinated oxide semiconductor. By using an oxide semiconductor, not only can the off-state current of a transistor be reduced, but also the carrier concentration can be increased. By using a low-purity highly purified oxide semiconductor, a device having a positive threshold voltage and a so-called To obtain a transistor with normally-off characteristics, the ratio of the off current to the on current should be increased.

[0023] In order to solve the above problems, the present invention provides a source wiring, a gate wiring, a source electrode, A conductive film containing copper as a main component, which has high electrical conductivity, is used for the drain electrode, and the conductive film and The oxide semiconductor layer is connected to the oxide semiconductor layer, which is highly purified and has a suppressed carrier concentration. The transistor using the semiconductor device may be sealed by surrounding it with an insulating film.

[0024] That is, one embodiment of the present invention is a method for manufacturing an insulating base film including silicon nitride over a substrate, and a first insulating film over the base film. a gate electrode made of a first conductive layer, a first insulating layer containing silicon nitride on the gate electrode, and a first A highly purified oxide semiconductor layer is formed on the insulating layer, and an end portion of the highly purified oxide semiconductor layer is overlapped on the gate electrode. The source electrode and the drain electrode are made of a second conductive layer in contact with the oxide semiconductor layer. a second insulating layer containing silicon nitride over the second conductive layer and the highly purified oxide semiconductor layer; The semiconductor device has a gate wiring formed of a first conductive layer and a source wiring formed of a second conductive layer. The first conductive layer and the second conductive layer include a conductive layer mainly composed of copper, and the highly purified acid The carrier concentration of the semiconductor layer is 1×10 12 cm -3It is a semiconductor device having a capacitance of less than 100 .mu.m.

[0025] In one embodiment of the present invention, the second conductive layer is a conductive layer mainly composed of copper. The semiconductor device is connected to the purified oxide semiconductor layer via an insulating film.

[0026] In one embodiment of the present invention, a gate wiring formed using a first conductive layer and a gate insulating film formed using a second conductive layer are The semiconductor device according to claim 1, wherein the source wirings are arranged to cross each other with a highly purified oxide semiconductor layer interposed therebetween. It is located.

[0027] In one embodiment of the present invention, a base film and a first insulating layer are in contact with each other and surround a periphery of a first conductive layer, The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are in contact with each other and surround the oxide semiconductor layer and the second conductive layer. The first insulating layer and the second insulating layer may include the same material.

[0028] In one embodiment of the present invention, an insulating base film containing silicon nitride is formed over a substrate, and a metal oxide film is formed on the base film. A gate electrode and a gate wiring are formed from a first conductive layer, and a silicon nitride film is formed on the first conductive layer. forming a first insulating layer containing The substrate with the semiconductor layer is heated to a temperature of 350°C to 700°C, and then dried in a dry oven containing oxygen. The semiconductor device is cooled in dry gas, and the end of the semiconductor device is overlapped on the gate electrode and electrically connected to the oxide semiconductor layer. A source electrode and a drain electrode are formed from the second conductive layer, and a source wiring is formed on the first insulating layer. a second insulating layer containing silicon nitride over the second conductive layer and the oxide semiconductor layer; A method for making a body device.

[0029] In one embodiment of the present invention, a substrate provided with an oxide semiconductor layer is heated in nitrogen, and the temperature of the substrate is After the temperature is reduced to 350° C. or more and 700° C. or less, the substrate is cooled and then heated in a dry gas containing oxygen. The temperature of the substrate is then lowered to 350° C. or higher and 700° C. or lower, and then the substrate is cooled. It is law.

[0030] In one embodiment of the present invention, the substrate provided with an oxide semiconductor layer is heated in nitrogen. The temperature is set to 350°C or higher and 700°C or lower, and the substrate is heated in a dry gas containing oxygen while maintaining the temperature. The method for manufacturing the semiconductor device includes heating and then cooling in a dry gas containing oxygen.

[0031] In this specification, the term "gate" refers to a gate electrode and a part or the whole of a gate wiring. The gate wiring is a wiring that connects at least one gate electrode of a transistor to another electrode or This refers to a wiring for electrically connecting to another wiring, and is used, for example, as a scanning The lines are also included in the gate wiring.

[0032] The source refers to a source region, a source electrode, and a part or all of a source wiring. The source region is a region of the semiconductor layer whose resistivity is equal to or lower than a certain value. The electrode refers to a conductive layer that is connected to a source region. In order to electrically connect the source electrode of one transistor to another electrode or another wiring, For example, a signal line in a display device is electrically connected to a source electrode. In this case, the source wiring also includes the signal line.

[0033] The drain refers to a part or all of the drain region, drain electrode, and drain wiring. The drain region is the region of the semiconductor layer whose resistivity is below a certain value. The drain electrode is the conductive layer that is connected to the drain region. The wiring is a wiring that connects the drain electrode of at least one transistor to another electrode or another wiring. For example, the signal line in a display device is a drain electrode. When the drain wiring is electrically connected to the electrode, the signal line is also included in the drain wiring.

[0034] In addition, in this document (specification, claims or drawings), The drains are interchangeable depending on the transistor structure and operating conditions, so Therefore, it is difficult to determine whether the semiconductor device is a source or a drain. In the claims or drawings, either the source or the drain may be arbitrarily selected. The selected terminal is referred to as one of the source and drain, and the other terminal is referred to as the other of the source and drain. It is written as "kata".

[0035] In this specification, silicon nitride oxide refers to a material containing more nitrogen than oxygen as its composition. Preferably, the composition range is within the range of 0.1 to 1.0 μm, as measured by RBS and HFS. The atomic percentage of oxygen is 5 to 30%, nitrogen is 20 to 55%, silicon is 25 to 35%, and water is 10 to 15%. This refers to a material that contains 10 to 30 atomic percent of elemental elements.

[0036] In this specification, the term "light-emitting device" refers to an image display device, a light-emitting device, or a light Also, the light emitting device is connected to a connector, such as FPC (Flexib le printed circuit) or TAB (Tape Automate d Bonding) tape or TCP (Tape Carrier Packag e) is attached to the module, the printed wiring board is attached to the end of the TAB tape or TCP. A module with a COG (Chip On Glass) s) All modules in which an IC (integrated circuit) is directly mounted using this method are included in the light-emitting device. Let us assume that. Effect of the Invention

[0037] According to the present invention, a semiconductor device having a large ratio of on-current to off-current and reduced wiring resistance is provided. We can provide it.

[0038] In addition, the transistor characteristics change due to impurities that enter the device from the outside over a long period of use. It is therefore possible to provide a semiconductor device that is difficult to manufacture.

[0039] In addition, it prevents the effects of voltage drops due to wiring resistance, as well as signal writing errors and poor gradation in pixels. As a result, it is possible to provide a semiconductor device, such as a display device, having better display quality.

[0040] In addition, a semiconductor device that operates at high speed can be provided.

[0041] In addition, a power-saving semiconductor device can be provided.

[0042] It is also possible to provide a transistor that operates stably and a semiconductor device using the same.

[0043] Moreover, a semiconductor device with excellent productivity can be provided.

[0044] Furthermore, a semiconductor device with excellent reliability can be provided. [Brief description of the drawings]

[0045] [Figure 1] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 2]A longitudinal cross-sectional view of an inverted staggered transistor using an oxide semiconductor [Diagram 3] Energy band diagram (schematic diagram) at the A-A' cross section of Figure 2 [Figure 4] (A) A diagram showing the state when a positive potential (+VG) is applied to the gate (G1), and (B) a diagram showing the state when a negative potential (-VG) is applied to the gate (G1). [Diagram 5] A diagram showing the relationship between the vacuum level, the work function of a metal (φM), and the electron affinity of an oxide semiconductor (χ) [Figure 6] A diagram showing the energy required for hot carrier injection in silicon (Si) [Figure 7] A diagram showing the energy required for hot carrier injection in an In-Ga-Zn-O oxide semiconductor (IGZO) [Figure 8] A diagram showing the energy required for hot carrier injection in silicon carbide (4H-SiC) [Figure 9] Figure showing the results of device simulations on short channel effects [Figure 10] Figure showing the results of device simulations on short channel effects [Figure 11] CV characteristics diagram [Figure 12] Diagram showing the relationship between Vg and (1 / C)2 [Figure 13] 1A to 1C illustrate a method for manufacturing a semiconductor device according to an embodiment; [Figure 14] 5A to 5C are diagrams illustrating a heating process according to the embodiment. [Figure 15] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 16] 1A and 1B are diagrams illustrating an inverter circuit according to an embodiment; [Figure 17] FIG. 1 is a block diagram illustrating a display device. [Figure 18] 1A and 1B are a diagram illustrating a configuration of a signal line driver circuit and a timing chart illustrating the operation of the signal line driver circuit. [Figure 19] FIG. 1 is a circuit diagram showing a configuration of a shift register. [Figure 20]1A and 1B are a diagram illustrating a configuration of a shift register and a timing chart illustrating the operation of the shift register; [Figure 21] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 22] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 23] 1A and 1B are diagrams illustrating a pixel equivalent circuit of a semiconductor device according to an embodiment; [Figure 24] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 25] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 26] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 27] 1A and 1B are diagrams illustrating examples of usage of electronic paper. [Figure 28] FIG. 1 is an external view showing an example of an electronic book. [Figure 29] FIG. 1 is an external view showing an example of a television device and a digital photo frame. [Diagram 30] FIG. 1 is an external view showing an example of a gaming machine. [Diagram 31] FIG. 1 is an external view showing an example of a mobile phone. [Diagram 32] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 33] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 34] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 35] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 36] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 37] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 38] 1A to 1C illustrate a semiconductor device according to an embodiment; [Figure 39] 1A to 1C illustrate a semiconductor device according to an embodiment; [Diagram 40] 1A to 1C illustrate a semiconductor device according to an embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0046] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation thereof will be omitted.

[0047] (Embodiment 1) In this embodiment, one mode of a circuit-equipped substrate of a display device as one mode of a semiconductor device is shown in FIG. This will be explained using:

[0048] The structure of a pixel provided in a display device is shown in FIG. 1. FIG. 1(A) is a top view showing the planar structure of a pixel. FIG. 1B is a cross-sectional view showing the stacked structure of a pixel. The dashed lines 1-A2, B1-B2, and C1-C2 represent the cross sections A1-A2 and A1-A2 in FIG. These correspond to sections B1-B2 and C1-C2, respectively.

[0049] The cross section A1-A2 shows the laminated structure of a transistor 151 used in a pixel portion. The transistor 151 is one embodiment of a bottom gate structure.

[0050] Also, the cross section B1-B2 shows the laminated structure of a capacitance section formed in a pixel section.

[0051] Also, the cross section C1-C2 shows the laminated structure at the intersection of the gate wiring and the source wiring.

[0052] The transistor 151 includes a base film 101 over a substrate 100 and a first conductive layer The gate electrode 111a is formed of a first insulating layer 102. A channel forming region is formed in contact with the first insulating layer 102 on the gate electrode 111a. The gate electrode 11 is formed of a second conductive layer. The first electrode 115a and the second electrode 115b are in contact with the oxide semiconductor layer 113a and overlap the end of the first electrode 115a and the end of the second electrode 115b. The first electrode 115a and the second electrode 115b are connected to the transistor 1. The first electrode 115a and the second electrode 115b function as a source electrode or a drain electrode of the first electrode 115a and the second electrode 115b. A second insulating layer is formed on the electrode 115b, the first insulating layer 102, and the oxide semiconductor layer 113a. A third insulating layer 108 is formed on the second insulating layer 107. A contact hole 12 formed in the second insulating layer 107 and the third insulating layer 108 is formed on the layer 108. The first pixel electrode 115b is connected to the second electrode 115b via the third conductive layer 118. It has 09.

[0053] The capacitance portion formed in the pixel portion is made up of a capacitance wiring 111b formed of a first conductive layer and a third conductive layer. The first insulating layer 102 and the second insulating layer 103 are disposed between the first pixel electrode 109 formed of the conductive layer. 07 and a third insulating layer 108 are sandwiched between the insulating layer 107 and the third insulating layer 108.

[0054] In addition, the intersection of the gate wiring and the source wiring is formed of the gate wiring 111 made of the first conductive layer. The first insulating layer 102 and the oxide semiconductor are disposed between the source wiring 115c formed of the second conductive layer and the source wiring 115b. A conductor layer 113b may be sandwiched between the oxide semiconductor layer 113b. The distance between the wires can be increased, and the capacitance generated at the intersection of the wires can be reduced.

[0055] In this embodiment, copper is used for the first conductive layer. A layer containing copper as a main component may be used as a single layer or may be laminated with other conductive layers. The first conductive layer included as a component has high conductivity and can reduce the wiring resistance.

[0056] In addition, Cr, Ta, Ti, Mo, A structure in which a high melting point metal material layer such as W or an alloy material containing the metal material is laminated. In addition, Si, Ti, Ta, W, Mo, Cr, Nd, Sc, Y, etc. can be formed on the Al film. Use an aluminum material that contains elements that prevent the formation of hillocks and whiskers. It is possible to improve the heat resistance of the conductive layer by using the above-mentioned method. It is preferable that the material has a heat resistance sufficient to meet the above requirement.

[0057] In addition, a tantalum nitride film, for example, is formed on the layer containing copper as the main component to suppress the diffusion of copper. A barrier film that prevents the formation of the oxide film may be formed.

[0058] In addition, the first conductive layer, which contains copper as its main component, blocks light with wavelengths of around 400 nm to 450 nm. A gate electrode overlapping with the oxide semiconductor layer is formed by using a first conductive layer mainly containing copper. By forming the electrode 111a, the wavelength of 400 nm or less is incident on the oxide semiconductor layer from the substrate 100 side. Therefore, light with wavelengths of around 400 nm can be prevented from reaching the oxide semiconductor layer. Since it is sensitive to light around 450 nm, it is made of a first conductive layer containing copper as the main component. The gate electrode 111a determines the electrical characteristics of a transistor using an oxide semiconductor layer or the electrical characteristics of a transistor using an oxide semiconductor layer. The operation of semiconductor devices using conductive layers becomes unstable due to light with wavelengths of around 400 nm to 450 nm. This can prevent the phenomenon from occurring.

[0059] The first conductive layer, which contains copper as a main component, is disposed between the base film 101 and the first insulating layer 102. is formed.

[0060] The wiring material may be appropriately selected depending on the performance required for the display device. Only the second conductive layer, including the source wiring, which requires higher transmission characteristics than the source wiring, is made of Cu-containing wiring. It may also be a line.

[0061] In this embodiment, the base film 101 is made of silicon nitride (SiN y (y>0) film is used. By using a base layer, the phenomenon of copper diffusion from the first conductive layer, which contains copper as a main component, is prevented. In addition, it is possible to prevent the phenomenon in which impurity elements are diffused from the substrate 100 into the semiconductor element. Cut.

[0062] The base film 101 and the first insulating layer 102 include at least a silicon nitride layer, and the other insulating layers Other insulating layers to be laminated include, for example, a silicon nitride oxide layer and a silicon oxynitride layer. , or silicon oxide layers, as well as layers of aluminum, tantalum, yttrium, or hafnium. At least two of the oxide, nitride, oxynitride, or oxynitride or their compounds are A compound layer containing more than one kind may also be used.

[0063] In particular, when a silicon nitride layer is used in combination with an insulating film having a higher dielectric constant than silicon nitride, This is preferable since it improves the characteristics as a gate insulating film.

[0064] In addition, by forming a first conductive layer containing copper as a main component between the two silicon nitride films, , the diffusion of copper can be suppressed.

[0065] The base film 101 and the first insulating layer 102 are formed by sputtering, CVD or high-density plasma. An insulating film produced by a CVD method is preferred.

[0066] In this embodiment, the carrier concentration is 1×10 12 cm -3 It is highly purified to less than 100% and has a wide band. An In-Ga-Zn-O oxide semiconductor having a gap between the active layer and the gate electrode is used for the oxide semiconductor layer.

[0067] Carrier concentration is 1×10 12 cm -3 Using an oxide semiconductor layer highly purified to less than The transistor has a positive threshold voltage and has a so-called normally-off characteristic. In addition, a transistor formed using an oxide semiconductor with a wide band gap has a low off-state current. The electrical characteristics of a transistor using an oxide semiconductor having such characteristics are as follows: This will be explained in detail at the end of this embodiment.

[0068] The oxide semiconductor used in the oxide semiconductor layer is a quaternary metal oxide, In-S n-Ga-Zn-O oxide semiconductors and In-Ga-Zn-O ternary metal oxides Oxide semiconductors, In-Sn-Zn-O oxide semiconductors, In-Al-Zn-O oxide semiconductors Conductor, Sn-Ga-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, S n-Al-Zn-O oxide semiconductors and In-Zn-O oxides, which are binary metal oxides Semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg- O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, I nO-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. The oxide semiconductor layer may contain silicon oxide. By including silicon oxide (SiOx(X>0)) which inhibits crystallization, In the case where a heat treatment is performed after the formation of an oxide semiconductor layer, crystallization of the oxide semiconductor layer is suppressed. It is possible.

[0069] The oxide semiconductor layer is InMO 3 (ZnO) m A thin film expressed as (m>0) Here, M is one selected from Ga, Al, Mn, and Co, or It indicates multiple metal elements. For example, M can be Ga, Ga and Al, Ga and Mn, or G a and Co. 3 (ZnO) m Oxide semiconductors with structures represented by (m>0) Among the conductor films, the oxide semiconductor having a structure containing Ga as M is the above-mentioned In-Ga-Zn- In this study, we call the thin film an In-Ga-Zn-O oxide semiconductor and call the thin film an In-Ga-Zn-O non-single crystal film. .

[0070] In addition, the oxide semiconductor layer is subjected to rapid thermal annealing (RTA). Use materials that have been dehydrated or dehydrogenated at high temperature for a short time using a method such as hot thermal annealing. This heating process reduces the grain size of the surface layer of the oxide semiconductor layer to 1 nm or more and 20 nm or less. The crystal region is made up of so-called nanocrystals (also written as nanocrystals). The rest of the material is amorphous, or a mixture of amorphous and microcrystalline regions with microcrystalline regions interspersed. It is to be noted that the size of the nanocrystals is merely an example, and the invention is not limited to the above numerical range. It is not to be interpreted.

[0071] By using an oxide semiconductor layer having such a structure, the surface layer is made of nanocrystals. The dense crystalline region prevents moisture from re-entering the surface and oxygen from escaping, resulting in an N-type structure. As a result, the deterioration of electrical characteristics caused by the N-type transistor, specifically the increase in off-state current, can be prevented. It can be prevented.

[0072] The crystalline region may include other substances than crystal grains. The crystal structure is not limited to the above, and may include crystal grains of other crystal structures. For example, In-Ga-Zn When using an In-O-based oxide semiconductor material, 2 Ga 2 ZnO 7 In addition to the grains of I nGaZnO 4 The crystal grains may also include.

[0073] In this embodiment mode, copper is used for the second conductive layer. For example, a tantalum nitride film may be formed to form a barrier film that suppresses copper diffusion.

[0074] The second conductive layer has at least a layer containing copper as a main component, similar to the first conductive layer. The second conductive layer may be a single layer or a laminate with another conductive layer. has high electrical conductivity and can reduce wiring resistance.

[0075] In a structure in which a layer containing copper as a main component of the second conductive layer is in contact with the oxide semiconductor layer, The heat treatment required for purifying the oxide semiconductor layer is used to convert the layer containing copper as a main component into an oxide semiconductor layer. In some cases, copper oxides are formed between layers of semiconductors. The copper oxide formed between the conductor layers is a semiconductor, and the electrical connection between the oxide semiconductor layer and the second conductive layer is Does not interfere with connectivity.

[0076] Note that in the structure in which the layer containing copper as a main component is in contact with the oxide semiconductor layer, However, unlike silicon semiconductors, the characteristics of oxide semiconductor layers is less susceptible to the diffusion of heavy atoms such as copper.

[0077] A second conductive layer is formed by providing another conductive layer between the layer containing copper as a main component and the oxide semiconductor layer. You may do so.

[0078] As another conductive layer provided between the layer containing copper as a main component and the oxide semiconductor layer, Materials containing metals with high oxygen affinity are preferred. Metals with high oxygen affinity include titanium (Ti), ma (Ma), and mercury (Mg). Examples include calcium (Mn), magnesium (Mg), zirconium, beryllium, and thorium. The material is selected from one or more of the above metals. preferable.

[0079] When an oxide semiconductor layer and a conductive layer with high oxygen affinity are formed in contact with each other, the carrier density near the interface The amount of charge increases, a low-resistance region is formed, and the contact resistance between the oxide semiconductor and the conductive layer can be reduced. This is because the conductive layer with high oxygen affinity extracts oxygen from the oxide semiconductor layer. At the interface between the oxide semiconductor layer and the conductive layer, a layer containing an excess of metal in the oxide semiconductor layer (also called a composite layer) is formed. This is due to the formation of either a conductive film that is oxidized or a conductive film that is oxidized, or both.

[0080] For example, in a structure in which an In-Ga-Zn-O-based oxide semiconductor layer is in contact with a titanium film, A layer containing excess indium and a titanium oxide layer are formed near the interface between the oxide semiconductor layer and the titanium film. Indium may be generated near the interface between the oxide semiconductor layer and the titanium film. In some cases, either an In-Ga-Zn-O layer or a titanium oxide layer may form. The layer with excess indium, which is deficient in oxygen from the oxide semiconductor layer, has high electrical conductivity and is oxidized. This can reduce the contact resistance between the semiconductor layer and the conductive layer.

[0081] Note that the conductive film in contact with the oxide semiconductor layer is formed using titanium or titanium oxide having conductivity. In that case, an In-Ga-Zn-O oxide semiconductor layer and a titanium oxide film In the case where the oxide semiconductor layer is in contact with the titanium oxide film, indium is added near the interface between the oxide semiconductor layer and the titanium oxide film. In some cases, an excessive layer of gum may be produced.

[0082] In addition, as another conductive layer provided between the layer containing copper as a main component and the oxide semiconductor layer, A conductive layer containing a metal with low electronegativity is preferred. Examples of metals with low electronegativity include titanium, mabium, and arsenic. Examples include magnesium, yttrium, aluminum, tungsten, and molybdenum. The material preferably contains one or more of the above metals.

[0083] A conductive layer containing a metal with low electronegativity is provided between a layer containing copper as a main component and an oxide semiconductor layer. By this, impurities such as moisture and hydrogen are released from the oxide semiconductor layer, and the oxide semiconductor layer becomes an i-type (intrinsic semiconductor) or By using an oxide semiconductor that is as close to the GaN type as possible, the threshold voltage is shifted by the above impurities. This can prevent the deterioration of transistor characteristics, such as the deterioration of the off-state current, from progressing. can.

[0084] Impurities such as hydrogen and water absorbed by the conductive layer containing a metal with low electronegativity are Impurities that form chemical bonds with metals in the conductive layer. The bond with the metal is stable, and once absorbed into the conductive layer, the oxide semiconductor layer It is difficult to release it into the

[0085] Therefore, impurities such as hydrogen or water are trapped in the conductive layer containing a metal with low electronegativity. The hydrogen concentration in the conductive layer containing the metal with low electronegativity is maintained at a level lower than that of the oxide semiconductor. Specifically, the hydrogen concentration in the first electrode 115a and the second electrode 115b is higher than that in the The hydrogen concentration is 1.2 times or more, preferably 5 times or more, as high as the hydrogen concentration in the oxide semiconductor layer.

[0086] The hydrogen concentration in the conductive layer was measured by secondary ion mass spectrometry (SIMS). Measurements using Ion Mass Spectroscopy (Ion Mass Spectroscopy) are used.

[0087] Here, the analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film will be described. The hydrogen concentration in the semiconductor film and the conductive film was measured by secondary ion mass spectrometry (SIMS). SIMS analysis is performed using 2D ion mass spectroscopy (SIMS). In principle, it is difficult to obtain accurate data near the sample surface or near the interface between layers of different materials. It is known that it is difficult to obtain a hydrogen concentration distribution in the thickness direction of the film. When analyzing by SIMS, the hydrogen concentration is extremely high in the area where the target film exists. The average value in the area where there is no fluctuation and the intensity is almost constant is adopted. When the thickness of the target film is small, the strength is almost constant due to the influence of the adjacent films. In some cases, the area where the film exists cannot be found. In this case, the maximum value, the minimum value, and the The smallest value is adopted as the hydrogen concentration. Furthermore, in the region where the film exists, the peak with the maximum value is adopted. If there is no peak or minimum value, the value at the inflection point is used as the hydrogen concentration.

[0088] Among the above metals with low electronegativity, titanium, molybdenum, and tungsten are oxides. The contact resistance with the semiconductor layer is low. Therefore, the first electrode having a low contact resistance with the oxide semiconductor layer It is possible to form the first electrode 115a and the second electrode 115b. By using tungsten for a conductive layer in contact with the oxide semiconductor film, the insulator layer in the oxide semiconductor film can be easily formed. The impurities can be reduced.

[0089] As another conductive layer provided between the layer containing copper as a main component and the oxide semiconductor layer, Al Metallic materials such as Cr, Ta, Ti, Mo, and W, or alloy materials containing such metallic materials can be used.

[0090] Alternatively, a conductive metal oxide can be used. In 2 O 3 ), tin oxide (SnO 2 ), zinc oxide (ZnO), indium oxide Tin oxide alloy (In 2 O 3 - SnO 2 (abbreviated as ITO), indium oxide zinc oxide alloy (In 2 O 3 -ZnO) or the metal oxide material contains silicon or silicon oxide The mixture can be used.

[0091] In addition, the conductive layer is not limited to a single layer, and a laminate of two or more layers can be used. The conductive film preferably has heat resistance sufficient to withstand at least a heat treatment.

[0092] In addition, one or both of the layers containing copper as the main component may contain high-molecular-weight elements such as Cr, Ta, Ti, Mo, and W. A layer of a high melting point metal may be laminated. Elements such as Nd, Sc, and Y are added to prevent the occurrence of hillocks and whiskers in the Al film. By using Al materials that have been proven to be effective, it is possible to improve heat resistance.

[0093] In this embodiment, silicon nitride (SiN y The (y>0) layer is referred to as the second insulating layer 107.

[0094] The second insulating layer 107 is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as The silicon nitride film is an inorganic insulating layer that prevents the penetration of copper from the main component. This can prevent the phenomenon of copper diffusing from the first conductive layer and the second conductive layer contained as components.

[0095] In this embodiment, the first insulating layer 102 and the second insulating layer 107 are both formed using silicon nitride. In addition, the first insulating layer 102 and the second insulating layer 107 are in contact with each other. In this way, the same type of inorganic insulating layers are in contact with each other and surround the transistor 151. By doing so, the transistor can be sealed in a better state. In the case of a structure in which the insulating films are in contact with each other, the above-mentioned inorganic insulating films can be used, but in particular, nitride insulating films are preferred. A silicon film is preferable because it has excellent impurity barrier properties.

[0096] The second insulating layer 107 includes at least a silicon nitride layer and may be laminated with another insulating layer. Other insulating layers to be laminated include an oxide insulating layer, an oxynitride insulating layer, a nitride insulating layer, and a nitride insulating layer. An inorganic insulating layer such as an oxide insulating layer can be used. For example, a silicon nitride oxide layer, a silicon oxide nitride layer, A silicon nitride layer, a silicon oxide layer, or the like may be laminated.

[0097] In addition, an oxide insulating film is provided in contact with the oxide semiconductor layer, and silicon nitride (Si N y By stacking the (y>0) layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Specifically, a silicon oxide layer (SiO x (x A silicon nitride layer may be formed on the silicon oxide layer. By covering the second conductive layer containing copper with a silicon nitride layer, the diffusion of copper can be suppressed.

[0098] In addition, the oxide semiconductor layer is resistant to moisture, hydrogen ions, and OH - To avoid contamination by impurities such as In particular, the second insulating layer 107 is preferably a film formed by sputtering.

[0099] A third insulating layer 108 may be provided. The third insulating layer 108 may be formed of a single layer or a laminated layer. This creates a flat surface by smoothing out the unevenness caused by structures such as transistors formed in the lower layer. The third insulating layer 108 is formed of, for example, polyimide, acrylic resin, or benzocyclohexyl. Use heat-resistant organic materials such as arylbutene resins, polyamides, and epoxy resins. In addition to the above organic materials, low-k materials and siloxane resins are also available. Examples of usable materials include polysilicon, polysilicon glass (PSG), and boron phosphorus glass (BPSG). The third insulating layer 108 is formed by stacking a plurality of insulating films made of these materials. It may be possible to do so.

[0100] The first pixel electrode 109 is electrically connected to a transistor and can be used as a pixel of a display device. The first pixel electrode 109 serves as an electrode of the display element and has a translucency to visible light. The conductive film is formed.

[0101] Examples of the light-transmitting conductive film include indium tin oxide (hereinafter referred to as ITO), indium Conductive materials with light-transmitting properties such as indium zinc oxide and indium tin oxide doped with silicon oxide Materials can be used.

[0102] Below the carrier concentration of 1×10 12 cm -3 It is highly purified to less than 100 nm and has a wide band gap. The significance of using an oxide semiconductor having such a structure as an oxide semiconductor layer will be described.

[0103] <Intrinsic oxide semiconductor> In oxide semiconductors, research into physical properties such as DOS (density of states) Many studies have been done, but these studies include the idea of ​​sufficiently reducing the localized level itself. In one embodiment of the disclosed invention, water and other substances that can cause DOS in the energy gap are By removing hydrogen from an oxide semiconductor, a highly purified and intrinsic (i-type) oxide semiconductor is obtained. This is based on the idea of ​​sufficiently reducing the localized level itself. This makes it possible to manufacture extremely superior industrial products.

[0104] When removing hydrogen and water, oxygen may be removed at the same time. Therefore, oxygen is supplied to the dangling bonds of the metal that are generated due to oxygen deficiency, and localization due to oxygen vacancies occurs. By reducing the intrinsic level, the oxide semiconductor can be further purified and made intrinsic (i-type). For example, an oxide film containing excess oxygen is formed in close contact with the channel formation region, and By performing heat treatment at a temperature of 00°C to 400°C, typically around 250°C, the acid By supplying oxygen from the oxide film, it is possible to reduce localized levels due to oxygen defects.

[0105] The cause of the deterioration of the characteristics of oxide semiconductors is the 0.1 eV to 0.2 eV lower conduction band caused by excess hydrogen. This is thought to be due to the low 50 eV level and the deep levels due to oxygen vacancies. To eliminate defects, hydrogen is thoroughly removed and a sufficient amount of oxygen is supplied.

[0106] Note that an oxide semiconductor is generally an n-type semiconductor. By removing impurities such as i and supplying oxygen, which is a constituent element of oxide semiconductors, In this respect, unlike silicon, which is made i-type by adding impurity elements, It can be said that this technology contains a technological concept that has never been seen before.

[0107] <Conduction mechanism of transistors using oxide semiconductors> A transistor using an oxide semiconductor has several features. This will be described with reference to Figs. 2 to 5. In the following description, an ideal The study assumes various situations, and not all of them necessarily reflect the actual situation. The following explanation is merely a consideration and does not affect the validity of the invention. The following is added.

[0108] FIG. 2 is a cross-sectional view of an inverted staggered transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate insulating layer (GI) and A source electrode (S) and a drain electrode (D) are provided on the A back gate (GE2) is provided through the layer.

[0109] FIG. 3 shows an energy band diagram (schematic diagram) in the A-A' cross section shown in FIG. (A) is the zero potential difference between the source and drain (equipotential, V D =V S = 0V) Figure 3(B) shows the case where the drain potential is increased relative to the source potential (V D >V S ) This shows that.

[0110] FIG. 4 shows an energy band diagram (schematic diagram) in the cross section taken along line BB' in FIG. FIG. 4(A) shows a case where a positive voltage (V G >0) is a given state, This shows the on-state where carriers (electrons) flow between the source and drain. (B) A negative voltage (V G <0) is applied, and the The figure shows the case where the minority carriers do not flow.

[0111] Figure 5 shows the relationship between the vacuum level and the work function (φ M ) and the electron affinity (χ) of the oxide semiconductor. show.

[0112] At room temperature, electrons in metals are degenerate, and the Fermi level is located within the conduction band. Conventional oxide semiconductors are n-type, and their Fermi level (E F ) is in the center of the band gap The intrinsic Fermi level (E i ) and is located closer to the conduction band. It is known that some hydrogen atoms act as donors in semiconductors, which is one of the factors that causes them to become n-type. There are.

[0113] In contrast, an oxide semiconductor according to one embodiment of the disclosed invention can convert hydrogen, which is a factor in making the oxide semiconductor n-type, into an oxide. The oxide semiconductor is made of a material that is free from elements (impurity elements) other than the main components of the oxide semiconductor. By purifying it to such a high level that it is no longer necessary to use it, it has become true (i-type), or is an attempt to make it true. In other words, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. By removing the impurities, it is possible to obtain a highly purified i-type (intrinsic semiconductor) or a semiconductor close to it. This results in the Fermi level (E F ) is the intrinsic Fermi level (E i ) and It is possible.

[0114] The band gap of oxide semiconductors (E g ) is 3.15 eV, and the electron affinity (χ) is 4.3 V It is said that the work function of copper (Cu), which constitutes the source and drain electrodes, is 4. 6 eV, which is slightly lower than the electron affinity (χ) of oxide semiconductors, and the work function of titanium (Ti) The number of electrons is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, the metal-oxide semiconductor interface At this surface, no significant Schottky-type barrier is formed for electrons.

[0115] When the work function (φM) of a metal and the electron affinity (χ) of an oxide semiconductor are almost equal, When touched, an energy band diagram (schematic diagram) like that shown in FIG. 3(A) appears.

[0116] In Fig. 3(B), the black circles (●) represent electrons, and a positive voltage (V D >0) is applied If no voltage is applied to the gate (V G =0) is shown by the dashed line, and a positive voltage ( V G The solid line shows the case where a positive voltage (V G>0) is applied When a positive potential is applied to the drain, electrons cross the barrier (h) and are injected into the oxide semiconductor. The barrier height (h) depends on the gate voltage and the drain voltage. It depends on the gate voltage (V G >0) is applied and a positive drain voltage is applied. In this case, the barrier height (h) in Figure 3(A) without voltage application, i.e., the band gap P(E g ) the barrier height (h) is lower than 1 / 2. No voltage is applied to the gate. In the case of On the other hand, when a positive voltage is applied to the gate, The potential barrier is lowered, indicating an on-state in which current flows.

[0117] At this time, the electrons injected into the oxide semiconductor are highly coupled to the gate insulating layer as shown in FIG. Near the interface with a purified oxide semiconductor (the lowest energetically stable part of the oxide semiconductor) Move.

[0118] Also, as shown in FIG. 4(B), a negative potential (reverse bias) is applied to the gate electrode (GE1). When the current is increased, the number of holes, which are minority carriers, is essentially zero, so the current approaches zero. The value is close.

[0119] In this way, high purity oxide semiconductors are used to minimize the amount of elements (impurity elements) other than the main components of the oxide semiconductor. By tempering, the gate insulating layer becomes intrinsic (i-type) or substantially intrinsic. Therefore, the gate insulating layer is required to have a good interface with the oxide semiconductor. Specifically, for example, the power supply frequency of the VHF band to the microwave band is required. Insulating layers are produced by the CVD method using high-density plasma generated by a large number of processes, and by sputtering. It is preferable to use an insulating layer produced by a method such as the above.

[0120] The oxide semiconductor is highly purified while the interface between the oxide semiconductor and the gate insulating layer is improved. For example, the channel width (W) of a transistor is 1×10 4 μm, channel length When (L) is 3 μm, 10 -13 Off-state current less than A, 0.1V / de c. The subthreshold swing value (S value) (gate insulating layer thickness: 100 nm) It can be realized.

[0121] In this way, the oxide semiconductor is highly processed so that elements other than the main components (impurity elements) are not included as much as possible. Purification can improve the operation of the transistor.

[0122] <Hot-carrier degradation resistance of transistors using oxide semiconductors> Next, the resistance to hot carrier degradation of a transistor including an oxide semiconductor will be described with reference to FIGS. In the following explanation, we will assume an ideal situation for ease of understanding. Not all of them necessarily reflect the reality. However, I would like to add that this is just one consideration.

[0123] The main cause of hot carrier degradation is channel hot electron injection (CHE injection). and drain avalanche hot carrier injection (DAHC injection). For simplicity, only electrons are considered.

[0124] CHE injection is an injection into the semiconductor layer that has energy equal to or greater than the barrier of the gate insulating layer. This is the phenomenon in which the electrons that have become electrons are injected into the gate insulating layer, etc. This is achieved by accelerating electrons through a low electric field.

[0125] DAHC injection is a method of receiving energy by the collision of electrons accelerated by a high electric field. This refers to the phenomenon in which electrons are injected into the gate insulating layer, etc. The difference between DAHC injection and CHE injection is The question is whether or not avalanche breakdown due to impact ionization occurs. Electrons with kinetic energy greater than or equal to the band gap of the semiconductor are required.

[0126] Figure 6 shows the energy required for various hot carrier injections estimated from the band structure of silicon (Si). The energy distribution of the In-Ga-Zn-O oxide semiconductor (IGZO) is shown in Fig. 7. The energy required for various hot carrier injections estimated from the gate structure is shown in Fig. 6(A). 6(B) and 7(C) represent CHE injection, and DAHC injection. vinegar.

[0127] In silicon, the degradation caused by DAHC implantation is more severe than that caused by CHE implantation. In the electron, only a very small number of carriers (e.g. electrons) are accelerated without collisions. This is because silicon has a small band gap and is prone to avalanche breakdown. The number of electrons that can cross the barrier of the gate insulating layer due to avalanche breakdown increases, and the CHE This easily outweighs the odds of injection.

[0128] In the case of In-Ga-Zn-O oxide semiconductors, the energy required for CHE injection is silicon This is not significantly different from the case of DAHC injection, and the probability is low. The required energy is about the same as that required for CHE injection due to the wide band gap. do.

[0129] In other words, the probability of CHE injection and DAHC injection is low, and the hot- The carrier has high resistance to degradation.

[0130] By the way, the band gap of In-Ga-Zn-O oxide semiconductors is This is comparable to the popular silicon carbide (SiC). The energy required for seed hot carrier injection is shown in Fig. 8(A). Also, Fig. 8(B) shows CHE injection. , FIG. 8(B) shows DAHC injection. As for CHE injection, the In-Ga-Zn-O system The oxide semiconductor has a slightly higher threshold and is therefore advantageous.

[0131] As mentioned above, the In-Ga-Zn-O oxide semiconductor has a higher hot carrier degradation rate than silicon. It can be seen that the resistance to carbonization and source-drain breakdown is very high. It can be said that the breakdown voltage is comparable to that of silicon.

[0132] <Short-channel effect in transistors using oxide semiconductors> Next, regarding the short-channel effect in a transistor including an oxide semiconductor, FIG. In the following explanation, an ideal situation is assumed for ease of understanding. The following explanations are based on the actual situation and may not reflect the actual situation. I would like to add that this is merely one consideration.

[0133] The short channel effect becomes evident as transistors become smaller (as the channel length (L)) The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and S value. Increase in leakage current, etc.

[0134] Here, we use the results of calculations (device simulation) to suppress short channel effects. Specifically, the carrier concentration and the thickness of the oxide semiconductor layer were investigated. Four models with different channel lengths (L) and threshold voltages (Vth) were prepared. The relationship between the oxide The carrier concentration of the semiconductor is 1.7×10 -8 / cm 3 , or 1.0 × 10 15 / cm 3 of The thickness of the oxide semiconductor layer was either 1 μm or 30 nm. The oxide semiconductor is an In-Ga-Zn-O oxide semiconductor, and the gate insulating layer is a 1 A silicon oxynitride film with a thickness of 0.00 nm was used. The band gap of the oxide semiconductor was set to 3.15 eV, electron affinity 4.3 eV, relative dielectric constant 15, electron mobility 10 cm 2 Assume / Vs The relative dielectric constant of the silicon oxynitride film was assumed to be 4.0. The simulation software "Atlas" was used.

[0135] There was no significant difference in the calculation results between the top gate structure and the bottom gate structure.

[0136] The calculation results are shown in Fig. 9 and Fig. 10. Fig. 9 shows the case where the carrier concentration is 1.7 × 10 -8 / cm 3 In the case of Figure 10, the carrier concentration is 1.0×10 15 / cm 3 This is the case in Fig. 9 and In Fig. 10, a transistor with a channel length (L) of 10 μm is used as a reference. The change in threshold voltage (Vth) when the thickness is changed from 10 μm to 1 μm (ΔVth As shown in Fig. 9, the carrier concentration of the oxide semiconductor is 1.7 × 10 -8 / cm 3 When the thickness of the oxide semiconductor layer is 1 μm, the change in threshold voltage (ΔVt h) had a ΔVth of -3.6 V. As shown in FIG. Carrier concentration is 1.7×10 -8 / cm 3 When the thickness of the oxide semiconductor layer is 30 nm, In the case of the MOS transistor, the change in threshold voltage (ΔVth) was ΔVth=-0.2 V. As shown in Fig. 1, when the carrier concentration of the oxide semiconductor is 1.0 × 10 15 / cm 3 and the oxide When the thickness of the semiconductor layer is 1 μm, the change in threshold voltage (ΔVth) is ΔVth=-3 10, the carrier concentration of the oxide semiconductor was 1.0 ×10 15 / cm 3 When the thickness of the oxide semiconductor layer is 30 nm, the threshold voltage The change (ΔVth) was ΔVth = -0.2 V. This result was obtained using an oxide semiconductor. In the transistor, the short channel effect can be suppressed by reducing the thickness of the oxide semiconductor layer. For example, when the channel length is about 1 μm, the carrier concentration Even if the oxide semiconductor layer has a sufficiently large thickness, it is possible to obtain a short channel if the thickness is set to about 30 nm. It is understood that the Neill effect can be sufficiently suppressed.

[0137] <About carrier concentration> The technical idea of ​​the disclosed invention is to sufficiently reduce the carrier concentration in the oxide semiconductor layer. The aim is to get as close to the intrinsic (i-type) as possible. , and the actually measured carrier concentration will be described with reference to FIG. 11 and FIG. 12. .

[0138] First, we will briefly explain how to calculate the carrier concentration. We fabricated a MOS capacitor and performed CV measurements (Capacitance-Voltage It is possible to obtain the value by evaluating the results of the measurement (CV characteristics) .

[0139] More specifically, the relationship between the gate voltage Vg and the capacitance C of a MOS capacitor is plotted as C -V characteristics are obtained, and the gate voltage Vg and (1 / C) are calculated from the CV characteristics. 2 A graph showing the relationship between Obtain a rough graph and calculate (1 / C) in the weak inversion region. 2 Calculate the differential value of By substituting the value of the carrier concentration N d The magnitude of is calculated. In (1), e is the elementary charge, ε 0 is the dielectric constant of a vacuum, and ε is the relative dielectric constant of an oxide semiconductor. do.

[0140]

number

[0141] Next, the carrier concentration actually measured using the above method is explained. A titanium film was formed on the glass substrate to a thickness of 300 nm, and a titanium nitride film was then formed on the titanium film to a thickness of 100 nm. The titanium nitride film is formed to a thickness of 100 nm, and an In-Ga-Zn-O oxide semiconductor is used on the titanium nitride film. A silicon oxynitride film was formed on the oxide semiconductor layer to a thickness of 300 nm. A sample (MOS crystal) with a thickness of 300 nm was formed on the silicon oxynitride film. The oxide semiconductor layer was made of a metal oxide containing In, Ga, and Zn. Sputtering using a metal target (In:Ga:Zn=1:1:0.5[atom%]) The oxide semiconductor layer was formed in a mixed atmosphere of argon and oxygen. Atmosphere (flow ratio is Ar:O 2 =30(sccm):15(sccm)).

[0142] Figure 11 shows the CV characteristics, and Figure 12 shows the relationship between Vg and (1 / C) 2 The relationship between and is shown in Fig. (1 / C) in the weak inversion region of 12 2 The carrier obtained from the differential value of The concentration is 6.0 x 10 10 / cm 3 It was.

[0143] In this way, an oxide semiconductor that has been made i-type or substantially i-type (for example, an oxide semiconductor having a carrier concentration of 1×10 12 / cm 3 Less than 1×10 11 / cm 3 More preferably, 1.4×10 10 / cm 3 By using a MOSFET with excellent off-state current characteristics, It is possible to obtain stars.

[0144] In this embodiment, a conductive layer containing copper as a main component is used for the first conductive layer and the second conductive layer. As a result, a semiconductor device with reduced wiring resistance can be provided. If the semiconductor device is applied to a large-screen display device or a high-definition display device, the signal This reduces the occurrence of delays in transmission and voltage drops in the power lines, and reduces display issues such as uneven display and poor gradation. It is possible to provide a display device with improved display quality.

[0145] In addition, the carrier concentration is 1×10 12 cm -3 Using an oxide semiconductor layer highly purified to less than By this, a switching element having a positive threshold voltage and a so-called normally-off characteristic is obtained. It can be achieved.

[0146] In addition, oxide semiconductors with a wide band gap of over 2 eV can be used for transistors. By doing so, the off-current can be reduced. For example, I Using n-Ga-Zn-O oxide semiconductor, a reverse bias MOSFET with a channel length of 10 μm was The leakage current at bias is 1×10 -16 A / μm (per 1μm channel width) or less In addition, the ratio of the on-current to the off-current is 10 10 The value is sufficiently large.

[0147] As a result, the semiconductor device consumes no power in the off state and has reduced leakage current, resulting in a power-saving device. It is also possible to provide a semiconductor device having a large ratio of on-current to off-current. It is possible to provide a display device with excellent contrast and high display quality.

[0148] In addition, by using a highly purified oxide semiconductor layer, the field-effect mobility is high and high-speed It is possible to provide a semiconductor device that operates smoothly.

[0149] In addition, the wiring, which mainly contains copper, is sealed with a nitride film, which suppresses copper diffusion. As a result, a highly reliable semiconductor device can be provided.

[0150] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0151] (Embodiment 2) In this embodiment mode, a manufacturing process of the semiconductor device described in the first embodiment mode will be described with reference to FIG. The following description will be given using the cross sections A1-A2, B1-B2, and C1 in FIG. -C2 are shown by the dashed lines A1-A2, B1-B2, and C1-C2 in FIG. FIG.

[0152] First, a base film 101 containing silicon nitride is formed on a substrate 100 to a thickness of preferably 50 nm to 300 nm. The substrate 100 is preferably a glass substrate, a ceramic substrate, or a ceramic substrate. In addition to the laminated substrate, a plastic with sufficient heat resistance to withstand the processing temperature of this manufacturing process is used. In addition, when the substrate does not need to be transparent, a stainless steel alloy can be used. The substrate may be a metal substrate having an insulating film formed on the surface thereof. For example, barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass It is recommended to use a non-alkali glass substrate such as quartz or sapphire. The substrate 100 may be a 3rd generation (550 mm×650 mm) 3.5 generation (600mm x 720mm, or 620mm x 750mm), 4th generation (6 80mm x 880mm, or 730mm x 920mm, 5th generation (1100mm x 1 300mm), 6th generation (1500mm x 1850mm), 7th generation (1870mm x 2 200mm), 8th generation (2200mm x 2400mm), 9th generation (2400mm x 2 800mm, 2450mm x 3050mm, 10th generation (2950mm x 3400mm) ) or other glass substrates can be used.

[0153] In this embodiment, aluminoborosilicate glass is used for the substrate 100 .

[0154] The base film 101 may be formed of a silicon nitride film or a silicon nitride oxide film in a single layer or a laminated layer. The undercoat film 101 can be formed by appropriately using a sputtering method, a CVD method, a coating method, a printing method, or the like. The film may be doped with phosphorus (P) or boron (B).

[0155] In this embodiment, a silicon nitride film having a thickness of 100 nm is formed on the undercoat film 101 by the PCVD method. Use.

[0156] Next, a gate electrode 111a, a storage capacitor line 111b, and a gate line 111c are formed. First, a metal film is formed on the undercoat film 101 by sputtering, vacuum deposition, or plating. Cu with a thickness of 100 nm to 500 nm, preferably 200 nm to 300 nm A first conductive layer including the above-mentioned is formed on the conductive layer by photolithography or ink jet printing. A mask is formed by a photolithography method or the like, and the first conductive layer is etched using the mask to form a gate electrode. The electrode 111a, the storage capacitor wiring 111b, and the gate wiring 111c are formed on the base film 101. In order to improve the adhesion between the first conductive layer and the base film 101, the first conductive layer in contact with the base film 101 is provided with W, T a. Metal layers using Mo, Ti, Cr, etc., or alloy layers combining these, if Alternatively, nitrides or oxides of these may be formed.

[0157] In addition, when the resist mask is formed by the inkjet method, a photomask is not used. This reduces manufacturing costs. In addition, the conductive nanopaste such as copper is applied by the inkjet method. The gate electrode 111a, the storage capacitor wiring 111b, and the like can be inexpensively formed by discharging the material onto a substrate and baking it. The gate wiring 111c can be formed.

[0158] In this embodiment, a Cu film having a thickness of 250 nm is formed on the undercoat film 101. The Cu film is selectively etched using a resist mask formed in the lithography process to form a gate. A storage electrode 111a, a storage capacitor line 111b, and a gate line 111c are formed.

[0159] Next, a first insulating layer 102 is formed. The first insulating layer 102 functions as a gate insulating layer. The first conductive layer and the undercoat film 101 are formed with a thickness of 50 nm to 800 nm, preferably 100 nm. The film is formed to a thickness of 600 nm or more.

[0160] In this embodiment mode, a silicon nitride layer is formed on the first conductive layer and the base film 101 by sputtering. (SiN y (y>0) is deposited to form a first insulating layer 102 having a thickness of 100 nm.

[0161] Note that an oxide semiconductor (high purity) that has been made i-type or substantially i-type by removing impurities is Since the insulating film (a highly-doped oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface between the oxide semiconductor and the insulating film is important. It is required to

[0162] For example, high-density plasma CVD using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is preferable because it allows the formation of a high-quality insulating film with high purity oxide semiconductor and high-quality gate. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0163] In addition, the insulating film obtained by the high density plasma CVD device can be formed with a consistent thickness. In addition, the insulating film obtained by the high-density plasma CVD apparatus has excellent step coverage. In this specification, the high density plastic film can precisely control the thickness of the thin film. The Zuma CVD system is 1×10 11 / cm 3 This refers to equipment that can achieve a plasma density of 1000 MPa or higher.

[0164] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other deposition methods such as the plasma CVD method and the like can be applied. Even if the insulating film has a gate insulating film quality and an interface property with an oxide semiconductor that are modified by In any case, the quality of the gate insulating film is good, and the oxidation Any material may be used as long as it can reduce the interface state density with the solid semiconductor and form a good interface.

[0165] Next, the oxide semiconductor film 103 is formed. The thickness of the oxide semiconductor film 103 is On the layer 102, 5 nm to 200 nm, preferably 10 nm to 20 nm, (See Figure 13(A)).

[0166] In this embodiment, an In-Ga-Zn-O based oxide semiconductor target is used as the oxide semiconductor film. A 15 nm thick In-Ga-Zn-O non-single crystal film was formed by sputtering using a do.

[0167] Note that before the oxide semiconductor film 103 was formed, argon gas was introduced to generate plasma. In this way, dust adhering to the surface of the first insulating layer 102 can be removed. Reverse sputtering is a process in which a voltage is applied to a substrate using an RF power source in an argon atmosphere. This is a method of modifying the surface by forming plasma. Note that nitrogen and helium are used instead of argon atmosphere. In addition, oxygen, N 2 With the addition of O etc. Alternatively, Cl may be added to the argon atmosphere. 2 , C.F. 4 You can also add some atmosphere to it. After the reverse sputtering process, the oxide semiconductor film is formed without being exposed to the air. In this case, it is possible to prevent dust and moisture from being attached to the interface between the insulating layer 102 and the oxide semiconductor film 103. can.

[0168] The oxide semiconductor film is an In-Sn-Ga-Z quaternary metal oxide described in Embodiment 1. nO-based oxide semiconductors and In-Ga-Zn-O-based oxide semiconductors, which are ternary metal oxides , In-Sn-Zn-O oxide semiconductor, In-Al-Zn-O oxide semiconductor, Sn- Ga-Zn-O oxide semiconductor, Al-Ga-Zn-O oxide semiconductor, Sn-Al-Z nO-based oxide semiconductors, In-Zn-O-based oxide semiconductors, which are binary metal oxides, and Sn -Zn-O based oxide semiconductor, Al-Zn-O based oxide semiconductor, Zn-Mg-O based oxide semiconductor Conductors, Sn-Mg-O oxide semiconductors, In-Mg-O oxide semiconductors, and In-O oxides For example, a Zn-O-based oxide semiconductor, a Sn-O-based oxide semiconductor, or a Zn-O-based oxide semiconductor can be used. The oxide semiconductor film may contain silicon oxide. The previously mentioned InMO 3 (ZnO) mA thin film represented by (m>0) can be used.

[0169] The oxide semiconductor film is heated under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or Formed by sputtering in an atmosphere of rare gas (typically argon) and oxygen In addition, when the sputtering method is used, SiO 2 Contains 2% by weight or more and 10% by weight or less The oxide semiconductor film is deposited using a target, and the oxide semiconductor film is formed using a SiOx (X>0) may be included.

[0170] Here, an oxide semiconductor target containing In, Ga, and Zn (with a molar ratio of In 2 O 3 :Ga 2 O 3 :ZnO=1:1:1, or In 2 O 3 :Ga 2 O 3 :ZnO=1:1: 2), the distance between the substrate and the target was set to 100 mm, the pressure was 0.6 Pa, and the direct current (D C) The film is formed in an oxygen atmosphere (oxygen flow rate 100%) with a power of 0.5 kW. A direct current (DC) power supply is preferred because it reduces the generation of dust and reduces the film thickness distribution. It is.

[0171] In this case, it is preferable to form the oxide semiconductor film while removing residual moisture in the treatment chamber. It is preferable that the oxide semiconductor film does not contain hydrogen, a substance having a hydroxyl group, or moisture. This is why.

[0172] The multi-chamber sputtering apparatus used in this embodiment is a silicon or silicon oxide sputtering apparatus. The device is equipped with a target for an oxide semiconductor film and a target for a base material (artificial quartz). The deposition chamber in which the oxide semiconductor film target is provided has a cryopump as an exhaust means. In addition, a turbo molecular pump is used instead of a cryopump, and the turbo molecular pump A cold trap may be provided on the intake of the pump to adsorb moisture. .

[0173] The deposition chamber evacuated using a cryopump contains, for example, hydrogen atoms and H 2 Hydrogen atoms such as O Since compounds containing carbon atoms and compounds containing carbon atoms are exhausted, the film is formed in the film formation chamber. By using this method, the concentration of impurities in the oxide semiconductor film can be reduced.

[0174] Note that the oxide semiconductor film is preferably formed successively over the first insulating layer 102.

[0175] The sputtering gas used in forming the oxide semiconductor film is hydrogen, water, a substance having a hydroxyl group, Or high-purity gas in which impurities such as hydrides have been removed to a concentration of ppm or ppb. It is preferable to use a .

[0176] The oxide semiconductor film may be formed while the substrate is heated. The temperature is set to 200°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor film, the concentration of impurities in the oxide semiconductor film can be reduced. do.

[0177] There are two types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal conductive films. It is used in such cases.

[0178] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of films in the same chamber. It is also possible to form a film by discharging two or more materials at the same time.

[0179] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There is a sputtering apparatus that uses this method.

[0180] In addition, in a film formation method using a sputtering method, a target material and a sputtering gas component are mixed during film formation. Reactive sputtering is a method of forming thin films of compounds by chemically reacting them with each other, and There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0181] Next, a second photolithography process is performed to form a resist mask and an In-Ga-Z The oxide semiconductor film 103 made of an nO-based non-single crystal film is etched into islands. For example, organic acids such as citric acid and oxalic acid can be used as etching agents. The edge of the island-shaped oxide semiconductor layer is etched to have a tapered shape, thereby forming a stepped shape. This prevents the line from being broken. Note that the etching method used here is limited to wet etching. However, dry etching may be used.

[0182] Next, a first heat treatment is performed on the substrate provided with the island-shaped oxide semiconductor layer, so that the island-shaped oxide semiconductor layer is The body layers are dehydrated or dehydrogenated.

[0183] In this specification, the heat treatment in an inert gas atmosphere such as nitrogen or a rare gas is referred to as dehydration. This is called heat treatment for dehydrogenation. 2 year Dehydrogenation does not only mean that hydrogen is removed by hydrogenation, but also that H, OH, etc. are removed. For convenience, this process is referred to as dehydration or dehydrogenation.

[0184] In this embodiment, the first heat treatment is performed by heating the substrate on which the island-shaped oxide semiconductor layer is provided. The temperature T is 700°C or less (or a temperature below the distortion point of the glass substrate). Preferably, the first heat treatment is performed at 350° C. or higher and 500° C. or lower for 1 minute or longer and 10 minutes or shorter. Rapid Thermal Anneal (RTA) processing is performed

[0185] In the first heat treatment, the temperature of the substrate is changed over time as shown in FIG.

[0186] In period a-1, the atmosphere including the substrate is a nitrogen atmosphere, and the substrate temperature is raised to T and maintained. After that, the temperature is lowered in a nitrogen atmosphere. In the next period a-2, the atmosphere containing the substrate is first changed from nitrogen to Then, the atmosphere is switched to oxygen or dry air. The substrate temperature is then raised to T and maintained at that temperature. After that, the temperature is lowered in an oxygen or dry air atmosphere.

[0187] The processing in period a-1 and the processing in period a-2 may be performed by different devices. By performing processes in parallel using different equipment, process times can be reduced.

[0188] In the first heat treatment, the temperature of the substrate is changed over time as shown in FIG. It may be allowed.

[0189] In period b-1, the atmosphere including the substrate is a nitrogen atmosphere, and the substrate temperature is raised to T and maintained. In the next period b-2, the substrate temperature is maintained at T, and the atmosphere containing the substrate is changed from nitrogen to oxygen. Alternatively, the atmosphere is switched to dry air, and the substrate temperature is maintained at T, after which oxygen or dry air is The temperature may be lowered by atmospheric pressure.

[0190] In addition, if the processing in period b-1 and the processing in period b-2 are performed in the same equipment, This is preferable because it can shorten the transportation time.

[0191] The inert gas atmosphere used in the first heat treatment is nitrogen or a rare gas (helium, nitrogen, etc.). The atmosphere is mainly composed of oxygen (carbon, argon, etc.), and does not contain water, hydrogen, etc. Alternatively, the purity of the inert gas introduced into the heat treatment device is preferably 6N (99 .9999%) or more, preferably 7N (99.99999%) or more (i.e. impurity concentration It is preferable to set the concentration to 1 ppm or less, and more preferably 0.1 ppm or less.

[0192] In addition, the oxygen and dry air introduced into the heat treatment device are high-purity oxygen gas and or ultra-dry air (dew point below -40°C, preferably below -60°C). .

[0193] In addition, when the oxide semiconductor layer is dehydrated or dehydrogenated, the oxide semiconductor layer is It is important not to expose it to the atmosphere and not to recontaminate it with water or hydrogen.

[0194] The heat treatment device for the first heat treatment is an electric furnace or a heat treatment device using a medium such as a heated gas. It may be a device that heats the workpiece by conduction or thermal radiation. For example, a GRT A (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid Thermal Annealing (RTA) equipment The LRTA device uses halogen lamps, Tal halide lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps The material to be treated is heated by the radiation of light (electromagnetic waves) emitted from lamps such as high-pressure mercury lamps. It is a heating device.

[0195] By using the RTA method, dehydration or dehydrogenation can be performed in a short time, so the strain point of the glass substrate can be reduced. The GRTA device can also process at temperatures above 1000°C. It is a device that performs processing.

[0196] The heat treatment is not limited to this timing, but may be performed before or after the photolithography process or the film formation process. You can do this multiple times.

[0197] The oxide semiconductor layer that has been sufficiently dehydrated or dehydrogenated under the above conditions is analyzed by thermal desorption spectrometry. (TDS: Thermal Desorption Spectroscopy) 45 Even when the temperature was raised to 0°C, two peaks were observed in the spectrum indicating the desorption of moisture, and at least 250-3 One peak that appears near 00°C is not detected.

[0198] Note that the oxide semiconductor layer is amorphous and has many dangling bonds when it is formed. By carrying out the first heat treatment of the dehydration or dehydrogenation treatment, dangling bonds in close proximity are homogenized. The molecules bond together to form an ordered amorphous structure. When the crystals are mixed with the amorphous material, a mixture of amorphous and microcrystalline regions is formed, with the microcrystalline regions interspersed with the amorphous regions.

[0199] In addition, the first heat treatment in nitrogen causes dehydration or dehydrogenation, and oxygen deficiency. The oxide semiconductor layer becomes low-resistance, that is, N-type (N - cation, N + For example, By the first heat treatment in nitrogen, the oxide semiconductor layer has a higher carrier density than immediately after the deposition. The concentration is increased, preferably to 1 × 10 18 / cm 3 The carrier concentration is equal to or greater than 100 nm.

[0200] However, N-type (N - cation, N + The oxide semiconductor layer that has been oxidized or annealed is placed in an oxygen or dry air atmosphere. The material is heated and cooled in an atmosphere, and oxygen is supplied to the oxygen-deficient areas. The oxide semiconductor layer thus formed has a high resistance, that is, is an i-type oxide semiconductor layer.

[0201] Through these steps, the oxide semiconductor layers 113a and 113b are highly purified. A transistor manufactured using the polymerized oxide semiconductor layer 113a has a positive threshold voltage Thus, a switching element having a so-called normally-off characteristic can be realized.

[0202] Among the electrical characteristics of a transistor, the threshold voltage (Vth) is particularly important. Even if the effective mobility is high, the threshold voltage is high, or the threshold voltage is negative. It is difficult to control the threshold voltage as a circuit. In the case of a transistor with a large capacitance, when the driving voltage is low, the transistor cannot switch. This may result in the device being unable to perform its function and may cause a burden.

[0203] In the case of an n-channel transistor, the channel is opened only when a positive voltage is applied to the gate. It is desirable to have a transistor in which a drain current flows out. There are transistors in which a channel does not form even under negative voltage conditions, and transistors in which a channel forms even under negative voltage conditions A transistor that has an in-current is not suitable for use in a circuit. If the threshold voltage of a transistor is negative, the source voltage is In this case, a current flows between the gate and drain electrodes, which is called a normally-on characteristic.

[0204] In active matrix display devices, the electrical characteristics of the transistors that make up the circuits The electrical characteristics of the transistors are important, and they determine the performance of the display device. If a positive threshold voltage as close as possible to 0V is applied to the gate, a channel is formed. It is desirable for the display device to have such a configuration.

[0205] Note that the first heat treatment of the oxide semiconductor layer is performed on the oxide semiconductor layer before it is processed into an island-shaped oxide semiconductor layer. The semiconductor film 103 may be subjected to the first heat treatment. In that case, the semiconductor film 103 may be removed from the heating device after the first heat treatment. The substrate is taken out and a photolithography process is carried out to process the substrate into an island-shaped oxide semiconductor layer. .

[0206] In addition, before forming the second conductive layer containing Cu, the first insulating layer 102 is selectively etched. A contact hole reaching the first conductive layer may be formed by etching the first conductive layer. If the second conductive layer is formed after the contact holes are formed, the contacts can be formed without going through another conductive layer. The first conductive layer and the second conductive layer can be directly connected. Reducing the thickness not only reduces the electrical resistance but also reduces the area occupied by the contact hole. It can be done.

[0207] Next, a second conductive layer containing Cu is formed. The second conductive layer containing Cu is a layer including an oxide semiconductor layer. 113a, 113b, and the first insulating layer are formed by sputtering, vacuum deposition, or By plating, 100 nm to 500 nm, preferably 200 nm to 300 nm Then, a photolithography method or an ink jet method is applied to the conductive layer. A mask is formed by a photolithography method or the like, and the second conductive layer is etched using the mask to form a source. A first electrode 115a, a second electrode 115b, and a source electrode The source wiring 115c is formed.

[0208] In this embodiment, a 2 mm thick insulating film is formed on the oxide semiconductor layers 113a and 113b and the first insulating film. A 50 nm Cu film is formed, and the resist mask formed in the third photolithography process is The Cu film is selectively etched using a SiO 2 film to form a first electrode serving as a source electrode and a drain electrode. The second electrode 115a, the second electrode 115b, and the source wiring 115c are formed.

[0209] Note that the oxide semiconductor layer may be removed in the third photolithography process depending on the etching conditions. In this case, the exposed area of ​​the gate electrode 111a may be etched. The thickness of the oxide semiconductor layer overlapping the first electrode 115a or the second electrode 115b is The thickness of the oxide semiconductor that does not overlap with the first electrode 115a or the second electrode 115b is thin (see FIG. 13(C)).

[0210] Note that the oxide semiconductor layer Copper oxide is generated on the surface of the Cu film that contacts the substrate, but since copper oxide is a semiconductor, it does not affect electrical connection. It's not a barrier.

[0211] Next, the second insulating layer 107 is formed. The second insulating layer 107 is made of at least a silicon nitride film. In order to prevent the highly purified oxide semiconductor layer from being contaminated by impurities such as water and hydrogen, In this case, a method that does not require a high-temperature treatment (such as sputtering) is selected and used.

[0212] In this embodiment, the first electrode 115a, the second electrode 115b, the source line 115c, A silicon nitride film is formed as a second insulating layer 107 in contact with the first insulating layer 102 and the oxide semiconductor layer. Base layer (SiN y (y>0)) is formed. y (y>0) is, for example, A silicon nitride target is sputtered in a rare gas (e.g., argon gas) using RF sputtering. A film with a thickness of 400 nm is formed.

[0213] The silicon nitride film is formed by sputtering using high purity gas and a cryopump. The sputtering is performed using a sputtering apparatus. Note that the nitride insulating film formed by the sputtering method is particularly dense. It can be used as a single layer as a protective film to suppress the diffusion of impurities into adjacent layers. It is possible.

[0214] At this stage, a region where the oxide semiconductor layer and the second insulating layer 107 are in contact with each other is formed. The oxide semiconductor layer is sandwiched between the first insulating layer 102 and the second insulating layer 107 and overlaps the base electrode. The conductive layer region becomes a channel forming region. The second insulating layer 107 also serves as a channel protection layer. (See Figure 13(D)).

[0215] Next, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature is 200°C or more and 400°C or less, preferably 250°C or more and 350°C or less. For example, the heat treatment may be performed at 250° C. for 1 hour in a nitrogen atmosphere. It is possible to reduce variation in electrical characteristics of the transistors. After the formation of the second insulating layer 107, the second heat treatment is performed. The cutting is not particularly limited as long as it is performed after the first heat treatment.

[0216] Next, the third insulating layer 108 is formed. The third insulating layer 108 has a thickness of 50 nm to 300 nm. The third insulating layer 108 is preferably formed to a thickness of 100 nm or more and 200 nm or less. The method for forming the insulating film is not particularly limited, and may be, for example, a sputtering method, a SOG method, a spin coating method, or the like, depending on the material. , dip, spray coating, droplet ejection method (inkjet method, screen printing, offset Printing, etc.) can be used.

[0217] When the third insulating layer 108 is formed by applying a material liquid and baking it, the second oxide semiconductor layer The heat treatment (200°C to 400°C, preferably 250°C to 350°C) is performed. The baking step of the third insulating layer 108 and the annealing step of the oxide semiconductor layer may be performed. By combining these functions, a semiconductor device can be manufactured efficiently.

[0218] Next, a contact hole for connecting the second electrode 115b and the first pixel electrode 109 is formed. 128 is formed on the second insulating layer 107 and the third insulating layer 108. A mask is formed on the substrate by photolithography or ink jet printing, and the mask is used to The second insulating layer 107 and the third insulating layer 108 are selectively etched to form contact holes. In this embodiment, the resist formed in the fourth photolithography step is The second insulating layer 107 and the third insulating layer 108 are selectively etched using a mask, A contact hole 128 is formed.

[0219] Next, the first pixel electrode 109 is formed. First, the third insulating layer 108 and the contact A conductive material having transparency to visible light is connected to the second electrode 115b through the hole 128. The film is formed to a thickness of 30 nm to 200 nm, preferably 50 nm to 100 nm. The conductive film is formed by a sputtering method, a vacuum deposition method, or the like. Alternatively, a mask is formed by an ink-jet method or the like, and the conductive film is etched using the mask. The first pixel electrode 109 is formed by etching.

[0220] In this embodiment, an indium carbide film having a thickness of 80 nm is used as a conductive film having a property of transmitting visible light. A layer of indium tin oxide (ITO) is formed, and then a fifth photolithography process is performed. The conductive film having a light transmitting property to visible light is selectively etched using the resist mask. Thus, the first pixel electrode 109 is formed (see FIG. 13(E)).

[0221] As the conductive film that transmits visible light, indium oxide containing tungsten oxide, oxide Indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium, ITO, indium zinc oxide, silicon oxide A conductive material such as indium tin oxide can be used.

[0222] In addition, the conductive film that transmits visible light is made of conductive polymers containing conductive polymers. The pixel electrode formed by using the conductive composition can be formed by the following steps. The resistance is 10,000Ω / ohm or less, and the light transmittance at a wavelength of 550 nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that:

[0223] In this embodiment, hydrogen atoms and H are generated using high purity gas and a cryopump. 2 O etc. The oxide semiconductor layer is formed by removing impurities, typically compounds containing hydrogen atoms. 1. An oxide semiconductor having a reduced carrier concentration by being highly purified through the heat treatment of As a result, an i-type or substantially i-type oxide semiconductor (e.g., Carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 (below) This makes it possible to fabricate transistors with extremely excellent off-state current characteristics. We can provide the star.

[0224] In this embodiment, the dehydration or dehydration in the inert gas atmosphere of the first heat treatment is The oxygen deficiency is replenished by oxygen or dry air in succession. This allows the process time to be shortened.

[0225] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0226] (Embodiment 3) In this embodiment, a form of a circuit board of a display device having a different configuration from that of the first embodiment is described as follows. This will be explained using FIG.

[0227] The structure of a pixel provided in a display device is shown in FIG. 15. FIG. 15(A) shows the planar structure of a pixel. FIG. 15(A) is a cross-sectional view showing the layered structure of a pixel, and FIG. 15(B) is a cross-sectional view showing the layered structure of a pixel. The dashed lines A1-A2, B1-B2, and C1-C2 in FIG. A2, cross section B1-B2, and cross section C1-C2, respectively.

[0228] The cross section A1-A2 shows the stacked structure of a transistor 152 used in a pixel portion. The transistor 152 is an embodiment of a bottom gate structure.

[0229] Also, the cross section B1-B2 shows the laminated structure of a capacitance section formed in a pixel section.

[0230] Also, the cross section C1-C2 shows the laminated structure at the intersection of the gate wiring and the source wiring.

[0231] The circuit board of the display device exemplified in this embodiment is the same as that of the display device exemplified in the first embodiment. A circuit board, a first insulating layer 102, a second insulating layer 107, and a second conductive layer The configuration is different. Also, the configuration of the intersection of the gate wiring and the source wiring is different.

[0232] Specifically, the first insulating layer 102 is a laminate of an insulating layer 102a and an insulating layer 102b. The insulating layer 107 is a laminate of an insulating layer 107a and an insulating layer 107b. The layer containing copper as a main component is in contact with the barrier layer. At the intersection of the wiring, the gate wiring 111c formed of the first conductive layer and the gate wiring 111b formed of the second conductive layer The first insulating layer 102 is sandwiched between the source wirings 115c to be formed.

[0233] The circuit board of the display device exemplified in this embodiment is the same as that of the display device exemplified in the first embodiment. A circuit board, a first insulating layer 102, a second insulating layer 107, and a second conductive layer The barrier layer in contact with the layer containing copper as the main component, and the structure of the intersection between the gate wiring and the source wiring Since the other components are the same, detailed description will be omitted here.

[0234] In this embodiment, the first insulating layer 102 is made of two layers. The insulating layer 102a on the side in contact with the conductive layer and the base film 101 is made of silicon nitride (SiN y (y>0) The insulating layer 102b on the side in contact with the oxide semiconductor layer is made of silicon oxide (SiO x (x>0) The thickness of the first insulating layer 102 is set to 100 nm.

[0235] The first insulating layer 102 functions as a gate insulating layer, and is formed on the first conductive layer and the base film 101 in a 5-layer structure. The thickness of the film is 0 nm or more and 800 nm or less, preferably 100 nm or more and 600 nm or less. .

[0236] Between the two silicon nitride films of the undercoat film 101 and the insulating layer 102a, a first layer containing copper as a main component is formed. By forming the conductive layer, the diffusion of copper can be suppressed.

[0237] Note that an oxide semiconductor (high purity) that has been made i-type or substantially i-type by removing impurities is Since the insulating layer (a highly polymerized oxide semiconductor) is extremely sensitive to the interface state and the interface charge, The interface with the film is important. Therefore, the insulating layer 102b in contact with the highly purified oxide semiconductor is There is a demand for higher quality.

[0238] For example, high-density plasma CVD using microwaves (2.45 GHz) produces dense, high-insulation-voltage This is preferable because it allows the formation of a high-quality insulating film with high purity oxide semiconductor and high-quality gate. By closely contacting the insulating film, the interface state is reduced and the interface characteristics are improved. Because it is possible.

[0239] In addition, the insulating film obtained by the high density plasma CVD device can be formed with a consistent thickness. In addition, the insulating film obtained by the high-density plasma CVD apparatus has excellent step coverage. can precisely control the thickness of thin films.

[0240] Of course, if a good quality insulating film can be formed as a gate insulating film, sputtering is also possible. Other deposition methods such as the plasma CVD method and the like can be applied. Even if the insulating film has a gate insulating film quality and an interface property with an oxide semiconductor that are modified by In any case, the quality of the gate insulating film is good, and the oxidation Any material may be used as long as it can reduce the interface state density with the solid semiconductor and form a good interface.

[0241] In this embodiment, the insulating layer 102b is formed using a high density plasma CVD apparatus (referred to as "high density plasma CVD apparatus" in this specification). High density plasma CVD equipment is 1×10 11 / cm 3 A device that can achieve plasma densities of 1000 times higher In the case of the plasma generation method, for example, a microwave power of 3 kW to 6 kW is applied to generate a plasma. is generated to form an insulating film.

[0242] The chamber was filled with monosilane gas (SiH 4 ) and nitrous oxide (N 2 O) and rare A gas is introduced to generate high-density plasma under a pressure of 10 Pa to 30 Pa, and the plasma is then heated to form a dielectric material such as glass. An insulating film is formed on the substrate having an edge surface. Then, the supply of monosilane gas is stopped and a large amount of Nitrous oxide (N2 O) and rare gas are introduced to perform plasma treatment on the insulating film surface. At least nitrous oxide (N 2 O) and rare gas are introduced onto the insulating film surface. The plasma treatment is performed after the deposition of the insulating film. It is an insulating film that can ensure reliability even if it is thin, for example, less than 100 nm. do.

[0243] When forming the insulating layer 102b, monosilane gas (SiH 4 ) and suboxide Nitrogen (N 2 The flow ratio of the gas to the chamber (O) should be in the range of 1:10 to 1:200. The rare gas introduced into the reactor may be helium, argon, krypton, xenon, or the like. Among these, it is preferable to use argon, which is inexpensive.

[0244] In addition, the insulating film obtained by the high-density plasma device can be formed with a consistent thickness. The insulating film obtained by the high-density plasma device has excellent step coverage. The thickness can be precisely controlled.

[0245] The insulating film obtained by the above process sequence is different from the insulating film obtained by the conventional parallel plate type PCVD apparatus. The etching rates are significantly different when comparing the etching rates using the same etchant. The insulating film obtained by the parallel plate type PCVD equipment is 10% or more or 20% slower and more efficient. The insulating film obtained using a high-density plasma device can be said to be a dense film.

[0246] In addition, a silicon oxide layer is formed as the insulating layer 102b by a CVD method using an organic silane gas. It is also possible to form a silane gas. i(OC 2 H 5 ) 4 ), tetramethylsilane (TMS: chemical formula Si(CH 3 ) 4 ), Tet Tetramethylcyclotetrasiloxane (TMCTS), Octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH( O.C. 2 H 5 ) 3 ), trisdimethylaminosilane (SiH(N(CH 3 ) 2 ) 3 ) etc. A recombinant compound can be used.

[0247] In this embodiment mode, the layer of the second conductive layer containing copper as a main component is in contact with the barrier layer. The barrier layer is made of conductive metal nitride, tantalum nitride. The first electrode 115a, the second electrode 115b, and the source wiring 11 5c has a structure in which a layer containing copper as a main component is laminated between tantalum nitride.

[0248] The barrier layer may be formed using a material that inhibits copper diffusion, and metal nitrides are particularly preferred. In addition, the first insulating layer 102 or the second insulating layer 10 in contact with the layer containing copper as a main component If 7 is a metal nitride, it may have a structure in which it also functions as a barrier layer.

[0249] In particular, the barrier layer in contact with the oxide semiconductor layer 113a is formed using a conductive metal nitride. For example, titanium nitride, tantalum nitride, tungsten nitride, etc. can be used for the barrier layer. The oxide semiconductor layer 113a and the second conductive layer, which is mainly made of copper, are formed through a conductive barrier layer. By stacking a layer containing copper as a component, the oxide semiconductor layer 113a and the layer containing copper as a main component of the second conductive layer can be electrically connected.

[0250] A barrier layer for a second conductive layer is formed over the oxide semiconductor layer 113a and the first insulating layer 102. A layer containing copper as a main component is formed on the barrier layer. 100nm to 500nm using a tarnishing method, vacuum deposition method, plating method, etc. Preferably, the insulating film is formed to a thickness of 200 nm or more and 300 nm or less.

[0251] Next, a mask is formed on the second conductive layer by photolithography, inkjet printing, or the like. and then etching is performed using the mask to form a layer that functions as a source electrode and a drain electrode. A first electrode 115a, a second electrode 115b, and a source wiring 115c are formed.

[0252] In this embodiment, the second insulating layer 107 has a laminated structure of an insulating layer 107a and an insulating layer 107b. The barrier layer of the second conductive layer and the insulating layer 107a in contact with the oxide semiconductor layer are formed of silicon oxide. (SiO x (x>0) layer, and insulating layer 107b in contact with insulating layer 107a is formed with a thickness of 40 0nm silicon nitride (SiN y (y>0) layer.

[0253] The second insulating layer 107 is formed by removing water, hydrogen, and the like so as not to contaminate the highly purified oxide semiconductor layer. A method that does not introduce impurities (such as sputtering) is selected and used.

[0254] The insulating layer 107a is made of a columnar polycrystalline B-doped silicon target (resistance 0.01 mm) with a purity of 6N. The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 1.01 Ωcm. Pulse was measured under an oxygen atmosphere (oxygen flow rate 100%) with a pressure of 0.4 Pa and a direct current (DC) power of 6 kW. The film is formed by DC sputtering. The film thickness is 300 nm.

[0255] The substrate temperature during film formation may be from room temperature to 300° C., and in this embodiment, it is set to 100° C. do.

[0256] The silicon oxide layer is formed by sputtering using high purity gas and a cryopump. This is done using a sputtering device. Also, under a rare gas (typically argon) atmosphere, oxygen It can be carried out under atmospheric conditions or under an atmosphere of rare gas (typically argon) and oxygen. Note that the oxide insulating film formed by the sputtering method is particularly dense, and impurities may enter the adjacent layer. It can be used even as a single layer as a protective film to suppress the diffusion phenomenon.

[0257] In addition, a silicon oxide target or a silicon target can be used as the target. In addition, phosphorus (P) or boron (B) doped targets are used to deposit phosphorus ( P) and boron (B) can also be added.

[0258] In the case where an oxide insulating film is formed in the insulating layer 107a in contact with the oxide semiconductor layer, for example, Silicon oxide (SiO x (x>0)) layer, the silicon target It is preferable to perform sputtering using a silicon target under an oxygen and rare gas atmosphere. The silicon oxide film formed by this method has dangling bonds of silicon or oxygen atoms. Contains a lot of it.

[0259] The impurities remaining in the oxide semiconductor layer are dangling bonds of silicon atoms or oxygen atoms. The oxide semiconductor is diffused into the insulating layer 107a containing a large amount of the bond and is fixed therein. Hydrogen atoms contained in the layer, H 2 Compounds containing hydrogen atoms such as O diffuse into the insulating layer 107a. The molecules become more mobile and are fixed to the insulating layer 107a.

[0260] At this stage, a region where the oxide semiconductor layer and the insulating layer 107a are in contact with each other is formed. A region of the oxide semiconductor layer that overlaps with the electrode and is in contact with and sandwiched between the insulating layer 102b and the insulating layer 107a The second insulating layer 107 functions as a channel protection layer. .

[0261] In this embodiment, the insulating layer 107b is formed by RF sputtering.

[0262] In this embodiment mode, a structure in which a layer containing copper as a main component of the second conductive layer is in contact with a barrier layer is provided. In addition, the oxide semiconductor is formed through a conductive barrier layer. By laminating a layer containing copper as the main component of the first conductive layer and a layer containing copper as the main component of the second conductive layer, the diffusion of copper is suppressed. In addition, the oxide semiconductor layer and the second conductive layer containing copper as a main component can be electrically connected to each other.

[0263] By using an oxide insulating layer for the second insulating layer on the side in contact with the oxide semiconductor layer, The oxygen deficiency in the conductor layer can be reduced.

[0264] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. .

[0265] (Embodiment 4) In this embodiment, a pair of electrodes is provided above and below a channel formation region of an oxide semiconductor layer with an insulating film interposed therebetween. An example of constructing an inverter circuit using two transistors with a four-terminal structure with polar layers is shown below. The following description will be given with reference to FIG. 16. The transistor shown in FIG. 16A is the same as that shown in FIG. The transistor 151 in this embodiment can be manufactured by the same method as that of the transistor 151 in this embodiment. The data circuit can be used as a driver circuit for driving a pixel portion.

[0266] The driving circuit for driving the pixel unit is arranged, for example, around the pixel unit, and includes an inverter circuit, The inverter circuit is constructed using capacitance, resistance, etc. One type of inverter circuit has two n-channel transistors. For example, enhancement type transistors are formed by combining enhancement type transistors. and a depletion type transistor (hereinafter referred to as EDMOS circuit) (hereinafter referred to as EEMOS circuit) and those formed by enhancement type transistors. There is a road called a "road."

[0267] A cross-sectional structure of the inverter circuit of the driver circuit is shown in FIG. A is a gate electrode 421 formed of a first conductive layer on a substrate 400 and an undercoat film on the undercoat film. a, and includes a channel forming region on the gate electrode 421a in contact with the first insulating layer 402. The gate electrode 421a is formed using a second conductive layer. The first electrode 455a and the second electrode 455b are in contact with the oxide semiconductor layer 404a and overlap each other at their ends. The first electrode 455a and the second electrode 455b are connected to the first transistor 55a. The first electrode 455a functions as a source electrode or a drain electrode of the first electrode 440A. A second insulating layer 402 is formed over the second electrode 455b, the first insulating layer 402, and the oxide semiconductor layer 404a. The semiconductor device has an insulating layer 428 and an electrode 422a made of a third conductive layer on the second insulating layer 428. do.

[0268] The second transistor 440B is formed of an undercoat film on the substrate 400 and a first conductive layer on the undercoat film. A gate electrode 421b is formed on the first insulating layer 402. The second conductive layer 404b includes an oxide semiconductor layer 404b including a channel formation region. The third electrode is disposed on the gate electrode 421b and overlaps with an end portion of the gate electrode 421b. The third electrode is in contact with the oxide semiconductor layer 404b. The third electrode 455c and the fourth electrode 45 5d functions as a source or drain electrode of the second transistor 440B. In addition, the third electrode 455c, the fourth electrode 455d, the first insulating layer 402, and the oxide semiconductor A second insulating layer 428 is provided on the conductive layer 404b. A third conductive layer is provided on the second insulating layer 428. The electrode 422b is made up of the following:

[0269] The first transistor 440A and the second transistor 440B are connected to the second wiring 410b. The second electrode 455b and the third electrode 455c are connected via the 455c is connected to the gate electrode of the second transistor 440B through the contact hole 408. It is connected to 421b.

[0270] The first transistor 440A and the second transistor 440B are the same as those in the second embodiment. Since the first insulating layer 402 can be formed, detailed description of the manufacturing method thereof will be omitted. After forming the contact hole 408, a second conductive layer is provided. The second wiring 410b and the gate electrode 421b are directly connected to the third electrode 455c via the gate electrode 421b. Since the number of contact holes required for the connection is small, the electrical resistance is low. Not only can the size of the contact hole be reduced, but the area occupied by the contact hole can also be reduced. The first electrode 455b, the third electrode 455c, and the second wiring 410b are formed of the second conductive layer. and electrically connected.

[0271] A first wiring 410a connected to a first electrode 455a of the first transistor 440A is a power supply line (negative power supply line) to which a negative voltage VDL is applied. This power supply line is connected to the ground potential. It may also be a power supply line (ground power supply line).

[0272] In addition, a third wiring 44 connected to a fourth electrode 455d of the second transistor 440B Reference numeral 10c denotes a power supply line (positive power supply line) to which a positive voltage VDH is applied.

[0273] A top view of the inverter circuit of the driver circuit is shown in FIG. , the cross section taken along the chain line Z1-Z2 corresponds to FIG. 16(A).

[0274] The equivalent circuit of the EDMOS circuit is shown in Figure 16(B). The circuit connection shown in Figure 16(A) is 16B, the first transistor 440A is an enhancement type n-channel The second transistor 440B is a depletion-type n-channel transistor. In this example, the OS represents an oxide semiconductor. This indicates that the transistor uses a ferroelectric conductor.

[0275] In this embodiment, the threshold voltages of the first transistor 440A and the second transistor 440B are In order to control the value, an insulating film is formed on a channel formation region of a highly purified oxide semiconductor layer. An electrode made of a third conductive layer provided as a second conductive layer is used. A is an enhancement type and the second transistor 440B is a depletion type. A voltage is applied to each of the electrodes 422a and 422b.

[0276] In addition, in FIG. 16(A) and FIG. 16(C), the second wiring 410b is formed on the first insulating layer 402. 4 shows an example in which the gate electrode 421b is directly connected to the contact hole 408 formed in the However, this is not particularly limited, and a connecting electrode may be separately provided to connect the second wiring 410b and the gate electrode 421. b may be electrically connected to

[0277] As described above, an electrode layer is disposed on the channel formation region of the oxide semiconductor layer via an insulating film. By using this, the threshold voltage of the transistor can be controlled and an inverter circuit can be constructed. By controlling the threshold voltage of a transistor, it is possible to obtain an enhancement effect without forming separate oxide semiconductor films. Since it is possible to fabricate both depletion-type and back-type transistors on the same substrate, The process is simple.

[0278] In addition, a transistor having high field-effect mobility using a highly purified oxide semiconductor and By using copper wiring with high conductivity, an inverter circuit with excellent dynamic characteristics can be provided.

[0279] This embodiment mode can be freely combined with other embodiment modes.

[0280] (Embodiment 5) In this embodiment, a pixel portion, a transistor included in the pixel portion, and a pixel region are formed on the same substrate. An example of fabricating at least a part of a driving circuit for driving the above will be described below.

[0281] The pixel portion and the transistors arranged in the pixel portion are formed according to any one of the first to third embodiments. The transistors described in any of the embodiments 1 to 3 are n-channel transistors. Since the driver circuit is a transistor, it can be composed of n-channel transistors. A part of the driver circuit is formed over the same substrate as the transistors in the pixel portion.

[0282] An example of a block diagram of an active matrix display device is shown in FIG. A pixel portion 5301, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, and a third scanning line driver circuit 5304 are provided on a substrate 5300. The pixel portion 5301 includes a signal line driver circuit 5303 and a signal line driver circuit 5304. is arranged extending from a signal line driver circuit 5304, and a plurality of scanning lines are arranged in a first scanning line driver circuit The scanning lines and the signal line driver circuit 5303 are arranged. At the intersections of the lines, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is a flexible printed circuit board (FPC). It is connected to a timing control circuit 5305 (also called a controller or control IC) via a connection part such as The NI 8110 is connected to the

[0283] In FIG. 17A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The signal line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. This reduces the number of external components such as drive circuits, and therefore reduces costs. In addition, when a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the wiring The number of connections increases. If a driver circuit is provided on the same board 5300, the number of connections between the wiring can be reduced. This can reduce the amount of damage, thereby improving reliability and yield.

[0284] The timing control circuit 5305 is, for example, A first scanning line driving circuit start signal (GSP1), a scanning line driving circuit clock signal (GCK1). The timing control circuit 5305 also supplies the second scanning line driving circuit For example, the second scanning line driver circuit start signal (GSP2) (start The signal line supplies the clock signal (GCK2) for the scanning line driver circuit. A start signal (SSP) for the signal line driver circuit and a clock for the signal line driver circuit are input to the driver circuit 5304. Clock signal (SCK), data for video signal (DATA) (also simply called video signal), Each clock signal is a multiple of the clock signal (LAT) with different periods. It may be a clock signal or may be supplied together with an inverted clock signal (CKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 53 It is possible to omit either 03 or 04.

[0285] In FIG. 17B, a circuit with a low driving frequency (for example, the first scanning line driving circuit 5302, The second scanning line driver circuit 5303) is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver The configuration in which the driving circuit 5304 is formed on a substrate different from that of the pixel portion 5301 is shown. Due to the structure, the field effect mobility is smaller than that of a transistor using a single crystal semiconductor. The transistors can be used to configure the driving circuits formed on the substrate 5300. This allows for the enlargement of display devices, the reduction of the number of steps, the reduction of costs, and the improvement of yields. It is possible.

[0286] The transistors described in any of Embodiments 1 to 3 are n-channel TFTs. In FIG. 18(A) and FIG. 18(B), a signal line driver circuit is configured with an n-channel TFT. An example of the operation will be described.

[0287] The signal line driver circuit includes a shift register 5601 and a switching circuit 5602 . The switching circuit 5602 includes switching circuits 5602_1 to 5602_N (N is a natural number). The switching circuits 5602_1 to 5602_N each have a , multiple transistors 5603_1 to 5603_k (k is a natural number) The transistors 5603_1 to 5603_k are N-channel TFTs. Reveal.

[0288] The connection relationship of the signal line driver circuit will be described using the switching circuit 5602_1 as an example. The first terminals of the transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. The second terminals of the transistors 5603_1 to 5603_k are connected to , and are connected to signal lines S1 to Sk. The gates of the transistors 5603_1 to 5603_k are , and is connected to wiring 5605_1.

[0289] The shift register 5601 sequentially outputs H level (H signal) to the wirings 5605_1 to 5605_N. , or high power supply potential level), and the switching circuits 5602_1 to 56 It has the function of selecting 02_N in sequence.

[0290] The switching circuit 5602_1 includes wirings 5604_1 to 5604_k and signal lines S1 to Sk. A function of controlling the conduction state (conduction between the first terminal and the second terminal) with the wiring 5604_ The switches have a function of controlling whether or not potentials of 1 to 5604_k are supplied to the signal lines S1 to Sk. In this way, the switching circuit 5602_1 has a function as a selector. The transistors 5603_1 to 5603_k are connected to the wirings 5604_1 to 5604_k, respectively. A function of controlling the conduction state between the lines S1 to Sk, that is, the potential of the wirings 5604_1 to 5604_k to the signal lines S1 to Sk. Each of the switches 5603_k functions as a switch.

[0291] In addition, the wirings 5604_1 to 5604_k each carry video signal data (DATA). The video signal data (DATA) is an analog signal corresponding to the image information or image signal. This is often a signal that

[0292] Next, the operation of the signal line driver circuit of FIG. 18(A) will be described with reference to the timing chart of FIG. 18(B). FIG. 18B shows signals Sout_1 to Sout_N and An example of Vdata_1 to Vdata_k is shown. These are examples of output signals of the shift register 5601, and signals Vdata_1 to Vdata _k are examples of signals input to the wirings 5604_1 to 5604_k, respectively. One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. The selection period is divided into periods T1 to TN, for example. This is a period for writing video signal data (DATA) to the pixels belonging to the selected row. be.

[0293] During the period T1 to the period TN, the shift register 5601 outputs an H-level signal to the wiring 560 For example, in the period T1, the shift registers 5 The transistor 5601 outputs a high-level signal to the wiring 5605_1. 03_1 to 5603_k will be turned on, so wires 5604_1 to 5604_k and signal lines At this time, the wirings 5604_1 to 5604_k are connected to Da ta(S1)~Data(Sk) are input. Data(S1)~Data(Sk) are , each of which is connected to a pixel in a selected row via a transistor 5603_1 to 5603_k. In this manner, during the periods T1 to TN, the selected pixels are written into the pixels in the first to k-th columns. The video signal data (DATA) is written to the pixels in the selected row in order of k columns. can be.

[0294] As described above, video signal data (DATA) is written to the pixels in multiple columns. This makes it possible to reduce the number of video signal data (DATA) or the number of wirings. This reduces the number of connections to external circuits. By writing directly to the memory, the writing time can be increased, and the video signal can be written more quickly. This can prevent under-crowding.

[0295] The shift register 5601 and the switching circuit 5602 may be the same as those in the first embodiment. A circuit formed using the transistors described in any one of the first to third embodiments can be used.

[0296] The configuration of the scanning line driver circuit will be described. The scanning line driver circuit has a shift register. In some cases, a level shifter, a buffer, etc. may be included. In the operation circuit, a clock signal (CLK) and a start pulse signal (S P) is input to generate a selection signal. The generated selection signal is buffered The signal is buffered and amplified at the 10th line and then supplied to the corresponding scanning line. The gate electrodes of the transistors are connected. must be turned on at the same time, so the buffer must be capable of passing a large current. is used.

[0297] Regarding one form of a shift register used as a part of a scanning line driver circuit and / or a signal line driver circuit, This will be explained with reference to FIG. 19 and FIG. 20.

[0298] Regarding the shift registers of the scanning line driver circuit and the signal line driver circuit, refer to FIG. 19 and FIG. 20. The shift register includes a first pulse output circuit 10_1 to an Nth pulse output circuit 10_2. The path 10_N (N is a natural number of 3 or more) is shown in FIG. 19(A). The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the shift register are A first clock signal CK1 is output from a first wiring 11, a second clock signal CK2 is output from a second wiring 12, A third wiring 13 transmits a third clock signal CK3, a fourth wiring 14 transmits a fourth clock signal CK4, and a fourth wiring 15 transmits a fourth clock signal CK5. A clock signal CK4 is supplied to the first pulse output circuit 10_1. The start pulse SP1 (first start pulse) from 5 is input. In the n-th pulse output circuit 10_n (n is a natural number of 2≦n≦N), A signal from the output circuit (called the previous signal OUT(n-1)) (n ≥ 2, a natural number) is input. In addition, in the first pulse output circuit 10_1, the third pulse output circuit 10_3, which is two stages behind, Similarly, in the n-th pulse output circuit 10_n in the second stage or later, a signal from the second stage The signal from the (n+2)th pulse output circuit 10_(n+2) in the latter stage (the latter stage signal OUT(n +2) is input. Therefore, the pulse output circuit of each stage outputs the following stage and / or The first output signal (OUT(1)(SR) to be input to the two preceding pulse output circuits UT(N)(SR)), a second output signal (OUT(1) electrically connected to another wiring, etc. OUT(N)) is output. As shown in FIG. 19(A), The last two stages do not receive the next stage signal OUT(n+2). A second start pulse SP2 is sent from the sixth wiring 16, and a third start pulse SP3 is sent from the seventh wiring 17. Alternatively, a separate shift register can be used to input the SP3. For example, the (n+1)th signal that does not contribute to the pulse output to the pixel unit may be used. ) pulse output circuit 10_(N+1), (N+2)th pulse output circuit 10_(N+2) (also called a dummy stage), and a second start pulse (SP2) and Alternatively, the signal generating unit 10 may generate a signal equivalent to the start pulse (SP3) of No. 3.

[0299] The clock signal (CK) goes between H and L levels (L signal, low power supply potential) at regular intervals. Here, the first clock signal (CK1) to the second clock signal (CK2) are The fourth clock signal (CK4) is delayed by 1 / 4 cycle in sequence. The first clock signal (CK1) to the fourth clock signal (CK4) are used to generate a pulse output circuit. The clock signal is GCK, depending on the input drive circuit. It is sometimes called SCK, but here we will explain it as CK.

[0300] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 to It is electrically connected to any one of the fourth wirings 14. For example, in FIG. The first pulse output circuit 10_1 has a first input terminal 21 electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is The second pulse output circuit 10_2 is electrically connected to the third wiring 13. The first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13. The third input terminal 23 is electrically connected to the fourth wiring 14. There are.

[0301] Each of the first pulse output circuit 10_1 to the N-th pulse output circuit 10_N has a first input terminal a first input terminal 21, a second input terminal 22, a third input terminal 23, a fourth input terminal 24, a fifth input terminal The input terminal 25, the first output terminal 26, and the second output terminal 27 (see FIG. 19(B)). In the first pulse output circuit 10_1, a first clock signal is input to a first input terminal 21. A first clock signal CK1 is input to the first input terminal 22, a second clock signal CK2 is input to the third input terminal 23, and a third clock signal CK3 is input to the second input terminal 24. A third clock signal CK3 is input to the input terminal 23 of the second clock CLK1, and a start signal CK4 is input to the fourth input terminal 24 of the third clock CLK2. A pulse SP1 is input, a subsequent signal OUT(3) is input to the fifth input terminal 25, and a first The first output signal OUT(1)(SR) is output from the output terminal 26, and the second output signal OUT(2)(SR) is output from the output terminal 2 7 outputs the second output signal OUT(1).

[0302] Next, an example of a specific circuit configuration of the pulse output circuit will be described with reference to FIG.

[0303] The first pulse output circuit 10_1 includes a first transistor 31 to an eleventh transistor 41. (See FIG. 19(C)). In addition, the first input terminal 21 to the fifth input terminal a first output terminal 25, a first output terminal 26, a second output terminal 27, and a first high power supply potential VDD a power supply line 51 to which a second high power supply potential VCC is supplied, a power supply line 52 to which a low power supply potential The first transistor 31 to the eleventh transistor 4 are connected to the power supply line 53 through which VSS is supplied. A signal or a power supply potential is supplied to the power supply line 1. The magnitude relationship of the potentials is such that the first high power supply potential VDD is equal to or higher than the second high power supply potential VCC, and the third high power supply potential VCC is equal to or higher than the first high power supply potential VCC. The second power supply potential VCC is set to a potential higher than the third power supply potential VSS. The fourth clock signal (CK1) through the fourth clock signal (CK4) go between H and L levels at regular intervals. It is a signal that repeats this cycle, with VDD when it is at H level and VSS when it is at L level. By setting the potential VDD of the power supply line 51 higher than the potential VCC of the power supply line 52, To keep the potential applied to the gate electrode of a transistor low without affecting the This makes it possible to reduce the shift in the threshold voltage of the transistor and suppress degradation.

[0304] In FIG. 19C, the first transistor 31 has a first terminal electrically connected to a power supply line 51. a second terminal electrically connected to a first terminal of a ninth transistor 39; is electrically connected to the fourth input terminal 24. The second transistor 32 is is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. a gate electrode electrically connected to the gate electrode of the fourth transistor 34; The third transistor 33 has a first terminal electrically connected to the first input terminal 21, The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power supply line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has a first terminal electrically connected to the power supply line 53, The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The gate electrode is electrically connected to the fourth input terminal 24. The transistor 36 of No. 6 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the second Electrically connected to the gate electrode of the transistor 32 and the gate electrode of the fourth transistor 34 The seventh transistor has a gate electrode electrically connected to the fifth input terminal 25. The eighth transistor 37 has a first terminal electrically connected to the power supply line 52 and a second terminal electrically connected to the eighth transistor 38. and a gate electrode electrically connected to a third input terminal 23. The eighth transistor 38 has a first terminal connected to the gate electrode of the second transistor 32 and The fourth transistor 34 is electrically connected to a gate electrode thereof, the gate electrode of which is connected to the second input terminal The ninth transistor 39 has a first terminal electrically connected to the first transistor 22. The second terminal is electrically connected to the second terminal of the second transistor 31 and the second terminal of the second transistor 32. The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are connected to The tenth transistor is electrically connected to the power supply line 51. The resistor 40 has a first terminal electrically connected to the first input terminal 21 and a second terminal electrically connected to the second output terminal 22. a gate electrode electrically connected to the second terminal of the ninth transistor 39; The eleventh transistor 41 has a first terminal electrically connected to the power supply line 53. the second terminal is electrically connected to the second output terminal 27, and the gate electrode is The gate electrode of the fourth transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected to each other. There are.

[0305] In FIG. 19C, the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 4 The connection point of the gate electrode of transistor 0 and the second terminal of transistor 939 is referred to as node A. In addition, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the second terminal of the eighth transistor The connection point of the first terminal of the transistor 38 and the gate electrode of the eleventh transistor 41 is node B. (See FIG. 20(A)).

[0306] A transistor is defined as an element having at least three terminals including a gate, a drain, and a source. The element has a channel region between a drain region and a source region, A current can be passed through the in-region, the channel region, and the source region. Which is the source and which is the drain depends on the transistor structure and operating conditions. Therefore, it is difficult to determine whether the source and drain are In some cases, the regions that function as a source or drain are not called source or drain. In these cases, they may be referred to as the first terminal and the second terminal, respectively.

[0307] Here, the timing of the shift register having a plurality of pulse output circuits shown in FIG. A shift register is a scanning line driver circuit. In this case, the period 61 in FIG. 20B corresponds to a vertical blanking period, and the period 62 corresponds to a gate selection period. do.

[0308] As shown in FIG. 20A, the ninth transistor has a gate to which the second power supply potential VCC is applied. By providing the transistor 39, the following can be achieved before and after the bootstrap operation: There are such advantages.

[0309] In the absence of the ninth transistor 39 having the gate electrode to which the second potential VCC is applied, the boot When the potential of the node A rises due to the strap operation, the second terminal of the first transistor 31 The potential of the source, which is the first power supply potential VDD, increases and becomes higher than the first power supply potential VDD. The source of the first transistor 31 is switched to the first terminal side, that is, the power supply line 51 side. In the first transistor 31, the gate and source, and the gate and drain are In addition, a large bias voltage is applied, which causes a large stress and leads to deterioration of the transistor. Therefore, the ninth transistor, whose gate electrode is applied with the second power supply potential VCC, By providing the transistor 39, the potential of the node A is set by the bootstrap operation. However, the potential of the second terminal of the first transistor 31 does not increase. That is, by providing the ninth transistor 39, The negative bias voltage applied between the gate and source of the transistor 31 can be reduced. Therefore, by using the circuit configuration of this embodiment, the gate of the first transistor 31 The negative bias voltage applied between the gate and source can also be reduced, reducing the first-order This makes it possible to suppress the deterioration of the transistor 31.

[0310] The ninth transistor 39 is provided at a position corresponding to the second gate of the first transistor 31. A terminal is connected between the terminal and the gate of the third transistor 33 via a first terminal and a second terminal. In addition, in the present embodiment, a system having a plurality of pulse output circuits may be provided. In the case of a soft register, the signal line driver circuit has more stages than the scan line driver circuit. The resistor 39 may be omitted, which has the advantage of reducing the number of transistors.

[0311] Note that the semiconductor layers of the first to eleventh transistors 31 to 41 are made of oxide semiconductor. By using a conductor, the off-state current of a transistor is reduced, and the on-state current and electric field The effective mobility can be increased and the degree of deterioration can be reduced, so In addition, a transistor using an oxide semiconductor can reduce malfunctions in the circuit. Compared to transistors using rufus silicon, a high potential is applied to the gate electrode. Therefore, the degree of deterioration of the transistor due to the second power supply potential VCC is small. The same operation can be obtained by supplying the first power supply potential VDD to the power supply line, and the Since the number of power supply lines can be reduced, the circuit can be made more compact.

[0312] The gate electrode of the seventh transistor 37 is connected to the third input terminal 23. A lock signal is supplied by the second input terminal 22 to the gate electrode of the eighth transistor 38. The clock signal to be input to the gate electrode of the seventh transistor is provided by the second input terminal 22. A clock signal is supplied to the eighth gate electrode by the third input terminal 23. The same effect can be obtained by changing the wiring relationship so that the signal becomes a clock signal. In the shift register shown in FIG. 1, a seventh transistor 37 and an eighth transistor 38 are both on, the seventh transistor 37 is off, and the eighth transistor 38 is on. Then, the seventh transistor 37 is turned off and the eighth transistor 38 is turned off. By this, the potentials of the second input terminal 22 and the third input terminal 23 are reduced. The resulting drop in the potential of node B causes a drop in the potential of the gate electrode of the seventh transistor 37, and This occurs twice due to the drop in the potential of the gate electrode of the eighth transistor 38 and once due to the drop in the potential of the gate electrode of the eighth transistor 38. On the other hand, in the shift register shown in FIG. The seventh transistor 37 is turned on, and the eighth transistor 38 is turned on. Then the seventh transistor 37 is off and the eighth transistor 38 is off. By turning off the input terminal 38, the voltages of the second input terminal 22 and the third input terminal 23 are The drop in the potential of node B caused by the drop in the potential of the eighth transistor 38 is suppressed by the gate voltage Therefore, the seventh transistor 37 A clock signal is supplied to the gate electrode of the eighth transistor from the third input terminal. The gate electrode of the clock input terminal 38 is connected to the second input terminal 39 so that a clock signal is supplied to the gate electrode of the clock input terminal 38. It is preferable that the number of times the potential of the node B changes is reduced, and noise can be reduced. That is why.

[0313] In this manner, the potentials of the first output terminal 26 and the second output terminal 27 are maintained at the L level. By configuring the node B to periodically receive a high-level signal during the period, the pulse output This makes it possible to suppress malfunction of the power circuit.

[0314] (Embodiment 6) In this embodiment, as an example of the semiconductor device of the present invention, the semiconductor device according to the first embodiment or the third embodiment will be described. The transistor formed in the same manner as above is included in the pixel portion and further in the driver circuit, and the display function is also included. The semiconductor device (also referred to as a display device) shown in FIG. A part or the whole of the driver circuit is integrated on the same substrate as the pixel section. This allows the formation of a system on panel.

[0315] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. Also, electronic inks and other electronic devices A display medium in which the contrast changes due to thermal effects can also be applied.

[0316] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above-mentioned is mounted. Regarding the element substrate, which corresponds to one form before the display element is completed in the process of manufacturing a display device The element substrate includes a means for supplying a current to each of the plurality of pixels. Specifically, the substrate may be in a state where only the pixel electrode layer of the display element is formed, or the pixel electrode layer may be in a state where the pixel electrode layer is not formed. After forming a conductive film to be a pixel electrode layer and before etching to form a pixel electrode layer It can be a state, or it can take any form.

[0317] In this specification, the term "display device" refers to an image display device, a display device, or an optical Also refers to connectors, such as FPC (Flexible Printed Circuit). inted circuit) or TAB (Tape Automated Bon ding tape or TCP (Tape Carrier Package) is used. Modules with printed wiring boards attached to the ends of TAB tape or TCP or the display element is mounted with an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0318] In this embodiment mode, the appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device of the present invention, will be described. The surface will be described with reference to FIG. 21. FIG. 21 shows a surface of the first embodiment of the present invention. The transistors 4010 and 4011 and the liquid crystal element 4013 formed in the same manner as above are The panel is sealed between the plate 4001 and the second substrate 4006 by a sealant 4005. FIG. 21(B) is a top view, and corresponds to a cross-sectional view at MN in FIG. 21(A1) and (A2). do.

[0319] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In this manner, a sealant 4005 is provided. A second substrate 4006 is provided on the path 4004. The line driving circuit 4004 is a liquid crystal layer 4004 formed by a first substrate 4001 and a second substrate 4006. The first substrate 4001 is sealed together with the sealing material 4005. In a region different from the surrounded region, a single crystal semiconductor film or a polycrystalline A signal line driver circuit 4003 formed of a semiconductor film may be mounted.

[0320] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method, a wire The ear bonding method, the TAB method, etc. can be used. This is an example of mounting a signal line driver circuit 4003 by the OG method. 4 is an example in which a signal line driver circuit 4003 is mounted by the method.

[0321] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 21B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. Insulating layers 4020 and 4021 are provided on the transistors 4010 and 4011. do.

[0322] The transistors 4010 and 4011 are, for example, the transistors shown in the first embodiment or the third embodiment. In this embodiment, transistors 4010 and 40 11 is an n-channel transistor.

[0323] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are overlapped. The portion where the pixel electrode layer 4030 is formed corresponds to the liquid crystal element 4013. The layer 4031 is provided with insulating layers 4032 and 4033 which function as alignment films. A liquid crystal layer 4008 is sandwiched between layers 4032 and 4033 .

[0324] The first substrate 4001 and the second substrate 4006 may be made of glass or metal (typically, stainless steel). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film or acrylic resin film Alternatively, you can use aluminum foil with a PVF film or polyester film. A sheet having a structure sandwiched between films can also be used.

[0325] Also, 4035 is a columnar spacer obtained by selectively etching the insulating film. In order to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 A spherical spacer may be used. The transistor 4010 is connected to the common potential line and the conductive particles provided on the same substrate. The conductive particles are contained in the sealing material 4005.

[0326] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, the liquid crystal layer 4008 is formed using a liquid crystal composition in which 5% by weight or more of a chiral agent is mixed. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 10 μs It is short (~100μs), does not require alignment treatment due to optical isotropy, and has low viewing angle dependency. Sai.

[0327] Note that this embodiment is an example of a transmissive liquid crystal display device, but one embodiment of the present invention is a reflective liquid crystal display device. The present invention can be applied to both liquid crystal display devices and semi-transmissive liquid crystal display devices.

[0328] In the liquid crystal display device of the present embodiment, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and In this example, the color layer and the electrode layer used for the display element are provided in that order, but the polarizing plate is provided on the inner side of the substrate. In addition, the laminated structure of the polarizing plate and the colored layer is not limited to that of the present embodiment. The color layer may be appropriately selected depending on the material and manufacturing process conditions of the color layer. A light-shielding film that functions as a light-shielding film may be provided.

[0329] In addition, in this embodiment, in order to reduce the influence of surface unevenness of the transistor, In order to improve the reliability of the transistor, the transistor obtained in the first or third embodiment is The transistor is covered with an insulating layer (insulating layer 4020, insulating layer 40) which functions as a protective film or a planarizing insulating film. 21) The protective film is made to protect the device from organic matter, metals, and water suspended in the air. The purpose of the protective film is to prevent the intrusion of contaminating impurities such as steam, and a dense film is preferable. A single layer of silicon nitride film, or silicon nitride and a silicon oxide film, a silicon oxynitride film, or a silicon oxynitride film , an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film. The lamination of the aluminum film may be formed by sputtering. Although a sputtering method is used as an example, the method is not particularly limited and various methods may be used.

[0330] In addition, after the protective film is formed, a layer of an oxide semiconductor containing indium, gallium, and zinc is Annealing (300° C. to 400° C.) may be performed.

[0331] In addition, an insulating layer 4021 is formed as a planarization insulating film. Heat-resistant resins such as amide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin. In addition to the above organic materials, low dielectric constant materials (L ow-k materials), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) Siloxane-based resins can have organic groups (e.g., arsenic) as substituents. Alternatively, the organic group may have a fluoro group. In addition, by laminating a plurality of insulating films made of these materials, the insulating layer 4 can be formed. 021 may be formed.

[0332] Siloxane-based resin is a type of Si-OS formed using siloxane-based materials as starting materials. Corresponds to a resin containing i bonds.

[0333] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, an SOG method, or the like, depending on the material. , spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen The insulating layer 4021 is formed using a material liquid. In the case of forming the semiconductor layer, an oxide semiconductor containing indium, gallium, and zinc is simultaneously formed in the baking step. The conductive layer may be annealed (at 300° C. to 400° C.). By combining the annealing of the oxide semiconductor layer containing indium, gallium, and zinc, This makes it possible to quickly manufacture a semiconductor device.

[0334] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide with tungsten oxide, indium oxide with titanium oxide, Indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide doped with silicon oxide A conductive material may be used.

[0335] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of a conductive polymer. The conductive composition may be used to form the conductive film. The pixel electrode layer thus formed has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 550 nm. It is preferable that the resistance of the conductive polymer contained in the conductive composition is 70% or more. It is preferable that the resistivity is 0.1 Ω·cm or less.

[0336] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0337] A signal line driver circuit 4003, a scanning line driver circuit 4004, and a pixel section 40 Various signals and potentials are applied to the input 02 via the FPC4018.

[0338] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. 30, and the terminal electrode 4016 is formed from the same conductive film as the transistors 4010 and 4011. The source electrode layer and the drain electrode layer are formed from the same conductive film.

[0339] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0340] In FIG. 21, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, the present embodiment is not limited to this configuration. Alternatively, a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately and mounted. Alternatively, the circuit board may be formed separately and mounted.

[0341] FIG. 22 shows a semiconductor device using a TFT substrate 2600 manufactured according to one embodiment of the present invention. 1 shows an example of a liquid crystal display module.

[0342] FIG. 22 shows an example of a liquid crystal display module, in which a TFT substrate 2600 and an opposing substrate 2601 are connected. The substrate 2602 is fixed to the substrate 2601 by a bonding material 2602, and a pixel portion 2603 including a TFT and the like and a liquid crystal layer are disposed between the substrate 2601 and the substrate 2602. A display element 2604 and a colored layer 2605 are provided to form a display area. is necessary for color display, and in the case of the RGB method, it corresponds to each color of red, green, and blue. A colored layer is provided corresponding to each pixel. On the outside, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are arranged. It is composed of a cathode ray tube 2610 and a reflector 2611, and a circuit board 2612 is a flexible wiring board. A wiring board 2609 is connected to the wiring circuit section 2608 of the TFT board 2600, and the controller The LCD has external circuits such as a filter circuit and a power supply circuit. The layers may be laminated with a retardation plate interposed therebetween.

[0343] The LCD module is available in TN (Twisted Nematic) mode, IPS (In-plane Switching) mode, n-Plane-Switching mode, FFS (Fringe Field Switching) switching mode, MVA (Multi-domain Vertical A alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. uid Crystal) mode can be used.

[0344] Through the above steps, a display device including a transistor with excellent operational stability can be manufactured. The liquid crystal display device of this embodiment is equipped with a transistor having excellent operational stability. High reliability.

[0345] In this embodiment, the wiring resistance is reduced by using a conductive layer containing copper as a main component. A large-screen display device and a high-definition display device to which the present embodiment is applied can be provided. This reduces the occurrence of delays in signal transmission to the end of the signal line and voltage drops in the power line, This improves display quality, such as reducing unevenness and poor gradation.

[0346] In addition, the carrier concentration is 1×10 12 cm-3 Using an oxide semiconductor layer highly purified to less than By doing so, 1×10 -13 This allows for an extremely small off-state current of less than A. It is possible to provide a display device in which leakage current is suppressed and power consumption is reduced. It is possible to provide a display device with a large ratio. In addition, the display device has excellent contrast and high display quality. can be provided.

[0347] In addition, the display device of this embodiment uses a field-effect transistor (FET) having a highly purified oxide semiconductor layer. Equipped with high-performance transistors, it operates at high speed and has excellent video display characteristics and high-definition It is possible to display.

[0348] In addition, the wiring, which mainly contains copper, is sealed with a nitride film, which suppresses copper diffusion. As a result, a highly reliable semiconductor device can be provided.

[0349] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0350] (Embodiment 7) In this embodiment mode, a light-emitting display device will be described as an example of a semiconductor device of the present invention. In this embodiment, a light-emitting element that utilizes electroluminescence is used as the display element. The light-emitting element that utilizes electroluminescence is an organic compound. Generally, the former are organic EL elements and the latter are inorganic compounds. are called inorganic EL elements.

[0351] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. These are then injected into a layer containing a light-emitting organic compound, causing a current to flow. When the electrons and holes recombine, the light-emitting organic compound forms an excited state, When the excited state returns to the ground state, light is emitted. The optical element is called a current-excited light-emitting element.

[0352] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this embodiment, an organic EL element is used as the light emitting element. He explains.

[0353] FIG. 23 shows an example of a semiconductor device to which digital time gray scale driving is applied. FIG. 1 is a diagram illustrating an example of a possible pixel configuration. Note that OS in the diagram is an oxide semiconductor. This indicates that the transistor is made using MOS transistors.

[0354] The configuration of a pixel to which digital time gray scale driving can be applied and the operation of the pixel will be described. In this embodiment, the oxide semiconductor layer (In-Ga-Zn A single pixel is formed by using an n-channel transistor that uses a SiO2-based semiconductor layer as the channel formation region. Here is an example of using two of them.

[0355] The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, The switching transistor 64 has a light emitting element 6404 and a capacitor element 6403. 01 has a gate connected to a scanning line 6406 and a first electrode (one of the source and drain electrodes) The first electrode (the other of the source electrode and the drain electrode) is connected to a signal line 6405, and the second electrode (the other of the source electrode and the drain electrode) is connected to a drive The driving transistor 6402 is connected to the gate of the driving transistor 6402. The gate is connected to a power supply line 6407 via a capacitor element 6403, and the first electrode is connected to a power supply line 640 7, and the second electrode is connected to the first electrode (pixel electrode layer) of the light-emitting element 6404. The second electrode of the light emitting element 6404 corresponds to a common electrode 6408. It is electrically connected to a common potential line formed on one substrate.

[0356] A low power supply potential is set to the second electrode (common electrode 6408) of the light emitting element 6404. Note that the low power supply potential is a low power supply potential with respect to the high power supply potential set to the power supply line 6407. Potential < High power supply potential. For example, GND, 0V, etc. are set as low power supply potential. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404. In order to make the light emitting element 6404 emit light by passing a current through the light emitting element 6404, a high power supply potential and the low power supply potential is set to be equal to or higher than the forward threshold voltage of the light emitting element 6404. A high power supply potential is applied to the common electrode 6408, and a low power supply potential is applied to the power supply line 6407. In that case, the current flowing through the light emitting element 6404 is reversed. The configuration of the light emitting element 6404 may be changed as appropriate.

[0357] The capacitor 6403 is omitted by substituting the gate capacitance of the driving transistor 6402. It is also possible to set the gate capacitance of the driving transistor 6402 as follows: A capacitance may be formed between the gate electrode layer and the transistor.

[0358] In the case of a voltage input voltage driving method, the gate of the driving transistor 6402 is The driving transistor 6402 is in two states, either fully on or fully off. A video signal is inputted, that is, the driving transistor 6402 is operated in a linear region. In order to operate the driving transistor 6402 in a linear region, the voltage of the power supply line 6407 must be higher than that of the driving transistor 6402. A high voltage is applied to the gate of the driving transistor 6402. A voltage equal to or higher than (power supply line voltage + Vth of the driving transistor 6402) is applied.

[0359] In addition, when analog gray scale driving is performed instead of digital time gray scale driving, the input of the signal is different. By doing so, the same pixel configuration as in FIG. 23 can be used.

[0360] In the case of performing analog gradation driving, a light emitting element 6404 is connected to the gate of a driving transistor 6402. A voltage equal to or higher than the forward voltage of the light emitting element 6401 and the Vth of the driving transistor 6402 is applied. The forward voltage in 04 refers to the voltage required to achieve the desired brightness, and should be at least 100% forward voltage. In addition, the video transistor 6402 is designed to operate in the saturation region. By inputting an optical signal, a current can be passed through the light emitting element 6404. In order to operate the transistor 6402 in the saturation region, the potential of the power supply line 6407 is The gate potential of the light emitting element 6402 is set higher than that of the gate of the transistor 6403. Analog gradation drive can be performed by passing a current corresponding to a video signal through 6404.

[0361] Note that the pixel configuration shown in FIG. 23 is not limited to this. For example, A switch, a resistive element, a capacitive element, a transistor, a logic circuit, or the like may be added.

[0362] Next, the structure of the light-emitting element will be described with reference to FIG. The cross-sectional structure of a pixel will be described below by taking the case where FT is n-type as an example. The driving TFTs 7011, 7021, and 7001 used in the semiconductor device of (C) are The transistor can be manufactured in a manner similar to that of the transistor described in Embodiment 1 or 3.

[0363] The light emitting element only needs to have at least one of the anode and cathode transparent in order to extract light. Then, a transistor and a light emitting element are formed on the substrate, and light is emitted from the surface opposite the substrate. The top emission is from the top surface, the bottom emission is from the bottom surface, and the bottom emission is from the bottom surface. There is a light-emitting element having a dual emission structure in which light is emitted from the side of the substrate. The present invention can be applied to any light emitting element with any emission structure.

[0364] A light emitting element having a bottom emission structure will be described with reference to FIG.

[0365] The driving TFT 7011 is an n-type TFT, and the light emitted from the light emitting element 7012 is incident on the first electrode 701. FIG. 24(A) shows a cross-sectional view of a pixel when light is emitted to the driving TFT 7011. A conductive material having a visible light transparency electrically connected to the source electrode or drain electrode of the A first electrode 7013 of the light emitting element 7012 is formed on the conductive film 7017. On the first electrode 7013, an EL layer 7014 and a second electrode 7015 are laminated in this order.

[0366] The conductive film 7017 having a visible light transmitting property is formed of indium tin oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium tin oxide with titanium oxide, indium tin oxide, indium zinc oxide Oxide, indium tin oxide with added silicon oxide, etc., have transparency to visible light An electrically conductive film may be used.

[0367] In addition, various materials can be used for the first electrode 7013 of the light-emitting element. When the electrode 7013 is used as a cathode, a material having a small work function, specifically, For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr, In addition to alloys containing these metals (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are also included. In FIG. 24A, the film thickness of the first electrode 7013 is set to a value that allows visible light to pass therethrough (preferably). Preferably, the thickness is about 5 nm to 30 nm. For example, an aluminum film having a thickness of 20 nm is used. The membrane is used as a first electrode 7013 .

[0368] After a conductive film having a light-transmitting property to visible light and an aluminum film are laminated, The conductive film 7017 and the first electrode 7013 are formed by etching the conductive film 7017. In this case, etching can be performed using the same mask, which is preferable. It is.

[0369] The periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimide. Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polymer films The partition wall 7019 is formed by using a photosensitive resin material. An opening is formed on the electrode 7013, and the sidewall of the opening is formed with a continuous curvature. It is preferable to form the partition wall 7019 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0370] The EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and the light-emitting device may be composed of a single layer or may be composed of multiple layers stacked together. The EL layer 7014 is composed of a plurality of layers, and the first electrode 7013 is When used as a cathode, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole transport layer are formed on the first electrode 7013. The hole transport layer and the hole injection layer are laminated in this order. Note that it is not necessary to provide all of these layers.

[0371] In addition, the stacking order is not limited to the above. When the first electrode 7013 is used as an anode, A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer may be laminated in this order. However, when comparing power consumption, the first electrode 7013 functions as a cathode and the first An electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed on the electrode 7013 in this order. Laminating is preferable because it can suppress the voltage rise in the drive circuit section and reduce power consumption. stomach.

[0372] In addition, the second electrode 7015 formed on the EL layer 7014 can be made of various materials. For example, when the second electrode 7015 is used as an anode, a material with a large work function can be used. Materials (specifically, 4.0 eV or more), such as ZrN, Ti, W, Ni, Pt, Cr, etc., A transparent conductive material such as ITO, IZO, or ZnO is preferable. A shielding film 7016, for example, a metal that blocks light or a metal that reflects light, is used. In this embodiment, an ITO film is used as the second electrode 7015, and a Ti film is used as the shielding film 7016. do.

[0373] An EL layer 7014 including a light-emitting layer is sandwiched between a first electrode 7013 and a second electrode 7015. In the case of the element structure shown in FIG. Light emitted from 7012 is emitted to the first electrode 7013 side as shown by the arrow.

[0374] In FIG. 24A, the light emitted from the light emitting element 7012 is reflected by the color filter layer. 7033, through the insulating layer 7032, the gate insulating layer 7030, and the substrate 7010. And then eject it.

[0375] The color filter layer 7033 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0376] The color filter layer 7033 is covered with an overcoat layer 7034, which is a protective insulating layer. In FIG. 24A, the overcoat layer 7034 is thin. As shown in the figure, the overcoat layer 7034 is made of a resin material such as an acrylic resin, and is colored. It has the function of flattening unevenness caused by the -filter layer 7033.

[0377] In addition, a source electrode or a drain electrode is formed on the protective insulating layer 7035 and the insulating layer 7032. The contact hole reaching the inner electrode is disposed at a position overlapping with the partition wall 7019 .

[0378] Next, a light emitting element having a dual emission structure will be described with reference to FIG.

[0379] In FIG. 24(B), the source electrode or drain electrode of the driving TFT 7021 is electrically connected to A first conductive film 7027 having a visible light-transmitting property is formed on the light-emitting element 7022. An electrode 7023 is formed, an EL layer 7024 is formed on the first electrode 7023, and a second electrode 7 025 are layered in order.

[0380] The conductive film 7027 having a visible light transmitting property is formed of indium tin oxide containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide, indium tin oxide with titanium oxide, indium tin oxide, indium zinc oxide Oxide, indium tin oxide with added silicon oxide, etc., have transparency to visible light An electrically conductive film may be used.

[0381] In addition, various materials can be used for the first electrode 7023. For example, When using 23 as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkaline metals such as Mg, Ca, Sr, and other alkaline earth metals, and alloys containing these metals In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred. Metal Film When the first electrode 7023 is made of a material having a thickness that allows light to pass therethrough (preferably, 5 nm or less), For example, when the first electrode 7023 is used as a cathode, the thickness of the first electrode 7023 is set to about 20 nm. An aluminum film having a thickness can be applied.

[0382] After a conductive film having a light-transmitting property to visible light and a metal film having a light-transmitting property are stacked, The conductive film 7027 and the first electrode 70 are selectively etched to have a light-transmitting property to visible light. 23 may be formed, in which case it can be etched using the same mask, which is preferred. It is.

[0383] The periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimide. Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polymer films The partition wall 7029 is formed by using a photosensitive resin material. 023, an opening is formed on the surface, and the side wall of the opening is formed with a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7029, In this case, the step of forming a resist mask can be omitted.

[0384] In addition, the EL layer 7024 formed over the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It is sufficient if the material is made up of a single layer or multiple layers are laminated. Either is acceptable. The EL layer 7024 is made up of multiple layers, and the first electrode 7023 is used as a cathode. When used, the electron injection layer, the electron transport layer, the light emitting layer, the hole transport layer, and the hole injection layer are stacked in this order. It is not necessary to provide all of these layers.

[0385] In addition, the stacking order is not limited to the above. When the first electrode 7023 is used as an anode, A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer may be laminated in this order. However, when comparing power consumption, the first electrode 7023 is used as a cathode and a It is better to stack the electron injection layer, electron transport layer, light emitting layer, hole transport layer, and hole injection layer in this order. This is preferable because it can suppress a voltage rise in the circuit section and consumes less power.

[0386] In addition, the second electrode 7025 formed on the EL layer 7024 can be made of various materials. For example, when the second electrode 7025 is used as an anode, a material with a large work function can be used. A transparent conductive material such as ITO, IZO, or ZnO can be preferably used. In this embodiment, the second electrode 7025 is used as an anode, and an ITO film containing silicon oxide is used as the anode. Form.

[0387] An EL layer 7024 including a light-emitting layer is sandwiched between a first electrode 7023 and a second electrode 7025. In the case of the element structure shown in FIG. The light emitted from 7022 is incident on the second electrode 7025 side and the first electrode 70 as shown by the arrow. 23 It is fired on both sides.

[0388] In FIG. 24B, the light emitted from the light-emitting element 7022 toward the first electrode 7023 is One light passes through the color filter layer 7043, and enters the insulating layer 7042 and the gate insulating layer 704. 0, and passes through the substrate 7020.

[0389] The color filter layer 7043 is formed by a droplet discharge method such as an inkjet method, a printing method, a photolithography method, or the like. Each is formed by an etching method using graphic technology.

[0390] The color filter layer 7043 is covered with an overcoat layer 7044, which is a protective insulating layer. Covered by layer 7045 .

[0391] In addition, a thin film is formed over the protective insulating layer 7045 and the insulating layer 7042 and reaches the drain electrode layer. The contact hole is disposed at a position overlapping with the partition wall 7029 .

[0392] However, when using a light-emitting element with a dual-side emission structure and making both display surfaces full color display, Since the light from the second electrode 7025 side does not pass through the color filter layer 7043, a separate color filter is used. It is preferable that a sealing substrate having a -filter layer is provided above the second electrode 7025.

[0393] Next, a light emitting element having a top emission structure will be described with reference to FIG.

[0394] In FIG. 24C, the driving TFT 7001 is an n-type TFT, and the light emitted from the light emitting element 7002 is FIG. 24C shows a cross-sectional view of a pixel when the driving electrode 7005 is inserted. A light-emitting element 7002 electrically connected to the source electrode or drain electrode of the TFT 7001 A first electrode 7003 is formed, and an EL layer 7004 and a second The electrodes 7005 are laminated in this order.

[0395] In addition, various materials can be used for the first electrode 7003. For example, When using 03 as a cathode, a material with a small work function, specifically, for example, Li or Cs Alkaline metals such as Mg, Ca, Sr, and other alkaline earth metals, and alloys containing these metals In addition to (Mg:Ag, Al:Li, etc.), rare earth metals such as Yb and Er are preferred.

[0396] The periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimide. Organic resin films such as acrylic resin, polyamide, and epoxy resin, inorganic insulating films, and organic polymer films The partition wall 7009 is formed by using a photosensitive resin material. An opening is formed on the electrode 7003, and the sidewall of the opening is formed with a continuous curvature. It is preferable to form the partition wall 7009 so as to have an inclined surface. In this case, the step of forming a resist mask can be omitted.

[0397] The EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least It is sufficient to include a light-emitting layer, and the light-emitting device may be composed of a single layer or may be composed of multiple layers stacked together. The EL layer 7004 is made up of multiple layers, and the first electrode 7003 is When used as a cathode, it is used as an electron injection layer, an electron transport layer, an emission layer, a hole transport layer, a hole injection layer, It is not necessary to provide all of these layers.

[0398] In addition, the stacking order is not limited to the above. When the first electrode 7003 is used as an anode, A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer and an electron injection layer may be laminated in this order. .

[0399] For example, the first electrode 7003 formed by laminating a Ti film, an aluminum film, and a Ti film is used as an anode. A hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer are laminated on the electrode in this order. A laminate of a Mg:Ag alloy thin film and ITO is then formed on top of it.

[0400] When the driving TFT 7001 is an n-type TFT, an electron injection layer and an electron transport layer are provided on the first electrode 7003. The order of lamination of the light-emitting layer, the hole-transport layer, and the hole-injection layer is favorable for reducing the current flow in the driving circuit. This is preferable because it can suppress the pressure rise and reduce power consumption.

[0401] The second electrode 7005 is formed using a conductive material that transmits visible light, for example. Indium oxide containing tungsten oxide, Indium zinc oxide containing tungsten oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide with silicon oxide added, etc. A conductive film that is transparent to visible light may be used.

[0402] An EL layer 7004 including a light-emitting layer is sandwiched between a first electrode 7003 and a second electrode 7005. In the case of the pixel shown in FIG. 24C, the light emitting element 700 Light emitted from 2 is emitted to the second electrode 7005 side as shown by the arrow.

[0403] In FIG. 24C, the drain electrode layer of the driving TFT 7001 is covered with a protective insulating layer 7 7052 and the insulating layer 7055 through a contact hole. Electrically connected. The planarization insulating layer 7053 is made of polyimide, acrylic resin, benzocyclo Resin materials such as butene resin, polyamide, and epoxy resin can be used. In addition to resin materials, low-k materials, siloxane resins, PSG (ringa Glass, BPSG (borophosphorus glass), etc. can be used. The planarization insulating layer 7053 may be formed by stacking a plurality of insulating films. The method for forming the flattened insulating layer 7053 is not particularly limited. Depending on the material, it may be a sputtering method, a SO G method, spin coating, dip, spray coating, droplet ejection method (inkjet method, screen Printing methods such as inkjet printing, offset printing, etc. can be used.

[0404] In addition, the first electrode 7003 is insulated from the first electrode 7008 (not shown) of the adjacent pixel. The partition wall 7009 is made of polyimide, acrylic resin, polyamide, etc. Formed using organic resin films such as mide and epoxy resin, inorganic insulating films, or organic polysiloxane The partition wall 7009 is made of a photosensitive resin material and has an opening on the first electrode 7003. The side wall of the opening is formed to have a slope having a continuous curvature. In the case where a photosensitive resin material is used for the partition wall 7009, a resist mask is preferably used. The step of forming the insulating film can be omitted.

[0405] In the structure of FIG. 24C, when a full-color display is performed, for example, the light-emitting element 70 02 is a green light emitting element, one adjacent light emitting element is a red light emitting element, and the other The light-emitting element is a blue light-emitting element. In addition to the three types of light-emitting elements, a white element is also added, making a total of four. A light-emitting display device capable of full-color display may be manufactured using a variety of light-emitting elements.

[0406] In the structure of FIG. 24(C), all the light emitting elements are white light emitting elements. A sealing substrate having a color filter or the like is disposed above the light emitting element 7002. A light-emitting display device capable of full-color display may be manufactured. By forming a material that emits light in a certain range, and combining it with a color filter or a color conversion layer, Error display can be performed.

[0407] Of course, a single-color display may be used. For example, a lighting device may be formed using white light. Alternatively, monochromatic light may be used to form an area color type light emitting device.

[0408] If necessary, an optical film such as a polarizing film, eg, a circular polarizing plate, may be provided.

[0409] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0410] In addition, the thin film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically However, a current control TFT is connected between the driving TFT and the light emitting element. The configuration may be such that the input / output terminals are connected to each other.

[0411] Note that the semiconductor device described in this embodiment mode is not limited to the configuration shown in FIG. Various modifications based on the technical concept of the present invention are possible.

[0412] Next, one embodiment of a semiconductor device to which the transistor described in Embodiment 1 or 3 is applied will be described. The appearance and cross section of a light-emitting display panel (also called a light-emitting panel) corresponding to the above embodiment are shown in FIG. FIG. 25 shows a transistor and a light-emitting element formed on a first substrate. FIG. 25(B) is a top view of a panel sealed between the substrate 2 and the substrate 3 by a sealant. This corresponds to a cross-sectional view taken along line HI in FIG.

[0413] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504 are provided on a first substrate 4501. A sealant 4505 is formed to surround the gate driver circuits 4504a and 4504b. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. It is sealed together with the filling material 4507 by the sealing material 4507. Protective films with little outgassing (laminated films, UV-cured resin films, etc.) It is preferable to package (enclose) it in a bar material.

[0414] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of transistors. In FIG. 25B, a transistor 4510 included in a pixel portion 4502 and a signal line driver A transistor 4509 included in the circuit 4503a is illustrated.

[0415] The transistors 4509 and 4510 are oxide semiconductor layers (In-Ga-Zn-O-based semiconductor layers In the present invention, the highly reliable transistor described in the first embodiment or the third embodiment is applied. In this embodiment, the transistors 4509 and 4510 are n-channel transistors. It is a transistor.

[0416] A channel of an oxide semiconductor layer of a transistor 4509 for a driver circuit is formed over an insulating layer 4544. A conductive layer 4540 is provided in a position overlapping with the hole formation region. By providing the conductor layer in a position overlapping with the channel formation region of the transistor 4509, The change in the threshold voltage can be suppressed. The second gate electrode layer may be the same as or different from the gate electrode layer of the gate electrode ... The conductive layer 4040 can also function as a layer. It may be in a floating state.

[0417] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the transistor 4510. The light emitting element 4511 is configured with a first electrode layer 4517, an electroluminescent layer 45 12, the second electrode layer 4513 has a stacked structure, but is not limited to the structure shown in this embodiment mode. The configuration of the light emitting element 4511 is determined according to the direction of the light to be extracted from the light emitting element 4511. can be changed appropriately.

[0418] The partition 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 4517, and the sidewall of the opening It is preferable that the inclined surface is formed so as to have a continuous curvature.

[0419] The electroluminescent layer 4512 may be composed of a single layer or a plurality of layers may be laminated. It doesn't matter whether it is done or not.

[0420] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on the partition wall 4513 and the partition wall 4520. The protective film may be formed of silicon nitride. It is possible to form a silicon oxide nitride film, a DLC film, etc.

[0421] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504b Various signals and potentials applied to the pixel portion 4502 are It is supplied by b.

[0422] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light emitting element 4511. The terminal electrode 4516 is formed from the same conductive film as the transistors 4509 and 451 The source and drain electrode layers in the second transistor 10 are formed from the same conductive film as those in the second transistor 10.

[0423] The connection terminal electrode 4515 is connected to the terminal of the FPC 4518a via the anisotropic conductive film 4519. The electrodes are electrically connected to each other.

[0424] The second substrate located in the direction of light extraction from the light emitting element 4511 is transparent to visible light. In that case, glass plates, plastic plates, polyester films, etc. A material that is transparent to visible light, such as a film or an acrylic film, is used.

[0425] In addition, filler 4507 can be inert gas such as nitrogen or argon, or ultraviolet-curing resin. It can be made of resin or thermosetting resin, and is suitable for PVC (polyvinyl chloride), acrylic resin, etc. Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate copolymer) can be used. Nitrogen is used as the filler.

[0426] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be provided on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates) and color filters may be provided as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0427] The signal line driver circuits 4503a and 4503b and the scanning line driver circuits 4504a and 4504b are A driving circuit formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is Also, only the signal line driver circuit, or a part of the signal line driver circuit, or the scanning line driver circuit may be mounted. Only the path or only a part of the path may be separately formed and mounted. In this embodiment, the structure shown in FIG. Not limited.

[0428] The light-emitting display device of this embodiment mode has a transistor having excellent operational stability. Highly reliable.

[0429] In this embodiment, the wiring resistance is reduced by using a conductive layer containing copper as a main component. A large-screen display device and a high-definition display device to which the present embodiment is applied can be provided. This reduces the occurrence of delays in signal transmission to the end of the signal line and voltage drops in the power line, This improves display quality, such as reducing unevenness and poor gradation.

[0430] In addition, the carrier concentration is 1×10 12 cm -3 Using an oxide semiconductor layer highly purified to less than By doing so, 1×10 -13 This allows for an extremely small off-state current of less than A. It is possible to provide a display device in which leakage current is suppressed and power consumption is reduced. It is possible to provide a display device with a large ratio. In addition, the display device has excellent contrast and high display quality. can be provided.

[0431] In addition, the display device of this embodiment uses a field-effect transistor (FET) having a highly purified oxide semiconductor layer. Equipped with high-performance transistors, it operates at high speed and has excellent video display characteristics and high-definition It is possible to display.

[0432] In addition, the wiring, which mainly contains copper, is sealed with a nitride film, which suppresses copper diffusion. As a result, a highly reliable semiconductor device can be provided.

[0433] Note that the structure shown in this embodiment mode may be used in appropriate combination with structures shown in other embodiment modes. It is possible to do so.

[0434] (Embodiment 8) In this embodiment, an example of an electronic paper is used as a display device which is an example of a semiconductor device of the present invention. show.

[0435] FIG. 26 shows an active matrix type electronic display device as an example of a display device to which one embodiment of the present invention is applied. The transistor 581 used in the display device is the same as that in the embodiment 1 or can be fabricated in the same manner as in the third embodiment.

[0436] The electronic paper in FIG. 26 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. This is a method of displaying information by controlling the orientation of spherical particles caused by the generation of light.

[0437] The source electrode layer or the drain electrode layer of the transistor 581 is a first electrode layer 587 and an insulating layer The first electrode layer 587 is electrically connected to the first electrode layer 585 through an opening formed therein. Between the first electrode layer 588 and the second electrode layer 589, there are black regions 590a and white regions 590b, and black regions 590c and 590d. 90a and a cavity 594 filled with liquid provided around the white area 590b. The spherical particle 589 is surrounded by a filler 595 such as a resin. In FIG. 26, 580 is a substrate, 583 is an interlayer. The insulating film is provided, and 596 is a substrate.

[0438] Also, instead of the twist ball, an electrophoretic element can be used. and a 10μm to 20μm diameter nanoparticle that contains positively charged white nanoparticles and negatively charged black nanoparticles. Microcapsules with a diameter of about 0 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, the microcapsules emit white light. White particles and black particles move in opposite directions to display either black or white. The display element that applies this principle is the electrophoretic display element, commonly known as electronic paper. Since electrophoretic display elements have a higher reflectivity than liquid crystal display elements, the auxiliary light is It does not require a touch panel, consumes little power, and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display, the image once displayed can be retained. Therefore, for example, a semiconductor device with a display function ( Even if the display device (also referred to simply as a display device or a semiconductor device having a display device) is moved away , it is possible to store the displayed image.

[0439] Through the above process, we were able to create electronic paper equipped with transistors that have excellent operational stability. The electronic paper of this embodiment is equipped with transistors that have excellent operational stability. High reliability.

[0440] In this embodiment, the wiring resistance is reduced by using a conductive layer containing copper as a main component. A large-screen display device to which this embodiment is applied can provide a display device having a large-screen display. This reduces the occurrence of signal transmission delays and voltage drops in the power lines, and reduces display unevenness and poor gradation. Which improves display quality.

[0441] In addition, the carrier concentration is 1×10 12 cm -3 Using an oxide semiconductor layer highly purified to less than By doing so, 1×10 -13 This allows for an extremely small off-state current of less than A. It is possible to provide a display device in which leakage current is suppressed and power consumption is reduced. It is possible to provide a display device with a large ratio. In addition, the display device has excellent contrast and high display quality. can be provided.

[0442] In addition, the wiring, which mainly contains copper, is sealed with a nitride film, which suppresses copper diffusion. As a result, a highly reliable semiconductor device can be provided.

[0443] This embodiment is implemented by appropriately combining with the configuration described in the first or third embodiment. It is possible to implement this.

[0444] (Embodiment 9) The display device of one embodiment of the present invention can be used as electronic paper. It can be used in any electronic device that displays information. For example, electronic paper can be used for electronic books, posters, and on trains and other vehicles. It can be used for in-car advertising, display on various cards such as credit cards, etc. An example of a child device is shown in FIG. 27 and FIG.

[0445] FIG. 27(A) shows a poster 2631 made of electronic paper. In the case of printed matter, the advertisements are exchanged manually. By using electronic paper, the display of advertisements can be changed in a short time. The poster is designed to transmit and receive information wirelessly. It is also possible to use the following.

[0446] FIG. 27(B) shows an advertisement 2632 on a train or other vehicle. In the case of paper prints, the advertisements are exchanged manually. By using electronic paper, it is possible to change the display of advertisements in a short time without requiring a lot of manpower. In addition, stable images can be obtained without display distortion. The configuration may be such that information can be transmitted and received.

[0447] FIG. 28 shows an example of an electronic book. For example, an electronic book 2700 has a housing 27 The housing 2701 and the housing 2703 are The opening and closing operations are performed by using the shaft portion 2711 as an axis. With this configuration, it becomes possible to operate like a paper book.

[0448] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 can also be used to display a continuous screen. Alternatively, a different screen may be displayed. For example, a sentence is displayed on the right display (display 2705 in FIG. 28) and In FIG. 28, an image can be displayed on a display unit 2707).

[0449] FIG. 28 shows an example in which the housing 2701 is provided with an operation unit. 701, a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The configuration may include a touch panel, a touch screen, a pointing device, etc. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB A configuration including a terminal that can be connected to various cables such as a cable, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary. This is also fine.

[0450] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. is also possible.

[0451] Through the above steps, a display device including a transistor with excellent operational stability can be manufactured. Display devices incorporating transistors with excellent operational stability are highly reliable.

[0452] (Embodiment 10) A semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. digital photo frames, mobile phones (also called mobile phones or mobile phone devices), These include large game machines such as small game machines, portable information terminals, audio playback devices, and pachinko machines. can be.

[0453] FIG. 29A shows an example of a television device. The television device 9600 includes: A display unit 9603 is incorporated in a housing 9601. The display unit 9603 displays images. In this embodiment, the housing 9601 is supported by the stand 9605. This shows a configuration in which the above is supported.

[0454] The television device 9600 can be operated using an operation switch on the housing 9601 or a separate remote control. This can be done by the remote control operation device 9610. The channel and volume can be controlled by the 9609, and the display 9603 shows In addition, the remote control unit 9610 can control the video. A display portion 9607 for displaying information output from 9610 may be provided.

[0455] The television device 9600 includes a receiver and a modem. It can receive more general television broadcasts, and can also be connected to a modem via wired or wireless connection. By connecting to a network, communication can be one-way (sender to receiver) or two-way. It is also possible to communicate information (between a sender and a receiver, or between receivers).

[0456] FIG. 29B shows an example of a digital photo frame. In the frame 9700, a display unit 9703 is incorporated in a housing 9701. 3 is capable of displaying various images, for example images taken with a digital camera. By displaying data, it can function just like a normal photo frame.

[0457] The Digital Photo Frame 9700 is equipped with an operation unit, external connection terminals (USB terminal, US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section, etc. These components may be installed on the same surface as the display unit, but they may be installed on the side or back. It is preferable to have a digital photo frame with a built-in memory card because it improves the design. A memory that stores image data taken with a digital camera is inserted into the body insertion section. The captured image data can be displayed on the display portion 9703 .

[0458] The digital photo frame 9700 may also be configured to transmit and receive information wirelessly. It is also possible to wirelessly import and display desired image data.

[0459] FIG. 30(A) shows a portable gaming machine, which is composed of two housings, a housing 9881 and a housing 9891. The housing 9881 is connected to a connector 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 30(A) also includes a speaker unit 9884 and a recording medium insertion unit 988. 6, LED lamp 9890, input means (operation keys 9885, connection terminals 9887, sensors 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration 9889) equipped with a microphone, etc. Of course, the configuration of the portable gaming machine is not limited to the above, and at least the present invention It is sufficient that the semiconductor device according to the present invention is included, and other auxiliary equipment is appropriately provided. The portable game machine shown in FIG. 30(A) can be configured as a game machine having a game data recorded on a recording medium. The function of reading out programs or data and displaying them on the display unit, as well as wireless communication with other portable gaming machines, The portable gaming machine shown in FIG. 30(A) has a function of communicating with the user and sharing information. The functions are not limited to these, and the device may have a variety of functions.

[0460] FIG. 30(B) shows an example of a slot machine, which is a large gaming machine. Slot Machine 9 The slot machine 900 includes a display unit 9903 built into a housing 9901. 900 also includes other operating means such as a start lever and stop switch, a coin slot, Of course, the configuration of the slot machine 9900 is not limited to the above. However, the present invention is not limited to the above, and may be configured to include at least a semiconductor device according to one embodiment of the present invention. Other auxiliary equipment may be provided as appropriate.

[0461] FIG. 31 shows an example of a mobile phone. A mobile phone 1000 is assembled in a housing 1001. In addition to the built-in display unit 1002, operation buttons 1003, an external connection port 1004, a speaker, 1005, microphone 1006, etc.

[0462] The mobile phone 1000 shown in FIG. 31 allows users to input information by touching the display unit 1002 with a finger or the like. In addition, operations such as making a phone call or composing an email can be performed by inputting the This can be done by touching the portion 1002 with a finger or the like.

[0463] The screen of the display unit 1002 has three main modes. The first is a display mode that is mainly used for displaying images. The first mode is a display mode, the second is an input mode for inputting information such as characters, and the third mode is a display mode. This is a display + input mode that combines the display mode and the input mode.

[0464] For example, when making a phone call or composing an e-mail, the display unit 1002 is used for inputting characters. The main character input mode is to input characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. I wish.

[0465] In addition, a sensor for detecting tilt, such as a gyro or an acceleration sensor, is installed inside the mobile phone 1000. By providing a detection device having the above configuration, the orientation of the mobile phone 1000 (portrait or landscape) can be determined and the display The screen display of the display unit 1002 can be automatically switched.

[0466] The screen mode can be changed by touching the display unit 1002 or by operating the housing 1001. This is done by operating the button 1003. Also, depending on the type of image displayed on the display unit 1002, For example, the image signal to be displayed on the display unit is a moving image. If it is data, the mode is switched to display mode, and if it is text data, the mode is switched to input mode.

[0467] In the input mode, the optical sensor of the display unit 1002 detects a signal and displays If there is no input by touch operation of the part 1002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0468] The display unit 1002 can also function as an image sensor. By touching the palm or fingers of the user on the sensor 02 and capturing an image of the palm print or fingerprint, the user can be authenticated. In addition, a backlight that emits near-infrared light to the display unit or a sensing light that emits near-infrared light By using a source, it is also possible to image finger veins, palm veins, etc.

[0469] Through the above steps, a display device including a transistor with excellent operational stability can be manufactured. The above electronic devices are equipped with transistors that have excellent operational stability, making them highly reliable. stomach.

[0470] (Embodiment 11) In this embodiment mode, the semiconductor device shown in Embodiment 1 or 3 will be described. An example of a liquid crystal display device using a liquid crystal element having a transistor will be described with reference to FIGS. 32 to 35. The TFT 628 and the TFT 629 used in the liquid crystal display device of FIG. The transistor described in Embodiment 1 can be used, and the process described in Embodiment 2 can be performed in the same manner. The TFT628 and TFT628 are transistors with excellent electrical characteristics and high reliability that can be fabricated by the above method. The FT629 is a transistor in which an oxide semiconductor layer is used as a channel formation region. In FIG. 35, an example of a transistor is shown, which is manufactured in the same manner as the transistor shown in FIG. The following description will be given of a case where a transistor that can be fabricated is used, but the present invention is not limited to this. stomach.

[0471] A VA (Vertical Alignment) type liquid crystal display device will be described below. The VA type is a type of method for controlling the arrangement of liquid crystal molecules in a liquid crystal display panel. When no voltage is applied, the liquid crystal molecules are oriented vertically to the panel surface. In this embodiment, a pixel is divided into several regions (sub-pixels). The molecules are divided into three parts (multi-domain) and tilted in different directions. In the following description, multi-domain design is taken into consideration. A liquid crystal display device will now be described.

[0472] 33 and 34 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a top view of the substrate on which electrodes are formed, showing a cross-sectional structure corresponding to a cutting line EF shown in the figure. FIG. 32 shows the structure. FIG. 34 shows a top view of the substrate on which the counter electrode is formed. The following description will be given with reference to these figures.

[0473] FIG. 32 shows a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 and the counter substrate 601 on which the counter electrode 640 and the like are formed are overlapped. , the liquid crystal is injected.

[0474] A colored layer 636 and a counter electrode 640 are formed on the counter substrate 601. An alignment film 648 is formed on the pixel electrode 624. An alignment film 646 is also formed on the electrodes 640 and the protrusions 644. A liquid crystal layer 650 is formed between the electrodes 601 .

[0475] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. The pixel electrode 624 includes a TFT 628, a wiring 618, and a storage capacitor 630. A contact hole is formed through an insulating layer 620 covering the first insulating layer 620 and a third insulating layer 622 covering the second insulating layer 620. The TFT 628 is connected to the wiring 618 through a hole 623. The transistor shown in the third embodiment can be used as appropriate. The first capacitance wiring 604 is formed at the same time as the gate wiring 602 of 628, and the gate The gate insulating layer 606 and the wirings 616 and 618 are formed at the same time as the second capacitance wiring. It is composed of line 617.

[0476] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0477] FIG. 33 shows the structure on the substrate 600. The pixel electrode 624 is made of indium containing tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium tin oxide (ITO) ), indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material having a good electrical conductivity can be used.

[0478] In addition, the pixel electrode 624 is made of a conductive material including a conductive polymer. The pixel electrode formed by using the conductive composition can be formed by a sheet Resistance is 10,000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that there is.

[0479] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0480] The pixel electrode 624 is provided with a slit 625. The slit 625 is used to control the alignment of the liquid crystal. This is for the purpose.

[0481] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. The TFT 628 and the TFT 629 are both connected to the wiring 616. The pixel is composed of a pixel electrode 624 and a pixel electrode 626. The electrode 624 and the pixel electrode 626 are a sub-pixel.

[0482] FIG. 34 shows the structure of the opposing substrate side. The opposing electrode 640 is made of the same material as the pixel electrode 624. On the counter electrode 640, there are protrusions 644 for controlling the alignment of the liquid crystal. has been formed.

[0483] The equivalent circuit of this pixel structure is shown in Figure 35. TFT628 and TFT629 both have gate The line 602 is connected to the wiring 616. In this case, the capacitance wiring 604 and the capacitance wiring 605 are connected to each other. By making the positions different, the operations of the liquid crystal elements 651 and 652 can be made different. That is, the potentials of the capacitance wiring 604 and the capacitance wiring 605 are individually controlled. The orientation of the liquid crystal is precisely controlled to widen the viewing angle.

[0484] When a voltage is applied to the pixel electrode 624 having the slit 625, The electric field is distorted (diagonal electric field). By arranging the 44 in an alternating interdigitated manner, a diagonal electric field is effectively generated and the alignment of the liquid crystal is By controlling the orientation, the liquid crystal orientation is made different depending on the location. The multi-domain structure widens the viewing angle of the LCD panel.

[0485] Next, a VA type liquid crystal display device different from the above will be described with reference to FIGS. 36 to 39. do.

[0486] 36 and 37 show the pixel structure of a VA type liquid crystal display panel. FIG. 36 shows a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The following description will refer to both figures.

[0487] In this pixel structure, one pixel has multiple pixel electrodes, each of which is connected to a TFT. Each TFT is configured to be driven by a different gate signal. That is, in a pixel with a multi-domain design, the signals applied to each pixel electrode are independent. The control circuit has a configuration in which the

[0488] The pixel electrode 624 is connected to the TFT 628 through the contact hole 623 by the wiring 618. The pixel electrode 626 is connected to the TFT through a contact hole 627 by a wiring 619. The gate wiring 602 of the TFT 628 and the gate wiring 629 of the TFT 629 are connected to each other. 603 is separated so that different gate signals can be applied. The wiring 616 that functions as a data line is used in common by the TFT 628 and the TFT 629. The TFT 628 and the TFT 629 are the transistors shown in the embodiment 1 or 3. The capacitor wiring 690 is also provided.

[0489] The pixel electrodes 624 and 626 have different shapes and are separated by a slit. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of the voltage applied to the pixel electrode 624 and the pixel electrode 626 is determined by the TFT 628 and the TFT The liquid crystal orientation is controlled by changing the FT629. The circuit is shown in FIG. 39. The TFT 628 is connected to the gate wiring 602, and the TFT 629 is connected to the gate wiring 603. The gate wiring 602 and the gate wiring 603 are connected to each other. By doing so, it is possible to make the operation timing of the TFT 628 and the TFT 629 different.

[0490] A colored layer 636 and a counter electrode 640 are formed on the counter substrate 601. A flattening layer 637 is formed between the electrode 36 and the counter electrode 640 to prevent the alignment of the liquid crystal from being disturbed. FIG. 38 shows the structure of the opposing substrate side. The opposing electrode 640 is shared between different pixels. The electrode has a slit 641 formed therein. The slit 641 and the pixel electrode 62 4 and the slit 625 on the pixel electrode 626 side are arranged so as to interdigitate with each other. Therefore, the electric field can be effectively generated to control the alignment of the liquid crystal. The direction in which the screen faces can be varied depending on the location, widening the viewing angle.

[0491] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped. The first liquid crystal element and the second liquid crystal element are formed in one pixel. It is a multi-domain structure in which children are provided.

[0492] In this embodiment, a liquid crystal display having the transistor described in Embodiment 1 or 3 is Although the VA type liquid crystal display device has been explained as the display device, IPS type liquid crystal display devices and T It is also applicable to N-type liquid crystal display devices.

[0493] The transistor in the pixel portion of the liquid crystal display device can be manufactured by the method for manufacturing the transistor described in Embodiment 2. By creating a transistor, the difference caused by the variation in the threshold voltage of the transistor in each pixel can be reduced. This makes it possible to suppress display unevenness.

[0494] (Embodiment 12) In this embodiment, a display device having a circuit configuration different from that of the first or third embodiment is provided. One embodiment of the substrate will be described with reference to FIG.

[0495] The structure of a pixel provided in a display device is shown in FIG. 40. FIG. 40 is a cross-sectional view showing the layered structure of a pixel. do.

[0496] The cross section A1-A2 shows the layered structure of a transistor 153 used in a pixel portion. The transistor 153 is one embodiment of a bottom gate structure.

[0497] Also, the cross section B1-B2 shows the laminated structure of a capacitance section formed in a pixel section.

[0498] Also, the cross section C1-C2 shows the laminated structure at the intersection of the gate wiring and the source wiring.

[0499] The transistor of the circuit-equipped substrate of the display device exemplified in this embodiment has a channel protection layer. This is the circuit-equipped substrate of the display device exemplified in the first embodiment. The configuration of the intersection of the source wiring is different.

[0500] Specifically, a channel formation region of the oxide semiconductor layer 113a of the transistor 153 is A fourth insulating layer 114a is provided to function as a panel protection layer. At the intersection of the source wiring, the gate wiring 111c formed of the first conductive layer and the second conductive layer A fourth insulating layer 114b is sandwiched between source wirings 115c formed of an insulating layer.

[0501] The circuit board of the display device exemplified in this embodiment is the same as that of the display device exemplified in the first embodiment. Except for the configuration in which the circuit board, the fourth insulating layer 114a, and the fourth insulating layer 114b are provided, Since they are the same, detailed description will be omitted here.

[0502] In this embodiment, the fourth insulating layer is made of silicon oxide (SiO x (x>0) layer, the thickness The thickness of the fourth insulating layer is 300 nm. In addition to silicon oxide, aluminum, tantalum, and indium are also used. One of the oxides, nitrides, oxynitrides, or oxynitrides of tritium or hafnium These compounds can be used in a laminated form.

[0503] In this embodiment, the fourth insulating layer is formed after the oxide semiconductor layer is highly purified. The insulating layer is formed so as not to contaminate the highly purified oxide semiconductor layer by impurities such as water and hydrogen. A method that does not involve deposition of metal (such as sputtering) is selected and used.

[0504] The fourth insulating layer in contact with the oxide semiconductor layer is made of silicon oxide (SiO x ( When forming a layer (x>0), a silicon target is preferred. Silicon oxide films formed by sputtering in a nitrogen or rare gas atmosphere are composed of silicon atoms or contains many dangling bonds of oxygen atoms.

[0505] The impurities remaining in the oxide semiconductor layer are dangling bonds of silicon atoms or oxygen atoms. The oxide semiconductor layer is then diffused into the fourth insulating layer, which contains a large amount of SiO2. Hydrogen atoms contained in 2 Compounds containing hydrogen atoms such as O diffuse into the fourth insulating layer. The fourth insulating layer is then immobilized thereon.

[0506] The fourth insulating layer is a columnar polycrystalline B-doped silicon target with a purity of 6N (resistance 0. The distance between the substrate and the target (TS distance) was 89 mm, and the pressure was 0.4 Pa, DC power supply 6 kW, pulsed in oxygen atmosphere (oxygen flow rate 100%) The film is formed by DC sputtering.

[0507] The substrate temperature during film formation may be from room temperature to 300° C., and in this embodiment, it is set to 100° C. do.

[0508] The deposition of silicon oxide films by sputtering is carried out using high-purity gases and a cryopump. This is done using a sputtering device. Also, under a rare gas (typically argon) atmosphere, oxygen It can be carried out under atmospheric conditions or under an atmosphere of rare gas (typically argon) and oxygen. Note that the oxide insulating film formed by the sputtering method is particularly dense, and impurities may enter the adjacent layer. It can be used even as a single layer as a protective film to suppress the diffusion phenomenon.

[0509] In addition, a silicon oxide target or a silicon target can be used as the target. In addition, phosphorus (P) or boron (B) doped targets are used to deposit phosphorus ( P) and boron (B) can also be added.

[0510] Next, a mask is formed on the fourth insulating layer by photolithography or inkjet printing. The mask is used to etch the fourth insulating layer 114a and the fourth insulating layer Form 114b.

[0511] In this embodiment, a fourth insulating layer made of an oxide insulating layer is formed on the highly purified oxide semiconductor layer. The impurities remaining in the oxide semiconductor layer are diffused into the fourth insulating layer and fixed. In addition, oxygen is supplied to the oxide semiconductor layer from the oxide insulating layer included in the fourth insulating layer. Oxygen vacancies in the oxide semiconductor layer can be reduced.

[0512] In addition, by sandwiching an oxide semiconductor layer and an oxide insulating film at the intersection of the gate wiring and the source wiring, This makes it possible to increase the distance between the wirings and reduce the capacitance generated at the intersections.

[0513] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. . [Explanation of symbols]

[0514] 10 Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Input terminal 22 Input terminal 23 Input terminal 24 Input terminals 25 Input terminal 26 Output terminal 27 Output terminal 31 Transistor 32 Transistor 33 Transistor 34 Transistor 35 Transistor 36 Transistor 37 Transistor 38 Transistor 39 Transistor 40 Transistor 41 Transistor 51 Power line 52 Power line 53 Power line 61 period 62 period 100 Substrates 101 Base film 102 Insulating layer 102a Insulating layer 102b Insulating layer 103 Oxide semiconductor film 107 Insulating layer 107a Insulating layer 107b Insulating layer 108 Insulating layer 109 Pixel electrode 111a Gate electrode 111b Capacitor wiring 111c Gate wiring 113a Oxide semiconductor layer 113b Oxide semiconductor layer 114a Insulating layer 114b Insulating layer 115a electrode 115b electrode 115c source wiring 128 Contact Hole 151 Transistor 152 Transistor 153 Transistor 400 Substrates 402 Insulating layer 404a Oxide semiconductor layer 404b Oxide semiconductor layer 408 Contact Hole 410a Wiring 410b Wiring 410c wiring 421a Gate electrode 421b Gate electrode 422a electrode 422b electrode 428 Insulating Layer 440A Transistor 440B Transistor 455a electrode 455b electrode 455c electrode 455d electrode 581 Transistor 585 Insulating Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 600 Substrates 601 Opposing substrate 602 Gate wiring 603 Gate wiring 604 Capacitance wiring 605 Capacitance wiring 606 Gate Insulation Layer 616 Wiring 617 Capacitance wiring 618 Wiring 619 Wiring 620 Insulating layer 622 Insulating layer 623 Contact Hole 624 Pixel electrode 625 Slit 626 Pixel electrode 627 Contact Hole 628 TFT 629 TFT 630 Holding capacity section 631 Holding capacity section 636 Colored layer 637 Planarization layer 640 Counter Electrode 641 Slit 644 Protrusion 646 Orientation Film 648 Orientation Film 650 Liquid crystal layer 651 Liquid crystal element 652 Liquid crystal element 690 Capacitance wiring 1000 Mobile Phones 1001 Case 1002 Display section 1003 Operation button 1004 External connection port 1005 Speaker 1006 Mike 2600 TFT substrate 2601 Opposing substrate 2602 Sealing material 2603 Pixel section 2604 Display element 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible wiring board 2610 cold cathode tube 2611 Reflector 2612 Circuit Board 2613 Diffuser 2631 Poster 2632 In-car advertising 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulation layer 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4040 Conductive layer 4501 Board 4502 Pixel section 4503a Signal line driver circuit 4504a Scanning line driver circuit 4505 Sealing material 4506 Board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulation layer 5300 Board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing Control Circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching transistor 6402 Driving transistor 6403 Capacitor 6404 Light emitting element 6405 Signal Line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Driving TFT 7002 Light emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7008 Electrode 7009 Bulkhead 7010 Substrate 7011 Driving TFT 7012 Light emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7020 Substrate 7021 Driving TFT 7022 Light emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Conductive film 7029 Bulkhead 7030 Gate insulation layer 7032 Insulation layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulation layer 7040 Gate insulation layer 7042 Insulation layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulation layer 7052 Protective insulation layer 7053 Planarizing insulating layer 7055 Insulation layer 9600 Television Equipment 9601 Case 9603 Display section 9605 Stand 9607 Display section 9609 Operation key 9610 Remote control device 9700 Digital Photo Frame 9701 Case 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 Slot Machine 9901 Case 9903 Display section

Claims

1. A first electrode; a first insulating layer over the first electrode; an oxide semiconductor layer located above the first insulating layer and having a region overlapping with the first electrode; a second electrode located above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer; a third electrode located above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer; a second insulating layer over the second electrode and over the third electrode; an organic resin layer above the second insulating layer; a pixel electrode located above the organic resin layer and electrically connected to the third electrode; each of the second electrode and the third electrode includes a first conductive layer and a second conductive layer having a region in contact with a top surface of the first conductive layer; an edge of a lower surface of the second conductive layer contacts an upper surface of the first conductive layer; the second conductive layer is not in contact with the oxide semiconductor layer.

2. A first electrode; a first insulating layer over the first electrode; an oxide semiconductor layer located above the first insulating layer and having a region overlapping with the first electrode; a second electrode located above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer; a third electrode located above the oxide semiconductor layer and electrically connected to the oxide semiconductor layer; a second insulating layer over the second electrode and over the third electrode; an organic resin layer above the second insulating layer; a pixel electrode located above the organic resin layer and electrically connected to the third electrode; each of the second electrode and the third electrode includes a first conductive layer and a second conductive layer having a region in contact with a top surface of the first conductive layer; the oxide semiconductor layer contains In, Ga, and Zn; an edge of a lower surface of the second conductive layer contacts an upper surface of the first conductive layer; the second conductive layer is not in contact with the oxide semiconductor layer.

Images