Semiconductor device, semiconductor module, and manufacturing method

Abstract

To improve a characteristic of a saturation current of a semiconductor device, and an ON-state voltage, etc.SOLUTION: A semiconductor device has a part operated as a transistor. The transistor includes: a gate trench part to which a gate voltage is applied; an emitter region that is contacted to the gate trench part; and a base region that is contacted to the gate trench part. A threshold value voltage that the transistor is transferred from an OFF state to an ON state at a circumference temperature of 25°C is larger than a first voltage for turning on the transistor.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, a semiconductor module, and a manufacturing method. [Background technology]

[0002] 2. Description of the Related Art Conventionally, in semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), techniques for adjusting characteristics by changing the arrangement of emitter regions, etc., have been known (see, for example, Patent Documents 1 to 3). Patent Document 1: JP 2008-91491 A Patent Document 2 Japanese Patent Application Laid-Open No. 10-173170 Patent Document 3: Japanese Patent Application Laid-Open No. 9-283755 Summary of the Invention [Problem to be solved by the invention]

[0003] In a semiconductor device, it is preferable to improve characteristics such as saturation current and on-voltage. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device having an upper surface and a lower surface, a semiconductor substrate provided with a drift region of a first conductivity type, and a portion that operates as a transistor. In the above semiconductor device, the transistor may include a gate conductive portion to which a gate voltage is applied, and a gate trench portion having a gate insulating film surrounding the gate conductive portion. In any of the above semiconductor devices, the transistor may have an emitter region of a first conductivity type that is exposed on the upper surface of the semiconductor substrate and contacts the gate trench portion. In any of the above semiconductor devices, the transistor may have a base region of a second conductivity type that is provided between the emitter region and the drift region and contacts the gate trench portion. In any of the above semiconductor devices, a first voltage may be applied to the gate trench portion as the gate voltage when the transistor is turned on. In any of the above semiconductor devices, a threshold voltage at which the transistor transitions from an off state to an on state at an ambient temperature of 25° C. may be greater than half of the first voltage.

[0005] In any of the above semiconductor devices, the threshold voltage may be equal to or greater than 55% of the first voltage.

[0006] In any of the above semiconductor devices, the threshold voltage may be 60% or more of the first voltage.

[0007] In any of the above semiconductor devices, the threshold voltage may be 70% or more of the first voltage.

[0008] In any of the above semiconductor devices, a second voltage may be applied to the gate trench when the transistor is turned off. In any of the above semiconductor devices, the threshold voltage may be closer to the first voltage than an intermediate voltage between the first voltage and the second voltage.

[0009] In any of the semiconductor devices described above, a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage may be 55% or more.

[0010] In any of the above semiconductor devices, a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage may be 60% or more.

[0011] In any of the above semiconductor devices, a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage may be 70% or less.

[0012] In any of the above semiconductor devices, the second voltage may be 0 V. In any of the above semiconductor devices, the second voltage may be −15 V.

[0013] In any one of the above semiconductor devices, a plurality of the gate trench portions may be arranged side by side.In any one of the above semiconductor devices, two dummy trench portions may be arranged between two of the gate trench portions.

[0014] The difference between the first voltage and the second voltage is Vge (V), and the total emitter width, which is the total length of the portion of the emitter region that contacts the gate trench portion per unit area, is W E (cm / cm 2 ) and the threshold voltage is V th In any one of the above semiconductor devices, the total emitter width W E may satisfy the following formula: 0.9×6.39×10 5 / (Vge+1.5-V th ) 2 ≦W E ≦1.1×6.39×10 5 / (Vge+1.5-V th ) 2

[0015] In any of the above semiconductor devices, the gate trench portion may be longitudinally aligned in a first direction on the top surface of the semiconductor substrate, and the emitter region may be longer in the first direction than in a second direction perpendicular to the first direction.

[0016] Any of the above semiconductor devices may include a second conductivity type contact region exposed on the upper surface of the semiconductor substrate and in contact with the gate trench portion. In any of the above semiconductor devices, the gate trench portion may be longitudinal in a first direction on the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the emitter region and the contact region may be alternately arranged along the first direction at a position in contact with the gate trench portion. In any of the above semiconductor devices, the length of the emitter region in the first direction may be greater than the length of the contact region in the first direction at a position in contact with the gate trench portion.

[0017] In any of the above semiconductor devices, the length of the emitter region in the first direction at a position in contact with the gate trench portion may be at least twice the length of the contact region in the first direction.

[0018] A second aspect of the present invention provides a semiconductor module including the semiconductor device according to the first aspect and a control unit that applies the gate voltage to the semiconductor device.

[0019] In a third aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a semiconductor substrate having an upper surface and a lower surface, a first conductivity type drift region, and a portion that operates as a transistor. The transistor may have a gate conductive portion to which a gate voltage is applied, and a gate insulating film surrounding the gate conductive portion, a gate trench portion having a first direction as a longitudinal direction, an emitter region of the first conductivity type provided in the semiconductor substrate and exposed to the upper surface and in contact with the gate trench portion, and a base region of the second conductivity type provided between the emitter region and the drift region and in contact with the gate trench portion. The manufacturing method may estimate a first characteristic indicating a relationship between an on-voltage of the transistor and a threshold voltage of the transistor at a set value of the saturation current based on a set value of a saturation current of the transistor, a capacitance of the gate insulating film, and a channel length that is a length of the base region in contact with the gate trench portion in a depth direction of the semiconductor substrate. Any of the manufacturing methods may determine the on-voltage and the threshold voltage based on the first characteristic. In any of the above manufacturing methods, the semiconductor device may be manufactured so as to satisfy the determined on-voltage and threshold voltage.

[0020] In any of the above manufacturing methods, the on-voltage may be determined, and the threshold voltage corresponding to the on-voltage may be determined based on the first characteristic.

[0021] In any of the above manufacturing methods, the threshold voltage may be determined, and the on-voltage corresponding to the threshold voltage may be determined based on the first characteristic.

[0022] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0023] [Figure 1] FIG. 1 is a diagram illustrating an example of a semiconductor device 100. [Diagram 2] 2 is an example of an enlarged view of region D in FIG. 1. [Diagram 3] FIG. 3 is a diagram showing an example of a cross section aa of FIG. 2. [Figure 4] FIG. 3 is a diagram showing an example of a bb cross section of FIG. 2. [Diagram 5] 1 is a diagram showing the relationship between the doping concentration of the base region 14 and the threshold voltage and the saturation current. [Figure 6] 1 is a diagram showing the IV output characteristics of the semiconductor device 100 for each threshold voltage Vth. [Figure 7] 1 is a diagram showing an example of a region D of the semiconductor device 100 according to the embodiment. [Figure 8] FIG. 8 is a diagram showing an example of a cc cross section in FIG. 7. [Figure 9] FIG. 9 is a diagram showing an example of a doping concentration distribution along the mm line in FIG. [Figure 10] 13 is a diagram showing another example of the structure of the semiconductor device 100 in the region D according to the embodiment. FIG. [Figure 11] FIG. 11 is a diagram showing an example of a cross section dd in FIG. [Figure 12] 13 is a diagram showing another example of the structure of the semiconductor device 100 in the region D according to the embodiment. FIG. [Figure 13] FIG. 2 is a diagram showing an example of the ICE-VCE characteristics of the semiconductor device 100. [Figure 14] 1 is a diagram showing the relationship between the threshold voltage and the on-voltage of the semiconductor device 100. FIG. [Figure 15] 13 is a diagram showing another example of the structure of the semiconductor device 100 in the region D according to the embodiment. FIG. [Figure 16] 2A to 2C are diagrams illustrating some steps in a manufacturing method of the semiconductor device 100. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0025] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0026] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0027] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction.

[0028] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0029] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0030] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0031] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0032] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor.

[0033] In this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than that of P type or N type. The unit system in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0034] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In addition, in an N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may be the acceptor concentration. In this specification, the doping concentration in an N-type region may be referred to as the donor concentration, and the doping concentration in a P-type region may be referred to as the acceptor concentration.

[0035] When the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. When the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom count notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0037] The concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which serves as a donor in a silicon semiconductor, or the acceptor concentration of boron, which serves as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which serves as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen. Each concentration in this specification may be a value at room temperature. As an example of the value at room temperature, a value at 300 K (Kelvin) (about 26.9° C.) may be used.

[0038] FIG. 1 is a diagram showing an example of a semiconductor module 200. The semiconductor module 200 includes a semiconductor device 100 and a control unit 190. The semiconductor device 100 is, for example, a semiconductor chip formed on a semiconductor substrate 10. The control unit 190 is a circuit that controls switching of the semiconductor device 100 by applying a gate voltage to the semiconductor device 100. The control unit 190 generates a predetermined first voltage or second voltage as the gate voltage. The first voltage is a voltage generated as the gate voltage when the semiconductor device 100 is turned on. The second voltage is a voltage generated as the gate voltage when the semiconductor device 100 is turned off. The semiconductor module 200 may include a housing that houses the semiconductor device 100 and the control unit 190. The housing may be made of resin. In another example, the control unit 190 may be disposed outside the housing.

[0039] Fig. 1 is a diagram showing an example of a semiconductor device 100. Fig. 1 shows the positions of each component projected onto the upper surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0040] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon.

[0041] The semiconductor substrate 10 has a first end side 161 and a second end side 162 in a top view. When simply referred to as a top view in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two pairs of first end sides 161 that face each other in a top view. The semiconductor substrate 10 of this example also has two pairs of second end sides 162 that face each other in a top view. In FIG. 1, the first end sides 161 are parallel to the X-axis direction. The second end sides 162 are parallel to the Y-axis direction. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The first end sides 161 are perpendicular to the extension direction or longitudinal direction of the gate trench portion described later. The second end sides 162 are parallel to the extension direction or longitudinal direction of the gate trench portion described later.

[0042] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG.

[0043] In this example, the active section 160 is provided with a transistor section 70 that operates as a transistor such as an IGBT. In another example, the transistor section 70 and a diode section including a diode element such as an FWD (Free Wheel Diode) may be alternately arranged along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. Although one transistor section 70 is provided in this example, a plurality of transistor sections 70 may be provided. A P+ type well region or a gate runner may be provided between the transistor sections 70.

[0044] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a surface MOS structure periodically arranged on the upper surface side of the semiconductor substrate 10, the surface MOS structure having an N+ type emitter region, a P- type base region, an N- type drift region, a gate conductive portion, and a gate insulating film.

[0045] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed in the vicinity of a first end side 161. The vicinity of the first end side 161 refers to the region between the first end side 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring 130 is hatched with oblique lines.

[0047] The gate wiring 130 is disposed between the active portion 160 and the first end side 161 or the second end side 162 in a top view. The gate wiring 130 of this example surrounds the active portion 160 in a top view. The area surrounded by the gate wiring 130 in a top view may be the active portion 160. The gate wiring 130 is connected to a gate pad 164. The gate wiring 130 is disposed above the semiconductor substrate 10. The gate wiring 130 may be a metal wiring containing aluminum or the like. The gate wiring 130 may be provided separately from the emitter electrode.

[0048] The P-type peripheral well region 11 is provided so as to overlap with the gate wiring 130. That is, similar to the gate wiring 130, the P-type peripheral well region 11 surrounds the active section 160 in a top view. The P-type peripheral well region 11 is also provided so as to extend by a predetermined width into an area where it does not overlap with the gate wiring 130. The P-type peripheral well region 11 is a region of the second conductivity type. In this example, the P-type peripheral well region 11 is P+ type. The doping concentration of the P-type peripheral well region 11 is 5.0×10 17 atoms / cm 3 Above 5.0 x 10 19atoms / cm 3 The doping concentration of the P-type peripheral well region 11 may be 2.0×10 18 atoms / cm 3 Above 2.0×10 19 atoms / cm 3 It may be the following:

[0049] The semiconductor device 100 may include a temperature sensor (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) which simulates the operation of the transistor section 70 provided in the active section 160. The temperature sensor may be connected to the anode pad and the cathode pad via wiring. When a temperature sensor is provided, it is preferably provided in the center of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction.

[0050] In the present example, semiconductor device 100 includes an edge termination structure 90 between active section 160 and first edge 161 or second edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and first edge 161 or second edge 162. Edge termination structure 90 relieves electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf that are provided in an annular shape surrounding active section 160.

[0051] FIG. 2 is an example of an enlarged view of region D in FIG. 1. FIG. 2 shows a comparative example of the structure of region D. Region D is a region including the transistor portion 70 of the active portion 160 shown in FIG. 1. FIG. 2 shows the structure of the upper surface of the semiconductor substrate 10 in region D. In region D, the semiconductor device 100 includes one or more gate trench portions 40, one or more emitter regions 12, and one or more contact regions 15. The semiconductor device 100 may further include one or more dummy trench portions 30. In this specification, the gate trench portion 40 and the dummy trench portion 30 may each be referred to as a trench portion. When simply referred to as a trench portion in this specification, the trench portion may be either the gate trench portion 40 or the dummy trench portion 30.

[0052] The gate trench portion 40 has a longitudinal direction in a first direction on the upper surface of the semiconductor substrate 10. In this example, the gate trench portion 40 is provided extending in the Y-axis direction, which is the first direction. The gate trench portion 40 is provided from the upper surface of the semiconductor substrate 10 to the inside of the semiconductor substrate 10. A gate conductive portion made of a conductive material such as polysilicon is disposed inside the gate trench portion 40. The gate conductive portion is electrically connected to the gate wiring 130 (see FIG. 1), and a predetermined gate voltage is applied to it.

[0053] In a second direction intersecting with the first direction, a plurality of trench portions are arranged at a predetermined interval. The second direction in this example is the X-axis direction perpendicular to the first direction (Y-axis direction). As shown in FIG. 2, the trench portion adjacent to the gate trench portion 40 in the Y-axis direction may be a dummy trench portion 30. However, the gate trench portions 40 may be arranged adjacent to each other in the Y-axis direction. As shown in FIG. 2, the trench portion adjacent to the dummy trench portion 30 in the Y-axis direction may be a gate trench portion 40 or a dummy trench portion 30. One or more dummy trench portions 30 may be arranged between two gate trench portions 40 in the Y-axis direction.

[0054] In the X-axis direction, the region of the semiconductor substrate 10 sandwiched between the two trench portions is defined as the mesa portion 60. Both ends of the mesa portion 60 in the X-axis direction are boundaries with the respective trench portions. The depth position of the lower end of the mesa portion 60 is the same as the depth position of the lower end of at least one of the trench portions on both sides.

[0055] The emitter region 12 is an N+ type region exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is in contact with the gate trench portion 40. The emitter region 12 may be provided in each mesa portion 60 in contact with the gate trench portion 40. The length of one emitter region 12 in the Y-axis direction is Y11, and the length in the X-axis direction is X11. The length X11 is the same as the width of the mesa portion 60 in the X-axis direction. The length X11 is greater than the length Y11. The emitter region 12 in this example has a longitudinal direction in the X-axis direction. Each emitter region 12 may have a band shape extending in the X-axis direction. In this example, the longitudinal direction of the emitter region 12 and the longitudinal direction of the trench portion are perpendicular to each other. In this specification, a structure in which the length of the emitter region 12 in the X-axis direction and the width of the mesa portion 60 in the X-axis direction are the same may be referred to as an emitter orthogonal type.

[0056] The contact region 15 is a P-type region exposed on the upper surface of the semiconductor substrate 10 in the mesa portion 60 and connected to an emitter electrode. The contact region 15 may be a part of a base region described later, or may be a P+ type region having a higher doping concentration than the base region. When the contact region 15 has a higher doping concentration than the base region, the contact resistance between the contact region 15 and the emitter electrode can be reduced.

[0057] The contact regions 15 and the emitter regions 12 are arranged alternately along the Y-axis direction. The contact regions 15 and the emitter regions 12 may be arranged alternately in the Y-axis direction at least at positions where the contact regions 15 contact the gate trench portions 40. The contact regions 15 also have a longitudinal direction in the X-axis direction. The width of the contact regions 15 in the X-axis direction is equal to the width of the mesa portion 60 in the X-axis direction.

[0058] Fig. 3 is a diagram showing an example of the aa cross section of Fig. 2. The aa cross section is an XZ cross section passing through the emitter region 12. In this cross section, the semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0059] The emitter electrode 52 is provided above the upper surface 21 of the semiconductor substrate 10. A portion of the upper surface 21 of the semiconductor substrate 10 is covered with the interlayer insulating film 38. The emitter electrode 52 contacts at least a portion of the upper surface 21 of the semiconductor substrate 10 that is not covered with the interlayer insulating film 38. The emitter electrode 52 in this example contacts the emitter region 12. As will be described later, the emitter electrode 52 also contacts the contact region 15.

[0060] The emitter electrode 52 is formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of a metal alloy such as aluminum or an aluminum-silicon alloy, e.g., AlSi, AlSiCu, or the like. The emitter electrode 52 may have a barrier metal made of titanium, titanium nitride, or the like below the region made of aluminum or the like. The barrier metal may be in contact with the semiconductor substrate 10. The emitter electrode 52 may have a metal plug made of tungsten or the like below the region made of aluminum or the like. The metal plug may have a portion formed below the upper surface 21 of the semiconductor substrate 10.

[0061] Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Collector electrode 24 is made of a metal material such as aluminum, similar to emitter electrode 52. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0062] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 may cover each of the trench portions.

[0063] A P-type base region 14 is provided in each mesa portion 60. The base region 14 is in contact with the gate trench portion 40. The base region 14 may be in contact with each of the trench portions on both sides of the mesa portion 60. At least a portion of the base region 14 is provided below the emitter region 12. The base region 14 may be in contact with the emitter region 12. When a predetermined first voltage is applied to the gate trench portion 40, the surface layer of the base region 14 in contact with the gate trench portion 40 is inverted to an N-type region to form a channel. The channel electrically connects the emitter region 12 to a drift region 18 described later.

[0064] As will be described later, the base region 14 is also provided below the contact region 15. The base region 14 is in contact with the contact region 15. As described above, a part of the base region 14 may function as the contact region 15. The base region 14 in this example is a P-type region having a lower doping concentration than the contact region 15. The doping concentration of the base region 14 is 3.0×10 17 atoms / cm 3 It may be the following:

[0065] The semiconductor substrate 10 has an N- type drift region 18. The emitter region 12 has a doping concentration higher than that of the drift region 18. The drift region 18 is provided below the base region 14. The drift region 18 may be in contact with the base region 14. In another example, an N+ type accumulation region 16 having a doping concentration higher than that of the drift region 18 may be provided between the drift region 18 and the base region 14. By providing the accumulation region 16, an electron injection enhancement effect is generated, and the on-voltage of the semiconductor device 100 can be reduced.

[0066] A P+ type collector region 22 is provided between the drift region 18 and the lower surface 23 of the semiconductor substrate 10. The doping concentration of the collector region 22 is higher than the doping concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron. The element serving as the acceptor is not limited to the above-mentioned example. The collector region 22 is exposed to the lower surface 23 of the semiconductor substrate 10 and is connected to a collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10.

[0067] An N+ type buffer region 20 may be provided between the drift region 18 and the collector region 22. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 may have one or more concentration peaks having a doping concentration higher than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0068] The buffer region 20 may be formed by ion implantation of an N-type dopant such as hydrogen (protons) or phosphorus. In this example, the buffer region 20 is formed by ion implantation of hydrogen. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the collector region 22.

[0069] One or more gate trench portions 40 are provided on the upper surface 21 side of the semiconductor substrate 10. In this example, a plurality of gate trench portions 40 are provided on the upper surface 21 side of the semiconductor substrate 10. In this example, each gate trench portion 40 reaches the drift region 18 from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14. The trench portion penetrating the doping region is not limited to being manufactured in the order of forming the doping region and then the trench portion. The trench portion penetrating the doping region also includes a trench portion formed in which a doping region is formed between the trench portions after the trench portions are formed.

[0070] The gate trench portion 40 has a groove-shaped gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate conductive portion 44 is formed of polysilicon, which is a conductive material. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10.

[0071] The gate conductive portion 44 in the gate trench portion 40 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring 130 at a position other than the cross section shown in FIG.

[0072] The dummy trench portion 30 has a structure similar to that of the gate trench portion 40. The dummy trench portion 30 of this example has a groove-shaped dummy trench, a dummy insulating film 32, and a dummy conductive portion 34. The structures of the dummy trench, the dummy insulating film 32, and the dummy conductive portion 34 are similar to those of the gate trench, the gate insulating film 42, and the gate conductive portion 44. The dummy trench portion 30 in this cross section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52 at a position other than the cross section shown in FIG. 3.

[0073] 4 is a diagram showing an example of the bb cross section of FIG. 2. The bb cross section is an XZ cross section passing through the contact region 15. The bb cross section has a structure similar to that of the aa cross section, except that the contact region 15 is arranged instead of the emitter region 12. The contact region 15 is in contact with the emitter electrode 52 on the upper surface 21 of the semiconductor substrate 10. The contact region 15 in this example is in contact with the base region 14.

[0074] The MOS structure provided on the upper surface 21 of the semiconductor substrate 10 described in FIG. 2 to FIG. 4 has a saturation characteristic in which the collector current saturates even if the voltage between the collector and the emitter is increased. As a result, the semiconductor device 100 has a short-circuit withstand characteristic in which the element is not destroyed within a certain time in a short-circuit state in which a large current and a large voltage are simultaneously applied. In a state in which the device is miniaturized, if a MOS structure is formed in all the mesas 60, the saturation current becomes very large. Therefore, the saturation current may be suppressed by a thinning structure in which a MOS structure is not formed in some of the mesas 60, or an emitter orthogonal structure in which the emitter regions 12 having their elongated sides in the X-axis direction are discretely arranged in the Y-axis direction. However, if the saturation current is suppressed by such a structure, the on-voltage becomes high.

[0075] The current saturation characteristic of a MOS structure is expressed by the following equation (1).

number

[0076] The channel resistance Rch of the MOS structure is expressed by the following equation (2).

number

[0077] In the following explanation, the values ​​of a semiconductor element having a withstand voltage class of 1200V and a rated current of 150A will be used. Fig. 5 is a diagram showing the relationship between the threshold voltage and the saturation current and the doping concentration of the base region 14. This example shows the characteristics of the emitter-orthogonal semiconductor device 100 described in Fig. 2 to Fig. 4. As shown in Fig. 5, the higher the doping concentration of the base region 14, the lower the threshold voltage and the higher the saturation current.

[0078] FIG. 6 shows the IV output characteristics of the semiconductor device 100 in terms of the threshold voltage V thThe IV output characteristic is a characteristic showing the relationship between the collector current and the collector voltage. The rated current of the semiconductor device 100 is set in a saturation region where the collector current changes according to the collector voltage. The on-voltage (collector voltage) at the rated current of the semiconductor device 100 is a threshold voltage V th 4 and 5 show the trade-off between adjusting the doping concentration of the base region 14 to reduce the saturation current and increasing the on-state voltage.

[0079] 7 is a diagram showing an example of a region D of the semiconductor device 100 according to the embodiment. In the semiconductor device 100 according to the embodiment, the doping concentration of the base region 14 is adjusted to set the threshold voltage V th is increased and the saturation current is decreased. By increasing the threshold voltage and decreasing the saturation current, the on-voltage increases, but in the semiconductor device 100 according to the embodiment, the total emitter width Z is adjusted to suppress the increase in the on-voltage or to decrease the on-voltage. This makes it possible to achieve both a relatively low on-voltage and a relatively low saturation current. Alternatively, the on-voltage can be decreased while maintaining the saturation current.

[0080] In the semiconductor device 100 of this example, the total emitter width Z is adjusted by adjusting the arrangement of the emitter regions 12 on the upper surface 21. For example, the total emitter width Z can be increased by making the length Y1 of the emitter regions 12 in the Y-axis direction greater than the length X1 in the X-axis direction. Increasing the total emitter width Z increases the saturation current amount and decreases the on-voltage.

[0081] The length Y1 may be 1.5 times or more, 2 times or more, or 3 times or more as large as the length X1. The length X1 of the emitter region 12 in the X-axis direction may be the same as the width of the mesa portion 60 in the X-axis direction. In this case, the emitter region 12 is continuously provided in the X-axis direction from a position where the emitter region 12 contacts one of two trench portions adjacent to each other in the X-axis direction to a position where the emitter region 12 contacts the other trench portion. The length of the contact region 15 in the X-axis direction may be the same as the length of the emitter region 12 in the X-axis direction. In another example, the length X1 of the emitter region 12 may be smaller than the width of the mesa portion 60 in the X-axis direction. In this case, the emitter region 12 is disposed in contact with the gate trench portion 40, and is not in contact with another trench portion (e.g., the dummy trench portion 30) adjacent to the gate trench portion 40.

[0082] The length Y1 of the emitter region 12 may be greater than the length Y2 of the contact region 15 in the Y-axis direction. This allows the total emitter width Z to be greater. The length Y1 may be 1.5 times or more, twice or more, or three times or more, of the length Y2. The lengths of the emitter region 12 and the contact region 15 in the Y-axis direction are the lengths at the positions where they contact the gate trench portion 40.

[0083] FIG. 8 is a diagram showing an example of the cc cross section in FIG. 7. The cc cross section is an XZ cross section passing through the emitter region 12. The semiconductor device 100 of this example differs from the comparative example of FIG. 3 etc. in the doping concentration of the base region 14. The semiconductor device 100 of this example has the same structure as the semiconductor device 100 described in FIG. 1 to FIG. 6 except for the doping of the base region 14. The base region 14 of this example is a P-type region having a higher doping concentration than the base region 14 of the comparative example. By increasing the doping concentration of the base region 14, the surface layer of the base region 14 is less likely to invert to N-type, and therefore the threshold voltage of the semiconductor device 100 is increased. The threshold voltage is the voltage at which a transistor transitions from an off state to an on state. As an example, the threshold voltage is determined by the collector current-gate voltage characteristic (I CE -Vge characteristic) in the linear operating region is approximated by a straight line, the collector current I CEis the value of the gate voltage Vge when becomes 0.

[0084] A first voltage for turning on a transistor such as an IGBT, or a second voltage for turning off the transistor section 70 is applied to the gate trench section 40 as the gate voltage Vge. As an example, the first voltage is 15V, and the second voltage is 0V. The second voltage may be a voltage having a different sign from the first voltage. The second voltage may be a voltage having a different sign from the first voltage and the same absolute value. The second voltage may be -15V. The control section 190 shown in FIG. 1 may generate the first voltage and the second voltage.

[0085] In the semiconductor device 100 of this example, the threshold voltage at an ambient temperature of 25° C. is greater than half the first voltage. For example, when the first voltage is 15V, the threshold voltage is greater than 7.5V. The threshold voltage may be closer to the first voltage than the intermediate voltage between the first and second voltages. The intermediate voltage between the first and second voltages is the average voltage of the first and second voltages. For example, when the first voltage is 15V and the second voltage is 0V, the intermediate voltage is 7.5V. In this case, the threshold voltage of this example is greater than 7.5V. In this specification, the threshold voltage at an ambient temperature of 25° C. is simply referred to as the threshold voltage. In the semiconductor device 100 of the comparative example, the threshold voltage is about 6.0V. By increasing the threshold voltage, the amount of saturation current decreases.

[0086] 7, in the semiconductor device 100 of this example, the on-voltage can be reduced although the saturation current increases by adjusting the arrangement of the emitter regions 12. Therefore, by increasing the total emitter width Z to increase the saturation current within the range of the saturation current that is reduced by increasing the threshold voltage, the on-voltage can be reduced while maintaining or reducing the saturation current.

[0087] Threshold voltage V th may be 55% or more of the first voltage. th The threshold voltage V may be 65% or more of the first voltage. thThe larger the threshold voltage V, the smaller the saturation current amount, and the greater the margin for reducing the on-state voltage. When the first voltage is 15 V, the threshold voltage may be 8.5 V or more, 9.5 V or more, or 10 V or more. th If V is set too high, the semiconductor device 100 becomes difficult to turn on. th The ratio may be 80% or less, or may be 70% or less.

[0088] The difference between the first voltage and the second voltage is defined as the reference voltage Vs. For example, if the first voltage is 15 V and the second voltage is 0 V, the reference voltage Vs is 15-0=15 V. th The difference between the first voltage and the second voltage is the relative voltage Vr. For example, if the second voltage is 0V, the relative voltage Vr is V th -0=V th The ratio of the relative voltage Vr to the reference voltage Vs may be 55% or more. The ratio of the relative voltage Vr to the reference voltage Vs may be 60% or more, or may be 65% or more. The larger the relative voltage is, the smaller the saturation current amount can be, and the greater the room for lowering the on-voltage. When the first voltage is 15V and the second voltage is 0V, the threshold voltage may be 8.5V or more, 9.5V or more, or 10V or more.

[0089] If the relative voltage Vr is made too large, it becomes difficult to turn on the semiconductor device 100. The ratio of the relative voltage Vr to the reference voltage Vs may be 80% or less, or may be 70% or less.

[0090] 9 is a diagram showing an example of the doping concentration distribution along the mm line in FIG. 8. The mm line is a straight line that passes through the emitter region 12, the base region 14, and the accumulation region 16 in the mesa portion 60 that contacts the gate trench portion 40, and is parallel to the Z axis. The mm line may pass through the emitter region 12, the base region 14, and the accumulation region 16 in the vicinity of the gate trench portion 40 or at a position that contacts the gate trench portion 40. In FIG. 9, the doping concentration distribution of the semiconductor device 100 according to the embodiment of FIG. 8 and the like is shown by a solid line, and the doping concentration distribution of the semiconductor device 100 according to the comparative example of FIG. 3 and the like is shown by a dashed line.

[0091] The emitter region 12, the base region 14, and the accumulation region 16 may each have a peak of doping concentration in the depth direction. The doping concentration distribution in regions other than the base region 14 is similar in the example and the comparative example.

[0092] The maximum value of the doping concentration in the base region 14 according to the embodiment is set to be the doping concentration Db in the base region 14. By increasing the doping concentration Db, the threshold voltage V th When the gate oxide film thickness (the film thickness of the gate insulating film 42 in the example of FIG. 8) is about 110 nm, the doping concentration Db is 4.0×10 17 atoms / cm 3 The doping concentration Db may be 5.0×10 17 atoms / cm 3 or more, 6.0×10 17 atoms / cm 3 or more, 7.0×10 17 atoms / cm 3 The threshold voltage V th To prevent the doping concentration Db from becoming too high, the doping concentration Db is set to 1.0×10 18 atoms / cm 3 may be less than or equal to 8.0 x 10 17 atoms / cm 3 may be less than or equal to 7.0 x 10 17 atoms / cm 3 It may be the following.

[0093] Fig. 10 is a diagram showing another example of the structure of the semiconductor device 100 in the region D according to the embodiment. The semiconductor device 100 of this example differs from the example shown in Fig. 7 in the arrangement of the emitter region 12 and the contact region 15. The other structures are similar to those of the semiconductor device 100 of any of the aspects described in Figs. 1 to 9.

[0094] In this embodiment, the emitter region 12 has a length X1 in the X-axis direction that is smaller than the width of the mesa portion 60 in the X-axis direction. The emitter region 12 is in contact with the gate trench portion 40, and is not in contact with the dummy trench portion 30 adjacent to the gate trench portion 40. A contact region 15 is disposed between the emitter region 12 and the dummy trench portion 30. The contact region 15 is also disposed between the emitter regions 12 that are discretely disposed in the Y-axis direction. According to this embodiment, even if the length Y1 of the emitter region 12 in the Y-axis direction is increased, the area of ​​the contact region 15 exposed on the upper surface of the mesa portion 60 can be secured. This makes it easy to adjust the on-voltage. In this specification, a structure in which the length X1 of the emitter region 12 in the X-axis direction is smaller than the width of the mesa portion 60 in the X-axis direction may be referred to as an emitter parallel type.

[0095] The length Y1 of the emitter region 12 may be two or more times, three or more times, or five or more times the length X1. By making the length Y1 larger than the length X1, the length in the Y-axis direction of the channel formed below the emitter region 12 can be increased, and the channel density can be improved.

[0096] As shown in FIG. 10, in one mesa portion 60, a plurality of emitter regions 12 may be disposed spaced apart from each other in the Y-axis direction. The distance between two adjacent emitter regions 12 in the Y-axis direction (length Y2 of contact region 15 in FIG. 10) may be smaller than length Y1, and may be half or less, ¼ or less, or 1 / 10 or less of length Y1. In another example, only one emitter region 12 may be disposed continuously in the Y-axis direction of one mesa portion 60. In this case, length Y1 of emitter region 12 may be half or more, or ¾ or more, of the length of mesa portion 60 in the Y-axis direction.

[0097] 11 is a diagram showing an example of a dd cross section of FIG. 10. The dd cross section is an XZ plane passing through the emitter region 12 and the contact region 15. As described above, the emitter region 12 is disposed in contact with the gate trench portion 40, and is not in contact with the dummy trench portion 30. The contact region 15 is disposed between the emitter region 12 and the dummy trench portion 30. The structure other than the emitter region 12 and the contact region 15 is the same as that of the semiconductor device 100 of any of the aspects described in FIG. 1 to FIG. 9.

[0098] 12 is a diagram showing another example of the structure of the semiconductor device 100 in region D according to the embodiment. In the semiconductor device 100 of this example, only one emitter region 12 is provided continuously in the Y-axis direction in one mesa portion 60. The other structures are similar to those of the semiconductor device 100 of any of the aspects described with reference to FIGS. 1 to 11. According to this example, the total emitter width Z can be further increased.

[0099] FIG. 13 shows the I CE -V CE FIG. 13 is a diagram showing an example of a characteristic of the threshold voltage V th 13 shows the characteristics of a plurality of semiconductor devices 100 having different threshold voltages V th In addition, by adjusting the total channel width Z, the saturation current amount of each semiconductor device 100 is made roughly constant (about 500 A).

[0100] As shown in Figure 13, for example, the on-state voltage (collector-emitter voltage V CE ) is the threshold voltage V th The larger the saturation current is, the smaller the on-state voltage is. According to the semiconductor device 100 of the embodiment, the on-state voltage can be reduced while maintaining or reducing the saturation current. The saturation current of the semiconductor device 100 may be adjusted to be 3 times or more and 7 times or less of the rated current.

[0101] FIG. 14 is a diagram showing the relationship between the threshold voltage and the on-voltage of the semiconductor device 100. The first voltage in FIG. 13 and FIG. 14 is 15V, and the second voltage is 0V. FIG. 14 shows the on-voltage when the total channel width Z is adjusted so that the saturation current amount is approximately constant, as in the example of FIG. 13. The square plots in FIG. 14 correspond to the channel orthogonal type semiconductor device 100 shown in FIG. 2 or FIG. 7. The black square plots correspond to the comparative example shown in FIG. 2. The circle plots in FIG. 14 correspond to the emitter parallel type semiconductor device 100 shown in FIG. 10. In FIG. 14, each plot is approximated by a dashed straight line. The straight line shows the relationship between the threshold voltage and the on-voltage when the saturation current is maintained at the same level as in the comparative example. In this specification, the straight line may be referred to as a first characteristic 210. As shown in FIG. 14, by increasing the threshold voltage and adjusting the total channel width Z, the on-voltage can be lowered while maintaining the saturation current amount.

[0102] The parallel emitter semiconductor device 100 can increase the upper limit of the total channel width Z while maintaining the contact area between the contact region 15 and the emitter electrode 52. Therefore, as shown in Fig. 14, the parallel emitter semiconductor device 100 can increase the total channel width Z and maintain the saturation current amount even if the threshold voltage is made higher than that of the perpendicular emitter semiconductor device 100. By making the semiconductor device 100 a parallel emitter type, the on-voltage can be further reduced.

[0103] The threshold voltage, the channel resistance, and the on-voltage before adjusting the doping concentration of the base region 14 and the total channel width Z are V th 1, R1, and V1. The threshold voltage, the channel resistance, and the on-voltage after adjusting the doping concentration of the base region 14 and the total channel width Z while maintaining the saturation current are represented by V th The channel resistance is the resistance in the depth direction of the region where the base region 14 in contact with the gate trench portion 40 is inverted to N type when a gate voltage is applied to the gate trench portion 40.

[0104] From equation (2), the resistance ratio R2 / R1 is expressed as equation (3) below. R2 / R1=(Vge-(V th2 -1.5)) / (Vge-(V th1 -1.5) Vge is the difference between the first voltage and the second voltage, and is, for example, 15 V. Furthermore, the threshold voltage V th decreases by approximately -0.1 V when the temperature rises by 10°C. In equation (3), 1.5 V is subtracted from each threshold voltage to convert the threshold voltage at room temperature to the threshold voltage when the chip temperature is 175°C.

[0105] The decrease in on-state voltage, V1-V2, is given by the following equation (4). V1-V2=V1-V1(R2 / R1)=(1-(R2 / R1))×V1 =((V th2 -V th1 ) / (16.5-V th1 ))×V1 In equation (4), Vge=15V. For example, when the collector-emitter voltage is 1200 V, the on-state voltage V1 is about 0.4 V. Also, the threshold voltage before adjustment V th1 is set to about 6 V. As a result, the decrease in the on-state voltage ΔVon=V1-V2 is expressed by the following equation (5). ΔVon=3.81×10 -2 (V th -6) However, V in Equation (5) th is the adjusted threshold voltage V th2 It is.

[0106] The threshold voltage V of the semiconductor device 100 is set so that the decrease in the on-state voltage ΔVon is 0.1 V or more. th In this case, the threshold voltage V th1 , V th2 satisfies the following equation. V th2 ≧4.13+0.75V th1 V th1 If is 6V, V th2is 8.6 V or more. The threshold voltage of the semiconductor device 100 may be 8.6 V or more.

[0107] The threshold voltage V of the semiconductor device 100 is set so that the decrease in the on-state voltage ΔVon is 0.15 V or more. th In this case, the threshold voltage V th1 , V th2 satisfies the following equation. V th2 ≧6.19+0.625V th1 V th1 If is 6V, V th2 is 9.9 V or more. The threshold voltage of the semiconductor device 100 may be 9.9 V or more.

[0108] The total emitter width per unit area before adjustment is W E1 (cm / cm 2 ), and the total emitter width per unit area after adjustment while maintaining the saturation current is W E2 (cm / cm 2 ) The total emitter width W E is the total length in the Y-axis direction of the portion where the emitter region 12 is in contact with the gate trench portion 40 per unit area. Total emitter width W E2 and total emitter width W E1 From equations (1) and (2), we obtain equation (6) below. W E2 =((Vge-(V th1 -1.5) 2 / (Vge-(V th2 -1.5) 2 )×W E1 =((16.5-V th1 ) 2 / (16.5-V th2 ) 2 )×W E1 In this example, the total emitter width W before adjustment E1 is 5.8 x 10 3 (cm / cm 2 ). In this case, the total emitter width W E2is expressed as equation (7) below. W E2 =(110.25 / (16.5-V th2 ) 2 )×5.8×10 3 =6.39×10 5 / (16.5-V th2 ) 2 Total emitter width W of semiconductor device 100 E may satisfy the following equation (8). 0.9×6.39×10 5 / (16.5-V th ) 2 ≦W E2 ≦1.1×6.39×10 5 / (16.5-V th ) 2 Equation (8) can also be written as follows using the gate voltage Vge: 0.9×6.39×10 5 / (Vge+1.5-V th ) 2 ≦W E2 ≦1.1×6.39×10 5 / (Vge+1.5-V th ) 2 However, the threshold voltage V th is the adjusted threshold voltage V th2 For example, the threshold voltage V th is closer to the first voltage than to the intermediate voltage between the first and second voltages.

[0109] As described above, the threshold voltage V of the semiconductor device 100 is set so that the decrease in the on-state voltage ΔVon is 0.1 V or more. th When the total emitter width W E is 1.02 × 10 4 (cm / cm 2 ) or more. In addition, if the on-state voltage drop ΔVon is to be 0.15V or more, the total emitter width W E is 1.47 x 104 (cm / cm 2 ) or more.

[0110] In the semiconductor device 100 of this example, the length Lch in the depth direction of the channel (i.e., the base region 14) is about 2 μm, the gate insulating film 42 is a thermal oxide film of silicon, and the thickness of the gate insulating film 42 is 110 nm. In the semiconductor device 100, the length Lch may be 1.5 μm or more and 2.5 μm or less, and the thickness of the gate insulating film 42 may be 55 nm or more and 165 nm or less. In the semiconductor device 100, the ratio of the number of gate trench portions 40 to the number of dummy trench portions 30 in the X-axis direction may be 1:2. While satisfying these conditions, the total emitter width W E However, equation (8) may be satisfied.

[0111] FIG. 15 is a diagram showing another example of the structure of the semiconductor device 100 in the region D according to the embodiment. As shown in FIG. 2 and the like, the semiconductor device 100 has a plurality of gate trench portions 40 arranged side by side in the X-axis direction. In the example of FIG. 2 and the like, one dummy trench portion 30 is provided between two gate trench portions 40 in the X-axis direction. In this example, two dummy trench portions 30 are provided between two gate trench portions 40 in the X-axis direction. In the mesa portion 60 sandwiched between the two dummy trench portions 30, a contact region 15 may be provided instead of the emitter region 12. The structure of the mesa portion 60 in contact with the gate trench portion 40 is the same as that of the semiconductor device 100 in any of the aspects described in FIG. 1 to FIG. 14. In FIG. 15, the emitter region 12 is shown as being orthogonal to the emitter region 12, but the emitter region 12 may be parallel to the emitter region 12.

[0112] The total emitter width Z is the length in the Y-axis direction of the emitter region 12 in contact with the gate trench portion 40. Therefore, as the density of the gate trench portion 40 in the X-axis direction decreases, the upper limit of the total emitter width Z decreases. For example, in the case where the density ratio of the gate trench portion 40 to the dummy trench portion 30 is 1:2 as shown in FIG. 15, compared with the case where the density ratio of the gate trench portion 40 to the dummy trench portion 30 is 1:1 as shown in FIG. 2, the upper limit of the total emitter width Z is smaller in the example of FIG. 15.

[0113] When the upper limit of the total emitter width Z becomes smaller, the adjustment range of the saturation current amount by adjusting the total emitter width Z becomes smaller. Therefore, the threshold voltage V th If the total emitter width Z is increased too much, the saturation current amount cannot be maintained even if the total emitter width Z is adjusted. In a structure in which the ratio of the number of gate trenches 40 to the number of dummy trenches 30 is 1:2 as shown in FIG. 15, the threshold voltage V th The ratio of the difference between the first voltage and the second voltage may be 70% or less. This makes it possible to lower the on-state voltage while maintaining the saturation current amount. In this case, the threshold voltage V th may be, for example, 10.5V or less.

[0114] In the case where the ratio of the number of gate trenches 40 to the number of dummy trenches 30 is 1:1 as shown in FIG. 2, the upper limit of the total emitter width Z becomes large. In this case, the threshold voltage V th The ratio of the difference between the first voltage and the second voltage may be 80% or less. This makes it possible to lower the on-state voltage while maintaining the saturation current amount. In this case, the threshold voltage V th For example, the total emitter width W E W E =W E1200V *1200 / [Voltage class]. [Voltage class] indicates the voltage value of the voltage class of the semiconductor device. For example, if the voltage class of the semiconductor device is 1200V, the [Voltage class] is 1200. E1200V is the total emitter width of a semiconductor device with a breakdown voltage class of 1200V.

[0115] 16 is a diagram showing some steps in a manufacturing method of the semiconductor device 100. The manufacturing method of this example includes a characteristic estimation step S1002, a design step S1004, and a manufacturing step S1006.

[0116] In the characteristic estimation step S1002, a first characteristic 210 of the semiconductor device 100 is estimated. The first characteristic 210 is a relationship between the on-voltage of the transistor section 70 and the threshold voltage V th 14. In the characteristic estimation step S1002, the first characteristic 210 is estimated based on the set value of the saturation current Isat of the transistor portion 70, the capacitance Cox of the gate insulating film 42, and the channel length Lch, which is the length of the contact between the base region 14 and the gate trench portion 40 in the depth direction of the semiconductor substrate 10. In the characteristic estimation step S1002, the voltage value of the first voltage and the voltage value of the second voltage may be acquired.

[0117] The set value of the saturation current Isat may be determined based on the specifications that the semiconductor device 100 must satisfy. The set value of the capacitance Cox of the gate insulating film 42 may be calculated from the material, thickness, and other shapes of the gate insulating film 42 of the semiconductor device 100 to be manufactured. The set value of the channel length Lch may be calculated from the thickness in the depth direction of the base region 14 that contacts the gate trench portion 40 of the semiconductor device 100 to be manufactured.

[0118] In the characteristic estimation step S1002, the first characteristic 210 may be estimated using equation (1). In the characteristic estimation step S1002, a first voltage (for example, 15 V) may be used as the gate voltage Vge in equation (1).

[0119] In the design stage S1004, the on-voltage and threshold voltage of the semiconductor device 100 are determined based on the first characteristic 210. In the design stage S1004, the on-voltage that the semiconductor device 100 should satisfy may be determined, and then the threshold voltage corresponding to the on-voltage may be determined based on the first characteristic 210. In the design stage S1004, the range of the on-voltage that the semiconductor device 100 can take may be determined based on whether the semiconductor device 100 is an emitter orthogonal type or an emitter parallel type. In the design stage S1004, the on-voltage may be determined within the range. In another example, in the design stage S1004, the threshold voltage that the semiconductor device 100 should satisfy may be determined, and then the on-voltage corresponding to the threshold voltage may be determined based on the first characteristic 210.

[0120] In the manufacturing step S1006, the semiconductor device 100 is manufactured so as to satisfy the determined on-voltage and threshold voltage. In the manufacturing step S1006, the total channel width Z is determined based on the on-voltage. The relationship between the on-voltage and the total channel width Z may be calculated by simulation or may be experimentally measured in advance. The total channel width W per unit area is determined so as to satisfy the formula (8). E In the manufacturing stage S1006, the doping concentration Db of the base region 14 is determined based on the threshold voltage. The relationship between the threshold voltage and the doping concentration Db of the base region 14 may be calculated by simulation or may be experimentally measured in advance. In the manufacturing stage S1006, the semiconductor device 100 is manufactured so as to have the determined total channel width Z and doping concentration Db. This makes it possible to manufacture the semiconductor device 100 with a low on-voltage while maintaining or reducing the saturation current.

[0121] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0122] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0123] 10 semiconductor substrate, 11 P-type outer well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 Gate trench portion, 42, gate insulating film, 44, gate conductive portion, 52, emitter electrode, 60, mesa portion, 70, transistor portion, 90, edge termination structure portion, 100, semiconductor device, 130, gate wiring, 160, active portion, 161, first end edge, 162, second end edge, 164, gate pad, 190, control portion, 200, semiconductor module, 210, first characteristic

Claims

1. A semiconductor device including a semiconductor substrate having an upper surface and a lower surface, and in which a drift region of a first conductivity type is provided, the semiconductor substrate having a portion that operates as a transistor, The transistor is a gate trench portion having a gate conductive portion to which a gate voltage is applied and a gate insulating film surrounding the gate conductive portion; an emitter region of a first conductivity type provided on the upper surface of the semiconductor substrate and in contact with the gate trench portion; a second conductivity type base region provided between the emitter region and the drift region and in contact with the gate trench portion; having A first voltage is applied to the gate trench portion as the gate voltage when the transistor is turned on, The threshold voltage at which the transistor transitions from an off state to an on state at an ambient temperature of 25° C. is greater than half the first voltage. Semiconductor device.

2. The threshold voltage is equal to or greater than 55% of the first voltage. The semiconductor device according to claim 1 .

3. The threshold voltage is equal to or greater than 60% of the first voltage. The semiconductor device according to claim 1 .

4. The threshold voltage is equal to or greater than 70% of the first voltage. The semiconductor device according to claim 1 .

5. A second voltage is applied to the gate trench portion when the transistor is turned off, The threshold voltage is closer to the first voltage than to an intermediate voltage between the first voltage and the second voltage. The semiconductor device according to claim 1 .

6. a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage is 55% or more; The semiconductor device according to claim 5 .

7. a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage is 60% or more; The semiconductor device according to claim 5 .

8. a ratio of a difference between the threshold voltage and the second voltage to a difference between the first voltage and the second voltage is 70% or less; The semiconductor device according to claim 5 .

9. The second voltage is 0V. The semiconductor device according to claim 5 .

10. The second voltage is −15V. The semiconductor device according to claim 5 .

11. A plurality of the gate trench portions are arranged side by side, Two dummy trench portions are disposed between the two gate trench portions. The semiconductor device according to claim 1 .

12. The difference between the first voltage and the second voltage is Vge (V), and the total emitter width, which is the total length of the portion of the emitter region that contacts the gate trench portion per unit area, is W Ｅ (cm / cm ２ ) and the threshold voltage is V ｔｈ (V), the total emitter width W Ｅ satisfies the following equation 0.9×6.39×10 ５ / (Vge+1.5-V ｔｈ ) ２ ≦W Ｅ ≦1.1×6.39×10 ５ / (Vge+1.5-V ｔｈ ) ２ The semiconductor device according to claim 5 .

13. the first direction is a longitudinal direction of the gate trench portion on the upper surface of the semiconductor substrate, The emitter region has a length in the first direction that is longer than a length in a second direction perpendicular to the first direction. The semiconductor device according to claim 1 .

14. a second conductivity type contact region provided on the upper surface of the semiconductor substrate and in contact with the gate trench portion; the first direction is a longitudinal direction of the gate trench portion on the upper surface of the semiconductor substrate, the emitter regions and the contact regions are alternately arranged along the first direction at positions in contact with the gate trench portion, At a position where the emitter region is in contact with the gate trench portion, the length of the emitter region in the first direction is greater than the length of the contact region in the first direction. The semiconductor device according to claim 1 .

15. At a position where the emitter region contacts the gate trench portion, the length in the first direction of the emitter region is equal to or greater than twice the length of the contact region in the first direction. The semiconductor device according to claim 14.

16. A semiconductor device according to claim 1 , and a control unit that applies the gate voltage to the semiconductor device. A semiconductor module comprising:

17. 1. A method for manufacturing a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, in which a drift region of a first conductivity type is provided, the semiconductor substrate having a portion that operates as a transistor, the method comprising the steps of: The transistor has a gate conductive portion to which a gate voltage is applied and a gate insulating film surrounding the gate conductive portion, the transistor having a gate trench portion whose longitudinal direction is a first direction, an emitter region of a first conductivity type that is exposed on the upper surface of the semiconductor substrate and in contact with the gate trench portion, and a base region of a second conductivity type that is provided between the emitter region and the drift region and in contact with the gate trench portion, The manufacturing method includes: a first characteristic indicating a relationship between an on-voltage of the transistor and a threshold voltage of the transistor at a set value of the saturation current, based on a set value of a saturation current of the transistor, a capacitance of the gate insulating film, and a channel length which is a length of the base region in contact with the gate trench portion in a depth direction of the semiconductor substrate; determining the on-voltage and the threshold voltage based on the first characteristic; The semiconductor device is manufactured so as to satisfy the determined on-voltage and threshold voltage. Manufacturing method.

18. The on-voltage is determined, and the threshold voltage corresponding to the on-voltage is determined based on the first characteristic. The method of claim 17.

19. The threshold voltage is determined, and the on-voltage corresponding to the threshold voltage is determined based on the first characteristic. The method of claim 17.

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