Manufacturing method for semiconductor device

Abstract

To provide a manufacturing method for a semiconductor device that can form a locally thick insulating film in which contamination of impurities is suppressed.SOLUTION: A manufacturing method for a semiconductor device according to an embodiment includes a first deposition step, a second deposition step, and an oxidation step. The first deposition step forms a first film made of silicon on the surface of a substrate composed of silicon carbide. The second deposition step forms a second film on the surface of the first film. The oxidation step forms a third film by thermally oxidizing the first film from the surface side. In the second deposition step, the second film is not formed on a portion of the first film and the portion is exposed, or in the second deposition step, the film thickness of the second film formed on a portion of the first film is smaller than the film thickness of the second film formed on another portion.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, as semiconductor devices become smaller, there is a demand for a structure that can increase the withstand voltage while achieving smaller dimensions by locally thickening the insulating film at locations in the semiconductor device where dielectric breakdown is likely to occur. Therefore, a method has been proposed in which a film formation method such as chemical vapor deposition (CVD: Chemical Vapor Deposition, hereinafter referred to as CVD) is used to locally form a thick insulating film, but this method has the problem that impurities are easily mixed into the insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-56912 A Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a semiconductor device that is capable of forming a locally thick insulating film while suppressing the intrusion of impurities. [Means for solving the problem]

[0005] The method for manufacturing a semiconductor device according to the embodiment includes a first film forming step, a second film forming step, and an oxidation step. In the first film forming step, a first coating made of silicon is formed on a surface of a substrate made of silicon carbide. In the second film forming step, a second coating is formed on the surface of the first coating. In the oxidation step, the first coating is thermally oxidized from the surface side to form a third coating. In the second film forming step, the second coating is not formed on a portion of the first coating, and the portion is exposed. Alternatively, in the second film forming step, the thickness of the second coating formed on the portion of the first coating is smaller than the thickness of the second coating formed on the other portion. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 3 is a flowchart of a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] 3A to 3C are schematic diagrams illustrating a base material forming step according to the first embodiment. [Figure 4] 3A to 3C are schematic diagrams illustrating an ion implantation process according to the first embodiment. [Diagram 5] 5A to 5C are schematic views of a trench formation step according to the first embodiment. [Figure 6] FIG. 3 is a schematic diagram of a first film-forming step according to the first embodiment. [Figure 7] FIG. 4 is a schematic diagram of an inhibitor adsorption step in the second film-forming step according to the first embodiment. [Figure 8] 5 is a schematic diagram of a precursor adsorption step in the second film-forming step according to the first embodiment. FIG. [Figure 9] 5A to 5C are schematic diagrams illustrating a film forming step in a second film forming process according to the first embodiment. [Figure 10] FIG. 2 is a schematic diagram of a first oxidation step of the first embodiment. [Figure 11] 5A to 5C are schematic diagrams illustrating an etching process according to the first embodiment. [Figure 12] FIG. 3 is a schematic diagram of the second oxidation step of the first embodiment. [Figure 13] 5A to 5C are schematic diagrams illustrating an electrode forming step according to the first embodiment. [Figure 14]5A to 5C are schematic views illustrating a step of forming an interlayer insulating film according to the first embodiment. [Figure 15] FIG. 4 is a schematic diagram of a first oxidation step of a modified example that can be used in the first embodiment. [Figure 16] 10A to 10C are schematic diagrams illustrating a second film forming step in a modified example that can be used in the first embodiment. [Figure 17] 10 is a part of a flowchart of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] FIG. 11 is a schematic view of a precursor adsorption step in a second film-forming step according to the second embodiment. [Figure 19] FIG. 11 is a schematic view of a film forming step in a second film forming process according to the second embodiment. [Figure 20] FIG. 4 is a schematic diagram of a first oxidation step of the second embodiment. [Figure 21] 5A to 5C are schematic diagrams of the first and second etching steps of the second embodiment; [Figure 22] FIG. 11 is a schematic diagram of a third etching step in the second embodiment. [Diagram 23] FIG. 11 is a schematic diagram of a third film-forming step according to the second embodiment. [Figure 24] FIG. 4 is a schematic diagram of the second oxidation step of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to the drawings.

[0008] In this specification, the concepts of "upper" and "lower" are not necessarily terms that indicate a relationship with the direction of gravity. In the following description, n, n - and p, p - The notation indicates the relative level of impurity concentration in each conductivity type. - indicates that the n-type impurity concentration is relatively lower than that of n. - indicates that the p-type impurity concentration is relatively lower than that of p. - The types are simply n-type and p-type. - The type is sometimes simply referred to as p-type.

[0009] (First embodiment) 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 according to the present embodiment is a trench-type metal-oxide-semiconductor field-effect transistor (MOSFET, hereinafter referred to as MOSFET).

[0010] The semiconductor device 1 includes a base material 10, an insulating film 30 (gate insulating film), a gate electrode 20, an interlayer insulating film 40, a source electrode 21, a drain electrode 24, a source wiring 22, and a protective electrode 25.

[0011] The substrate 10 is made of silicon carbide (SiC). The silicon carbide constituting the substrate 10 preferably has a hexagonal crystal structure, and more preferably has the polytype 4H. The substrate 10 is formed by epitaxially growing silicon carbide on a single crystal substrate of silicon carbide. Silicon carbide (SiC) has a dielectric breakdown field approximately ten times larger than that of silicon (Si). For this reason, by using silicon carbide as the substrate 10 of the semiconductor device 1, it is possible to increase the impurity concentration while maintaining the withstand voltage, and to form a low-resistance, high-power MOSFET with little loss. The substrate 10 is made of n - The semiconductor device includes a layer 12 , a p-type body layer 13 , an n-region 14 , and a contact region 15 .

[0012] n - The layer 12 is doped with a donor to have an n-type conductivity. The p-type body layer 13 is - The n region 14 is disposed on the layer 12 and has an n-type conductivity. - Layer 12 is n - The n region 14 is provided on the p-type body layer 13. The n region 14 is n-type due to the p-type body layer 13. - The n region 14 is separated from the n layer 12. - The contact region 15 has a p-type impurity concentration higher than that of the layer 12. The p-type body layer 13 has a p -The contact region 15 is formed on a part of the p-type body layer 13 so as to be connected to the p-type body layer 13. The contact region 15 has a relatively higher p-type impurity concentration than the p-type body layer 13.

[0013] The substrate 10 has a trench 5. The trench 5 opens upward. The inner surface of the trench 5 includes a bottom surface 5b and a sidewall surface 5a extending upward from the bottom surface 5b. The bottom surface 5b of the trench 5 is n - The sidewall surface 5a of the trench 5 is disposed in the p-type body layer 13 from the top surface of the n-type region 14. - Extends to layer 12.

[0014] The insulating film 30 covers the inner surface of the trench 5, that is, the sidewall surface 5a and the bottom surface 5b. The insulating film 30 has a sidewall film 31 provided on the sidewall surface 5a of the trench 5 and a bottom film 32 provided on the bottom surface 5b. The sidewall film 31 extends upward from the bottom film 32. The thickness T2 of the bottom film 32 is larger than the thickness T1 of the sidewall film 31. When the semiconductor device 1 is driven, an electric field tends to concentrate at the corner between the bottom surface 5b and the sidewall surface 5a of the trench 5, and the withstand voltage at that point tends to become a problem. According to this embodiment, the semiconductor device 1 can be miniaturized by relatively thinning the thickness T1 of the sidewall film 31, while the withstand voltage at the corner can be increased by relatively thickening the thickness T2 of the bottom film 32, thereby forming a semiconductor device 1 with excellent insulation characteristics. The thickness T2 of the bottom film 32 is preferably, for example, 1 nm or more larger than the thickness T1 of the sidewall film 31 (T2-T1≧1 nm), and more preferably 10 nm or more larger (T2-T1≧10 nm).

[0015] The gate electrode 20 is buried in the trench 5. An insulating film 30 is interposed between the gate electrode 20 and the inner side surface of the trench 5. That is, the insulating film 30 separates the substrate 10 and the gate electrode 20 in the trench 5. The gate electrode 20 faces the surface of the p-type body layer 13 via the insulating film 30. The upper surface of the gate electrode 20 is at approximately the same height as the upper surface of the portion of the insulating film 30 located on the upper surface of the n region 14. An interlayer insulating film 40 is provided so as to cover the gate electrode 20 and the portion of the insulating film 30 that extends onto the upper surface of the n region 14.

[0016] The source electrode 21 penetrates the interlayer insulating film 40 and is in contact with each of the n region 14 and the contact region 15. The source wiring 22 is provided on the source electrode 21 and the interlayer insulating film 40 so as to be in contact with the source electrode 21. The drain electrode 24 is provided on the surface of the substrate 10 opposite to the surface on which the trench 5 is provided. The protective electrode 25 covers the drain electrode 24.

[0017] Next, a method for manufacturing the semiconductor device 1 will be described. Fig. 2 is a flow chart showing each step of the method for manufacturing the semiconductor device 1 of this embodiment. The method for manufacturing the semiconductor device 1 of this embodiment includes a base material forming step S10, an ion implantation step S20, a trench forming step S30, a first film forming step S40, a second film forming step S50, a first oxidation step (oxidation step) S60, an etching step S70, a second oxidation step (oxide film forming step) S80, a gate electrode forming step S90, an interlayer insulating film forming step S100, a source electrode forming step S110, a source wiring forming step S120, a drain electrode forming step S130, and a protective electrode forming step S140.

[0018] 3 is a schematic diagram of the base material forming step S10 of the present embodiment. In the base material forming step S10, for example, a silicon carbide single crystal substrate is formed on a silicon carbide single crystal substrate prepared in advance. - The layer 12 is formed by epitaxial growth to produce the base material 10. The single crystal substrate is removed, for example, by polishing in a final step, but this is not shown in the figure.

[0019] 4 is a schematic diagram of the ion implantation step S20 of this embodiment. In the ion implantation step S20, a p-type body layer 13, an n region 14, and a contact region 15 are formed. In the ion implantation step S20, acceptor ions such as aluminum (Al) are implanted from the upper surface of the substrate 10 to form the p-type body layer 13. In the ion implantation step S20, next, donor ions such as phosphorus (P) are implanted from the upper surface of the substrate 10 to form the n region 14. As a result, the n - A substrate 10 is formed having a layer 12, a p-type body layer 13, and an n-region 14. In an ion implantation step S20, ions of an acceptor such as aluminum are then implanted to form a contact region 15. In the manufacturing method of the present embodiment, the p-type body layer 13 and the n-region 14 may be formed by epitaxial growth accompanied by the addition of an impurity, instead of the ion implantation step S20.

[0020] Next, an activation heat treatment is performed to activate the impurities added by ion implantation. The temperature of this heat treatment is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The heat treatment time is, for example, about 30 minutes. The heat treatment atmosphere is preferably an inert gas atmosphere, for example, an argon (Ar) atmosphere.

[0021] 5 is a schematic diagram of the trench formation step S30 of this embodiment. In the trench formation step S30, a trench is formed in a substrate 10 made of silicon carbide. In the trench formation step S30, a mask 91 having an opening 91a that partially exposes the n region 14 is first formed on the substrate 10. The opening 91a of the mask 91 is formed to correspond to the position of the trench 5. In the opening 91a of the mask 91, the n region 14, the p-type body layer 13, and the n - A portion of the layer 12 is removed by etching, thereby forming a trench 5 in the substrate 10. After the trench 5 is formed, the mask 91 is removed.

[0022] 6 is a schematic diagram of the first film-forming step S40 of this embodiment. The first film-forming step S40 is a step of forming a silicon coating (first coating) 50 on the inner surface of the trench 5. The silicon coating 50 is made of silicon. In the first film-forming step S40, the silicon coating 50 is formed by, for example, low-pressure CVD (LP-CVD).

[0023] 7 to 9 are schematic diagrams showing the steps of the second film-forming step S50 of this embodiment. The second film-forming step S50 of this embodiment includes an inhibitor adsorption step S51 (FIG. 7), a precursor adsorption step S52 (FIG. 8), and a film formation step S53 (FIG. 9). The second film-forming step S50 is a step of forming a barrier film (second film) 60 by atomic layer deposition (ALD: Atomic Layer Deposition, hereinafter referred to as ALD) on a part of the silicon film 50 provided on the inner surface of the trench 5. In the following description, the region of the silicon film 50 provided on the sidewall surface 5a of the trench 5 is called the sidewall film 51, and the region provided on the bottom surface 5b of the trench 5 is called the bottom film 52. In the second film-forming step S50 of this embodiment, the barrier film 60 is formed only on the bottom film 52. In this embodiment, the barrier film 60 is made of silicon oxide (SiO2). However, the material of the barrier coating 60 is not limited to this embodiment.

[0024] FIG. 7 is a schematic diagram of the inhibitor adsorption step S51 of this embodiment. The inhibitor adsorption step S51 is a step of adsorbing a factor (hereinafter, referred to as an inhibitor 71) that inhibits the adsorption of a precursor 72 (see FIG. 8) described later to the sidewall coating 51. In the manufacturing method of the semiconductor device 1 of this embodiment, examples of the inhibitor 71 include SAMs (Self-Assembled Monolayers), SIMs (small molecule inhibitors), and surface termination using nitrogen atoms (N) and hydrogen atoms (H). In the inhibitor adsorption step S51, the inhibitor 71 is formed on the silicon coating 50 by CVD. More specifically, a gas containing the inhibitor 71 is introduced into the processing chamber. After the inhibitor 71 is adsorbed, the gas containing the inhibitor 71 is exhausted from the processing chamber.

[0025] In the inhibitor adsorption step S51 of this embodiment, the pressure of the gas containing the inhibitor 71 and the introduction time of the gas are controlled so that the inhibitor 71 does not reach the deepest part of the inner surface of the trench 5. Therefore, the inhibitor 71 is adsorbed to the upper region of the sidewall coating 51 on the inner surface of the trench 5, but is not adsorbed to the lower region of the sidewall coating 51 and the bottom coating 52.

[0026] FIG. 8 is a schematic diagram of the precursor adsorption step S52 of this embodiment. In the precursor adsorption step S52, a gas containing a precursor 72 is introduced into a processing chamber. In the manufacturing method of the semiconductor device 1 of this embodiment, the precursor 72 may be, for example, TDMAS, Orthrus, 3DMAS, or SAM24. The precursor 72 is not adsorbed to the portion of the surface of the silicon film 50 where the inhibitor 71 is adsorbed. Therefore, the precursor 72 is selectively adsorbed to the region below the sidewall film 51 and the bottom film 52 of the inner surface of the trench 5. After the precursor 72 is adsorbed, the gas containing the precursor 72 is exhausted from the processing chamber. Note that plasma may be generated when the precursor 72 is adsorbed.

[0027] FIG. 9 is a schematic diagram of the film formation step S53 of this embodiment. In the film formation step S53, a reaction gas containing a reactant that is the basis of the barrier coating 60 is introduced into the processing chamber. In the manufacturing method of the semiconductor device 1 of this embodiment, in the film formation step S53, O3 or radicals in the plasma (e.g., O radicals) are reacted with adsorbed molecules (precursors) to form SiO2. The reaction gas reacts with the atoms of the precursor 72 only at the positions where the precursor 72 is adsorbed, forming the barrier coating 60 made of silicon oxide (SiO2). Therefore, the barrier coating 60 is formed only in the region below the sidewall coating 51 and the bottom coating 52. After forming the barrier coating 60, the reaction gas is exhausted from the processing chamber.

[0028] Through the above-described second film-forming step S50, the barrier coating 60 is formed only on the region below the sidewall coating 51 and the bottom coating 52. That is, in the second film-forming step, a portion (bottom coating 52) of the silicon coating 50 provided on the inner surface of the trench 5 is covered with the barrier coating 60, and the other portion (sidewall coating 51) of the silicon coating 50 is exposed from the barrier coating 60. Therefore, the combined coating of the silicon coating 50 and the barrier coating 60 becomes locally thick in the portion where the barrier coating 60 is formed. In this embodiment, the barrier coating 60 has a thickness TA. When ALD is adopted as the second film-forming step S50, the thickness TA of the barrier coating 60 is preferably set to, for example, 300 nm or less from the viewpoint of productivity in consideration of the film-forming speed of ALD.

[0029] According to this embodiment, ALD is adopted in the second film formation step S50. In ALD, atomic layers can be formed one by one, so that the barrier film 60 can be formed with a stoichiometric composition while reducing the inclusion of impurities. Therefore, by adopting ALD as the second film formation step S50, the barrier film 60 having a uniform and highly precisely controlled film thickness can be selectively formed on a part of the inner side surface of the trench 5. In addition, when ALD is adopted in the second film formation step S50, the film formation on the sidewall film 51 can be partially restricted by using an inhibitor, so that a part of the silicon film 50 (sidewall film 51) can be exposed. In this embodiment, the case where the barrier film 60 is not formed on the sidewall film 51 in the second film formation step S50 has been described. However, as will be described in a modified example (FIG. 16) in the following paragraph, a thin barrier film 60A may be formed on the sidewall film 51. In this case, it is only necessary that the thickness of the barrier coating 60A formed on the sidewall coating 51 is smaller than the thickness of the barrier coating 60A formed on the bottom coating 52.

[0030] 10 is a schematic diagram of the first oxidation step S60 of this embodiment. The first oxidation step S60 is a step of thermally oxidizing the silicon coating 50 from the surface side to form a first oxide coating 80 made of silicon oxide (SiO2). In the first oxidation step S60, the temperature, time, oxygen concentration, etc. are adjusted to thermally oxidize only a part of the surface side of the silicon coating 50 to form the first oxide coating (third coating) 80. This thermal oxidation is performed at a temperature at which silicon is thermally oxidized but silicon carbide is not substantially thermally oxidized.

[0031] In the following description, the portion of the first oxide film 80 formed on the sidewall coating 51 is referred to as the first portion 80a, and the portion formed on the bottom coating 52 is referred to as the second portion 80b. Through the first oxidation step S60, the first portion 80a having a thickness T3 is formed on the surface of the sidewall coating 51. In addition, the second portion 80b having a thickness T4 is formed on the interface side of the bottom coating 52 with the barrier coating 60. Since the thermal oxidation of the bottom coating 52 proceeds below the first oxide film 80, it proceeds slightly slower than the thermal oxidation of the sidewall coating 51. Therefore, the thickness T4 of the second portion 80b of the first oxide film 80 is slightly smaller than the thickness T3 of the first portion 80a.

[0032] Through the first oxidation step S60, a silicon oxide (SiO2) film consisting of only the first oxide film 80 (first portion 80a) having a thickness T3 is formed on the sidewall coating 51. On the other hand, a laminated film is formed on the bottom coating 52 after the first oxidation step S60, in which the barrier coating 60 having a thickness TA and the first oxide film 80 (second portion 80b) having a thickness T4 are laminated. Here, the sum (TA+T4) of the thicknesses of the barrier coating 60 and the first oxide film 80 on the bottom coating 52 is larger than the thickness T3 of the first oxide film 80 on the sidewall coating 51 (TA+T4>T3). Therefore, the thickness (TA+T4) of the oxide film on the silicon coating 50 at the portion formed on the bottom surface 5b of the trench 5 is larger than the thickness T3 at the portion formed on the sidewall surface 5a.

[0033] FIG. 11 is a schematic diagram of the etching step S70 of the present embodiment. The etching step S70 is a step of etching and removing a part of the barrier film 60 and the first oxide film 80. The etching step S70 can be performed by various means such as wet etching using hydrofluoric acid, chemical dry etching, and reactive ion etching (RIE).

[0034] The etching step S70 of the present embodiment removes a predetermined film thickness from the surface side of the oxide film formed on the surface of the base material 10. The film thickness TB removed in the etching step S70 is larger than the film thickness T3 of the first portion 80a shown in FIG. 10 and smaller than the sum of the film thicknesses of the barrier film 60 and the second portion 80b (TA + T4) (T3 < TB < TA + T4). Therefore, only the second portion 80b of the first oxide film 80 located on the bottom surface 5b remains on the inner surface of the trench 5 after the etching step S70, and the first portion 80a on the side wall surface 5a is removed.

[0035] Note that the film thickness TB removed in the etching step S70 is preferably larger than the film thickness TA of the barrier film 60 (TB > TA). Thereby, it is possible to suppress the remaining of the oxide film derived from the barrier film 60 on the bottom surface 5b, and only the oxide film formed by thermal oxidation can be left, and the uniformity of the crystal of the insulating film 30 can be improved. Note that the barrier film 60 does not necessarily have to be completely removed and may be left.

[0036] FIG. 12 is a schematic diagram of the second oxidation step S80 of the present embodiment. The second oxidation step S80 is a step of forming the insulating film 30 by thermally oxidizing the entire silicon film 50 remaining after the first oxidation step S60 and the etching step S70. That is, the second oxidation step S80 is a step of forming an insulating film (fourth film) 30 made of silicon oxide on the inner surface of the trench 5. This thermal oxidation is performed at a temperature at which silicon is thermally oxidized and silicon carbide is not substantially thermally oxidized.

[0037] Through the second oxidation step S80, the sidewall coating 51 and the bottom coating 52 of the silicon coating 50 are oxidized, and a second oxide coating 59 derived from the silicon coating 50 is formed on the inner surface of the trench 5. The second oxide coating 59 derived from the silicon coating 50 and the first oxide coating 80 formed on the second oxide coating 59 combine to form the insulating film 30 on the inner surface of the trench 5. As described above, since the first oxide coating 80 remains only on the bottom surface 5b of the trench 5, the bottom film 32 of the insulating film 30 is composed of the second oxide coating 59 and the first oxide coating 80 derived from the silicon coating 50. On the other hand, the sidewall film 31 of the insulating film 30 is composed only of the second oxide coating 59 derived from the silicon coating 50. Therefore, in the insulating film 30, the thickness T2 of the bottom film 32 is larger than the thickness T1 of the sidewall film 31.

[0038] 13 is a schematic diagram of the gate electrode formation step S90 of the present embodiment. In the gate electrode formation step S90, the gate electrode 20 is formed inside the trench 5 and on the insulating film 30. The gate electrode 20 can be formed, for example, by depositing a conductor or doped polysilicon and performing CMP (Chemical Mechanical Polishing).

[0039] 14 is a schematic diagram of the interlayer insulating film forming step S100 of this embodiment. In the interlayer insulating film forming step S100, an interlayer insulating film 40 is formed on the gate electrode 20 and the insulating film 30 so as to cover the exposed surface of the gate electrode 20.

[0040] Next, although not specifically shown in the drawings, a source electrode forming step, a source wiring forming step, a drain electrode forming step, and a protective electrode forming step are performed, and the source electrode 21, the source wiring 22, the drain electrode 24, and the protective electrode 25 are formed in this order, as shown in Fig. 1. The source electrode 21 is formed after forming an opening in the interlayer insulating film 40 and the insulating film 30 by etching, and exposing the n region 14 and the contact region 15.

[0041] Through the above steps, a semiconductor device 1 can be manufactured that has an insulating film 30 whose film thickness T2 on the bottom surface 5b of the trench is larger than the film thickness T1 on the sidewall surface 5a.

[0042] Next, a first modified example that can be adopted in this embodiment will be described. In the manufacturing method of the semiconductor device 1 of this embodiment, in the first oxidation step S60, only a part of the silicon film 50 is oxidized from the surface side, and the oxidized part is removed in the subsequent etching step S70. However, in the first oxidation step S60, the entire silicon film 50 may be oxidized and used as it is as a part of the insulating film 30. FIG. 15 is a schematic diagram of the first oxidation step S60 of a modification that can be adopted in this embodiment. In the first oxidation step S60 of this modification, the entire silicon film 50 is thermally oxidized to form a first oxide film 80A. Also, a film consisting of the barrier film 60 and the first oxide film 80A is defined as the insulating film 30A of the modification. In the insulating film 30A of this modification, only the first oxide film 80A is disposed on the sidewall surface 5a of the trench, whereas the barrier film 60 is disposed on the bottom surface 5b in addition to the first oxide film 80A. Therefore, the insulating film 30A can have a thickness T5b on the bottom surface 5b larger than the thickness T5a on the sidewall surface 5a. After the first oxidation step S60 of this modification is performed, the gate electrode formation step S90 and subsequent steps are performed in the above-mentioned order without performing the etching step S70 and the second oxidation step S80. That is, according to this modification, it is possible to omit some steps for forming the insulating film 30A, and the manufacturing process of the semiconductor device 1 can be simplified. Note that in the above-mentioned embodiment, the barrier coating 60 is removed in the etching step S70, and the thickness of the insulating film 30 is ensured by separate thermal oxidation. As a result, in the above-mentioned embodiment, only the oxide coating formed by thermal oxidation is used as the insulating film 30, and the uniformity of the crystallinity of the insulating film 30 is improved.

[0043] Furthermore, a second modified example that can be adopted in this embodiment will be described. In the present embodiment, the case has been described in which only the silicon coating 50 remaining without being oxidized in the first oxidation step S60 (FIG. 10) is thermally oxidized in the second oxidation step S80 (FIG. 12) and used as the insulating film 30. However, after the etching step S70 (FIG. 11), a new coating made of silicon may be formed on the silicon coating 50 and the first oxide coating 80. In this case, the new silicon coating is thermally oxidized together with the silicon coating 50 in the second oxidation step S80, and forms the insulating film 30 together with the first oxide coating 80 remaining after the etching step S70 (FIG. 11). In this case, it is possible to form an insulating film 30 that is thicker than that in the present embodiment.

[0044] Furthermore, a third modified example that can be adopted in this embodiment will be described. In addition, in this embodiment, the case where ALD is adopted in the second film formation process S50 has been described. However, as a modified example of the second film formation process S50, a case where CVD is adopted is also assumed. FIG. 16 is a schematic diagram showing the modified second film formation process S50. Examples of CVD that can be adopted as the second film formation process S50 of this modified example include HDPCVD (high density plasma Chemical. Vapor Deposition), SACVD (Selective Area Chemical Vapor Deposition), and PECVD (Plasma-Enhanced Chemical. Vapor Deposition). The barrier film 60A of this modified example is formed not only on the bottom surface 5b of the trench 5 but also on the side wall surface 5a, but the film thickness TCa of the barrier film 60A on the side wall surface 5a is smaller than the film thickness TCb on the bottom surface 5b. That is, in the second film formation step S50, the thickness TCa of the barrier film 60A formed on a portion (sidewall film 51) of the silicon film 50 is smaller than the thickness TCb of the barrier film 60A formed on the other portion (bottom film 52). In this modification, similar to the above embodiment, the entire barrier film 60A is removed by the etching step S70 after the silicon film 50 is thermally oxidized in the first oxidation step S60 to form the first oxide film 80. Similar to the above embodiment, in the etching step S70, the first oxide film 80 can be left on the bottom surface 5b depending on the thickness difference of the barrier film 60A.

[0045] The components of the first embodiment will be summarized below. The manufacturing method of the semiconductor device 1 of this embodiment includes a first film formation step S40, a second film formation step S50, and a first oxidation step (oxidation step) S60. The first film formation step S40 is a step of forming a silicon coating 50 made of silicon (Si) on the surface of a substrate 10 made of silicon carbide (SiC). The second film formation step S50 is a step of forming a barrier coating 60 on a part of the surface of the silicon coating 50. The first oxidation step S60 is a step of forming a first oxide coating 80 by thermally oxidizing the silicon coating 50 from the surface side. In the second film formation step S50, the barrier coating 60 is not formed on a part of the silicon coating 50 and the part is exposed, or the thickness of the barrier coating 60 formed on the part of the silicon coating 50 is smaller than the thickness of the barrier coating 60 formed on the other part.

[0046] According to the above-mentioned configuration, after the first oxidation step S60, the thickness of the composite coating of the barrier coating 60 and the first oxide coating 80 can be locally changed on the surface of the base material 10. In the above-mentioned embodiment, the composite coating is etched (etching step S70) to leave a part of the first oxide coating 80 and form a locally thick insulating film 30. In the above-mentioned modified example (see FIG. 15), the composite coating is used as it is as the insulating film 30A to form a locally thick insulating film 30A in which the barrier coating 60 and the first oxide coating 80 are laminated. In this way, according to the above-mentioned configuration, it is possible to form the insulating films 30, 30A whose arrangement and thickness are freely adjusted by selectively adjusting the thickness of the barrier coating 60. As a result, it is possible to manufacture a semiconductor device 1 that is small in size and has excellent voltage resistance by forming the insulating films 30, 30A thick only in the parts where the insulating performance needs to be improved. According to the above-mentioned configuration, the insulating film 30A can be formed of an oxide film obtained by thermally oxidizing a film formed as silicon, or an oxide film formed by ALD. That is, according to the above-mentioned configuration, a film formed by CVD is not used as the insulating film 30, 30A. Therefore, compared to the case where an insulating film is formed by CVD, it is possible to form locally thick insulating films 30, 30A with reduced inclusion of impurities.

[0047] In the above-described configuration, the first oxidation step S60 may be a step of thermally oxidizing only a portion of the silicon film 50 to form the first oxide film 80 (FIG. 10), or a step of thermally oxidizing the entire silicon film 50 to form the first oxide film 80A (see FIG. 15).

[0048] The manufacturing method of the semiconductor device 1 of this embodiment includes an etching step S70 and a second oxidation step (oxide film forming step) S80. The etching step S70 is a step of etching the barrier film 60 and at least a part of the first oxide film 80. The second oxidation step S80 is a step of forming an insulating film (fourth film) 30 made of silicon oxide (SiO2) on the surface of the base material 10.

[0049] According to the above-mentioned configuration, the barrier coating 60 can be removed by etching in the etching step S70, and then the insulating film 30 can be formed in the second oxidation step S80. Therefore, the insulating film 30 can be formed only by thermal oxidation without leaving a coating derived from the barrier coating 60 on the insulating film 30, and the uniformity of the crystals of the insulating film 30 can be improved.

[0050] The manufacturing method of the semiconductor device 1 of this embodiment includes a trench forming step S30 of forming a trench 5 in the base material 10 before the first film forming step S40. The part of the silicon film 50 on which the barrier film 60 is not formed (or only a thin barrier film is formed) is a part formed on the sidewall surface 5a of the trench 5. The other part of the silicon film 50 on which the barrier film 60 is formed is a part formed on the bottom surface 5b of the trench 5. According to this configuration, the barrier film 60 is formed only on the bottom surface 5b of the trench 5, or the barrier film 60 on the bottom surface 5b can be made thicker than the barrier film 60 on the sidewall surface 5a. This makes it possible to improve the insulating performance of the bottom film 32 of the insulating film 30, 30A, for example, more than the insulating performance of the thinly formed part (sidewall film 31). When the semiconductor device 1 is a trench-type MOSFET, an electric field is likely to concentrate near the corner of the bottom surface 5b of the trench 5, and dielectric breakdown is likely to occur. As shown in this embodiment, by making the bottom film 32 of the insulating film 30 thicker than other portions, the insulating characteristics of the trench MOSFET can be improved.

[0051] In the manufacturing method of the semiconductor device 1 of this embodiment, the barrier coating 60 is silicon oxide (SiO2). With this configuration, both the barrier coating 60 and the first oxide coating 80 are made of silicon oxide. Therefore, the oxygen diffusion coefficients of the barrier coating 60 and the first oxide coating 80 are approximately the same, and an oxide coating of sufficient thickness can be formed below the barrier coating 60 in the first oxidation step S60. Furthermore, when the etching step S70 is performed, the barrier coating 60 and the first oxide coating 80 can be etched simultaneously, which can simplify the manufacturing process.

[0052] Second embodiment 17 is a flowchart showing some steps of a manufacturing method of the semiconductor device 1 according to the second embodiment. In the following description of each embodiment, the same components as those in the already described embodiments are denoted by the same reference numerals, and the description thereof will be omitted.

[0053] As shown in FIG. 17, the second embodiment includes a second film forming step S150, a first oxidation step S160, an etching step S170, and an oxide film forming step S180. Note that, in the manufacturing method of the second embodiment, the same configuration as the manufacturing method of the first embodiment will not be described. That is, in the second embodiment, the description of the base material forming step S10, the ion implantation step S20, the trench forming step S30, and the first film forming step S40 performed before each step shown in FIG. 17, and the description of the gate electrode forming step S90, the interlayer insulating film forming step S100, the source electrode forming step S110, the source wiring forming step S120, the drain electrode forming step S130, and the protective electrode forming step S140 performed after each step shown in FIG. 17 will not be described.

[0054] The second film formation step S150 of this embodiment includes a precursor adsorption step S151 and a film formation step S152. The second film formation step S150 is a step of forming a barrier coating (second coating) 160 by ALD on a part of the silicon coating 50 provided on the inner side surface of the trench 5. In this embodiment, the barrier coating 160 is silicon nitride (SiN).

[0055] 18 is a schematic diagram of the precursor adsorption step S151 of this embodiment. In the precursor adsorption step S151, a gas containing a precursor 172 is introduced into a processing chamber. Examples of the precursor 172 in this embodiment include chlorosilane, organic silane, and heterosilane. In addition, the gas containing the precursor 172 is exhausted from the processing chamber before it sufficiently reaches the bottom surface 5b of the trench 5. As a result, in the precursor adsorption step S151 of this embodiment, the precursor 172 is adsorbed to the sidewall coating 51 of the inner surface of the trench 5, and is not adsorbed to the bottom coating 52 and the sidewall coating 51 in the vicinity of the bottom coating 52.

[0056] 19 is a schematic diagram of the film formation step S152 of this embodiment. In the film formation step S152, a reaction gas containing a reactant that is the basis of the barrier coating 160 is introduced into the processing chamber. An example of the reaction gas is NH3 plasma. The reaction gas reacts with the atoms of the precursor 172 only at the position where the precursor 172 is adsorbed to form the barrier coating 160. Therefore, the barrier coating 160 is formed only in the region above the sidewall coating 51 in the trench 5. After forming the barrier coating 160, the reaction gas is exhausted from the processing chamber.

[0057] Through the above-described second film-forming step S150, the barrier film 160 made of silicon nitride (SiN) is formed only in the region above the sidewall film 51 in the trench 5. That is, in the second film-forming step S150, the barrier film 160 is not formed on a portion (bottom film 52) of the silicon film 50, and the portion is exposed.

[0058] As a modification of the second film formation step S150, the barrier coating 160 may be formed with a uniform thickness on the entire inner side surface including the bottom surface 5b of the trench 5 by ALD, and then only the barrier coating 160 on the bottom coating 52 may be removed by reactive ion etching (RIE). In this case, in the precursor adsorption step, the precursor is adsorbed on the entire inner side surface of the trench 5. As a result, in the film formation step, a barrier coating is formed on the entire inner side surface of the trench 5.

[0059] FIG. 20 is a schematic diagram of the first oxidation step S160 of this embodiment. The first oxidation step S160 is a step of thermally oxidizing the silicon coating 50 from the surface side to form the first oxide coating (third coating) 180. Silicon nitride (SiN) constituting the barrier coating 160 has a smaller oxygen diffusion coefficient than silicon oxide (SiO2). Therefore, in the first oxidation step S160, the thermal oxidation progresses more slowly below the barrier coating 160. Therefore, in the first oxidation step S160, the film thickness T6 of the first portion 180a of the first oxide coating 180 formed below the barrier coating 160 is smaller than the film thickness T7 of the second portion 180b exposed from the barrier coating 160. In this embodiment, only a portion of the silicon coating 50 below the barrier coating 60 on the boundary side with the barrier coating 60 becomes the first oxide coating 180. On the other hand, the silicon coating 50 exposed from the barrier coating 160 is oxidized throughout its thickness to become a first oxide coating 180 .

[0060] In this embodiment, the case where silicon nitride is used as the barrier coating 160 has been described. However, if the barrier coating 160 has an oxygen diffusion coefficient smaller than that of silicon oxide, a similar first oxide coating 180 can be formed.

[0061] 21 and 22 are schematic diagrams of the etching step S170 of this embodiment. The etching step S170 of this embodiment includes a first etching step S171 and a second etching step S172 shown in FIG. 21, and a third etching step S173 shown in FIG. 22. As shown in FIG. 21, the first etching step S171 and the second etching step S172 are steps of etching and removing the barrier coating 160 and a part of the first oxide coating 180. Furthermore, as shown in FIG. 22, the third etching step S173 is a step of etching and removing the silicon coating 50. That is, in the etching step S170 of this embodiment, etching for removing the barrier coating 160 made of silicon nitride, etching for removing the first oxide coating 180 made of silicon oxide, and etching for removing the silicon coating 50 made of silicon are performed stepwise.

[0062] As shown in FIG. 21, in the first etching step S171, the barrier film 160 is entirely removed. In the second etching step S172, only the film thickness T6 of the first portion 180a of the first oxide film 180 is etched. Therefore, after the second etching step S172, only the first oxide film 180 remains on the lower region of the sidewall surface 5a and the bottom surface 5b of the inner surface of the trench 5, and only the silicon film 50 remains on the upper region of the sidewall surface 5a. As shown in FIG. 22, in the third etching step S173, the silicon film 50 is entirely removed. Only the first oxide film 180 remains in the trench 5 after the etching step S170.

[0063] 23 and 24 are schematic diagrams of the oxide film forming step S180. The oxide film forming step S180 is a step of forming an insulating film (fourth film) 130 made of silicon oxide (SiO2) on the surface of the substrate 10. The oxide film forming step S180 of this embodiment includes a third film forming step S181 shown in FIG. 23 and a second oxidation step S182 shown in FIG.

[0064] 23, the third film-forming step S181 is a step of forming a silicon film 155 made of silicon (Si) and having a uniform thickness on the surface of the substrate 10. In the third film-forming step S181, the silicon film 155 is formed by, for example, a low-pressure CVD method (LP-CVD).

[0065] As shown in FIG. 24, the second oxidation step S182 is a step of thermally oxidizing the silicon film 155 formed in the third film formation step S181 to form a second oxide film 159. The second oxidation step S182 is performed at a temperature at which silicon is thermally oxidized and silicon carbide is not substantially thermally oxidized. Through the second oxidation step S182, a first oxide film 180 and a second oxide film 159 derived from the silicon film 155 are disposed on the inner side surface of the trench 5. The first oxide film 180 and the second oxide film 159 constitute the insulating film 130. As described above, the first oxide film 180 remains only on the bottom surface 5b of the trench 5 and on the side wall surface 5a in the vicinity of the bottom surface 5b. Therefore, on the inner side surface after the oxide film formation step S180, a locally thick insulating film 130 is formed in the lower region of the bottom surface 5b and the side wall surface 5a.

[0066] According to the manufacturing method of the semiconductor device 1 of this embodiment, the insulating film 130 can be formed locally with a large thickness on the inner side surface of the trench 5. This makes it possible to improve the insulating performance of the thickly formed portion compared to the thinly formed portion, and to manufacture a semiconductor device 1 that is small in size and has excellent voltage resistance. Furthermore, according to this embodiment, a coating film formed by CVD is not used as the insulating film 130, and it is possible to form a locally thick insulating film 130 with reduced intrusion of impurities compared to the case of forming an insulating film by CVD.

[0067] In the manufacturing method of the semiconductor device 1 of this embodiment, as shown in Fig. 20, in the second film-forming step S150, the barrier coating 160 is provided only on the upper region of the sidewall coating 51, but not on the lower region. Therefore, as shown in Fig. 24, the insulating film 130 finally formed has a stepped shape on the sidewall surface 5a of the trench 5, which further improves the insulation properties of the corners of the trench 5. However, in the second film-forming step S150, the barrier coating 160 may be provided on the entire sidewall coating 51, thereby forming an insulating film 30 having a uniform thickness on the sidewall surface 5a.

[0068] The components of the second embodiment will be summarized below. According to the manufacturing method of the semiconductor device 1 of the present embodiment, in the second film-forming step S150, the silicon coating 50 (i.e., the sidewall coating 51) provided on the sidewall surface 5a of the trench 5 is covered with the barrier coating 160, and the silicon coating 50 (i.e., the bottom coating 52) provided on the bottom surface 5b of the trench 5 is exposed from the barrier coating 160. According to this configuration, the barrier coating 160 can be formed on the sidewall surface 5a of the trench 5, and a locally thick portion can be formed on the sidewall surface 5a of the trench 5 as a coating consisting of the silicon coating 50 and the barrier coating 160.

[0069] In the manufacturing method of the semiconductor device 1 of this embodiment, similarly to the first embodiment (see FIG. 2), a trench forming step S30 of forming a trench 5 in the substrate 10 is included before the first film forming step S40. As shown in FIG. 19, a portion of the silicon coating 50 on which the barrier coating 160 is not formed (or on which only a thin barrier coating is formed) is a portion formed on the bottom surface 5b of the trench 5. The other portion of the silicon coating 50 on which the barrier coating 160 is formed is a portion formed on the sidewall surface 5a of the trench 5. In this manner, the region on which the barrier coating 160 is formed may be selected to locally thicken the film thickness of the insulating film 130.

[0070] In the manufacturing method of the semiconductor device 1 of this embodiment, the barrier coating 160 has a smaller oxygen diffusion coefficient than silicon oxide. According to this configuration, in the first oxidation step S160, the first oxide coating 180 can be formed to be thin under the barrier coating 160 and thick in the portion exposed from the barrier coating 160, as shown in FIG.

[0071] In the above-described embodiments and the modified examples, the film thickness of the insulating film 30, 30A, 130 on the bottom surface 5b in the trench 5 is locally made thicker than other portions. However, by using a similar method, the insulating film near the opening of the trench 5 can also be locally made thicker. Furthermore, even in a structure that does not have a trench 5, a locally thick insulating film can be formed.

[0072] Moreover, the above-mentioned embodiments and their modified examples can be combined with each other. As an example, a barrier coating made of the material (silicon nitride) described in the second embodiment may be provided at the position of the barrier coating described in the first embodiment. Similarly, a barrier coating made of the material (silicon oxide) described in the first embodiment may be provided at the position of the barrier coating described in the second embodiment. In these cases, for example, an insulating film can be formed in which the thicknesses of the bottom and sidewalls are reversed.

[0073] According to at least one of the embodiments described above, the barrier coatings 60, 60A, 160 can be used to form coatings of different thicknesses on the surface of the substrate 10, and locally thick insulating films 30, 30A can be formed that suppress the inclusion of impurities.

[0074] The present invention includes the following additional aspects. (Appendix 1) a first film forming step of forming a first coating made of silicon on a surface of a substrate made of silicon carbide; a second film-forming step of forming a second film on a surface of the first film; and an oxidation step of thermally oxidizing the first coating from the surface side to form a third coating, In the second film forming step, the second coating is not formed on a portion of the first coating, and the portion is exposed. Alternatively, a thickness of the second coating formed on the portion of the first coating is smaller than a thickness of the second coating formed on the other portion of the first coating. A method for manufacturing a semiconductor device. (Appendix 2) an etching step of etching the second coating and at least a portion of the third coating; and forming an oxide film on the surface of the base material, the fourth film being made of silicon oxide. 2. A method for manufacturing the semiconductor device according to claim 1. (Appendix 3) A trench forming step of forming a trench in the substrate before the first film forming step, the portion of the first coating is a portion formed on a sidewall surface of the trench, The other portion of the first coating is a portion formed on a bottom surface of the trench. 3. A method for manufacturing the semiconductor device according to claim 1 or 2. (Appendix 4) A trench forming step of forming a trench in the substrate before the first film forming step, the portion of the first coating is a portion that is deposited on a bottom surface of the trench; The other portion of the first coating is a portion formed on a sidewall surface of the trench. 3. A method for manufacturing the semiconductor device according to claim 1 or 2. (Appendix 5) The second film forming step is a step of forming the second coating by atomic layer deposition. 5. A method for manufacturing a semiconductor device according to any one of claims 1 to 4. (Appendix 6) The second coating is silicon oxide. 6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5. (Appendix 7) The second coating has a smaller oxygen diffusion coefficient than silicon oxide. 6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5.

[0075] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0076] 1…semiconductor device, 5…trench, 5a…side wall surface, 5b…bottom surface, 10…substrate, 12…layer, 30, 130…insulating film (fourth film), 50…silicone film (first film), 60, 160…baria film (second film), 80, 180…first oxidized film (third film), S30…trench formation process, S40…first film formation process, S5 0, S150...2nd film forming process, S53, S152...Film forming process, S60...1st acidification process (acidification process), S70, S170...Etching process, S80...2nd acidification process (acidification film forming process), S180...Acidification film forming process, T1, T2, T3, T4, T6, T7, TA, T5a, T5b, TCa, TCb...Film thickness

Claims

1. a first film forming step of forming a first coating made of silicon on a surface of a substrate made of silicon carbide; a second film forming step of forming a second film on a surface of the first film; and an oxidation step of thermally oxidizing the first coating from the surface side to form a third coating, In the second film forming step, the second coating is not formed on a portion of the first coating, and the portion is exposed. Alternatively, a thickness of the second coating formed on the portion of the first coating is smaller than a thickness of the second coating formed on the other portion of the first coating. A method for manufacturing a semiconductor device.

2. an etching step of etching the second coating and at least a portion of the third coating; and forming an oxide film on the surface of the base material, the fourth film being made of silicon oxide. The method for manufacturing a semiconductor device according to claim 1 .

3. A trench forming step of forming a trench in the substrate before the first film forming step, the portion of the first coating is a portion formed on a sidewall surface of the trench, The other portion of the first coating is a portion formed on a bottom surface of the trench. The method for manufacturing a semiconductor device according to claim 1 .

4. A trench forming step of forming a trench in the substrate before the first film forming step, the portion of the first coating is a portion that is deposited on a bottom surface of the trench; The other portion of the first coating is a portion formed on a sidewall surface of the trench. The method for manufacturing a semiconductor device according to claim 1 .

5. The second film forming step is a step of forming the second coating by an atomic layer deposition method. The method for manufacturing a semiconductor device according to any one of claims 1 to 4.

6. The second coating is silicon oxide. The method for manufacturing a semiconductor device according to any one of claims 1 to 4.

7. the second coating has a smaller oxygen diffusion coefficient than silicon oxide; The method for manufacturing a semiconductor device according to any one of claims 1 to 4.

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