Circuit board

Abstract

To provide a circuit board that achieves both improved reliability and miniaturization of a solder joint.SOLUTION: In an electronic control device 1, a circuit board 10 includes: a multilayer circuit where insulating layers 41 and wiring layers are alternately laminated; and a pad which is arranged on a surface layer of the multilayer circuit, and forms a joint 13a between ends 11c, 11a of an electronic component 11 to electrically connect the ends. The wiring layers include a first wiring layer 22 and a second wiring layer 23. The insulating layers include: a first via 31a which electrically connects the pad to the first wiring layer; and a second via 31b which electrically connects the first wiring layer to the second wiring layer. Among the pads, a first pad 21a is connected to the first via and a second pad 21b is not connected to the first via. The first via is arranged at a position overlapping in a lamination direction with the joint on the first pad. The second via is arranged at a position away toward the position on the other end 11a side of the electronic component relative to the position on the one end 11c side of the electronic component that is at least close to the position of the first via.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit board. [Background technology]

[0002] In order to meet the demand for autonomous driving of vehicles, in-vehicle control devices are required to be miniaturized with high density mounting. In addition, along with miniaturization, reliability of the joints of the control devices is also required. For example, Patent Document 1 discloses a circuit board in which vias other than the first via are shifted in the planar direction to improve the connection reliability of the joints. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2005-123332 A Summary of the Invention [Problem to be solved by the invention]

[0004] The technology described in Patent Document 1 does not take into consideration the inward shift in the longitudinal direction to achieve miniaturization, nor the amount of shift in the stacking direction to avoid overlapping, which also improves the reliability of other solder joints. As a result, the wiring area expands, resulting in the issue of being unable to accommodate miniaturization. [Means for solving the problem]

[0005] a first via electrically connecting the pad and the first wiring layer and a second via electrically connecting the first wiring layer and the second wiring layer; a first pad connected to the first via and a second pad not connected to the first via; the first via is arranged at a position overlapping the joint on the first pad in the stacking direction; and the second via is arranged at a position away from a position on one end of the electronic component that is closer to the position of the first via, the second via being arranged at a position toward the other end of the electronic component than a position on one end of the electronic component that is closer to the position of the first via. Effect of the Invention

[0006] According to the present invention, it is possible to provide a circuit board which achieves both improved reliability of solder joints and miniaturization. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention; [Diagram 2] 1 is a plan view of a circuit board according to an embodiment of the present invention; [Diagram 3] First variant of FIG. [Figure 4] Second Variation [Diagram 5] Third Modification DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0009] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0010] (First embodiment of the present invention and overall configuration) (Fig. 1, Fig. 2) The electronic control device 1 has a circuit board 10 formed of a multi-layer circuit, and an electronic component 11 electrically connected to the circuit board 10. The circuit board 10 has a multi-layer circuit in which insulating layers 41 and wiring layers are alternately laminated. The wiring layer has a first wiring layer 22 and a second wiring layer 23. Note that although the description of the third wiring layer and below is omitted in FIG. 1, a wiring layer and a core layer may be formed below the third wiring layer. Pads 21a and 21b that are electrically connected to the ends of the electronic component 11 are provided on the surface layer of the circuit board 10.

[0011] Each insulating layer 41 may be, for example, a glass epoxy substrate made of woven glass fiber and impregnated with epoxy resin. Each wiring layer is, for example, a wiring pattern made of copper foil formed on the surface of the insulating layer 41, and is formed through a well-known process.

[0012] Pads 21a, 21b are made of, for example, copper foil formed on one surface of insulating layer 41, and electronic component 11 is bonded to the upper surface thereof using bonding material 13 such as solder by a well-known method. Electrodes 12 formed on ends 11a, 11c of electronic component 11 are solder-bonded to the upper surfaces of pads 21a, 21b via solder fillets of bonding material 13. Note that electrodes 12 of electronic component 11 need only be formed on at least the lower and side surfaces of ends 11a, 11c of electronic component 11.

[0013] The circuit board 10 has a first via 31a, a second via 31b, a third via 32a, and a fourth via 32b between each insulating layer 41 and the wiring layers 22 and 23. The first via 31a and the third via 32a electrically connect the first wiring layer 22 to the pads 21a and 21b. The second via 31b and the fourth via 32b electrically connect the first wiring layer 22 to the second wiring layer 23. The first pad 21a is directly or indirectly electrically connected to the first via 31a and the second via 31b. The second pad 21b is directly or indirectly electrically connected to the third via 32a and the fourth via 32b.

[0014] The first via 31a electrically connects the first pad 21a and the first wiring layer 22. The second via 31b electrically connects the first wiring layer 22 and the second wiring layer 23. The third via 32a electrically connects the second pad 21b and the first wiring layer 22. The fourth via 32b electrically connects the first wiring layer 22 and the second wiring layer 23. Note that the reference numerals of the vias connecting the second wiring layer 23 and the third wiring layer are not described, but in FIG. 1, this via is provided at a position overlapping the second via 31b or the fourth via 32b in the stacking direction.

[0015] Ends 11a and 11c of electronic component 11 are electrically connected to pads 21a and 21b via electronic component electrode portions 12 and bonding material 13, and bonding portions 13a are provided at the connection portions. In FIG. 1, bonding portions 13a are provided between pads 21a and 21b and bonding material 13.

[0016] The first pad 21a is disposed on the first via 31a. Here, the first via 31a is located approximately at the center of the first pad 21a, and is disposed at a position overlapping with the electrodes on the lower and side surfaces of the end 11c of the electronic component 11 in the stacking direction. The second via 31b is provided at a position away from the position on the one end 11c side of the electronic component 11 closer to the position of at least the first via 31a toward the other end 11a of the electronic component 11.

[0017] The third via 32a electrically connected to the second pad 21b is provided at a position away from the center position of the bonding portion 13a on the second pad 21b, and does not overlap with the bonding portion 13a on the second pad in the stacking direction.

[0018] The direction in which the second via 31b is disposed away from the position of the first via 31a is the same as the direction in which the third via 32a is disposed away from the position of the bonding portion 13a on the second pad 21b. Note that the distances (movement amounts) by which the second via 31b and the third via 32a are disposed away from their respective reference positions are not necessarily the same.

[0019] In this way, by moving the second via 31b to a position away from one end 11c of the electronic component 11, which is closer to the position of the first via 31a, toward the other end 11a of the electronic component 11, the wiring area on the circuit board 10 can be reduced, and the electronic control device 1 can be made smaller.

[0020] The linear expansion coefficient of the vias and pads (both copper) is 16.8×10-6 / K, and the linear expansion coefficient of the insulating layer 120 (glass epoxy resin) is 40.0×10-6 / K. Therefore, when the temperature of the insulating layer 41, pads, and vias of the circuit board 10 rises in the thickness direction (direction perpendicular to the board surface) of the circuit board 10, the pads and vias shrink relative to the insulating layer 120, and tensile stress is generated in the solder fillets of the bonding material 13 located above the pads. In addition, if the temperature of the circuit board 10 rises and falls repeatedly, the solder fillets gradually become fatigued, and cracks may occur in the solder fillets.

[0021] For example, in a conventional configuration in which the first via 31a and the second via 31b are arranged overlapping in the thickness direction of the circuit board 10, the thermal expansion coefficients of the insulating layer 41 of the circuit board 10 and the vias are different, and therefore the first via 31a and the second via 31b, which have a smaller thermal expansion coefficient, cannot follow the deformation of the insulating layer 41, which has a larger thermal expansion coefficient, during temperature changes, and the first pad 21a is deformed as if pulled up and down. As a result, the distortion of the solder joint 13a on the first pad 21a increases, causing a decrease in joint reliability.

[0022] In contrast, the second via 31b of the circuit board 10 in one embodiment of the present invention is provided at a position farther toward the other end of the electronic component 11 than a position on one end of the electronic component 11 that is closer to the position of the first via 31a. This prevents or reduces the placement of a member (via) with a small thermal expansion coefficient at a position that overlaps with the first pad 21a in the thickness direction of the circuit board 10, and reduces the force that pulls the first pad 21a up and down by the first via 31a and the second via 31b, thereby improving the reliability of the solder joint 13a in the first pad 21a.

[0023] The second via 31b is provided at a position that does not overlap with the bonding portion 13a on the second pad 21b in the stacking direction. As described above, the third via 32a electrically connected to the second pad 21b is provided at a position that does not overlap with the bonding portion 13a on the second pad 21b in the stacking direction.

[0024] In this way, tilting of the electronic component 11 due to a via with a small thermal expansion coefficient deforming the second pad 21b in the vertical direction during temperature changes, which previously occurred when the solder joint 13a of the second via 31b and the second pad 21b overlapped in the stacking direction, or when the solder joint 13a of the third via 32a and the second pad 21b overlapped in the stacking direction, can be prevented, and a decrease in solder joint reliability on the other end 11a side can be suppressed, thereby improving the solder joint reliability.

[0025] Here, the electronic component 11 can be, for example, a chip component such as a chip resistor or a chip capacitor as an EC. Note that, regarding the size of each component described in the present invention, for example, the electronic component 11 has a longitudinal length of 0.6 mm, a height of 0.23 mm, and a lateral length of 0.3 mm, the longitudinal and lateral lengths of the first pad are 0.35 mm, the longitudinal length of the second pad is 0.76 mm, and a lateral length of 0.35 mm, and the diameter of the via is 0.1 mm, but is not limited to these sizes.

[0026] In recent years, electronic components have been miniaturized to improve the mounting density on a circuit board. When the electronic component 11 is miniaturized, if the second via 31b is shifted in a direction away from the electronic component 11 (starting from a position on one end side of the electronic component 11 close to the position of the first pad 21a and moving away from the other end side of the electronic component 11) in order to improve the reliability of the solder joint 13a of the first pad 21a, the wiring area will expand, and the demand for miniaturization will not be met. On the other hand, when the electronic component 11 is miniaturized, the reliability of the solder joint 13a of other pads (for example, the second pad 21b) will decrease depending on the shift direction and shift amount of the second via 31b, so that the shift direction and shift amount of the second via 31b are restricted. For example, if the second via 31b is shifted in the short-side direction of the electronic component 11, the electronic component 11 will tilt in the shift direction of the second via 31b, and the reliability of the solder joint 13a will decrease.

[0027] Therefore, in one embodiment of the present invention, the circuit board 10 has the second via 31b located at a position toward the other end of the electronic component 11 away from the position of one end of the electronic component 11 that is closer to the position of the first via 31a, and also located at a position that does not overlap with the joint 13a on the second pad 21b in the stacking direction.This makes it possible to improve the reliability of the solder joint 13a while preventing the wiring area from expanding, even when the electronic component 11 is miniaturized.

[0028] (First Modification) (Figure 3) The second via 31b is provided at a position away from the position of the first via 31a along the longitudinal direction of the electronic component 11. The fourth via 32b is provided at a position away from the position of the third via 32a toward the arrangement position of the electronic component 11. This can reduce deformation of the second pad 21b that occurs when the third via 32a and the fourth via 32b overlap, and can further improve the reliability of the bonding portion 13a.

[0029] (Second Modification) (Figure 4) The configuration shown in Figure 3, for example, by arranging the second wiring layer 23 to which the second via 31b is connected and the second wiring layer 23 to which the fourth via 32b is connected close to each other along the longitudinal direction of the electronic component 11 and shifting them in the short direction of the electronic component 11 so that they do not overlap, not only improves the reliability of the joint 13a but also makes it possible to further miniaturize the electronic control device 1 in the longitudinal direction of the electronic component 11.

[0030] (Third Modification) (Figure 5) In the circuit board 10 described above, the vias provided in a layer further below the second wiring layer 23 will be described. The second wiring layer 23 and the third wiring layer 24 are electrically connected by the fifth via 31c and the sixth via 32c. The fifth via 31c is provided so as to overlap the second via 31b in the stacking direction. The sixth via 32c does not overlap the fourth via 32b in the stacking direction. In other words, of the third via 32a, the fourth via 32b, and the sixth via 32c that are directly or indirectly connected to the second pad 21b, only the fourth via 32b is provided at a position away from the positions of the third via 32a and the sixth via 32c toward the position where the electronic component 11 is arranged. In this way, the deformation of the second pad 21b can be reduced, and the reliability of the solder joint 13a is improved.

[0031] According to the embodiment of the present invention described above, the following advantageous effects are achieved.

[0032] (1) A circuit board 10 electrically connected to an electronic component 11, comprising a multilayer circuit in which insulating layers 41 and wiring layers are alternately stacked, and a pad 21 disposed on a surface layer of the multilayer circuit and electrically connected to an end of the electronic component 11 by forming a joint 13a with the end of the electronic component 11. The wiring layer has a first wiring layer 22 and a second wiring layer 23, the insulating layer 41 has vias, the vias having a first via 31a electrically connecting the pad 21 to the first wiring layer 22 and a second via 31b electrically connecting the first wiring layer 22 to the second wiring layer 23, and the pad 21 has a first pad 21a connected to the first via 31a and a second pad 21b not connected to the first via 31a. The first via 31a is disposed at a position overlapping the bonding portion 13a on the first pad 21a in the stacking direction, and the second via 31b is provided at a position away from a position on one end side of the electronic component 11 closer to the position of at least the first via 31a toward the other end side of the electronic component 11. In this way, it is possible to provide a circuit board 10 that achieves both improved reliability of the solder bonding portion 13a and miniaturization.

[0033] (2) First vias 31a are arranged at positions overlapping in the stacking direction with electrodes 12 on the bottom and side surfaces of the end portion of electronic component 11. This makes it possible to provide circuit board 10 that achieves both improved reliability of solder joints 13a and reduced size.

[0034] (3) The second via 31b does not overlap the joint portion 13a on the second pad 21b in the stacking direction, which can improve the solder joint reliability.

[0035] (4) The second via 31b is provided at a position away from the position of the first via 31a along the longitudinal direction of the electronic component 11. This can improve the reliability of the solder joint.

[0036] (5) The vias include a third via 32a electrically connected to the second pad 21b, and the third via 32a does not overlap the bonding portion 13a of the second pad 21b in the stacking direction. This can improve the solder joint reliability.

[0037] (6) The vias include a third via 32a electrically connected to the second pad 21b, and the third via 32a does not overlap the bonding portion 13a of the second pad 21b in the stacking direction, and the direction in which the second via 31b is disposed away from the position of the first via 31a is the same as the direction in which the third via 32a is disposed away from the position of the bonding portion 13a on the second pad 21b. This can improve the solder joint reliability.

[0038] (7) The vias include a third via 32a that electrically connects the second pad 21b and the first wiring layer 22, and a fourth via 32b that electrically connects the first wiring layer 22 and the second wiring layer 23, the third via 32a does not overlap the bonding portion 13a of the second pad 21b in the stacking direction, and the fourth via 32b is provided at a position away from the position of the third via 32a toward the position of the electronic component 11. This can improve the solder joint reliability.

[0039] The present invention is not limited to the above-described embodiment, and various modifications and other configurations can be combined without departing from the spirit of the present invention. Furthermore, the present invention is not limited to those having all of the configurations described in the above-described embodiment, and includes those in which some of the configurations are omitted. [Explanation of symbols]

[0040] 1 Electronic control device 10 Circuit Board 11 Electronic Components 11a Outer end (second pad side) 11c Outer end (first pad side) 12 Electronic component electrode section 13 Bonding materials 13a Joint 21 Pad 21a 1st pad 21b 2nd pad 22 1st wiring layer 23 2nd wiring layer 24 3rd wiring layer 31a 1st via 31b 2nd via 32a 3rd via 32b 4th Via 33 5th Beer 41 Insulating layer

Claims

1. A circuit board electrically connected to an electronic component, A multilayer circuit in which insulating layers and wiring layers are alternately laminated, and a pad disposed on a surface layer of the multilayer circuit and forming a joint with an end of the electronic component to electrically connect the electronic component, the wiring layer includes a first wiring layer and a second wiring layer, the insulating layer has a via; the vias include a first via that electrically connects the pad and the first wiring layer, and a second via that electrically connects the first wiring layer and the second wiring layer; the pad includes a first pad connected to the first via and a second pad not connected to the first via; the first via is disposed at a position overlapping the bonding portion on the first pad in a stacking direction; The second via is provided at a position farther toward the other end of the electronic component than a position on one end of the electronic component that is closer to the position of the first via. Circuit board.

2. 2. The circuit board according to claim 1, The first via is disposed at a position overlapping with electrodes on a bottom surface and a side surface of the end portion of the electronic component in a stacking direction. Circuit board.

3. 2. The circuit board according to claim 1, The second via does not overlap the bonding portion on the second pad in the stacking direction. Circuit board.

4. 2. The circuit board according to claim 1, The second via is provided at a position spaced apart from the position of the first via along a longitudinal direction of the electronic component. Circuit board.

5. 2. The circuit board according to claim 1, the vias include a third via electrically connected to the second pad; The third via does not overlap the bonding portion of the second pad in the stacking direction. Circuit board.

6. 2. The circuit board according to claim 1, the vias include a third via electrically connected to the second pad; the third via does not overlap the bonding portion of the second pad in the stacking direction, A direction in which the second via is disposed away from the position of the first via and a direction in which the third via is disposed away from the position of the bonding portion on the second pad are the same direction. Circuit board.

7. 2. The circuit board according to claim 1, the vias include a third via that electrically connects the second pad and the first wiring layer, and a fourth via that electrically connects the first wiring layer and the second wiring layer; the third via does not overlap the bonding portion of the second pad in the stacking direction, The fourth via is provided at a position away from the position of the third via toward the position of the electronic component. Circuit board.

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