Semiconductor device

Abstract

To provide a semiconductor device in which variation of forward voltage can be suppressed.SOLUTION: A base layer 12 is an ion implantation layer. A second base layer 12b has a peak position P2 in which impurity density is maximum in a boundary of an emitter region 17 and in a depth being different from a boundary of a barrier region 16, between the emitter region 17 and the barrier region 17. A contact region 18 and a first conductivity type stabilization layer 19 are formed in a surface layer part of a second base layer 12b of an FWD region. A first electrode 22 is electrically connected to the contact region 18 and the stabilization layer 19 in the FWD region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device in which an insulated gate bipolar transistor (hereinafter referred to as IGBT) element having an insulated gate structure and a free wheel diode (hereinafter referred to as FWD) element are formed on a common semiconductor substrate. [Background technology]

[0002] Conventionally, semiconductor devices in which an IGBT element is formed have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a P-type base layer is disposed on an N-type drift layer, and an N-type emitter region is formed in a surface layer of the base layer. In this semiconductor device, an N-type barrier region is disposed in the base layer to divide the base layer in the thickness direction so as to suppress the inflow of holes (i.e., carriers) from the drift layer to the base layer when the IGBT region is in an on-state.

[0003] In addition, in this semiconductor device, the base layer is composed of an ion-implanted layer in which P-type impurities are ion-implanted. In detail, the base layer is configured as follows, with the drift layer side portion of the base layer being the first base layer and the portion located on the opposite side of the barrier region to the first base layer being the second base layer. That is, the first base layer is formed so that the first peak position where the P-type impurity concentration is maximum is located between the barrier region and the drift layer. The second base layer is formed so that the second peak position where the P-type impurity concentration is maximum is located between the emitter region and the barrier region. The first peak position is adjusted to be a position different from the boundary with the barrier region or the drift layer, for example, adjusted to be a position that is approximately the center between the barrier region and the drift layer. The second peak position is adjusted to be a position different from the boundary with the emitter region or the barrier region, for example, adjusted to be a position that is approximately the center between the emitter region and the barrier region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2010-103326 A Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors are considering a semiconductor device having a so-called RC (short for Reverse Conducting)-IGBT structure in which an IGBT element and an FWD element are formed on a common semiconductor substrate. The present inventors are considering making the base layer of the FWD element have the same structure as that of the IGBT element in order to simplify the manufacturing process. In this semiconductor device, the base layer, emitter region, etc. are formed on one side of the semiconductor substrate.

[0006] In this case, when the second peak position of the second base layer is adjusted as described above, since the base layer is composed of an ion-implanted layer, the impurity concentration of the portion of the second base layer that constitutes one surface of the semiconductor substrate is gradually reduced from the second peak position, and the impurity concentration is likely to vary. Therefore, the forward voltage of the FWD element may vary.

[0007] An object of the present disclosure is to provide a semiconductor device capable of suppressing variations in forward voltage. [Means for solving the problem]

[0008] According to one aspect of the present disclosure, a semiconductor device has an IGBT region and an FWD region, and includes a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, a collector layer (24) of the second conductivity type formed on the side of the drift layer opposite to the base layer side in the IGBT region, and a cathode layer (25) of the first conductivity type formed on the side of the drift layer opposite to the base layer side in the FWD region, and includes a semiconductor substrate having a surface on the base layer side as one surface (10a) and a surface on the collector layer and cathode layer sides as the other surface (10b), a barrier region (16) of the first conductivity type formed in the base layer and dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on the one surface side of the semiconductor substrate, a gate insulating film (14) formed on a wall surface of a trench (13) that penetrates the base layer and the barrier region in the IGBT region to reach the drift layer, and a gate electrode (15) formed on the gate insulating film. the first electrode (22) is disposed on one surface side of the semiconductor substrate and electrically connected to the emitter region and the contact region; and a second electrode (26) is disposed on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer, wherein the base layer is an ion-implanted layer, and the second base layer has a peak position (P2) where the impurity concentration is maximum, between the emitter region and the barrier region, and at a depth different from the boundary with the emitter region and the boundary with the barrier region. A stabilization layer (19) of the first conductivity type is formed in the surface portion of the second base layer in the FWD region together with the contact region, and the first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

[0009] According to this, in the FWD region, one surface of the semiconductor substrate connected to the first electrode includes an N-type stabilization layer, and the first electrode is electrically connected to the contact region and the stabilization layer. Therefore, compared to a case in which the one surface of the semiconductor substrate in the FWD region is composed of only the contact region and the second base layer, the proportion of the second base layer, which is prone to variation in impurity concentration, in the one surface of the semiconductor substrate can be reduced, and variation in the forward voltage of the FWD element can be suppressed.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a plan view of the semiconductor device shown in FIG. [Diagram 3] FIG. 1 is a perspective cross-sectional view of an FWD element. [Figure 4] FIG. 1 is a diagram showing the relationship between the depth of a semiconductor substrate and the impurity concentration of a P-type impurity. [Diagram 5] FIG. 1 is a diagram showing the relationship between the forward voltage and forward current in an FWD element and the surface concentration of a stabilization layer. [Figure 6] FIG. 11 is a plan view of a semiconductor device according to a second embodiment. [Figure 7] FIG. 1 is a diagram showing the relationship between the emitter-collector voltage and the collector current in an IGBT element, and the surface concentration of a stabilization layer. [Figure 8] FIG. 1 is a diagram showing the relationship between the gate-emitter voltage and collector current in an IGBT element, and the peak position of the stabilization layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) A semiconductor device according to a first embodiment will be described with reference to Figures 1 to 4. The semiconductor device according to the present embodiment is suitable for use as a power switching element used in power supply circuits such as inverters and DC / DC converters.

[0014] The semiconductor device is configured by forming an IGBT region 1 that functions as an IGBT element, and an FWD region 2 that is adjacent to the IGBT region 1 and functions as an FWD element. That is, the semiconductor device of this embodiment is an RC-IGBT in which the IGBT region 1 and the FWD region 2 are formed in a common semiconductor substrate 10, which will be described later. Note that, as will be described in detail later, in this embodiment, the portion on the collector layer 24 located on the other surface 10b of the semiconductor substrate 10 is the IGBT region 1, and the portion on the cathode layer 25 located on the other surface 10b of the semiconductor substrate 10 is the FWD region 2.

[0015] The semiconductor device is N - The semiconductor substrate 10 has a P-type drift layer 11. A P-type base layer 12 is formed on the drift layer 11. Hereinafter, the surface of the semiconductor substrate 10 on the base layer 12 side is also referred to as one surface 10a, and the surface of the semiconductor substrate 10 opposite to the one surface 10a is also referred to as the other surface 10b. The semiconductor substrate 10 is formed of, for example, a silicon substrate.

[0016] A plurality of trenches 13 are formed in the semiconductor substrate 10 so as to penetrate the base layer 12 from the one surface 10a side to reach the drift layer 11. As a result, the base layer 12 is divided into a plurality of pieces by the trenches 13. In this embodiment, the plurality of trenches 13 are formed in the IGBT region 1 and the FWD region 2, respectively. In this embodiment, the plurality of trenches 13 are formed in a stripe shape with the longitudinal direction being a direction intersecting the arrangement direction of the IGBT region 1 and the FWD region 2 (i.e., the depth direction of the paper in FIG. 1). In the following, the longitudinal direction of the trenches 13 is simply referred to as the longitudinal direction, and in FIG. 2, the vertical direction of the paper is the longitudinal direction. The interval between adjacent trenches 13 (i.e., the pitch interval) is, for example, about 2 μm.

[0017] Each trench 13 is filled with a gate insulating film 14 formed so as to cover the wall surface of each trench 13, and a gate electrode 15 made of polysilicon or the like formed on this gate insulating film 14. This forms a trench gate structure.

[0018] The gate electrode 15 disposed in the trench 13 formed in the IGBT region 1 is connected to a drive circuit (not shown) via a gate wiring (not shown). A predetermined pulse-like gate voltage is applied to the gate electrode 15. The gate electrode 15 disposed in the trench 13 formed in the FWD region 2 is electrically connected to an upper electrode 22 (to be described later) and is maintained at a predetermined potential.

[0019] An N-type barrier region 16 having a higher impurity concentration than the drift layer 11 is formed in the base layer 12 so as to divide the base layer 12 in the depth direction of the semiconductor substrate 10. Hereinafter, the portion of the base layer 12 on the drift layer 11 side is also referred to as a first base layer 12a, and the portion of the base layer 12 on the one surface 10a side of the semiconductor substrate 10 is also referred to as a second base layer 12b. The base layer 12 in the IGBT region 1 and the base layer 12 in the FWD region 2 have the same configuration.

[0020] The surface layer of the second base layer 12b is made of N + The emitter region 17 and the base layer 12 are made of a P + A contact region 18 of a type is formed. In this embodiment, the emitter region 17 and the contact region 18 are formed so that a part of the surface layer of the second base layer 12b remains. That is, the emitter region 17 and the contact region 18 are formed so that one surface 10a of the semiconductor substrate 10 in the IGBT region 1 includes the second base layer 12b, the emitter region 17, and the contact region 18. In this embodiment, the emitter region 17 and the contact region 18 are formed in the IGBT region 1 so that the contact region 18, the emitter region 17, the contact region 18, and the second base layer 12b are repeatedly arranged in this order in the longitudinal direction between adjacent trenches 13.

[0021] In addition, the surface layer of the base layer 12 is provided with a P + In the FWD region 2, an N-type contact region 18 is formed. The contact region 18 in the FWD region 2 has the same configuration as the contact region 18 in the IGBT region 1. Furthermore, an N-type stabilization layer 19 is formed in the surface layer portion of the base layer 12 in the FWD region 2. In this embodiment, one surface 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the stabilization layer 19. That is, in the FWD region 2 of this embodiment, the stabilization layer 19 is formed in the entire region of the one surface 10a of the semiconductor substrate 10 except for the region where the contact region 18 is formed.

[0022] In this embodiment, the length of the contact region 18 along the longitudinal direction in the FWD region 2 is shorter than the length of the contact region 18 along the longitudinal direction in the IGBT region 1. However, the length of the contact region 18 along the longitudinal direction in the FWD region 2 and the length of the contact region 18 along the longitudinal direction in the IGBT region 1 can be changed as appropriate. For example, in the FWD region 2, the longer the length of the contact region 18 along the longitudinal direction, the smaller the forward voltage Vf becomes when the FWD element operates as a diode.

[0023] Here, the first base layer 12a and the second base layer 12b in this embodiment are ion-implanted layers formed by ion-implanting P-type impurities into the semiconductor substrate 10 and diffusing the P-type impurities. The second base layer 12b is formed so that a second peak position P2 at which the impurity concentration is maximum is between the emitter region 17 and the barrier region 16, as shown in Fig. 4. The first base layer 12a is formed so that a first peak position P1 at which the impurity concentration is maximum is between the barrier region 16 and the drift layer 11.

[0024] FIG. 4 shows the relationship between the P-type impurity concentration along the line VV in FIG. 1 and the depth from the surface 10a of the semiconductor substrate 10. The first peak position P1 is adjusted to be a position different from the boundary between the first base layer 12a and the barrier region 16 or the drift layer 11, for example, adjusted to a position that is approximately the center between the barrier region 16 and the drift layer 11. The second peak position P2 is adjusted to be a position different from the boundary between the second base layer 12b and the emitter region 17 or the barrier region 16, for example, adjusted to a position that is approximately the center between the emitter region 17 and the barrier region 16. By forming the first base layer 12a and the second base layer 12b in this manner, even if the thickness (i.e., position) of the emitter region 17 or the thickness (i.e., position) of the barrier region 16 changes slightly due to manufacturing errors or the like, the maximum values ​​of the impurity concentrations of the first base layer 12a and the second base layer 12b are the peak positions P1 and P2. Therefore, it is possible to suppress the threshold voltage Vth from fluctuating. Although not shown, the emitter region 17, the barrier region 16, and the drift layer 11 have an N-type impurity concentration higher than the P-type impurity concentration, so that the emitter region 17, the barrier region 16, and the drift layer 11 are made N-type as a whole.

[0025] An interlayer insulating film 21 made of BPSG (abbreviation of borophosphosilicate glass) or the like is formed on one surface 10a of the semiconductor substrate 10. In the interlayer insulating film 21, contact holes 21a are formed in the IGBT region 1 to expose the emitter region 17, the contact region 18, and the second base layer 12b. In the interlayer insulating film 21, contact holes 21b are formed in the FWD region 2 to expose the contact region 18 and the stabilization layer 19.

[0026] An upper electrode 22 is formed on the interlayer insulating film 21 in the IGBT region 1, electrically connected to the emitter region 17, the contact region 18, and the second base layer 12b through a contact hole 21a formed in the interlayer insulating film 21. An upper electrode 22 is formed on the interlayer insulating film 21 in the FWD region 2, electrically connected to the contact region 18 and the stabilization layer 19 through a contact hole 21b formed in the interlayer insulating film 21. In other words, an upper electrode 22 is formed on the interlayer insulating film 21, which functions as an emitter electrode in the IGBT region 1 and functions as an anode electrode in the FWD region 2.

[0027] In this embodiment, the upper electrode 22 is in ohmic junction with the emitter region 17 and the contact region 18, and the upper electrode 22 is in Schottky junction with the second base layer 12b.

[0028] In this embodiment, a contact hole 21c exposing the gate electrode 15 is formed in the interlayer insulating film 21 in the FWD region 2. The upper electrode 22 is also connected to the gate electrode 15 through this contact hole 21b. As a result, the gate electrode 15 formed in the FWD region 2 is maintained at the same potential as the upper electrode 22. In this embodiment, the upper electrode 22 corresponds to a first electrode.

[0029] An N-type field stop (hereinafter, also referred to simply as an FS layer) 23 having a higher impurity concentration than the drift layer 11 is formed on the side of the drift layer 11 opposite to the base layer 12 side (i.e., the other surface 10b side of the semiconductor substrate 10). This FS layer 23 is not necessarily required, but is provided to improve the performance of the breakdown voltage and steady loss by preventing the spread of a depletion layer, and to control the amount of holes injected from the other surface 10b side of the semiconductor substrate 10.

[0030] In the IGBT region 1, the FS layer 23 is sandwiched between the drift layer 11 and the P + In the FWD region 2, a collector layer 24 of the N type is formed on the side opposite to the drift layer 11 with the FS layer 23 interposed therebetween.+ A cathode layer 25 of a type is formed on the other surface 10b of the semiconductor substrate 10. That is, the IGBT region 1 and the FWD region 2 are defined by whether the layer formed on the other surface 10b of the semiconductor substrate 10 is a collector layer 24 or a cathode layer 25. The region on the collector layer 24 is the IGBT region 1, and the region on the cathode layer 25 is the FWD region 2.

[0031] A lower electrode 26 electrically connected to the collector layer 24 and the cathode layer 25 is formed on the side opposite to the drift layer 11 (i.e., the other surface 10b of the semiconductor substrate 10) with the collector layer 24 and the cathode layer 25 interposed therebetween. That is, the lower electrode 26 is formed to function as a collector electrode in the IGBT region 1 and to function as a cathode electrode in the FWD region 2. In this embodiment, the lower electrode 26 is in ohmic junction with the collector layer 24 and the cathode layer 25. In this embodiment, the lower electrode 26 corresponds to a second electrode.

[0032] By configuring the semiconductor device of the present embodiment in this way, an IGBT element is configured in the IGBT region 1, with the base layer 12 and contact region 18 as a base, the emitter region 17 as an emitter, and the collector layer 24 as a collector. Also, in the FWD region 2, an FWD element is configured by PN junction, with the base layer 12 and contact region 18 as an anode, and the drift layer 11, FS layer 23, and cathode layer 25 as a cathode.

[0033] The above is the configuration of the semiconductor device in this embodiment. + Type, N - The type corresponds to the first conductivity type, and P type, P + In the present embodiment, the semiconductor substrate 10 is configured as described above, and includes the collector layer 24, the cathode layer 25, the drift layer 11, the base layer 12, the barrier region 16, the emitter region 17, the contact region 18, the stabilization layer 19, and the like.

[0034] Next, the operation of the semiconductor device will be described, and the detailed configuration of the semiconductor device will be further described.

[0035] In the above-described semiconductor device, when a voltage higher than that of the upper electrode 22 is applied to the lower electrode 26, the PN junction formed between the base layer 12 and the drift layer 11 becomes reverse conductive and a depletion layer is formed. When a low-level gate voltage (e.g., 0 V) ​​that is lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15, no collector current flows between the upper electrode 22 and the lower electrode 26.

[0036] To turn on the IGBT element, a high-level gate voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 15 of the IGBT region 1 while a voltage higher than that of the upper electrode 22 is applied to the lower electrode 26. As a result, in the IGBT region 1, an inversion layer is formed in a portion of the base layer 12 that contacts the trench 13. Then, in the IGBT element, electrons are supplied to the drift layer 11 from the emitter region 17 via the inversion layer, and holes are supplied to the drift layer 11 from the collector layer 24. As a result, in the IGBT element, the resistance value of the drift layer 11 is reduced by conductivity modulation, and a collector current flows between the upper electrode 22 and the lower electrode 26.

[0037] At this time, in this embodiment, the barrier region 16 makes it difficult for holes supplied to the drift layer 11 to escape to the base layer 12 side. Therefore, the on-voltage can be reduced.

[0038] Furthermore, when the IGBT element is turned off and the FWD element is turned on (i.e., the FWD element is operated as a diode), the voltages applied to the upper electrode 22 and the lower electrode 26 are switched, and a forward bias is applied to the upper electrode 22 such that a voltage higher than that of the lower electrode 26 is applied. As a result, holes are supplied to the base layer 12 and electrons are supplied to the cathode layer 25, causing the FWD element to operate as a diode.

[0039] At this time, in this embodiment, in the FWD region 2, one surface 10a of the semiconductor substrate 10 is formed of a P-type contact region 18 and an N-type stabilization layer 19. That is, in the FWD region 2, the second base layer 12b, whose impurity concentration is likely to vary, is not exposed on the one surface 10a of the semiconductor substrate 10, and the upper electrode 22 is not in contact with the second base layer 12b. For this reason, the forward voltage Vf of the FWD element depends on the contact region 18. This makes it possible to suppress variation in the forward voltage Vf of the FWD element.

[0040] In the present embodiment, the second base layer 12b is exposed from the surface 10a of the semiconductor substrate 10 in the IGBT region 1, and the second base layer 12b is Schottky-junctioned with the upper electrode 22. Therefore, compared to a semiconductor device in which the second base layer 12b is the contact region 18, for example, it is possible to reduce the number of holes that can be injected into the second base layer 12b of the IGBT region 1 when the FWD element is in the on state. Therefore, when the voltage between the upper electrode 22 and the lower electrode 26 is switched to a reverse bias, the injection of holes is suppressed, so that the recovery current can be reduced and the recovery time can be shortened. Therefore, the switching loss can be reduced.

[0041] The inventors further studied stabilization layer 19 and obtained the following results. As shown in FIG. 5, it was confirmed that the forward voltage Vf of the FWD element increases as the surface concentration of stabilization layer 19 increases. For this reason, it is preferable to adjust the surface concentration of stabilization layer 19 appropriately depending on the application. Note that the surface concentration of stabilization layer 19 here refers to the N-type impurity concentration of stabilization layer 19 on one surface 10a of semiconductor substrate 10.

[0042] According to the present embodiment described above, in the FWD region 2, one surface 10a of the semiconductor substrate 10 connected to the upper electrode 22 includes an N-type stabilization layer 19. The upper electrode 22 is electrically connected to the contact region 18 and the stabilization layer 19. Therefore, compared to the case where the one surface 10a of the semiconductor substrate 10 in the FWD region 2 is configured from the contact region 18 and the second base layer 12b, the proportion of the second base layer 12b, which is prone to variation in impurity concentration, on the one surface 10a of the semiconductor substrate 10 can be reduced, and variation in the forward voltage Vf of the FWD element can be suppressed.

[0043] (1) In this embodiment, the FWD region 2 is formed on one surface 10a of the semiconductor substrate 10 by the contact region 18 and the stabilization layer 19. This prevents the upper electrode 22 from directly contacting the second base layer 12b, and further suppresses variations in the forward voltage Vf of the FWD element.

[0044] Second embodiment The second embodiment will be described. In contrast to the first embodiment, this embodiment has a stabilization layer 19 formed also in the IGBT region 1. As the rest is similar to the first embodiment, a description thereof will be omitted here.

[0045] In the semiconductor device of this embodiment, as shown in FIG. 6, a stabilization layer 19 is formed in the surface layer of the second base layer 12b together with the emitter region 17 and the contact region 18. The surface 10a of the semiconductor substrate 10 in the IGBT region 1 is formed of the emitter region 17, the contact region 18, and the stabilization layer 19. Specifically, in the IGBT region 1, the contact region 18, the emitter region 17, the contact region 18, and the stabilization layer 19 are repeatedly formed in this order along the longitudinal direction between adjacent trenches 13. That is, in the IGBT region 1 of this embodiment, the stabilization layer 19 is formed in the surface 10a of the semiconductor substrate 10 in the portion where the second base layer 12b in the first embodiment was exposed. The impurity concentration of the stabilization layer 19 is lower than that of the contact region 18.

[0046] The above is the configuration of the semiconductor device in this embodiment. The stabilization layer 19 in such a semiconductor device is formed as follows. That is, the stabilization layer 19 is formed by ion-implanting N-type impurities after forming the emitter region 17 and the contact region 18 in the surface layer portion of the second base layer 12b. In this case, the impurity concentration of the stabilization layer 19 is lower than that of the contact region 18, so that even if the N-type impurities are ion-implanted without placing a mask, the contact region 18 is not turned back to the N type. Therefore, in this embodiment, the stabilization layer 19 is also formed in the IGBT region 1, so that the stabilization layer 19 can be formed by ion-implanting N-type impurities without placing a mask, and the manufacturing process can be simplified.

[0047] Here, if the stabilization layer 19 is formed in the IGBT region 1, there is a concern that the latch-up resistance will decrease due to the increase in the N-type layer, since the stabilization layer 19 is N-type. However, according to the study by the present inventors, the results shown in FIG. 7 were obtained as a relationship between the collector-emitter voltage Vce and the collector current Ic, and the surface concentration of the stabilization layer 19. Note that FIG. 7 shows the relationship between the surface concentration of the emitter region 17 and 2.0×10 20 / cm 3 This is the result when

[0048] 7, it is confirmed that the latch-up current hardly changes when the surface concentration of the stabilization layer 19 is lower than the surface concentration of the emitter region 17. For this reason, it is preferable that the stabilization layer 19 has a lower impurity concentration than the emitter region 17 in order to suppress a decrease in the latch-up resistance.

[0049] Furthermore, when the stabilization layer 19 is formed in the IGBT region 1, the stabilization layer 19 may affect the threshold voltage Vth (i.e., the gate-emitter voltage Vge) of the IGBT element. According to the study by the present inventors, the results shown in FIG. 8 were obtained as the relationship between the gate-emitter voltage Vge and the collector current Ic and the peak position of the stabilization layer 19. Note that FIG. 8 shows the depth from the surface 10a of the semiconductor substrate 10 to the peak position where the impurity concentration of the stabilization layer 19 is maximum as the peak position of the stabilization layer 19. Also, FIG. 8 shows the depth from the surface 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b as 0.86 μm. The peak position of the stabilization layer 19 in FIG. 8 being 0 means that the stabilization layer 19 is not formed.

[0050] 8, it is confirmed that the threshold voltage Vth does not change substantially if the peak position where the impurity concentration of the stabilization layer 19 is maximum is 0.5 μm or less. That is, it is confirmed that the threshold voltage Vth does not change if the depth from the surface 10a of the semiconductor substrate 10 to the peak position where the impurity concentration of the stabilization layer 19 is maximum is 58% or less of the depth from the surface 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b. Therefore, it is preferable that the depth of the stabilization layer 19 to the peak position where the impurity concentration is maximum is 58% or less of the depth from the surface 10a of the semiconductor substrate 10 to the second peak position P2 of the second base layer 12b.

[0051] According to the present embodiment described above, the FWD region 2 is configured such that one surface 10a of the semiconductor substrate 10 connected to the upper electrode 22 includes an N-type stabilization layer 19. Therefore, the same effects as those of the first embodiment can be obtained.

[0052] (1) In this embodiment, a stabilization layer 19 is also formed in the IGBT region 1, and the stabilization layer 19 has a lower impurity concentration than the contact region 18. Therefore, the stabilization layer 19 can be formed by ion implantation of N-type impurities without placing a mask, and the manufacturing process can be simplified.

[0053] (2) In this embodiment, the surface concentration of the stabilization layer 19 is set lower than the surface concentration of the emitter region 17, so that a decrease in the latch-up resistance can be suppressed.

[0054] (3) In this embodiment, the stabilization layer 19 is formed so that the peak position of the stabilization layer 19 relative to the second peak position P2 of the second base layer 12b is 58% or less, thereby making it possible to suppress fluctuations in the threshold voltage Vth.

[0055] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0056] For example, in each of the above embodiments, the semiconductor device in which the first conductivity type is N type and the second conductivity type is P type has been described, but the semiconductor device in which the first conductivity type is P type and the second conductivity type is N type may also be used. Also, in each of the above embodiments, the trench gate structure does not have to be formed in the FWD region 2.

[0057] In addition, in each of the above embodiments, an example has been described in which the surface 10a of the semiconductor substrate 10 in the FWD region 2 is formed of the contact region 18 and the stabilization layer 19. However, the stabilization layer 19 may be formed in a part of the surface layer of the second base layer 12b, so that the second base layer 12b is exposed from the surface 10a of the semiconductor substrate 10. Even in such a semiconductor device, the proportion of the second base layer 12b, which is prone to variation in impurity concentration, on the surface 10a of the semiconductor substrate 10 can be reduced compared to a case in which the surface 10a of the semiconductor substrate 10 in the FWD region 2 is formed of the contact region 18 and the second base layer 12b. Therefore, the same effect as in the first embodiment can be obtained.

[0058] Similarly, in the above second embodiment, an example has been described in which one surface 10a of the semiconductor substrate 10 in the IGBT region 1 is formed by the emitter region 17, the contact region 18, and the stabilization layer 19. However, the stabilization layer 19 may be formed in a part of the surface layer portion of the second base layer 12b in the IGBT region 1, so that the second base layer 12b is exposed from the one surface 10a of the semiconductor substrate 10.

[0059] In the second embodiment, the surface concentration of the stabilization layer 19 may be higher than the surface concentration of the emitter region 17. The stabilization layer 19 may be formed at a depth at which the peak position of the stabilization layer 19 is greater than 58% of the second peak position P2 of the second base layer 12b. Even in this semiconductor device, the proportion of the second base layer 12b, which is likely to have a variable impurity concentration, on the one surface 10a of the semiconductor substrate 10 can be reduced compared to the case in which the one surface 10a of the semiconductor substrate 10 in the FWD region 2 is composed of the contact region 18 and the second base layer 12b. Therefore, the same effect as in the first embodiment can be obtained.

[0060] [Disclosure of the Invention] The present disclosure described above can be understood from the following viewpoints, for example. [First viewpoint] A semiconductor device in which an IGBT region (1) having an IGBT element and an FWD region (2) having an FWD element are formed on a common semiconductor substrate (10), the semiconductor substrate having the IGBT region and the FWD region, including a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, a collector layer (24) of the second conductivity type formed on a side of the drift layer opposite to the base layer side in the IGBT region, and a cathode layer (25) of the first conductivity type formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (10a) and a surface on the collector layer and cathode layer sides as the other surface (10b); a barrier region (16) of a first conductivity type formed in the base layer and dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on one surface side of the semiconductor substrate; a trench gate structure including a gate insulating film (14) formed on a wall surface of a trench (13) that penetrates the base layer and the barrier region of the IGBT region to reach the drift layer, and a gate electrode (15) formed on the gate insulating film; a first conductivity type emitter region (17) formed in a surface layer portion of the second base layer in the IGBT region and in contact with the trench; a second conductive type contact region (18) formed in a surface layer portion of the base layer in the FWD region and having a higher impurity concentration than the base layer; a first electrode (22) disposed on one surface side of the semiconductor substrate and electrically connected to the emitter region and the contact region; a second electrode (26) disposed on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer; the base layer is an ion-implanted layer; the second base layer has a peak position (P2) between the emitter region and the barrier region, at a depth different from a boundary with the emitter region and a boundary with the barrier region, where the impurity concentration is maximum; a first conductivity type stabilization layer (19) is formed in a surface layer portion of the second base layer in the FWD region together with the contact region; The first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

[0061] [Second viewpoint] The semiconductor device according to a first aspect, wherein the stabilization layer is formed in the FWD region over an entire region of a portion of one surface of the semiconductor substrate different from the contact region.

[0062] [Third Perspective] The semiconductor device according to the first or second aspect, wherein the stabilization layer is also formed on a surface layer portion of the second base layer in the IGBT region.

[0063] [Fourth viewpoint] the contact region is also formed in a surface layer portion of the second base layer in the IGBT region; The semiconductor device according to the first or second aspect, wherein the stabilization layer is formed in the FWD region over the entire region of a portion of one surface of the semiconductor substrate that is different from the contact region, and further formed in the IGBT region over the entire region of a portion of one surface of the semiconductor substrate that is different from the emitter region and the contact region, and has a lower impurity concentration than the contact region.

[0064] [Fifth viewpoint] The semiconductor device according to the third or fourth aspect, wherein a stabilization layer in the IGBT region has a depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the stabilization layer is at its maximum that is 58% or less of a depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the emitter region is at its maximum. [Explanation of symbols]

[0065] 1 IGBT area 2 FWD area 10. Semiconductor Substrate 10a one side 10b Other side 11 Drift layer 12 Base Layer 12a First base layer 12b Second base layer 13. Trench 14 Gate insulating film 15 Gate electrode 16 Barrier Region 17 Emitter Area 18 Contact Area 22 Upper electrode (1st electrode) 24 Collector layer 25 Cathode layer 26 Lower electrode (second electrode)

Claims

1. A semiconductor device in which an IGBT region (1) having an IGBT element and an FWD region (2) having an FWD element are formed on a common semiconductor substrate (10), the semiconductor substrate having the IGBT region and the FWD region, including a drift layer (11) of a first conductivity type, a base layer (12) of a second conductivity type formed on the drift layer, a collector layer (24) of a second conductivity type formed on a side of the drift layer opposite to the base layer side in the IGBT region, and a cathode layer (25) of a first conductivity type formed on a side of the drift layer opposite to the base layer side in the FWD region, the semiconductor substrate having a surface on the base layer side as one surface (10a) and a surface on the collector layer and cathode layer sides as the other surface (10b); a barrier region (16) of a first conductivity type formed in the base layer and dividing the base layer into a first base layer (12a) on the drift layer side and a second base layer (12b) on one surface side of the semiconductor substrate; a trench gate structure including a gate insulating film (14) formed on a wall surface of a trench (13) that penetrates the base layer and the barrier region of the IGBT region to reach the drift layer, and a gate electrode (15) formed on the gate insulating film; an emitter region (17) of a first conductivity type formed in a surface layer portion of the second base layer of the IGBT region and in contact with the trench; a second conductive type contact region (18) formed in a surface layer portion of the base layer in the FWD region and having a higher impurity concentration than the base layer; a first electrode (22) disposed on one surface side of the semiconductor substrate and electrically connected to the emitter region and the contact region; a second electrode (26) disposed on the other surface side of the semiconductor substrate and electrically connected to the collector layer and the cathode layer; the base layer is an ion-implanted layer; the second base layer has a peak position (P2) between the emitter region and the barrier region, at a depth different from a boundary with the emitter region and a boundary with the barrier region, at which the impurity concentration is maximum; a first conductivity type stabilization layer (19) is formed in a surface layer portion of the second base layer in the FWD region together with the contact region; The first electrode is electrically connected to the contact region and the stabilization layer in the FWD region.

2. 2 . The semiconductor device according to claim 1 , wherein the stabilization layer is formed in the FWD region over the entire area of ​​a portion of one surface of the semiconductor substrate that is different from the contact region.

3. 2. The semiconductor device according to claim 1, wherein the stabilization layer is also formed on a surface layer portion of the second base layer in the IGBT region.

4. the contact region is also formed in a surface layer portion of the second base layer in the IGBT region; 2. The semiconductor device according to claim 1, wherein the stabilization layer is formed in the FWD region over an entire region of a portion of one surface of the semiconductor substrate different from the contact region, and further formed in the IGBT region over an entire region of a portion of one surface of the semiconductor substrate different from the emitter region and the contact region, and has an impurity concentration lower than that of the contact region.

5. 5. The semiconductor device according to claim 3, wherein the stabilization layer in the IGBT region has a depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the stabilization layer is at its maximum that is 58% or less of the depth from one surface of the semiconductor substrate to a peak position where the impurity concentration in the emitter region is at its maximum.

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