Designing method, semiconductor device, and mask set

Abstract

To provide a method of designing a semiconductor device that can be favorably manufactured.SOLUTION: A designing method includes: arranging a plurality of bonding electrode patterns corresponding to bonding electrodes in kerf regions of first and second masks (S14p, S14m); identifying each unplaceable region in each of the kerf regions of the first and second masks; removing the bonding electrode patterns placed in the unplaceable region (S15p, S15m); using the first and second masks for generating first and second pattern groups formed in the kerf regions upon performing three or more times of exposures while changing a position; extracting sections where multiple positions of the bonding electrode patterns included in the first pattern group and in the second pattern group do not overlap when the first wafer and the second wafer are bonded (S16pm); and removing the bonding electrode patterns placed in a non-overlapping section in each of the kerf regions of the first mask and the second mask (S18p, S18m).SELECTED DRAWING: Figure 32

Description

[Technical field]

[0001] The present embodiment relates to a design method, a semiconductor device, and a mask set. [Background technology]

[0002] There is known a method for manufacturing a semiconductor device in which a first wafer corresponding to a first chip and a second wafer corresponding to a second chip are manufactured and these two wafers are bonded together. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0101911 [Patent Document 2] U.S. Pat. No. 1,322,466 [Patent Document 3] U.S. Patent No. 10998301 [Patent Document 4] JP 2022-112911 A Summary of the Invention [Problem to be solved by the invention]

[0004] A method for designing a semiconductor device that can be suitably manufactured, a semiconductor device, and a mask set are provided. [Means for solving the problem]

[0005] A design method according to one embodiment is a design method for a mask set used for exposure when patterning a plurality of bonding electrodes of a first wafer and a second wafer bonded together via the plurality of bonding electrodes. The mask set includes a first mask and a second mask. The first wafer and the second wafer each include a plurality of device regions and a kerf region surrounding the plurality of device regions. The plurality of bonding electrodes include a plurality of first bonding electrodes provided in the device regions and a plurality of second bonding electrodes provided in the kerf region and each electrically unconnected.

[0006] In this design method, the size and shape of the second bonding electrode are specified, a plurality of second bonding electrode patterns corresponding to the second bonding electrode are arranged in the kerf regions of the first mask and the second mask, and arrangement-prohibited regions in which the second bonding electrode cannot be arranged are specified in the kerf regions of the first mask and the second mask. In addition, the second bonding electrode pattern arranged in the arrangement-prohibited region of the first mask is deleted in the kerf region of the first mask. In addition, a first pattern group is generated that is formed in an exposure region adjacent to other exposure regions on both sides of the first direction and both sides of the second direction among nine or more exposure regions formed when exposure is performed three or more times while changing the position in the first direction and three or more times while changing the position in the second direction intersecting the first direction using the first mask. In addition, in the kerf region of the second mask, the second bonding electrode pattern arranged in the arrangement-prohibited region of the second mask is deleted. Furthermore, a second pattern group is generated in an exposure area adjacent to other exposure areas on both sides in the first direction and on both sides in the second direction among nine or more exposure areas formed when the second mask is used and exposure is performed three or more times while changing the position in the first direction and three or more times while changing the position in the second direction. Furthermore, when the first wafer and the second wafer are bonded to each other, a portion where a plurality of positions of the plurality of second bonding electrode patterns included in the first pattern group do not overlap with a plurality of positions of the plurality of second bonding electrode patterns included in the second pattern group is extracted as viewed from a direction intersecting the surfaces of the first wafer and the second wafer, and the second bonding electrode patterns arranged in the respective non-overlapping portions of the kerf region of the first mask and the kerf region of the second mask are deleted. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic exploded perspective view showing a configuration example of a memory die MD according to an embodiment. FIG. [Diagram 2] 2 is a schematic bottom view showing an example of the configuration of the chip CM. FIG. [Diagram 3] 2 is a schematic bottom view showing an example of the configuration of the chip CM. FIG. [Figure 4] 2 is a schematic plan view showing a configuration example of a chip CP. FIG. [Diagram 5] 2 is a schematic cross-sectional view showing a configuration of a portion of a memory die MD. [Figure 6] FIG. 6 is a schematic cross-sectional view showing an enlarged portion of FIG. 5. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an enlarged portion of FIG. 6. [Figure 8] 1A and 1B are schematic bottom views for explaining a manufacturing method of a memory die MD according to an embodiment. [Figure 9] 1A and 1B are schematic bottom views for explaining a manufacturing method of a memory die MD according to an embodiment. [Figure 10] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of a memory die MD according to an embodiment. [Figure 11] 1A to 1C are schematic cross-sectional views for explaining a manufacturing method of a memory die MD according to an embodiment. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 16] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] FIG. 2 is a schematic perspective view for explaining the same manufacturing method. [Figure 21] FIG. 2 is a schematic perspective view for explaining the same manufacturing method. [Figure 22] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 23] 1A to 1C are schematic plan views for explaining the manufacturing method. [Figure 24] 11 is a schematic cross-sectional view showing the structure of the wafers WM and WP in the case where the bonding electrodes Pk1x and Pk2x are not provided in the kerf region RK. FIG. [Diagram 25] 11 is a schematic cross-sectional view showing the structure of wafers WM and WP when bonding electrodes Pk1x and Pk2x are provided in a kerf region RK. FIG. [Figure 26] 10 is a schematic plan view illustrating a partial configuration including the kerf region of the wafers WM and WP after bonding. FIG. [Figure 27] 10 is a schematic cross-sectional view illustrating a partial configuration including the kerf region of the wafers WM and WP after bonding. FIG. [Figure 28] 10 is a schematic plan view illustrating a partial configuration including the kerf region of the wafers WM and WP after bonding. FIG. [Figure 29] 10 is a schematic cross-sectional view illustrating a partial configuration including the kerf region of the wafers WM and WP after bonding. FIG. [Diagram 30] 10 is a schematic plan view illustrating a partial configuration including the kerf region of the wafers WM and WP after bonding. FIG. [Diagram 31] 10 is a schematic cross-sectional view illustrating a partial configuration including the kerf region of the wafers WM and WP after bonding. FIG. [Diagram 32] 13 is a flowchart showing a procedure for designing mask data used in manufacturing the bonding electrodes Pk1x, Pk2x in the kerf region RK. [Diagram 33] 33 is a flowchart showing an example of a specific process procedure of steps S15p, S15m, and S16pm of FIG. 32. [Diagram 34] FIG. 13 is a plan view showing an example of a laminated electrode part PARX for the X-side of the kerf region. [Diagram 35] 13 is a plan view showing an example of a laminated electrode part PARY for the Y side of the kerf region. FIG. [Diagram 36] FIG. 11 is a plan view showing an example of a laminated electrode part PARCX for an intersection position of the kerf region. [Figure 37]13 is a plan view showing an example of frame data FRdat of a mask used in manufacturing laminated electrodes Pk1x, Pk2x in a kerf region RK. FIG. [Figure 38] 38 is a plan view showing a case where the bonded electrode parts PARX, PARY, and PARCX are laid out in the frame data FRdat shown in FIG. 37. [Figure 39] 13 is a plan view showing an example of frame data FRPdat of a mask used in manufacturing a bonding electrode Pk2x in a kerf region RK of a wafer WP. FIG. [Diagram 40] 10 is a plan view showing an example of frame data FRMdat of a mask used in manufacturing a bonding electrode Pk1x in a kerf region RK of a wafer WM. FIG. [Diagram 41] 13 is a plan view showing an example of frame data FRPidat (FRMidat) in which a lithography mark used in lamination is arranged. FIG. [Diagram 42] 42 is a plan view showing an example of an arrangement of lithography marks in a state in which the frame data FRPidat (FRMidat) in FIG. 41 is step-and-repeat. FIG. [Diagram 43] 43 is a plan view showing an example of frame data FRPidat in a state where a region such as a TEG is added to the frame data FRPidat in FIG. 42. [Diagram 44] 43 is a plan view showing an example of frame data FRMidat ​​in a state where a region such as TEG is added to the frame data FRMidat ​​in FIG. 42. [Diagram 45] 44 is a plan view showing an example of frame data FRPidat in a state where a frame data area is added to the frame data FRPidat in FIG. 43. [Figure 46] 45 is a plan view showing an example of frame data FRMidat ​​in a state where a frame data area is added to the frame data FRMidat ​​in FIG. 44. [Figure 47] FIG. 11 is a plan view showing placement impossible areas bP1 and bP2 due to a lithography mark in frame data FRPidat. [Figure 48] FIG. 11 is a plan view showing placement impossible areas bM1 and bM2 caused by lithography marks in frame data FRMidat. [Figure 49] 13 is a plan view for explaining a laminated electrode pattern PKX that is missing due to a lithographic mark, a TEG area, frame data, or a placement prohibited area RbPX (RbMX) that is an area where placement is not permitted. FIG. [Figure 50] FIG. 40 is a plan view showing frame data FRPdatSR in a state in which the frame data FRPdat in FIG. 39 has been step-and-repeat. [Figure 51] FIG. 41 is a plan view showing frame data FRMdatSR that reproduces the state in which the frame data FRMdat in FIG. 40 is step-and-repeat processed. [Figure 52] FIG. 40 is a plan view showing an example of reproduction data FRPdatSR2 obtained by reproducing the state in which the frame data FRPdat in FIG. 39 is step-and-repeat-processed. [Figure 53] FIG. 41 is a plan view showing an example of reproduced data FRMdatSR2 obtained by reproducing the state in which the frame data FRMdat in FIG. 40 is step-and-repeat-processed. [Figure 54] FIG. 11 is a plan view showing data FRPMdif indicating mismatched locations of the laminated electrode pattern PKX in the kerf region after step-and-repeat. [Figure 55] 40 is a plan view showing the frame data FRPdat obtained by deleting the pasted electrode pattern PKX at the mismatched portion RKno from the pasted electrode pattern PKX of the frame data FRPdat in FIG. 39. [Figure 56] 41 is a plan view showing the frame data FRMdat obtained by deleting the pasted electrode pattern PKX of the mismatched portion RKno from the pasted electrode pattern PKX of the frame data FRMdat in FIG. 40. [Figure 57] FIG. 57 is a plan view showing frame data FRPdatSR in a state in which the frame data FRPdat in FIG. 56 has been step-and-repeat. [Figure 58] FIG. 58 is a plan view showing frame data FRMdatSR that reproduces the state in which the frame data FRMdat in FIG. 57 is step-and-repeat. [Figure 59]FIG. 57 is a plan view showing an example of reproduction data FRPdatSR2 obtained by reproducing the state in which the frame data FRPdat in FIG. 56 is step-and-repeat-processed. [Figure 60] FIG. 57 is a plan view showing an example of reproduced data FRMdatSR2 obtained by reproducing the state in which the frame data FRMdat in FIG. 56 is step-and-repeat-processed. [Figure 61] 10 is a schematic plan view illustrating the configuration of a portion of a kerf region RK of a mask after the mask data is designed. FIG. [Figure 62] 10 is a schematic plan view illustrating the configuration of a portion of a kerf region RK of a mask after the mask data is designed. FIG. [Figure 63] FIG. 13 is a plan view conceptually showing frame data Covdat according to a modified example, and frame data FRdat in which litho marks ALM and TEG are arranged. [Figure 64] 13 is a plan view conceptually showing frame data Covdat according to a modified example, and frame data FRdat in which a pasted electrode pattern PKX of a kerf region is arranged. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Next, the semiconductor device according to the embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations thereof may be omitted.

[0009] In addition, when the term "semiconductor device" is used in this specification, it can refer to a die after dicing or a wafer before dicing, and in the former case, it can refer to a die after packaging or a die before packaging.

[0010] In addition, in this specification, a "wafer" may or may not include a substrate such as silicon (Si). Therefore, for example, even if two wafers including a substrate such as silicon (Si) are bonded together and the substrate is removed from one of the wafers, this configuration still includes two wafers.

[0011] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0012] In this specification, a predetermined direction parallel to the surface of the substrate is called the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the surface of the substrate is called the Z direction.

[0013] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] In addition, when expressions such as "upper" and "lower" are used in this specification, for example, of two chips or two wafers included in a memory die or wafer, the one provided with an external pad electrode connectable to a bonding wire may be referred to as the upper side, and the one not provided with such an external pad electrode may be referred to as the lower side. Furthermore, when referring to a configuration included in a memory die or wafer, for example, the direction away from the semiconductor substrate included in the lower wafer along the Z direction may be referred to as the upper side, and the direction approaching the semiconductor substrate included in the lower wafer along the Z direction may be referred to as the lower side. Furthermore, when referring to a certain configuration, the lower surface or lower end may mean the surface or end on the semiconductor substrate side included in the lower wafer of this configuration, and the upper surface or upper end may mean the surface or end on the opposite side to the semiconductor substrate included in the lower wafer of this configuration. Furthermore, a surface that intersects with the X direction or Y direction may be referred to as a side surface, etc.

[0015] In addition, in this specification, when referring to a configuration, member, etc., "width" or "length" in a specified direction, this may mean the width or length in a cross section observed by SEM (Scanning electron microscopy), TEM (Transmission electron microscopy), etc.

[0016] [Embodiment] [Memory Die MD Structure] 1 is a schematic exploded perspective view showing a configuration example of a memory die MD according to the present embodiment. As shown in FIG. 1, the memory die MD includes a chip C on the memory cell array side. M and the peripheral circuit chip C P And, it is equipped with.

[0017] Chip C M On the upper surface of the X Also, chip C M On the underside of I1 Also, chip C P On the upper surface of the I2The following is Chip C M Regarding the multiple laminated electrodes P I1 The surface on which the external pad electrodes P X The surface on which the chip C is provided is called the back surface. P Regarding the multiple laminated electrodes P I2 The surface on which the chip C is provided is called the front surface, and the surface opposite the front surface is called the back surface. P The surface of the chip C P The chip C is located above the back surface of the chip C. M The back side of the chip is C M The surface of the substrate is provided above the substrate.

[0018] Chip C M and Chip C P is Chip C M Surface and chip C P The surface of the laminated electrodes P I1 is a plurality of laminated electrodes P I2 , and a plurality of bonding electrodes P I2 The electrode is placed in a position where it can be attached to the I1 and the laminated electrode P I2 What is Chip C? M and Chip C P The laminate functions as a laminate electrode for bonding the two and electrically connecting them.

[0019] In the example of FIG. 1, chip C M The corners a1, a2, a3, and a4 of the chip C P These correspond to corners b1, b2, b3, and b4.

[0020] 2 and 3 show chip C M FIG. 3 is a schematic bottom view showing a configuration example of the laminated electrode P I1 Some of the configuration such as the above is omitted. PFIG. 5 is a schematic plan view showing a configuration example of the memory die MD. FIG. 6 is a schematic cross-sectional view showing an enlarged view of a portion of FIG. 5. FIG. 7 is a schematic cross-sectional view showing an enlarged view of a portion of FIG. 6. Although FIG. 7 shows a YZ cross section, a structure similar to that of FIG. 7 is observed when a cross section other than the YZ cross section along the central axis of the semiconductor layer 120 (for example, an XZ cross section) is observed.

[0021] [Chip C M Structure of Chip C M For example, as shown in FIG. 2, four memory plane regions R MP Also, chip C M is a four-memory plane region R MP A peripheral region R P The surrounding area R P is a set of multiple input / output regions R arranged in the X direction. IO Also, chip C M These four memory plane regions R MP and multiple input / output regions R IO The guard ring area R surrounding GD is provided.

[0022] Chip C M For example, as shown in FIG. 5, the base structure L SB and base structure L SB A memory cell array layer L MCA1 ,L MCA2 and the memory cell array layer L MCA1 ,L MCA2 The memory cell array layer L includes an electrode layer CH provided below the memory cell array layer L, and a plurality of wiring layers M0, M1, and MB provided below the electrode layer CH. MCA1 ,L MCA2 are a plurality of word line layers L arranged in the Z direction. WL A plurality of word line layers L arranged in the Z direction WL An interlayer insulating layer 111 such as silicon oxide (SiO2) is provided between them.

[0023] [Chip C M Base structure L SB Structure of For example, as shown in FIG. 5, SB The memory cell array layer L MCA1 The semiconductor device comprises a conductive layer 100 provided on the upper surface of the substrate, an insulating layer 101 provided on the upper surface of the conductive layer 100, a back surface wiring layer MA provided on the upper surface of the insulating layer 101, and an insulating layer 102 provided on the upper surface of the back surface wiring layer MA.

[0024] The conductive layer 100 may include, for example, a semiconductor layer such as silicon (Si) doped with an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B), may include a metal such as tungsten (W), or may include a silicide such as tungsten silicide (WSi).

[0025] The conductive layer 100 functions as a part of the source line of the NAND flash memory. The conductive layer 100 is arranged in four memory plane regions R aligned in the X and Y directions. MP There are four memory plane areas R MP At the ends in the X and Y directions, a region VZ not including the conductive layer 100 is provided.

[0026] The insulating layer 101 includes, for example, silicon oxide (SiO2).

[0027] The back wiring layer MA includes a plurality of wirings ma. These wirings ma may include, for example, aluminum (Al).

[0028] Some of the wirings ma function as part of the source lines of the NAND flash memory. The wirings ma are arranged in the four memory plane regions R aligned in the X and Y directions. MP 2. The wirings ma are electrically connected to the conductive layer 100.

[0029] In addition, some of the wirings ma are connected to the external pad electrodes P XThis wiring ma functions as a multiple input / output area R IO A plurality of wirings ma are provided corresponding to the conductive layer 100 in the region VZ not including the conductive layer 100. MCA1 ,L MCA2 The wiring ma is connected to a via contact electrode CC in the insulating layer 102. A part of the wiring ma is exposed to the outside of the memory die MD through an opening TV provided in the insulating layer 102.

[0030] The insulating layer 102 is, for example, a passivation layer containing a resin material such as polyimide in its upper layer portion.

[0031] [Chip C M The memory cell array layer L MCA1 ,L MCA2 Memory plane region R MP Structure in For example, as shown in FIG. MCA1 ,L MCA2 5, a plurality of memory blocks BLK arranged in the Y direction are provided. As shown in FIG 5, an inter-block structure ST is provided between two memory blocks BLK adjacent to each other in the Y direction.

[0032] The memory block BLK is, for example, as shown in FIG. WL The semiconductor device includes a plurality of conductive layers 110 aligned in the Z direction corresponding to the plurality of conductive layers 110, a plurality of semiconductor layers 120 extending in the Z direction, and a plurality of gate insulating films 130 respectively provided between the plurality of conductive layers 110 and the plurality of semiconductor layers 120.

[0033] The conductive layer 110 has a generally plate-like shape extending in the X-direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B).

[0034] Among the multiple conductive layers 110, one or more conductive layers 110 located in the uppermost layer function as a select gate line of the NAND flash memory and gate electrodes of multiple select transistors connected thereto. These multiple conductive layers 110 are electrically independent for each memory block BLK.

[0035] Further, the multiple conductive layers 110 located below the above function as word lines of the NAND flash memory and gate electrodes of multiple memory cells (memory transistors) connected thereto. Each of the multiple conductive layers 110 is electrically independent for each memory block BLK.

[0036] Moreover, one or more conductive layers 110 located below them function as select gate lines of the NAND flash memory and gate electrodes of multiple select transistors connected thereto. These multiple conductive layers 110 have a smaller width in the Y direction than the other conductive layers 110. Furthermore, an insulating layer SHE such as silicon oxide (SiO2) is provided between two conductive layers 110 adjacent to each other in the Y direction.

[0037] The semiconductor layer 120 is arranged in a predetermined pattern in the X direction and the Y direction. The semiconductor layer 120 functions as a memory cell of the NAND flash memory and a channel region of a selection transistor. The semiconductor layer 120 includes, for example, polycrystalline silicon (Si) or the like. The semiconductor layer 120 has a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide is provided in the center portion.

[0038] The semiconductor layer 120 is a memory cell array layer L MCA1 Semiconductor region 120 included in L and the memory cell array layer L MCA2 Semiconductor region 120 included in U The semiconductor layer 120 includes a semiconductor region 120. L and the semiconductor region 120 U A semiconductor region 120 connected to the top end of J and semiconductor region 120 L an impurity region 122 connected to the upper end of the semiconductor region 120;U and an impurity region 121 connected to the lower end of the

[0039] Semiconductor region 120 L The semiconductor region 120 has a substantially cylindrical shape extending in the Z direction. L The outer peripheral surfaces of the memory cell array layer L MCA1 The semiconductor region 120 is surrounded by a plurality of conductive layers 110 included in the semiconductor region 120 and faces the plurality of conductive layers 110. L The radial width W of the upper end of 120LL The semiconductor region 120 L The radial width W of the lower end of 120LU Less than.

[0040] Semiconductor region 120 U The semiconductor region 120 has a substantially cylindrical shape extending in the Z direction. U The outer peripheral surfaces of the memory cell array layer L MCA2 The semiconductor region 120 is surrounded by a plurality of conductive layers 110 included in the semiconductor region 120 and faces the plurality of conductive layers 110. U The radial width W of the upper end of 120UL The semiconductor region 120 U The radial width W of the lower end of 120UU and the above width W 120LU Less than.

[0041] Semiconductor region 120 J are the memory cell array layers L MCA1 1, the memory cell array layer L is provided below the plurality of conductive layers 110 included in the MCA2 The semiconductor region 120 is disposed above the conductive layers 110 included in the semiconductor region 120. J The radial width W 120J is the above width W 120LU ,W 120UU Greater than.

[0042] The impurity region 122 is connected to the conductive layer 100. In the example of FIG. LThe boundary between the impurity region 122 and the doped region 124 is indicated by a dashed line. The impurity region 122 contains, for example, an N-type impurity such as phosphorus (P) or a P-type impurity such as boron (B).

[0043] The impurity region 121 contains an N-type impurity such as phosphorus (P). In the example of FIG. U The dashed line indicates the boundary between the impurity region 121 and the bit line BL. The impurity region 121 is connected to the bit line BL through a via contact electrode ch and a via contact electrode Vy (FIG. 5).

[0044] The gate insulating film 130 has a substantially cylindrical shape covering the outer peripheral surface of the semiconductor layer 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 stacked between the semiconductor layer 120 and the conductive layer 110, as shown in FIG. 7, for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor layer 120 except for the contact portion between the semiconductor layer 120 and the conductive layer 100. In addition, as shown in FIG. 6, an insulating layer 126 such as silicon oxide (SiO2) is provided between the gate insulating film 130 and the conductive layer 100.

[0045] 7 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may include a floating gate such as polycrystalline silicon containing N-type or P-type impurities.

[0046] 6, the inter-block structure ST includes a conductive layer 141 extending in the Z direction and the X direction, and an insulating layer 142 provided on a side surface of the conductive layer 141. The conductive layer 141 is connected to the conductive layer 100. The conductive layer 141 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 141 functions, for example, as a part of a source line of a NAND flash memory.

[0047] [Chip C M The memory cell array layer L MCA1 ,L MCA2 The surrounding area R P Structure in Surrounding area R P For example, as shown in FIG. X A plurality of via contact electrodes CC are provided corresponding to the external pad electrodes P X It is connected to the wiring MA which functions as

[0048] [Chip C M [Structure of the electrode layer CH] The electrode layer CH includes a plurality of via contact electrodes ch. The plurality of via contact electrodes ch are, for example, MCA1 ,L MCA2 Configuration and Chip C P The via contact electrodes ch are electrically connected to at least one of the structures in the semiconductor layer 120. The via contact electrodes ch may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes ch are provided corresponding to the semiconductor layers 120 and are connected to the lower ends of the semiconductor layers 120.

[0049] [Chip C M [Structure of wiring layers M0, M1, MB] For example, as shown in FIG. 5, a plurality of wirings included in the wiring layers M0, M1, and MB are, for example, a memory cell array layer L MCA1 ,L MCA2 Configuration and Chip C PThe semiconductor device is electrically connected to at least one of the components.

[0050] The wiring layer M0 includes a plurality of wirings m0. The plurality of wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). Some of the plurality of wirings m0 function as bit lines BL. The bit lines BL are, for example, aligned in the X direction and extend in the Y direction.

[0051] The wiring layer M1 includes a plurality of wirings m1, as shown in Fig. 5. The plurality of wirings m1 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0052] The wiring layer MB is made up of a plurality of bonding electrodes P I1 These multiple laminated electrodes P I1 For example, a barrier conductive film p such as titanium nitride (TiN) I1B and copper (Cu) and other metal films I1M The insulating film may include a laminated film.

[0053] [Chip C P Structure of Chip C P For example, as shown in FIG. 4, the memory plane area R MP Four peripheral circuit regions R arranged in the X and Y directions corresponding to PC Also, chip C P is the surrounding area R P A circuit area R C Circuit area R C is a set of multiple input / output regions R arranged in the X direction. IO Also, chip C P These four peripheral circuit regions R PC and input / output region R IO The guard ring region R surrounding GD is provided.

[0054] Also, Chip C PFor example, as shown in FIG. 5, the semiconductor substrate 200 includes an electrode layer GC provided above the semiconductor substrate 200, and wiring layers D0, D1, D2, D3, D4, and DB provided above the electrode layer GC.

[0055] [Chip C P Structure of the semiconductor substrate 200 The semiconductor substrate 200 includes P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the semiconductor substrate 200, an N-type well region 200N containing N-type impurities such as phosphorus (P), a P-type well region 200P containing P-type impurities such as boron (B), a semiconductor substrate region 200S in which the N-type well region 200N and the P-type well region 200P are not provided, and an insulating region 200I are provided. The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S each function as a part of a plurality of transistors Tr and a plurality of capacitors that configure a peripheral circuit.

[0056] [Chip C P [Structure of electrode layer GC] 5, an electrode layer GC is provided on the upper surface of the semiconductor substrate 200 via an insulating layer 200G. The electrode layer GC includes a plurality of electrodes gc facing the surface of the semiconductor substrate 200 in the Z direction. In addition, each region of the semiconductor substrate 200 and the plurality of electrodes gc included in the electrode layer GC are connected to a via contact electrode CS.

[0057] The N-type well region 200N, the P-type well region 200P, and the semiconductor substrate region 200S of the semiconductor substrate 200 function as channel regions of a plurality of transistors Tr constituting the peripheral circuit, one electrode of a plurality of capacitors, and the like, respectively.

[0058] The electrodes gc included in the electrode layer GC function as gate electrodes of the transistors Tr constituting the peripheral circuit, the other electrodes of the capacitors, and the like.

[0059] The via contact electrode CS extends in the Z direction, and its lower end is connected to the upper surface of the semiconductor substrate 200 or the electrode gc. An impurity region containing N-type impurities or P-type impurities is provided at the connection portion between the via contact electrode CS and the semiconductor substrate 200. The via contact electrode CS may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0060] [Chip C P [Structure of wiring layers D0, D1, D2, D3, D4, DB] For example, as shown in FIG. 5, a plurality of wirings included in D0, D1, D2, D3, D4, and DB are, for example, a memory cell array layer L MCA1 ,L MCA2 Configuration and Chip C P The semiconductor device is electrically connected to at least one of the components.

[0061] The wiring layers D0, D1, and D2 each include a plurality of wirings d0, d1, and d2. The plurality of wirings d0, d1, and d2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

[0062] The wiring layers D3 and D4 include a plurality of wirings d3 and d4, respectively. The plurality of wirings d3 and d4 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0063] The wiring layer DB is made up of a plurality of bonding electrodes P I2 These multiple laminated electrodes P I1 For example, a barrier conductive film p such as titanium nitride (TiN) I2B and copper (Cu) and other metal films I2M The insulating film may include a laminated film.

[0064] Here, the bonded electrode P I1 and the laminated electrode P I2 In addition, metal films such as copper (Cu) I1M ,p I2M When using the metal film p I1Mand metal film p I2M However, the alignment error of the laminated electrode P due to the alignment error is small. I1 and the laminated electrode P I2 Distortion of the shape of the laminated conductive film p I1B ,p I2B The bonded structure can be confirmed by the positional misalignment (the occurrence of discontinuous parts on the side). I1 and laminated electrode P I2 When the laminated electrode P is formed by the damascene method, each side surface has a tapered shape. I1 and the laminated electrode P I2 The cross-sectional shape along the Z direction at the portion where the laminated electrodes P are laminated together is not a straight line, but a non-rectangular shape. I1 and the laminated electrode P I2 When these are bonded together, the bottom, sides, and top of each Cu that forms them are covered with barrier metal. In contrast, in a typical wiring layer that uses Cu, an insulating layer (SiN or SiCN, etc.) that has the function of preventing oxidation of Cu is provided on the top surface of the Cu, and no barrier metal is provided. For this reason, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0065] [Manufacturing method] Next, a method for manufacturing a memory die MD will be described with reference to FIG. 8 to FIG. 23. FIG. 8 to FIG. 11 are schematic bottom views for explaining the method for manufacturing a memory die MD according to the embodiment. FIG. 12 to FIG. 14 are schematic cross-sectional views for explaining the same manufacturing method. FIG. 15 and FIG. 16 are schematic plan views for explaining the same manufacturing method. FIG. 17 to FIG. 19 are schematic cross-sectional views for explaining the same manufacturing method. FIG. 20 and FIG. 21 are schematic perspective views for explaining the same manufacturing method. FIG. 22 and FIG. 23 are schematic plan views for explaining the same manufacturing method. Note that FIG. 12 to FIG. 14 show a cross section corresponding to FIG. 6. Also, FIG. 17 to FIG. 19 show a cross section corresponding to FIG. 5. In the drawings referred to below, hatching is appropriately added to the plan view to make the drawing easier to see. Hatching added to the plan view does not necessarily relate to the material or characteristics of the component to which the hatching is added.

[0066] In manufacturing the memory die MD according to this embodiment, the chip C M Wafer W corresponding to M , and Chip C P Wafer W corresponding to P (See FIG. 20) and these two wafers W M ,W P After forming the back wiring layer MA (FIG. 5) and the like, the substrate is diced into individual pieces (FIG. 23).

[0067] [Wafer W M Manufacturing method FIG. 8 shows a wafer W M 9 shows a surface of the semiconductor substrate 150 corresponding to the device region R1 in the X-direction and the Y-direction. As shown in FIG. 8, the surface of the semiconductor substrate 150 has a plurality of device regions R1 aligned in the X-direction and the Y-direction. MD and structure region R ST and these multiple device regions R MD and structure region R ST The kerf area R between K and the structure region R STKerf region R on one side of the X or Y direction K ´ and the margin area R M An insulating layer 112 such as silicon oxide (SiO2) is provided between the semiconductor substrate 150 and the conductive layer 100 (see FIG. 14).

[0068] Device Region R MD is a substantially rectangular area that will become part of the memory die MD after dicing, and the chip C M The device region R MD is a region of other device regions R on both sides in the X direction and on both sides in the Y direction. MD or structure region R ST and next to each other.

[0069] Structure area R ST Wafer W M In the manufacture of the device region R MD The device region R MD It includes a configuration similar to that of the structure region R ST is not normally used as part of the memory die MD after dicing. ST is a device region R on one side in the X direction and one side in the Y direction. MD or other structure region R ST Some structural regions R ST is the device region R MD Similarly, the device region R MD These structural regions R ST is the kerf area R K In the X direction, the Y direction, or the diagonal direction on the XY plane, the margin area R M These structure regions R ST Margin area R M The distance to the device area R MD The width in the X direction and the width in the Y direction of the other structure region R ST The outer periphery of the wafer W M along the periphery of the device region R MDIt has a smaller area than

[0070] Kerf Area R K is the area including the dicing line. Kerf area R K The structure in the kerf region R is not used for inputting or outputting voltages to or from the memory cell array, or inputting or outputting data signals or other signals to or from the memory cell array. K The test patterns and wafer W used in the manufacture of memory dies MD to evaluate and analyze defects that occur during manufacturing are included in the M The alignment marks are used as reference marks when positioning the components in the XY plane. K The wiring layer MB in the middle is made up of two wafers W M ,W P A plurality of bonding electrodes P used when bonding k1x (second bonding electrode) is provided. k1x are electrically disconnected (floating state). k1x Wafer W M ,W P After bonding, all of the electrodes P k2x It is located in a position overlapping with (Figure 16).

[0071] Kerf Area R K ´ is basically the kerf area R K The kerf area R K ´ wiring layer MB k1x The number of is the kerf area R K The bonding electrode P arranged on the wiring layer MB k1x The number of kerf regions R K The bonding electrode P per unit area in the wiring layer MB of k1x The area of ​​the kerf area R K The number of electrodes P per unit area on the wiring layer MB k1x The area of ​​the kerf area R is smaller than that of the K ´ denotes a plurality of structure regions R arranged in the X and Y directions.ST Located on the entire circumference. Kerf area R K ´ is the structure region R ST and margin area R M It is provided between.

[0072] Margin area R M are areas that will not be exposed in the process described below with reference to FIGS.

[0073] Next, the wafer W M ,W P The bonding electrode P is used when bonding I1 ,P k1x For example, as shown in FIGS. 10 and 11, the patterning of the wafer W M is exposed multiple times while changing the position in the X direction and multiple times while changing the position in the Y direction using a mask used for exposure, and multiple exposure regions R EX Then, the exposure region R EX In the device region R MD and structure region R ST There are multiple electrodes P I1 Multiple electrode patterns corresponding to the kerf area R are transferred. K ,R K ´ has multiple laminated electrodes P k1x A plurality of bonding electrode patterns corresponding to the wafer W are transferred onto the wafer W. M ,W P This is a process in which a circuit or the like is printed by irradiating light such as ultraviolet light through a mask onto the wafer. This exposure may be a stepper (step and repeat) type exposure in which the entire mask pattern is exposed onto the wafer at once, or a scan (step and scan) type exposure in which the mask pattern is scanned and gradually exposed onto the wafer. Also, for example, as shown in FIG. 8, in this embodiment, each exposure area R EX The four device regions R are arranged in the X and Y directions. MD An example including the above will be described.

[0074] Laminated electrode P I1 ,P k1xFor example, as shown in FIGS. 12 to 14, the insulating film 11 is formed by a damascene process.

[0075] For example, as shown in Fig. 12, an insulating layer gMB such as silicon oxide (SiO2) is formed on the surface of the wiring layer M1. This step is performed by a method such as CVD (Chemical Vapor Deposition).

[0076] Next, as shown in FIG. I1 An aperture PA is placed at the position corresponding to FIG. I1 This step is performed by, for example, a method such as RIE (Reactive Ion Etching). I1 The insulating layer gMB at the position corresponding to is removed.

[0077] Next, for example, as shown in FIG. I1 This step is performed by forming a conductive layer by sputtering or the like, and then removing a portion of the conductive layer by a method such as CMP (Chemical Mechanical Polishing).

[0078] Although not shown in the figure, the laminated electrode P described in Figs. I1 In parallel with the formation of the kerf region R K The adhesive electrode P k1x is formed.

[0079] [Wafer W P Manufacturing method FIG. 15 shows a wafer W P 16 shows a surface of a semiconductor substrate 250 corresponding to the semiconductor substrate 150. FIG. 16 shows an enlarged view of a portion of FIG. 15. As shown in FIG. 15, the surface of the semiconductor substrate 250 also has a plurality of device regions R aligned in the X direction and the Y direction, similar to the surface of the semiconductor substrate 150. MD and structure region R ST and these multiple device regions R MD and structure region R ST The kerf area R between Kand the structure region R ST The kerf region R is provided in the vicinity of K ´ and the margin area R M And, it is provided.

[0080] Wafer W P Device region R MD Basically, the wafer W M Device region R MD However, the wafer W P Device region R MD is Chip C M Instead of the configuration corresponding to chip C P It includes a configuration corresponding to.

[0081] Wafer W P Structure region R ST Basically, the wafer W M Structure region R ST However, the wafer W P Structure region R ST Wafer W M Device region R MD Instead, wafer W P Device region R MD It includes a configuration substantially similar to that of the above.

[0082] Wafer W P Kerf area R K Wafer W M Kerf area R K The wafer W is constructed in a substantially similar manner. P Kerf area R K For example, as shown in FIG. 16, two wafers W M ,W P The bonding electrode P is used when bonding k2x (fourth bonded electrode) is provided. k2x are electrically disconnected (floating state). k2x Wafer W M ,W P After bonding, all of the electrodes Pk1x It is located in a position overlapping with (Figure 9).

[0083] Wafer W P Kerf area R K ´ is the wafer W M Kerf area R K The wafer W is constructed in a similar manner to that shown in FIG. P Kerf area R K A plurality of bonding electrodes P are provided on k2x At least a part of the wafer W M ,W P After bonding, which of the bonded electrodes P k1x They are placed in a position where they do not overlap with each other.

[0084] Wafer W P Middle margin area R M Wafer W M Middle margin area R M It is configured almost the same way.

[0085] Next, the wafer W M ,W P The bonding electrode P is used when bonding I2 ,P k2x For example, similar to the process described with reference to FIGS. P is exposed multiple times while changing the position in the X direction and multiple times while changing the position in the Y direction using a mask used for exposure, and multiple exposure regions R EX Then, the exposure region R EX In the device region R MD and structure region R ST There are multiple electrodes P I2 Multiple electrode patterns corresponding to the kerf area R are transferred. K ,R K ´ has multiple laminated electrodes P k2x In this embodiment, the corresponding electrode patterns are transferred to the exposure regions R EX The four device regions R are arranged in the X and Y directions. MDAn example including the above will be described.

[0086] Laminated electrode P I2 ,P k2x For example, as shown in FIGS. 17 to 19, the insulating film 11 is formed by a damascene process.

[0087] For example, an insulating layer gDB such as silicon oxide (SiO2) is formed on the surface of the wiring layer D4 as shown in Fig. 17. This step is performed by a method such as CVD.

[0088] Next, as shown in FIG. I2 An aperture PA is placed at the position corresponding to FIG. I2 This step is performed by, for example, a method such as RIE. In this step, for example, the laminated electrode P I2 The insulating layer gDB is removed at a position corresponding to the position.

[0089] Next, as shown in FIG. I2 This step is performed by forming a conductive layer by sputtering or the like, and then removing a portion of the conductive layer by a method such as CMP.

[0090] Although not shown in the figure, the laminated electrode P described in Figs. I2 In parallel with the formation of the kerf region R K The adhesive electrode P k2x is formed.

[0091] [Wafer W M ,W P Process after lamination] Wafer W M ,W P After the manufacturing of the wafer W, as shown in FIG. M The surface of the wafer W P For example, as shown in FIG. 21, the surface of the wafer W M ,W P Next, the wafer W MAfter removing the semiconductor substrate 150 and the insulating layer 112, a back wiring layer MA and the like are formed to obtain the base structure L described with reference to FIG. SB Form.

[0092] Next, as shown in Figs. 22 and 23, the kerf region R K The bonded wafer W is diced along the dicing line DL provided in the M ,W P 10 to form a plurality of memory dies MD.

[0093] [Wafer W M ,W P Kerf area R K The bonded electrode P k1x ,P k2x ] Figure 24 shows the kerf area R K Electrode P k1x ,P k2x When the wafer W is not provided with M ,W P FIG. 25 is a schematic cross-sectional view showing the structure of the kerf region R K Electrode P k1x ,P k2x When the wafer W is provided M ,W P FIG. 2 is a schematic cross-sectional view showing the structure of the

[0094] As mentioned above, the wafer W M ,W P are made separately, and the bonding surface S B For example, in the example shown in Figure 24, the device area R MD Electrode P I1 ,P I2 The kerf area R K The electrode P k1x ,P k2x In such a configuration, the bonding surface S B In the device region R MD and kerf area R K If a step occurs, the wafer W may be stuck to the surface of the substrate during the bonding process. M and wafer WP This generates a void Voi between the two, increasing the possibility of poor bonding.

[0095] Therefore, in this embodiment, as shown in FIG. MD and kerf area R K Electrode P attached to both sides I1 ,P I2 ,P k1x ,P k2x By providing M ,W P Lamination surface S B This flattens the surface and suppresses the generation of voids Voi during the lamination process.

[0096] [Wafer after bonding W M ,W P Configuration Next, referring to FIGS. 26 to 31, the wafer W after bonding is M ,W P 26, 28, and 30 show the structure of the wafer W after bonding. M ,W P 27, 29, and 31 are schematic plan views illustrating a partial configuration including the kerf region of the wafer W after bonding. M ,W P Fig. 27 is a schematic cross-sectional view illustrating a portion of the configuration including the kerf region of Fig. 26. Fig. 27 is a diagram of the configuration shown in Fig. 26 cut along dotted line AA'. Fig. 29 is a diagram of the configuration shown in Fig. 28 cut along dotted line BB'. Fig. 30 is a diagram of the configuration shown in Fig. 29 cut along dotted line CC'.

[0097] As mentioned above, the kerf area R K The bonding electrodes P are provided on the wiring layers MB and DB. k1x ,P k2x 26 and 27, the kerf region R K Wiring m1 formed in wiring layers M1, D2, D1, D0, etc. k ,d2 k ,d1 k ,d0k is the device region (device region R MD The wiring layers M1, D2, D1, D0, etc. are formed at the same time as the wirings m1, d2, d1, d0 formed in the wiring layers M1, D2, D1, D0, etc. k ,d2 k ,d1 k ,d0 k is electrically unconnected (floating state).

[0098] For example, as shown in FIG. M Kerf area R K The memory cell array layer L MCA1 ,L MCA2 An insulating layer such as silicon oxide (SiO2) is provided on a part of the word line layer L WL For example, as shown in Figs. 26 and 27, the kerf region R K In the wiring layer M1, the wiring m1 k and wiring d2 of wiring layers D2, D1, and D0 k ,d1 k ,d0 k In the example shown in FIG. 27, the kerf region R K In the wiring m1 k is every other wire in the Y direction, and wiring d2 k ,d1 k ,d0 k are provided at positions where every third one overlaps in the Y direction. K Wafer inside W M ,W P Since peeling can be suppressed, the progression of the peeling to the device region can be suppressed.

[0099] Also, for example, as shown in FIG. M Kerf area R K The memory cell array layer L MCA1 ,L MCA2 In another part of the word line layer L WLA plurality of conductive layers 110k are provided in the Z direction in correspondence with the word line layers L WL An interlayer insulating layer 111k such as silicon oxide (SiO2) is provided between the conductive layer 110k. The conductive layer 110k may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). For example, as shown in FIG. 28 and FIG. 29, the kerf region R K In the wiring layer M1, the wiring m1 k and wiring d2 of wiring layers D2, D1, and D0 k ,d1 k ,d0 k In this configuration, the wafer W is diced. M ,W P This can prevent peeling from progressing to the device region.

[0100] Here, as shown in Fig. 29, the region where the multiple conductive layers 110k and the multiple interlayer insulating layers 111k are formed is harder and may be difficult to dice appropriately, compared to the region where the multiple conductive layers 110k and the multiple interlayer insulating layers 111k are not formed, as shown in Fig. 27. For this reason, in this embodiment, the coverage of the wiring layers M1, D2, D1, and D0 in the region described with reference to Fig. 29 is set smaller than the coverage of the wiring layers M1, D2, D1, and D0 in the region described with reference to Fig. 27. As a result, the region described with reference to Fig. 29 can be diced appropriately, similar to the region described with reference to Fig. 27.

[0101] As shown in FIG. M Kerf area R K An insulating layer such as silicon oxide (SiO2) is formed on the wafer W. P Kerf area R K Mark M on wiring layer D0 k In such a region, a kerf region R K The wiring layer D0 of k However, the wafer W PKerf area R K The wiring layer D0 is located above the wiring layer D0 in the Z direction, that is, the wiring layers M1, D2, and D1 have wiring m1. k ,d2 k ,d1 k ,d0 k In addition, the wiring layers MB and DB are provided with a bonding electrode P I1 ,P I2 The wafer W P Kerf area R K The mark M formed on the wiring layer D0 of k is used when forming a layer between the wiring layer D1 and the wiring layer D0, but is not used when forming layers above the wiring layer D1. k Above the wire m1 k For example, as shown in FIG. 30 and FIG. 31, the memory die MD can be preferably manufactured by providing the kerf region R K In the wiring layer M1, the wiring m1 k and wiring d2 of wiring layers D2 and D1 k ,d1 k are arranged so as to overlap at a constant interval when viewed from the Z direction.

[0102] [Kerf area R K Adhesive electrode P k1x ,P k2x How to design As described with reference to FIGS. 24 and 25, in this embodiment, the device region R MD and kerf area R K Electrode P attached to both sides I1 ,P I2 ,P k1x ,P k2x Here, the wafer W M ,W P In order to bond the wafer W M ,W P Lamination surface S B (Surface) Attached electrode P I1 ,P I2 ,P k1x ,P k2x Coverage rate (pasting surface S B P per unit area of ​​laminated electrodes I1 ,P I2,P k1x ,P k2x However, as will be described later in detail, due to various reasons, M ,W P Kerf area R K Inside, each of the laminated electrodes P k1x ,P k2x In addition, there are areas where the bonding electrode P k1x and the laminated electrode P k2x It is desirable that the electrodes P and P are provided at positions where they overlap when viewed from the Z direction. k1x and laminated electrode P k2x When one of the electrodes is disposed at a position where it does not overlap with the other, k1x ,P k2x This is because there is a risk that metal atoms such as copper (Cu) in the electrode may diffuse. k1x ,P k2x Wafer W M ,W P While avoiding each of the areas where placement is not possible, k1x and the laminated electrode P k2x The kerf area R is set so that it overlaps when viewed from the Z direction. K It is desirable to place as many of them as possible in the

[0103] Hereinafter, the kerf region R according to this embodiment will be described with reference to FIGS. K Adhesive electrode P k1x ,P k2x A method for designing a mask used in the manufacture of the kerf region R K Adhesive electrode P k1x ,P k2x Fig. 33 is a flowchart showing a procedure for designing mask data used in the manufacture of a semiconductor device. Fig. 33 is a flowchart showing an example of a specific procedure for steps S15p, S15m, and S16pm in Fig. 32. These procedures may be performed by a computer including a memory and a processor (microprocessor), for example, by the processor executing a control program stored in the memory, or may be performed by an operator giving instructions to the computer.

[0104] 34 to 36 are plan views showing an example of a laminated electrode part for a kerf region. X FIG. 35 is a plan view showing an example of a laminated electrode part PAR for the Y side of the kerf region. Y FIG. 36 is a plan view showing an example of a laminated electrode part PAR for an intersection position of the kerf region. CX FIG.

[0105] For example, as shown in FIG. 32, first, in steps S11p to S13p, a wafer W P The laminated electrode part PAR for the X side of the kerf area in the mask data used for manufacturing X (Fig. 34), Y-side adhesive electrode part PAR Y (Fig. 35), PAR electrode part for crossing position CX As shown in Fig. 34 to Fig. 36, the laminated electrode part PAR X ,PAR Y ,PAR CX are a plurality of laminated electrodes P k2x (Second bonding electrode) corresponding to a plurality of bonding electrode patterns P KX In steps S11p to S13p, the size, shape, and each of the plurality of adhesive electrode patterns PAR are determined. X ,PAR Y ,PAR CX The order of steps S11p to S13p is an example and can be changed as appropriate. X ,PAR Y ,PAR CX The electrode pattern P KX The size, shape and pitch of the conductor may be specified.

[0106] In steps S11m to S13m, the wafer W MThe laminated electrode part PAR for the X side of the kerf area in the mask data used for manufacturing X (Fig. 34), Y-side adhesive electrode part PAR Y (Fig. 35), PAR electrode part for crossing position CX (Figure 36) Create these laminated electrode parts PAR X ,PAR Y ,PAR CX are a plurality of laminated electrodes P k1x A plurality of bonding electrode patterns P corresponding to the (first bonding electrode) KX In steps S11m to S13m, the size, shape, and each of the plurality of adhesive electrode patterns PAR X ,PAR Y ,PAR CX The order of steps S11m to S13m is an example, and can be changed as appropriate. As described above, the laminated electrode parts PAR for the X side, the Y side, and the intersection position are defined. X ,PAR Y ,PAR CX The electrode pattern P KX The size, shape and pitch of the conductor may be specified.

[0107] Figure 37 shows the kerf area R K Adhesive electrode P k1x ,P k2x Mask frame data FR used in manufacturing dat 38 is a plan view showing an example of the frame data FR shown in FIG. dat PAR adhesive electrode part for X side X , Y-side bonding electrode part PAR Y and electrode parts for crossing positions PAR CX 37 and 38 are plan views showing a rectangular device region R dev and device region R dev The kerf area R surrounding K The device region R dev are chip C P ,C MThe device region R MD This is the area corresponding to.

[0108] Next, in step S14p, the laminated electrode part PAR created in steps S11p to S13p is X ,PAR Y ,PAR CX The kerf area R K In step S14m, the laminated electrode part PAR created in steps S11m to S13m is placed on the X ,PAR Y ,PAR CX The kerf area R K Place in.

[0109] More specifically, the frame data FR shown in FIG. dat Kerf area R K The bonded electrode parts PAR created in steps S11p to S13p and steps S11m to S13m X ,PAR Y ,PAR CX As a result, the frame data FR dat Kerf area R K 2, the bonding electrode pattern P KX is laid out.

[0110] FIG. 39 shows a wafer W P Kerf area R K Adhesive electrode P k2x Mask frame data FR used in manufacturing Pdat FIG. 40 is a plan view showing an example of the wafer W. M Kerf area R K Adhesive electrode P k1x Mask frame data FR used in manufacturing Mdat FIG.

[0111] Next, in step S15p, the laminated electrode part PAR X ,PAR Y ,PAR CX Electrode pattern P included in KXFrom the kerf area R K The electrode pattern P in the non-placeable area KX In step S15p, the wafer W P Frame data FR Pdat Kerf area R K The placement-prohibited area is identified, and the pasted electrode pattern P KX Frame data FR Pdat From the above, the electrode pattern P KX This results in the laminated electrode pattern P shown in Figure 39. KX The frame data FR Pdat can be obtained.

[0112] Here, the kerf area R K The area where placement is not possible is the kerf area R K This is an area where a bonding electrode pattern cannot be placed on the wafer W. M ,W P The litho mark, frame data, and TEG to be used after lamination of the wafer W are formed. The lengths of these areas in the X and Y directions are greater than the lengths of the lamination electrode pattern in the X and Y directions, respectively. P ,W P These marks include alignment marks used for positioning wiring and openings formed after lamination, and detection marks for measuring overlay accuracy.

[0113] In step S15m, the laminated electrode part PAR arranged in step S14m is X ,PAR Y ,PAR CX Electrode pattern P included in KX From the kerf area R K The electrode pattern P in the non-placeable area KX In step S15m, the wafer W M Frame data FR Mdat Kerf area R K The placement-unavailable area is identified, and the pasted electrode pattern PKX The frame data FR Mdat From the above, the electrode pattern P KX This results in a laminated electrode pattern P as shown in Figure 40. KX The frame data FR Mdat can be obtained.

[0114] Here, an example of a specific processing procedure of step S15p and step S15m will be described with reference to Fig. 33 and Fig. 41 to Fig. 49. Fig. 41 shows frame data FR in which a lithography mark used in lamination is arranged. Pidat (FR Midat FIG. 42 is a plan view showing an example of the frame data FR Pidat (FR Midat 43 is a plan view showing an example of the arrangement of lithography marks in a state where the frame data FR in FIG. Pidat Frame data FR with TEG and other regions added Pidat 44 is a plan view showing an example of the frame data FR in FIG. Midat Frame data FR with TEG and other regions added Midat 45 is a plan view showing an example of the frame data FR of FIG. Pidat Frame data FR with frame data area added Pidat 46 is a plan view showing an example of the frame data FR of FIG. Midat Frame data FR with the frame data area added Midat FIG. 47 is a plan view showing an example of the frame data FR Pidat Placement impossible area due to litho mark in b P1 ,b P2 FIG. 48 is a plan view showing the frame data FR Midat Placement impossible area due to litho mark in b M1 ,b M2 FIG. 49 is a plan view showing a lithography mark, a TEG area, frame data, or a placement prohibited area Rb PX (Rb MX) The laminated electrode pattern P is missing due to KX FIG.

[0115] In steps S151p and S151m, first, a state in which a lithography mark to be used in lamination is arranged is created. For example, as shown in FIG. 41, the frame data FR shown in FIG. dat In the alignment mark ALM P , alignment mark ALM M , Overlay mark OLM PM Frame data FR with Pidat ,FR Midat Create an alignment mark ALM. P is the frame data FR Pdat Alignment mark ALM M is the frame data FR Mdat The overlay mark OLM shown in FIG. PM is the overlapping mark M CP ,M CM It consists of the superposition mark M CP is the frame data FR Pdat The registration mark M CM is the frame data FR Mdat is formed.

[0116] Next, in steps S152p and S152m, a step-and-repeat state is created. For example, the frame data FR in FIG. Pidat (FR Midat ), a state is created in which exposure is performed three times while changing the position in the X direction and three times while changing the position in the Y direction, thereby creating a step-and-repeat state. In the example of FIG. 42, a state is created in which exposure is performed three times while changing the position in the X direction and three times while changing the position in the Y direction. In this case, as shown in FIG. 42, the frame data FR Pidat (FR Midat In region a of the substrate 1, a lithographic mark formed by step-and-repeat is placed.

[0117] Next, in steps S153p and S153m, a region such as TEG is added. For example, as shown in FIG. 43, the frame data FR shown in FIG. Pidat In the TEG region, P ,TEG M Frame data FR with Pidat Also, as shown in FIG. 44, for example, the frame data FR Pidat In the TEG region, P ,TEG M Frame data FR with Midat Create a region such as TEG P is the frame data FR Pidat The TEG is formed in the region M is the frame data FR Midat is formed.

[0118] Next, in step S154p, the frame data FR shown in FIG. Pidat For example, as shown in FIG. 45, the frame data FR shown in FIG. 43 is added to the frame data FR Pidat In the frame data area Cov Pdat Frame data FR with Pidat Create a.

[0119] Here, the frame data is the exposure area R EX This defines a light-shielding area to prevent double exposure of the laminated electrode pattern and other patterns at the end of the mask (see FIG. 8). The frame data has a pattern in which all areas are exposed once and none of the areas are exposed twice when exposure is performed three or more times while changing the position of the mask in the X direction and three or more times while changing the position of the mask in the Y direction.

[0120] For example, the frame data FR in Figure 45 Pidat is the kerf region R provided at one end in the X direction. K A part of the area of ​​the frame data Cov Pdatand a kerf region R K The other part of the area is the area Cov Pdat The shape and area of ​​the region obtained by combining these regions and the other regions are determined by the kerf region R K , and a kerf region R provided at the other end in the X direction K The shape and area are the same as those of

[0121] Also, the frame data FR Pidat is a kerf region R provided at one end in the Y direction. K The whole area is the frame data area Cov Pdat and a kerf region R K is the area of ​​the frame data Cov Pdat The kerf region R K The shape and area of ​​the kerf region R K The shape and area are the same as those of

[0122] Also, the frame data FR Pidat Three of the four corner regions are within the frame data Cov Pdat The remaining area is the area Cov Pdat The shapes and areas of these four corner regions are the same.

[0123] In step S154m, the frame data FR shown in FIG. Midat For example, as shown in FIG. 46, the frame data FR shown in FIG. Midat In the frame data FR Midat The frame data area Cov Mdat Frame data FR with Midat The area of ​​the frame data is Cov Pdat and the area of ​​the frame data Cov MdatThe shapes of the regions Cov are different. Pdat At least a part of the region Cov Mdat Similarly, the area Cov Mdat At least a part of the region Cov Pdat is provided at a position that does not overlap with at least a part of the

[0124] Next, in step S155p, the frame data FR Pidat Kerf area R K In the frame data FR Pidat In the case of the lithomark-induced placement-prohibited area b P1 ,b P2 Identify the prohibited area b P1 is the overlapping mark OLM PM This is the area where "B" was placed. P2 is the alignment mark ALM P This is the area where the

[0125] In step S155m, the frame data FR Midat Kerf area R K In the frame data FR Midat In the case of the lithomark-induced placement-prohibited area b M1 ,b M2 Identify the prohibited area b M1 is the overlapping mark OLM PM This is the area where "B" was placed. M2 is the alignment mark ALM M This is the area where the

[0126] Next, in step S156p, the frame data FR Pdat Kerf area R K Paste electrode pattern P KXFrom the above, the lithography mark, the TEG area, the frame data, and the laminated electrode pattern P that overlaps with the placement impossible area are KX In the next step S157p, the frame data FR Pdat Kerf area R K The missing electrode pattern P KX Delete.

[0127] Here, using FIG. 49, the missing laminated electrode pattern P KX The prohibited placement area Rb PX (Rb MX ) is the frame data FR Pidat (FR Midat ) in which the pasted electrode pattern P kx The frame data FR is an area where placement is not possible, such as a litho mark, a TEG area, frame data, or a placement-unavailable area. Pidat For example, as shown in FIG. FG The electrode pattern P KX Only a part of the prohibited area Rb PX In this case, the kerf area R K Paste electrode pattern P KX From the prohibited placement area Rb PX The laminated electrode pattern P overlaps with KX When you remove it, the area R FG The electrode pattern P KX A part of the laminated electrode pattern P is missing. KX Therefore, in step S157p, the frame data FR Pdat Kerf area R K The missing electrode pattern P KX Delete.

[0128] In this way, as shown in FIG. 39, the laminated electrode pattern P KX Frame data FR Pdat From the above, the electrode pattern P KX The deleted frame data FR Pdatcan be obtained.

[0129] In step S156m, the frame data FR Midat Kerf area R K Paste electrode pattern P KX From the above, the lithography mark, the TEG area, the frame data, and the laminated electrode pattern P that overlaps with the placement impossible area are KX In the next step S157m, the frame data FR Midat Kerf area R K The missing electrode pattern P KX Delete the frame data FR Midat For example, as shown in FIG. FG The electrode pattern P KX Only a part of the prohibited area Rb MX In this case, the kerf area R K Paste electrode pattern P KX From the prohibited placement area Rb MX The laminated electrode pattern P overlaps with KX When you remove it, the area R FG The electrode pattern P KX A part of the laminated electrode pattern P is missing. KX Therefore, in step S157m, the frame data FR Mdat Kerf area R K The missing electrode pattern P KX Delete.

[0130] In this way, as shown in FIG. 40, the laminated electrode pattern P KX The frame data FR Mdat From the above, the electrode pattern P KX The deleted frame data FR Mdat can be obtained.

[0131] Next, the process of step S16pm will be described with reference to Fig. 32 and Fig. 33 and Fig. 50 to Fig. 54. Fig. 50 shows the process of the frame data FR Pdat Frame data FR in the step-and-repeat state PdatSR 51 is a plan view showing the frame data FR Mdat Frame data FR that reproduces the step-and-repeat state of MdatSR 52 is a plan view showing the frame data FR Pdat Reproduced data FR that reproduces the step-and-repeat state of PdatSR2 FIG. 52 is a plan view showing an example of the reproduced data FR PdatSR2 For example, the frame data FR Pdat 53 shows the frame data FR of FIG. 40. The data shows the state where the exposure was performed three times while changing the position in the X direction and three times while changing the position in the Y direction using a mask created from the above. Mdat Reproduced data FR that reproduces the step-and-repeat state of MdatSR2 FIG. 53 is a plan view showing an example of the reproduced data FR MdatSR2 For example, the frame data FR Mdat FIG. 54 shows the data of the kerf region R after step and repeat, which is reproduced by exposing three times while changing the position in the X direction and three times while changing the position in the Y direction using a mask made from the above. K Paste electrode pattern P KX Data showing discrepancies in FR PMdif FIG.

[0132] Next, in step S16pm, the kerf region R after step and repeat is K 33, the step-and-repeat on the memory cell array side and the step-and-repeat on the peripheral circuit side are reproduced in steps S161p and S161m.

[0133] In step S161p, as shown in FIG.KX The frame data FR PdatSR More specifically, the frame data FR in FIG. Pdat By reproducing the state where the exposure was performed three times while changing the position in the X direction and three times while changing the position in the Y direction, the reproduced data FR PdatSR2 As shown in Fig. 1, the laminated electrode pattern P KX The frame data FR PdatSR is obtained.

[0134] In step S161m, as shown in FIG. KX The frame data FR MdatSR More specifically, the frame data FR in FIG. Mdat By reproducing the state where the exposure was performed three times while changing the position in the X direction and three times while changing the position in the Y direction, the reproduced data FR MdatSR2 As shown in Fig. 1, the laminated electrode pattern P KX The frame data FR MdatSR is obtained.

[0135] 33, in step S162pm, a region where the pasted electrode patterns on the memory cell array side and the peripheral circuit side do not match is extracted, taking into consideration the state after step-and-repeat. For example, as shown in FIG. 54, the frame data FR PdatSR and the frame data FR in Figure 51 MdatSR The electrode pattern P does not match KX has been extracted.

[0136] Next, the processing of steps S17pm, S18p, and S18m will be described with reference to Fig. 32 and Fig. 33 and Fig. 55 and Fig. 56. Fig. 55 shows the frame data FR Pdat Paste electrode pattern P KX From the mismatched part R Kno The electrode pattern P KX Frame data FR with deleted Pdat 56 is a plan view showing the frame data FR MdatPaste electrode pattern P KX From the mismatched part R Kno Paste electrode pattern P KX Frame data FR with deleted Mdat FIG.

[0137] In step S17pm, the kerf area R after step and repeat K As a result of comparing the pasted electrode patterns of the two, it is determined whether the patterns match. More specifically, in step S171pm, it is determined whether an area in which the pasted electrode patterns on the memory cell array side and the peripheral circuit side do not match has been extracted in step S162pm.

[0138] Kerf Area R K If the pasted electrode patterns match (match in step S17pm), that is, if an area where the pasted electrode patterns on the memory cell array side and the peripheral circuit side do not match can be extracted (no in step S171pm), the process ends.

[0139] On the other hand, the kerf area R K If it is determined that the pasted electrode patterns do not match (mismatch in step S17pm), that is, if an area in which the pasted electrode patterns on the memory cell array side and the peripheral circuit side do not match cannot be extracted (yes in step S171pm), the pasted electrode patterns in the mismatched areas are deleted in steps S18p and S18m.

[0140] In step S18p, as shown in FIG. 55, the frame data FR Pdat The laminated electrode pattern P KX From the mismatched part R Kno The electrode pattern P KX Similarly, in step S18m, as shown in FIG. 56, the frame data FR Mdat The laminated electrode pattern P KX From the mismatched part R Kno The electrode pattern P KX Delete.

[0141] Next, the process after steps S18p and S18m will be described with reference to Fig. 32 and Fig. 33 and Fig. 57 to Fig. 60. Fig. 57 shows the frame data FR Pdat Frame data FR in the step-and-repeat state PdatSR FIG. 58 is a plan view showing the frame data FR Mdat Frame data FR that reproduces the step-and-repeat state of MdatSR FIG. 59 is a plan view showing the frame data FR Pdat Reproduced data FR that reproduces the step-and-repeat state of PdatSR2 FIG. 59 is a plan view showing an example of the reproduced data FR PdatSR2 For example, the frame data FR Pdat 60 shows the frame data FR of FIG. 56. The data shows the state where the exposure was performed three times while changing the position in the X direction and three times while changing the position in the Y direction using a mask created from the above. Mdat Reproduced data FR that reproduces the step-and-repeat state of MdatSR2 FIG. 60 is a plan view showing an example of the reproduced data FR MdatSR2 For example, the frame data FR Mdat This data reproduces the state in which a mask created from the above was used to perform three exposures while changing the position in the X direction and three exposures while changing the position in the Y direction.

[0142] Next, in the second step S16pm, the kerf area R after step and repeat K 33, in step S161p and step S161m of the second iteration, the step-and-repeat on the memory cell array side and the step-and-repeat on the peripheral circuit side are reproduced.

[0143] In the second step S161p, as shown in FIG. KX The frame data FR PdatSRMore specifically, the frame data FR in FIG. Pdat By reproducing the state where the exposure was performed three times while changing the position in the X direction and three times while changing the position in the Y direction, the reproduced data FR PdatSR2 As shown in Fig. 1, the laminated electrode pattern P KX The frame data FR PdatSR The frame data FR shown in FIG. 57 and FIG. 59 is obtained. PdatSR Area aa p is the frame data FR of FIG. 50 and FIG. 52 obtained in the first step S161p. PdatSR Compared with the pasted electrode pattern P KX indicates areas that have not been reproduced.

[0144] In the second step S161m, as shown in FIG. KX The frame data FR MdatSR More specifically, the frame data FR in FIG. Mdat By reproducing the state where the exposure was performed three times while changing the position in the X direction and three times while changing the position in the Y direction, the reproduced data FR MdatSR2 As shown in Fig. 1, the laminated electrode pattern P KX The frame data FR MdatSR The frame data FR shown in FIG. 58 and FIG. 60 is obtained. MdatSR Area aa m is the frame data FR of FIG. 51 and FIG. 53 obtained in the first step S161m. MdatSR Compared with the pasted electrode pattern P KX indicates areas that have not been reproduced.

[0145] Next, as shown in Fig. 33, in the second step S162pm, the area where the pasted electrode patterns on the memory cell array side and the peripheral circuit side do not match is extracted, taking into account the state after the step-and-repeat. For example, as can be seen by comparing Figs. 57 and 58, the frame data FR PdatSR and the frame data FR in Figure 58 MdatSR The laminated electrode pattern PKX Therefore, the kerf region R K Adhesive electrode P k1x ,P k2x The design process of the mask data to be used in the manufacture of the mask is completed.

[0146] It should be noted that the processes after steps S18p and S18m do not have to be performed. More specifically, it is not necessary to perform steps S161m, S161p, S162pm, and S171pm in the second round.

[0147] [Mask used for patterning wiring layers MB and DB] 61 and 62 are schematic plan views illustrating the configuration of a mask used for patterning the wiring layers MB and DB. P Mask GM used for patterning the wiring layer DB inside P The third mask region R in FIG. G3 is the device region R dev FIG. 62 shows the area of ​​the wafer W M Mask GM used for patterning the wiring layer MB inside M The first mask region R in FIG. G1 is the device region R dev This is the area corresponding to.

[0148] Mask GM shown in FIG. 62 and FIG. 61 M ,GM P is a plurality of laminated electrodes P I1 ,P I2 ,P k1x ,P k2x Wafer W bonded via M ,W P A plurality of laminated electrodes P I1 ,P I2 ,P k1x ,P k2x This is a mask set used for exposure when patterning. Mask GM M ,GM Pis made of, for example, quartz glass, a metal such as chromium (Cr), or the like.

[0149] Mask GM shown in FIG. M (First mask) is a wafer W M Multiple device regions R (first wafer) dev (first device region) and a plurality of bonding electrodes P I1 ,P k1x Part of the laminated electrode P I1 ) corresponding to a plurality of first bonding electrode patterns P I1P A plurality of first mask regions R G1 and device region R dev Kerf region R surrounding (first device region) K A plurality of pasted electrodes P I1 ,P k1x Other part (adhesive electrode P k1x ) corresponding to the electrically disconnected second bonding electrode pattern P K1X A second mask region R including G2 It is equipped with.

[0150] This second mask region R G2 As shown in FIG. 62, the first region R G2R1x and the second region R G2R2x and the third region R G2R3x The first region R G2R1x are a pair of first mask regions R adjacent in the X direction. G1 The second region R G2R2x is multiple device regions R dev The third region R is provided on one side in the X direction (the positive side in the X direction in the figure). G2R3x is multiple device regions R dev 1, is provided on the other side in the X direction (the - side in the X direction in the drawing).

[0151] In addition, this second mask region R G2 As shown in FIG. 62, the first region R G2R1y and the second region R G2R2y and the third region R G2R3y The first region RG2R1y are a pair of first mask regions R adjacent to each other in the Y direction. G1 The second region R G2R2y is multiple device regions R dev The third region R is provided on one side in the Y direction (the positive side in the Y direction in the figure). G2R3y is multiple device regions R dev 1, is provided on the other side in the Y direction (the - side in the Y direction in the drawing).

[0152] Mask GM shown in FIG. P (Second mask) is the wafer W P (Second wafer) multiple device regions R dev (second device region) and a plurality of bonding electrodes P I2 ,P k2x Other part (adhesive electrode P I2 ) corresponding to a plurality of third bonding electrode patterns P I2P A plurality of third mask regions R G3 and device region R dev Kerf area R surrounding (second device area) K A plurality of pasted electrodes P I2 ,P k2x Other part (adhesive electrode P k2x ) corresponding to the fourth laminated electrode pattern P K2X A fourth mask region R including G4 It is equipped with.

[0153] This fourth mask region R G4 As shown in FIG. 61, the fourth region R G4R4x and the fifth region R G4R5x and the sixth region R G4R6x The fourth region R G4R4x are a pair of third mask regions R adjacent in the X direction. G3 The fifth region R G4R5x is multiple device regions R dev The sixth region R is provided on one side in the X direction (the positive side in the X direction in the figure). G4R6x is multiple device regions R dev1, is provided on the other side in the X direction (the - side in the X direction in the drawing).

[0154] In addition, this fourth mask region R G4 As shown in FIG. 61, the fourth region R G4R4y and the fifth region R G4R5y and the sixth region R G4R6y The fourth region R G4R4y A pair of third mask regions R adjacent to each other in the Y direction G3 The fifth region R G4R5y is multiple device regions R dev The sixth region R is provided on one side in the Y direction (the positive side in the Y direction in the figure). G4R6y is multiple device regions R dev 1, is provided on the other side in the Y direction (the - side in the Y direction in the drawing).

[0155] A plurality of second bonding electrode patterns P K1X is the first region R G2R1x ,R G2R1y A plurality of second bonding electrode patterns P K1X But the fourth region R G4R4x ,R G4R4y A plurality of fourth bonding electrode patterns P K2X In addition, the second bonding electrode patterns P K1X is the second region R G2R2x ,R G2R2y A plurality of second bonding electrode patterns P K1X and the third region R G2R3x ,R G2R3y A plurality of second bonding electrode patterns P K1X A plurality of second bonding electrode patterns P in the pattern group obtained by combining K1X But the fifth region R G4R5x ,R G4R5y A plurality of fourth bonding electrode patterns P K2X and the sixth region R G4R6x ,R G4R6y A plurality of fourth bonding electrode patterns P K2X A plurality of fourth bonded electrode patterns P in the pattern group obtained by combining K2XIt is provided at a position overlapping with either one of the above.

[0156] And the mask GM in FIG. 62 and FIG. 61 M ,GM P Now, the second region R G2R2x ,R G2R2y A plurality of second bonding electrode patterns P K1X At least a part of the fifth region R G4R5x ,R G4R5y A plurality of fourth bonding electrode patterns P K2X It is provided at a position where it does not overlap with any of the above.

[0157] Also, the mask GM in FIG. 62 and FIG. 61 M ,GM P In each of the above, different frame data are used.

[0158] More specifically, the mask GM shown in FIG. M is the second region R G2R2x ,R G2R2y 2. A plurality of second bonding electrode patterns P K1X and the lengths in the X and Y directions are equal to or smaller than the second laminated electrode pattern P K1X A first light-shielding region having a length in the X direction and a length in the Y direction greater than that of the third region R G2R3x ,R G2R3y 2. A plurality of second bonding electrode patterns P K1X and the lengths in the X and Y directions are equal to or smaller than the second laminated electrode pattern P K1X and a second light-shielding region having a length greater than the length of the first light-shielding region in the X direction and the length of the second light-shielding region in the Y direction. The first light-shielding region and the second light-shielding region are provided at positions where they do not overlap.

[0159] Also, the mask GM shown in FIG. P is the fifth region R G4R5x ,R G4R5y and a plurality of fourth bonding electrode patterns P K2X and the lengths in the X and Y directions are equal to or larger than the fourth laminated electrode pattern P K2X a third light-shielding region having a length in the X direction and a length in the Y direction greater than that of the third region R G2R3x ,R G2R3yand a plurality of fourth bonding electrode patterns P K2X and the lengths in the X and Y directions are equal to or larger than the fourth laminated electrode pattern P K2X and a fourth light-shielding region having a length greater than the lengths of the third light-shielding region in the X and Y directions. The third light-shielding region and the fourth light-shielding region are provided at positions where they do not overlap.

[0160] The shape of the pattern group obtained by combining the first and second light-shielding regions is different from the shape of the pattern group obtained by combining the third and fourth light-shielding regions. The shape of the pattern group corresponds to the shape of the frame data described above.

[0161] Typically, the size of the pattern of the laminated electrode is about several hundreds of nm to several μm. On the other hand, the size of the pattern of the frame data is about several tens of μm to several hundreds of μm in width and several tens of mm in length. In other words, the sizes of the two differ by one order of magnitude or more.

[0162] [Kerf area R of the lamination surface due to exposure K A wafer W on which M ,W P ] Wafer W M In the manufacture of the mask GM shown in FIG. M 10 and 11, the wiring layer MB on the bonding surface is formed by exposing the wafer W several times while changing the position in the X direction and the position in the Y direction. P In the manufacture of the mask GM shown in FIG. P By using the above, the wiring layer MB of the bonding surface is formed by performing exposure multiple times while changing the position in the X direction and multiple times while changing the position in the Y direction. In this way, in order to form the wiring layer MB of the bonding surface by a method of performing exposure multiple times while changing the position in the X direction and the Y direction, the wafer W described with reference to FIG. M Kerf area R K ´ Adhesive electrode P k1x At least some of the positions of the wafer W described with reference to FIG. P Kerf area R KAny of the laminated electrodes P k2x Similarly, the position of the wafer W described with reference to FIG. P Kerf area R K ´ Adhesive electrode P k1x At least some of the positions of the wafer W described with reference to FIG. M Kerf area R K Any of the laminated electrodes P k2x The position of the sigma-based ...

[0163] As described with reference to FIGS. 10 and 11, the mask GM M (GM P ) to change the position in the X and Y directions and perform multiple exposures. EX A part of the wafer W M (W P ) in some places. In these protruding parts, the structure region R ST is formed.

[0164] [Effects of the embodiment] According to the embodiment, the wafer W M ,W P is the bonding surface S B Since the occurrence of voids can be suppressed even when the substrate is laminated, the manufacturing yield of the semiconductor device can be improved. This effect will be described below.

[0165] The wafer W according to this embodiment M ,W P According to the configuration of M ,W P Kerf area R K Electrode P k1x ,P k2x Masks used in manufacturing GM M ,GM P Frame data with different shapes are formed in the kerf area R K The bonding electrode P is provided k1x ,P k2x The positions of the two are manufactured so that they overlap when they are bonded together. BThe wafer W is then flattened. M ,W P is the bonding surface S B When the device is bonded to the device area R MD and kerf area R K It is possible to suppress the generation of voids in the vicinity of the boundary with the substrate.

[0166] In addition, the mask GM according to this embodiment M ,GM P According to the design method of the wafer W M ,W P Kerf area R K Electrode P k1x ,P k2x Masks used in manufacturing GM M ,GM P Even if frame data with different shapes is formed in the kerf area R K The bonding electrode P is provided k1x ,P k2x The respective positions can be manufactured so that they overlap and match when laminated.

[0167] Furthermore, Mask GM M ,GM P In the kerf region R, the alignment marks to be used after lamination are formed, so that they do not interfere with the alignment process after lamination. K Electrode P k1x ,P k2x Place the kerf area R K In the laminated electrode P k1x The coverage of the kerf area R K The area of ​​the laminated electrode P in the unit area of k1x The kerf area R is calculated as a percentage of the area of ​​the K In the laminated electrode P k1x The placement rate of Mask GM M ,GM P The kerf area R of the circumference K The laminated electrode P is arranged k1x The coverage rate of is HA, and the mask GM excluding the frame data area is M ,GM P Electrode P is attached to the entire outer circumference of k1xWhen the coverage rate when the above is placed is HB, it is calculated as (HA / HB) × 100.

[0168] And the mask GM according to this embodiment M ,GM P According to the design method of the above, the wafer W is designed by taking into consideration the step-and-repeat or step-and-scan state. M ,W P Kerf area R K Electrode P k1x ,P k2x This allows the placement rate to be improved. K The lamination surface S that can be made flat at B The area of ​​the wafer W can be increased. M ,W P is the bonding surface S B When the device is bonded to the device area R MD and kerf area R K It is possible to suppress the generation of voids in the vicinity of the boundary with the substrate.

[0169] [Other embodiments] The design method, semiconductor device, and mask set according to the embodiment have been described above. However, the above design method, semiconductor device, and mask set are merely examples, and specific configurations and the like can be adjusted as appropriate. For example, when a mask GM with a device region of 2×2 is used, M ,GM P 2x2 or 6x6 frame data FR Mdat ,FR Pdat The device region configuration and kerf region R K The arrangement of the bonding electrodes, TEG, and lithography marks formed in the frame data FR of 2×9 may be changed as appropriate. dat Here, FIG. 63 shows the frame data Cov dat , frame data FR in which the lithomark ALM and TEG are arranged dat FIG. 64 is a plan view conceptually showing the frame data Cov dat , kerf area RK Paste electrode pattern P KX The frame data FR dat It is a plan view conceptually showing the blank area Pb k The area of ​​the lithography mark used on the back side and the TEG are arranged, and the bonding electrode pattern P KX This shows an area that has not been placed.

[0170] In the embodiment, the semiconductor device is a chip C M The example in which a NAND flash memory is mounted on a chip C has been described. However, the configuration of the semiconductor device can be adjusted as appropriate. For example, M Chip C may be equipped with 2D or 3D DRAM or SRAM. M When an SRAM is mounted on the chip, the SRAM may be a FinFET, a Nano sheet, a fork sheet, or the like. M A component other than a memory may be mounted on the chip C. M may be equipped with a plurality of photodiodes that constitute an imaging element.

[0171] In addition, the present specification discloses the following items. [Matter 1] A first mask is used to transfer a plurality of first bonding electrode patterns onto a first wafer; forming a plurality of first bonding electrodes on the first wafer along the plurality of first bonding electrode patterns; A second mask is used to transfer a plurality of second bonding electrode patterns onto a second wafer; forming a plurality of second bonding electrodes on the second wafer along the plurality of second bonding electrode patterns; The first wafer and the second wafer are bonded together via the plurality of first bonding electrodes and the plurality of second bonding electrodes; The first mask is A plurality of first mask regions are provided at positions corresponding to a plurality of first device regions of the first wafer, and include a plurality of first bonding electrode patterns corresponding to a portion of the plurality of first bonding electrodes; a second mask region provided at a position corresponding to a first kerf region surrounding the first device region, the second mask region including a plurality of second adhesive electrode patterns corresponding to another part of the plurality of first adhesive electrodes; Equipped with The second mask is A plurality of third mask regions are provided at positions corresponding to a plurality of second device regions of the second wafer, and include a plurality of third bonding electrode patterns corresponding to some of the plurality of second bonding electrodes; a fourth mask region provided at a position corresponding to a second kerf region surrounding the second device region and including a plurality of fourth adhesive electrode patterns corresponding to another part of the plurality of second adhesive electrodes; Equipped with The plurality of first adhesive electrode patterns are provided at positions overlapping the plurality of third adhesive electrode patterns, At least a portion of the second adhesive electrode patterns is provided at a position not overlapping any of the fourth adhesive electrode patterns. A method for manufacturing a semiconductor device.

[0172] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0173] GM M ,GM P ... Mask, P kx …Laminated electrode pattern, P k1x ,P k2x ...Laminated electrode, W M ,W P ...Wafer, R MD ,R dev …device region, R K...Kerf area, DL...Dicing line, FR Pdat ,FR Mdat ,FR MdatSR ,FR PdatSR ...frame data, 200...semiconductor substrate, GC...electrode layer, L WL ...word line layer, 110...conductive layer, 120...semiconductor layer, 130...gate insulating film

Claims

1. A method for designing a mask set used for exposure when patterning a plurality of bonding electrodes of a first wafer and a second wafer bonded together via the plurality of bonding electrodes, comprising: the mask set includes a first mask and a second mask; the first wafer and the second wafer each include a plurality of device regions and a kerf region surrounding the plurality of device regions; The plurality of adhesive electrodes include a plurality of first adhesive electrodes provided in the device region and a plurality of second adhesive electrodes provided in the kerf region and each of which is electrically unconnected; The design method includes: The size and shape of the second adhesive electrode are defined, A plurality of second adhesive electrode patterns corresponding to the second adhesive electrode are arranged in the kerf regions of the first mask and the second mask; Identifying an unplaceable area in which the second adhesive electrode cannot be placed in each of the kerf area of ​​the first mask and the kerf area of ​​the second mask, In the kerf region of the first mask, the second attached electrode pattern arranged in the arrangement prohibited region of the first mask is removed; generating a first pattern group formed in an exposure region adjacent to another exposure region on both sides in the first direction and on both sides in the second direction out of nine or more exposure regions formed by performing exposure three or more times while changing a position in a first direction and three or more times while changing a position in a second direction intersecting the first direction using the first mask; In the kerf region of the second mask, the second laminated electrode pattern arranged in the arrangement unavailable region of the second mask is removed; generating a second pattern group formed in an exposure region adjacent to another exposure region on both sides in the first direction and on both sides in the second direction out of nine or more exposure regions formed by performing exposure three or more times while changing the position in the first direction and three or more times while changing the position in the second direction using the second mask; When the first wafer and the second wafer are bonded to each other, when viewed from a direction intersecting the surfaces of the first wafer and the second wafer, a plurality of positions of the second bonding electrode patterns included in the first pattern group and a plurality of positions of the second bonding electrode patterns included in the second pattern group are extracted, where the positions do not overlap with each other; The second adhesive electrode pattern arranged in the non-overlapping portions of the kerf region of the first mask and the kerf region of the second mask is removed. Design method.

2. The first mask and the second mask each include a plurality of mask regions corresponding to the plurality of device regions; a mask region corresponding to the kerf region; Equipped with The mask area of ​​the first mask corresponding to the kerf area is a first region provided between a pair of mask regions corresponding to the device regions adjacent to each other in the first direction; a second region provided on one side in the first direction with respect to a plurality of mask regions corresponding to the plurality of device regions; a third region provided on the other side in the first direction with respect to a plurality of mask regions corresponding to the plurality of device regions; Equipped with The mask area of ​​the second mask corresponding to the kerf area is a fourth region provided between a pair of mask regions corresponding to the device regions adjacent to each other in the first direction; a fifth region provided on one side in the first direction with respect to a plurality of mask regions corresponding to the plurality of device regions; a sixth region provided on the other side in the first direction with respect to a plurality of mask regions corresponding to the plurality of device regions; Equipped with The plurality of second adhesive electrode patterns are The second adhesive electrode patterns provided in the first region are provided at positions overlapping with the fourth adhesive electrode patterns provided in the fourth region, A plurality of second adhesive electrode patterns in a pattern group obtained by combining the plurality of second adhesive electrode patterns provided in the second region and the plurality of second adhesive electrode patterns provided in the third region are provided at positions overlapping any one of a plurality of fourth adhesive electrode patterns in a pattern group obtained by combining the plurality of fourth adhesive electrode patterns provided in the fifth region and the plurality of fourth adhesive electrode patterns provided in the sixth region; At least a part of the second adhesive electrode patterns provided in the second region is provided at a position not overlapping any of the fourth adhesive electrode patterns provided in the fifth region. The design method according to claim 1 .

3. At least a part of the second adhesive electrode patterns provided in the third region is provided at a position not overlapping any of the fourth adhesive electrode patterns provided in the sixth region. The design method according to claim 2.

4. A plurality of fourth adhesive electrode patterns in the pattern group obtained by combining the plurality of fourth adhesive electrode patterns provided in the fifth region and the plurality of fourth adhesive electrode patterns provided in the sixth region are provided at positions overlapping any of a plurality of second adhesive electrode patterns in the pattern group obtained by combining the plurality of second adhesive electrode patterns provided in the second region and the plurality of second adhesive electrode patterns provided in the third region; At least a part of the plurality of fourth adhesive electrode patterns provided in the fifth region is provided at a position not overlapping any of the plurality of second adhesive electrode patterns provided in the second region. The design method according to claim 2.

5. the no-placement area of ​​the first mask includes a first light-shielding area pattern; a shape and an area of ​​a pattern group obtained by combining a portion of the first light-shielding region pattern corresponding to the second region and a portion of the first light-shielding region pattern corresponding to the third region are the same as shapes and areas of the second region and the third region; the no-placement area of ​​the second mask includes a second light-shielding area pattern; a shape and an area of ​​a pattern group obtained by combining a portion of the second light-shielding region pattern corresponding to the fifth region and a portion of the second light-shielding region pattern corresponding to the sixth region are the same as the shapes and areas of the fifth region and the sixth region; The shape of the first light blocking region pattern is different from the shape of the second light blocking region pattern. The design method according to claim 2.

6. The placement unavailable area of ​​the first mask further includes a third light-shielding area pattern, the third light-shielding area pattern having a length in the first direction and a length in the second direction that are greater than the length in the first direction and the length in the second direction of the second adhesive electrode pattern, respectively; The placement unavailable area of ​​the second mask further includes a second light-shielding area pattern having a length in the first direction and a length in the second direction that are greater than a length in the first direction and a length in the second direction of the second adhesive electrode pattern, respectively. The design method according to claim 5.

7. The substrate includes a first wafer and a second wafer bonded together via a plurality of bonding electrodes, The first wafer is a plurality of rectangular first device regions arranged in a first direction and a second direction intersecting the first direction; a plurality of first structure regions arranged in the first direction or the second direction with respect to any one of the plurality of first device regions; a first kerf region surrounding each of the first device regions and the first structure regions; a margin area in which none of the plurality of first device areas, the plurality of first structure areas, and the first kerf area is provided; Equipped with the first device region has an outer periphery spaced from an outer periphery of the first wafer; a distance from the margin region to the first device region is greater than one or both of a width of the first device region in the first direction and a width of the first device region in the second direction; a portion of the first structure region has an outer periphery along an outer periphery of the first wafer; a distance from the margin region to another part of the first structure region is smaller than a width of the first device region in the first direction and a width of the first device region in the second direction; The first wafer is An internal element; a first laminated electrode layer including a part of the plurality of laminated electrodes; Equipped with The first laminated electrode layer is a plurality of first bonding electrodes provided in the plurality of first device regions and the plurality of first structure regions and electrically connected to the internal element; a plurality of second bonded electrodes provided in the first kerf region and each of which is in an electrically disconnected state; Equipped with The second wafer is a plurality of second device regions provided at positions overlapping the plurality of first device regions when viewed from a stacking direction intersecting the first direction and the second direction; a plurality of second structure regions provided at positions overlapping the plurality of first structure regions when viewed from the stacking direction; A second kerf region provided at a position overlapping the first kerf region when viewed from the stacking direction; Equipped with The second wafer is A plurality of transistors; a second bonded electrode layer provided on the first wafer side and including another part of the plurality of bonded electrodes; Equipped with The second laminated electrode layer is a plurality of third bonding electrodes provided in the plurality of second device regions and the plurality of second structure regions and electrically connected to the plurality of transistors; a plurality of fourth attached electrodes provided in the second kerf region and each of which is in an electrically disconnected state; Equipped with The first kerf region comprises: a first region provided between a pair of the first device regions adjacent to each other in the first direction; a second region provided between any one of the plurality of first structure regions and the blank region; Equipped with The second kerf region comprises: a third region provided at a position overlapping the first region when viewed from the stacking direction; a fourth region provided at a position overlapping the second region when viewed from the stacking direction; Equipped with The second adhesive electrodes provided in the first region are provided at positions overlapping with the fourth adhesive electrodes provided in the third region when viewed from the stacking direction; At least a part of the second adhesive electrodes provided in the second region is provided at a position not overlapping any of the fourth adhesive electrodes provided in the fourth region when viewed from the stacking direction. Semiconductor device.

8. the first kerf region comprises one or both of a litho mark and a TEG; The plurality of bonding electrodes are provided at positions not overlapping one or both of the lithography mark and the TEG when viewed from the stacking direction.

8. The semiconductor device according to claim 7.

9. the first kerf area comprises a litho mark; The plurality of bonding electrodes are provided at positions overlapping the lithography marks when viewed from the stacking direction.

8. The semiconductor device according to claim 7.

10. The fourth adhesive electrodes provided in the third region are provided at positions overlapping with any of the second adhesive electrodes provided in the first region when viewed from the stacking direction, At least a part of the plurality of fourth adhesive electrodes provided in the fourth region is provided at a position not overlapping any of the plurality of second adhesive electrodes provided in the second region when viewed from the stacking direction.

8. The semiconductor device according to claim 7.

11. Among the plurality of first structure regions, a portion of the periphery of which is along the periphery of the first wafer and the second wafer has an area smaller than that of the first device region.

8. The semiconductor device according to claim 7.

12. Another part of the plurality of first structure regions is rectangular and has the same area as the first device region. The semiconductor device according to claim 11.

13. The first wafer is A plurality of first conductive layers stacked in a stacking direction; a first wiring layer provided between the plurality of first conductive layers and the first laminated electrode layer; Further comprising: The first kerf region comprises: a region including a plurality of second conductive layers stacked in the stacking direction corresponding to the plurality of first conductive layers; a region outside the region including the plurality of second conductive layers; Including, In the first wiring layer, a coverage rate of the wiring provided in the region including the plurality of second conductive layers is smaller than a coverage rate of the wiring provided in the outer region.

8. The semiconductor device according to claim 7.

14. The first wafer further includes a plurality of first conductive layers stacked in a stacking direction, The second wafer further includes a second wiring layer provided between the plurality of transistors and the second bonding electrode layer, The first kerf region comprises: a region including a plurality of second conductive layers stacked in the stacking direction corresponding to the plurality of first conductive layers; a region outside the region including the plurality of second conductive layers; Including, In the second wiring layer, a coverage rate of the wiring provided in the region including the plurality of second conductive layers is smaller than a coverage rate of the wiring provided in the outer region.

8. The semiconductor device according to claim 7.

15. A mask set used for exposure when patterning a plurality of bonding electrodes of a first wafer and a second wafer bonded together via the plurality of bonding electrodes, the mask set includes a first mask and a second mask; The first mask is A plurality of first mask regions are provided at positions corresponding to a plurality of first device regions of the first wafer, and include a plurality of first bonding electrode patterns corresponding to a portion of the plurality of bonding electrodes; a second mask region including a plurality of second adhesive electrode patterns corresponding to another part of the plurality of adhesive electrodes, the second mask region being provided at a position corresponding to a first kerf region surrounding the first device region; Equipped with The second mask is A plurality of third mask regions are provided at positions corresponding to a plurality of second device regions of the second wafer, and include a plurality of third bonding electrode patterns corresponding to other parts of the plurality of bonding electrodes; a fourth mask region provided at a position corresponding to a second kerf region surrounding the second device region and including a plurality of fourth attached electrode patterns corresponding to another part of the plurality of attached electrodes; Equipped with The plurality of first adhesive electrode patterns are provided at positions overlapping the plurality of third adhesive electrode patterns, At least a portion of the second adhesive electrode patterns is provided at a position not overlapping any of the fourth adhesive electrode patterns. Mask set.

16. The second mask region is a first region provided between a pair of first mask regions adjacent to each other in a first direction; a second region provided on one side of the first mask regions in the first direction; a third region provided on the other side of the first mask regions in the first direction; Equipped with The fourth mask region is a fourth region provided between a pair of third mask regions adjacent to each other in the first direction; a fifth region provided on the other side in the first direction with respect to the third mask regions; a sixth region provided on the one side in the first direction with respect to the plurality of third mask regions; Equipped with The plurality of second adhesive electrode patterns are The second adhesive electrode patterns provided in the first region are provided at positions overlapping with the fourth adhesive electrode patterns provided in the fourth region, A plurality of second adhesive electrode patterns in a pattern group obtained by combining the plurality of second adhesive electrode patterns provided in the second region and the plurality of second adhesive electrode patterns provided in the third region are provided at positions overlapping any one of a plurality of fourth adhesive electrode patterns in a pattern group obtained by combining the plurality of fourth adhesive electrode patterns provided in the fifth region and the plurality of fourth adhesive electrode patterns provided in the sixth region; At least a part of the second adhesive electrode patterns provided in the second region is provided at a position not overlapping any of the fourth adhesive electrode patterns provided in the fifth region. The mask set according to claim 15.

17. At least a part of the second adhesive electrode patterns provided in the third region is provided at a position not overlapping any of the fourth adhesive electrode patterns provided in the sixth region.

17. The mask set of claim 16.

18. A plurality of fourth adhesive electrode patterns in the pattern group obtained by combining the plurality of fourth adhesive electrode patterns provided in the fifth region and the plurality of fourth adhesive electrode patterns provided in the sixth region are provided at positions overlapping any of a plurality of second adhesive electrode patterns in the pattern group obtained by combining the plurality of second adhesive electrode patterns provided in the second region and the plurality of second adhesive electrode patterns provided in the third region; At least a part of the plurality of fourth adhesive electrode patterns provided in the fifth region is provided at a position not overlapping any of the plurality of second adhesive electrode patterns provided in the second region.

17. The mask set of claim 16.

19. When the pattern group is generated by combining the second adhesive electrode patterns provided in the second region and the second adhesive electrode patterns provided in the third region, the second adhesive electrode patterns provided in the second region are provided at positions that do not overlap any of the second adhesive electrode patterns provided in the third region.

17. The mask set of claim 16.

20. the first mask includes a first light-shielding region that does not include any of the plurality of second adhesive electrode patterns; a shape and an area of ​​a region obtained by combining a portion of the first light-shielding region corresponding to the second region and a portion of the first light-shielding region corresponding to the third region are the same as the shapes and areas of the second region and the third region; the second mask includes a second light-shielding region that does not include any of the plurality of fourth adhesive electrode patterns; a shape and an area of ​​a region obtained by combining a portion of the second light-shielding region corresponding to the fifth region and a portion of the second light-shielding region corresponding to the sixth region are the same as the shapes and areas of the fifth region and the sixth region; At least a part of the first light-shielding region that corresponds to the second region is provided at a position that does not overlap with at least a part of the second light-shielding region that corresponds to the fifth region.

17. The mask set of claim 16.

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