Semiconductor device

Abstract

To provide a semiconductor device capable of preventing a sintered metal layer from forming a rising part in a region between two adjacent semiconductor chips.SOLUTION: A semiconductor device 1 includes: a substrate 2 with a wiring layer 4; a first semiconductor chip 5A and a second semiconductor chip 5B that are joined adjacent to each other to a common wiring layer 4 among the wiring layers 4; and a sintered metal layer 6 that bonds the first semiconductor chip 5A and the second semiconductor chip 5B to a common wiring layer 4. The common wiring layer 4 has a recess 4A that is lower in height than that of a region where the first semiconductor chip 5A and the second semiconductor chip 5B are bonded in a region between the first semiconductor chip 5A and the second semiconductor chip 5B.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] As an example of a semiconductor device, for example, Patent Document 1 discloses in FIGS. 1(a) and 1(b) a semiconductor module in which a plurality of semiconductor chips are bonded to a wiring layer on a substrate via a sintered metal layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-167527 A Summary of the Invention [Problem to be solved by the invention]

[0004] FIG. 2 is a cross-sectional view illustrating a problem with a conventional semiconductor device.

[0005] 2, the substrate 2 is composed of an insulating substrate 3 and a wiring layer 4. A first semiconductor chip 5A and a second semiconductor chip 5B, which are arranged adjacent to each other as the semiconductor chips 5, are bonded to the wiring layer 4 via a sintered metal layer 6.

[0006] Here, unlike solder bonding, the sintered metal bonding is performed by applying a sintered metal paste onto the wiring layer 4, placing the semiconductor chip 5 thereon, and then heating the sintered metal while applying pressure to the semiconductor chip 5. Therefore, in the region between the first semiconductor chip 5A and the second semiconductor chip 5B that are adjacent to each other, if the gap between them is narrow, the pressurized sintered metal paste may come into contact with each other and rise up, forming a raised portion 6A. As a result, the raised portion 6A may come into contact with the electrode on the front side of the semiconductor chip 5 or the bonding wire 7 connected to the electrode on the front side of the semiconductor chip 5, or may come into close proximity and cause a discharge.

[0007] An object of the present invention is to provide a semiconductor device capable of suppressing the formation of a protruding portion of a sintered metal layer in a region between two adjacent semiconductor chips. [Means for solving the problem]

[0008] In order to solve the above-mentioned problems, the semiconductor device of the present invention comprises a substrate having a wiring layer, a first semiconductor chip and a second semiconductor chip which are joined adjacent to each other to a common wiring layer of the wiring layer, and a sintered metal layer which joins the first semiconductor chip and the second semiconductor chip to the common wiring layer, and is characterized in that the common wiring layer has a recess in a region between the first semiconductor chip and the second semiconductor chip which is lower in height than the region where the first semiconductor chip and the second semiconductor chip are joined. Effect of the Invention

[0009] According to the present invention, it is possible to suppress the formation of a protruding portion of the sintered metal layer in the region between two adjacent semiconductor chips. [Brief description of the drawings]

[0010] [Figure 1] FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment. [Diagram 2]1 is a cross-sectional view illustrating a problem of a conventional semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In each drawing, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted.

[0012] FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment.

[0013] The semiconductor device 1 includes a substrate 2 , a semiconductor chip 5 , and a sintered metal layer 6 .

[0014] The substrate 2 has an insulating substrate 3, such as a ceramic substrate made of SiN, and a wiring layer 4 bonded to the insulating substrate 3 via a brazing material (not shown). The wiring layer 4 is made of a conductive metal, such as copper.

[0015] The semiconductor chip 5 is joined to the wiring layer 4 via a sintered metal layer 6. The wiring layer 4 is divided into multiple parts when viewed in a plan view, forming a circuit pattern. The sintered metal layer 6 can be, for example, a sintered copper layer or a sintered silver layer.

[0016] The semiconductor chip 5 has a first semiconductor chip 5A and a second semiconductor chip 5B. The first semiconductor chip 5A and the second semiconductor chip 5B are disposed adjacent to each other and are joined to a common wiring layer 4 of the wiring layer 4. Here, the common wiring layer 4 means that it is an integrated pattern that is not divided when viewed in a plan view, and is an electrically connected pattern.

[0017] Here, if the gap between the first semiconductor chip 5A and the second semiconductor chip 5B arranged adjacent to each other is narrow, the sintered metal paste applied under pressure during the manufacturing process may come into contact with each other and rise up, resulting in a problem of forming a raised portion 6A as shown in Figure 2.

[0018] 1, the common wiring layer 4 has a recess 4A in the region between the first semiconductor chip 5A and the second semiconductor chip 5B that is lower in height than the region where the first semiconductor chip 5A and the second semiconductor chip 5B are bonded. This allows the sintered metal paste pressurized during the manufacturing process to enter the recess 4A, and the sintered metal layer 6 also exists in the recess 4A, so that the formation of the raised portion 6A can be suppressed.

[0019] In the recess 4A, the sintered metal layer 6 bonding the first semiconductor chip 5A and the sintered metal layer 6 bonding the second semiconductor chip 5B may or may not be in contact with each other. Since the first semiconductor chip 5A and the second semiconductor chip 5B are bonded to a common wiring layer 4, there is no problem even if they are in contact with each other and electrically connected.

[0020] 1 shows an example in which the raised portion 6A is not formed, but the present invention is not limited to this, and the raised portion 6A may be formed to a size that does not cause a problem of the raised portion 6A contacting or discharging in close proximity to the electrodes on the front surface of the semiconductor chip 5 or the bonding wires 7 connected to the electrodes on the front surface of the semiconductor chip 5. Even when the raised portion 6A is formed, the size of the raised portion 6A can be made smaller than when there is no recess 4A.

[0021] It is desirable that the recess 4A is a non-penetrating recess that does not penetrate the common wiring layer 4. This can reduce an increase in the electrical resistance of the common wiring layer 4 caused by providing the recess 4A. However, without being limited thereto, the recess 4A may be formed by a through hole that penetrates the common wiring layer 4.

[0022] As described above, according to the semiconductor device 1 of this embodiment, it is possible to prevent the formation of the raised portion 6A of the sintered metal layer 6 in the region between two semiconductor chips 5 adjacent to each other.

[0023] Although the embodiment of the present invention has been described above, the present invention is not limited to the configurations described in the embodiment, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in the embodiment may be combined and applied. [Explanation of symbols]

[0024] 1 Semiconductor device 2. Board

Claims

1. A substrate having a wiring layer; a first semiconductor chip and a second semiconductor chip adjacent to each other and bonded to a common wiring layer among the wiring layers; a sintered metal layer that bonds the first semiconductor chip and the second semiconductor chip to the common wiring layer; a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being joined to each other;

2. In claim 1, The semiconductor device is characterized in that the sintered metal layer is also present in the recess.

3. In claim 1, The semiconductor device according to the present invention is characterized in that the recess is a non-penetrating recess that does not penetrate the common wiring layer.

4. In claim 1, The semiconductor device, wherein the sintered metal layer is a sintered copper layer.

5. In claim 1, The semiconductor device, wherein the sintered metal layer is a sintered silver layer.

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