Semiconductor device, and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device capable of preventing a semiconductor chip from displacing even when the solder under the chip is melted again by melting the solder under the substrate.SOLUTION: A semiconductor device 20 includes: multiple semiconductor chips 1; an insulating substrate 6; a circuit pattern 3 formed on the surface of the insulating substrate: a solder under the chip 7 joining the semiconductor chip 1 and the circuit pattern 3; a metal layer 8 formed on the back side of the insulating substrate 6; a base member 10; a solder under a substrate 9 joining the base member 10 and the metal layer 8; multiple wires 4 and 5 joining the semiconductor chips 1 or between the semiconductor chip 1 and the circuit pattern 3; first insulating resins 15 and 16 bonding multiple wires 4 connecting the semiconductor chips 1 or bonding the multiple wires 5 connecting between the semiconductor chip 1 and the circuit pattern 3; and a sealing resin 17 that seals at least the multiple semiconductor chips 1, the multiple wires 4 and 5, and the first insulating resins 15 and 16.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, when manufacturing a semiconductor device such as a power semiconductor module, a first soldering process may be performed in which a semiconductor chip is joined to a circuit pattern formed on the front side of an insulating substrate via solder (solder under the chip), and a second soldering process may be performed in which a metal layer formed on the back side of the insulating substrate is joined to a base member via solder (solder under the substrate).

[0003] Such a technique is disclosed, for example, in FIG. 1 and paragraphs 0028-0029 of Patent Document 1.

[0004] Furthermore, Patent Document 2 describes a technique for suppressing discharge by applying an insulating resin solution to the ends of a circuit pattern (electrode) bonded to an insulating substrate and then curing the solution. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-179538 A [Patent Document 2] JP 2018-6569 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the second soldering process, when melting the under-substrate solder that joins the metal layer and the base member, there was a problem that the under-chip solder that joined the semiconductor chip and the circuit pattern in the first soldering process could re-melt, causing the semiconductor chip to become misaligned.

[0007] Incidentally, in paragraph 0029 of Patent Document 1, it is stated that "In this embodiment, the solder 3 under the chip and the solder 16 under the board are made of solder with the same melting point, so that the soldering under the board was examined by remelting the previously joined solder under the chip, and there was no problem of misalignment due to vibration," but as a result of examination by the inventor of this application, when the solder under the chip remelted, the molten solder flowed and caused the semiconductor chip to shift in some cases. Misalignment of the semiconductor chip can lead to poor characteristics and reliability (reduced solder life) of the semiconductor module.

[0008] Furthermore, in paragraph 0030 of Patent Document 1, it is stated that "Next, a polyimide-based or polyamide-imide-based resin, which is flexible and has adhesiveness to the Si chip 1, Al, etc., is diluted with a solvent and uniformly and thinly sprayed or applied to the surface and side of the mounted Si chip 1 and ceramic substrate 102, and the surface of the base substrate 4, so that the thickness of the cured polyimide-based resin 9 is 10 μm to 50 μm. Next, a polyimide-based resin having a low Young's modulus and a linear expansion coefficient (20.5×10 -6 Epoxy resin 10, which has a linear expansion coefficient approximately equal to that of the resin applied previously (1000 MPa / °C), is potted on top of the resin applied previously and hardened." It also states that after the second soldering process, the surface of the semiconductor chip, etc. is covered with a thin resin and then sealed with epoxy resin. However, since this is formed after the second soldering process, it cannot solve the problem of the semiconductor chip being misaligned.

[0009] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can prevent the semiconductor chip from shifting even when the solder under the substrate melts and the solder under the chip remelts. [Means for solving the problem]

[0010] In order to solve the above-mentioned problems, the semiconductor device of the present invention is characterized in having a plurality of semiconductor chips, an insulating substrate, a circuit pattern formed on the front side of the insulating substrate, under-chip solder joining the semiconductor chip and the circuit pattern, a metal layer formed on the back side of the insulating substrate, a base member, under-substrate solder joining the base member and the metal layer, a plurality of wires connecting the semiconductor chips to each other or between the semiconductor chips and the circuit pattern, a first insulating resin bonding the plurality of wires connecting the semiconductor chips to each other or the plurality of wires connecting the semiconductor chips to the circuit pattern, and a sealing resin sealing at least the plurality of semiconductor chips, the plurality of wires, and the first insulating resin.

[0011] In addition, the manufacturing method of a semiconductor device of the present invention is a manufacturing method of a semiconductor device for manufacturing the above-mentioned semiconductor device, and is characterized by having a semiconductor chip bonding process in which under-chip solder is melted to bond a semiconductor chip and a circuit pattern, a wire bonding process after the semiconductor chip bonding process in which the multiple wires are bonded together with the first insulating resin, and a base member bonding process after the wire bonding process in which under-substrate solder is melted to bond the base member and the metal layer. Effect of the Invention

[0012] According to the present invention, even if the solder under the substrate melts and then the solder under the chip remelts, it is possible to prevent the semiconductor chip from becoming misaligned. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a top view of the semiconductor device of the first embodiment. [Diagram 2] Cross section AA of Figure 1. [Diagram 3] FIG. 4 is a cross-sectional view illustrating a state in which wires are bonded to each other in the semiconductor device of the first embodiment. [Figure 4] 3A to 3C are cross-sectional views illustrating the manufacturing method of the semiconductor device according to the first embodiment. [Diagram 5]3A to 3C are cross-sectional views illustrating the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] FIG. 11 is a top view of a semiconductor device according to a second embodiment. [Figure 7] Cross-sectional view taken along line AA in Figure 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing and each embodiment, the same or similar components are designated by the same reference numerals, and duplicated explanations will be omitted. EXAMPLES

[0015] Fig. 1 is a top view of the semiconductor device of Example 1. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. Note that in Fig. 1, some components such as a base member 10, a sealing resin 17, and a case 18 are omitted for the sake of convenience.

[0016] The semiconductor device 20 of this embodiment has a semiconductor chip 1, an insulating substrate 6, a circuit pattern 3, solder under the chip 7, a metal layer 8, a base member 10, solder under the substrate 9, wires 4, 5, insulating resins 11-16, a case 18, and a sealing resin 17.

[0017] The semiconductor chip 1 may be, for example, a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a diode, etc. In this embodiment, an example having a plurality of semiconductor chips 1 is shown.

[0018] The insulating substrate 6 may be a ceramic substrate made of, for example, AlN. A circuit pattern 3 is formed on the front side of the insulating substrate 6, and a metal layer 8 is formed on the rear side of the insulating substrate 6. The circuit pattern 3 and the metal layer 8 are made of, for example, copper. The circuit pattern 3 is made of a plurality of patterns. A semiconductor chip 1 is joined to the circuit pattern 3 via under-chip solder 7. The insulating substrate 6 is connected to a base member 10 by joining the metal layer 8 on the rear side to the base member 10 with under-board solder 9. The base member 10 functions as a heat dissipation member.

[0019] Case 18 accommodates at least semiconductor chip 1. Semiconductor chip 1 and other members inside case 18 are sealed with sealing resin 17 inside case 18. Sealing resin 17 may be a soft resin such as silicone gel, or a hard resin such as epoxy resin.

[0020] The wires 4 are inter-chip connection wires that connect the semiconductor chips 1 together, and a plurality of wires 4 are connected in parallel. The wires 4 are connected to the electrodes 2 on the front side of the semiconductor chip 1. The back side of the semiconductor chip 1 also has electrodes that are connected to the circuit pattern 3, but these are not shown in the figure.

[0021] The wires 5 are for connecting between the chip circuit patterns, connecting between the semiconductor chip 1 and the circuit pattern 3, and a plurality of wires 5 are connected in parallel. The wires 5 are connected to the electrodes 2 on the front side of the semiconductor chip 1 and the circuit pattern 3.

[0022] FIG. 3 is a cross-sectional view illustrating a state in which wires are bonded to each other in the semiconductor device of the first embodiment.

[0023] In this embodiment, the plurality of wires 4 are bonded together by insulating resin 15 for bonding the wires together. Similarly, the plurality of wires 5 are bonded together by insulating resin 16 for bonding the wires together.

[0024] This increases the rigidity of the multiple wires 4 and the multiple wires 5 compared to when the wires are not bonded together, thereby preventing the semiconductor chip 1 from shifting even if the solder 9 under the board melts and the solder 7 under the chip re-melts.

[0025] In this embodiment, the periphery of the semiconductor chip 1 is covered with insulating resin 13. Insulating resin 13 covers at least the outer periphery of the semiconductor chip 1 and the under-chip solder 7. It is also desirable for insulating resin 13 to cover the upper surface of the circuit pattern 3, for example, between the semiconductor chips 1. This insulating resin 13 can also prevent the semiconductor chip 1 from shifting even if the under-chip solder 7 is remelted.

[0026] Although any one of insulating resin 13, insulating resin 15, and insulating resin 16 alone can provide the effect of preventing semiconductor chip 1 from shifting, it is preferable to use two or more of them in combination, since the effect may be insufficient using only one of them.

[0027] In order to obtain the above-mentioned effects, at least one of insulating resin 13, insulating resin 15, and insulating resin 16 may be provided before under-substrate solder 9 is melted.

[0028] For example, with regard to insulating resin 15 and insulating resin 16, the manufacturing method of semiconductor device 20 of this embodiment may include a semiconductor chip bonding process in which under-chip solder 7 is melted to bond semiconductor chip 1 and circuit pattern 3, a wire bonding process subsequent to the semiconductor chip bonding process in which multiple wires 4, 5 are bonded together with insulating resins 15, 16, and a base member bonding process subsequent to the wire bonding process in which under-substrate solder 9 is melted to bond base member 10 and metal layer 8.

[0029] Similarly, with regard to the insulating resin 13, the manufacturing method of the semiconductor device 20 of this embodiment may include a semiconductor chip bonding process, a semiconductor chip outer periphery covering process for forming insulating resin 13 after the semiconductor chip bonding process, and a base member bonding process performed after the semiconductor chip outer periphery covering process.

[0030] The sealing step of sealing with the sealing resin 17 may be performed after the base member bonding step. As a result, the wires 4, 5 and the insulating resins 13, 15, and 16 are also sealed with the sealing resin 17.

[0031] In this embodiment, the periphery of the circuit pattern 3 is covered with insulating resin 11, and the spaces between the circuit patterns 3 are covered with insulating resin 12. Also, in this embodiment, the connection portions between the electrodes 2 on the upper surface of the semiconductor chip 1 and the wires 4 and 5 are covered with insulating resin 14. The insulating resins 11, 12, and 14 make it possible to suppress discharge.

[0032] For example, but not limited to, polyamide-imide resin can be used as the insulating resins 11 to 16. In this embodiment, an example is shown in which the insulating resins 11 to 16 are provided, but the present invention is not limited to this, and some of the insulating resins 11 to 16 may be omitted as necessary.

[0033] In this embodiment, the insulating resins 15 and 16 overlap at least a portion of the insulating resins 12 and 13. Therefore, the insulating resins 12 and 13 that cover at least one of the outer periphery of the semiconductor chip 1, the under-chip solder 7, the areas between the semiconductor chips 1, and the areas between the circuit patterns 3, and the insulating resins 15 and 16 may be formed together from the same insulating resin material. This makes it possible to shorten the application time and hardening time of the insulating resin compared to forming them separately.

[0034] 4 and 5 are cross-sectional views for explaining the manufacturing method of the semiconductor device of Example 1. Here, the wire 4 and the insulating resins 13 and 15 will be explained, but the same applies to the wire 5 and the insulating resins 12 and 16.

[0035] As shown in Fig. 4, in the wire bonding process, droplets 19 of insulating resin are dropped onto the wires 4 using, for example, a JET dispenser, and then cured, thereby bonding the wires 4 together with the insulating resin 15, and covering the wires with the insulating resin 13 in the regions that at least partially overlap with the insulating resin 15, as shown in Fig. 5. When a JET dispenser is used, the droplets 19 are smaller in size than the gaps between the wires 4.

[0036] Next, another problem that occurs when the solder 9 under the board is melted and the solder 7 under the chip is remelted, and a means for solving this problem will be described.

[0037] In the case of having insulating resin 13 covering the outer periphery of semiconductor chip 1 and under-chip solder 7, when under-substrate solder 9 melts and under-chip solder 7 remelts, the volume of under-chip solder 7 and voids in under-chip solder 7 expand, and part of under-chip solder 7 may erupt, for example, breaking through the interface between insulating resin 13 and other components or through insulating resin 13 itself. When part of under-chip solder 7 erupts, the amount of solder may decrease, causing poor bonding, or the erupted solder may splash onto areas that should be insulated, causing poor insulation.

[0038] Therefore, in the semiconductor device 20 of this embodiment, it is desirable that the strength of the insulating resin 13 that covers the periphery of the semiconductor chip 1 and the under-chip solder 7 is higher than the strength of the insulating resin 11 that covers the periphery of the circuit pattern 3, or the insulating resin 12 that covers the spaces between the circuit patterns 3. Methods for increasing the strength include, for example, making the film thickness of the insulating resin 13 larger than the film thickness of the insulating resin 11 or the insulating resin 12, or making the elastic modulus of the insulating resin 13 higher than the elastic modulus of the insulating resin 11 or the insulating resin 12. EXAMPLES

[0039] Fig. 6 is a top view of a semiconductor device according to Example 2. Fig. 7 is a cross-sectional view taken along line AA in Fig. 6.

[0040] In Example 2, the shape of the insulating resin 13 is different from that of Example 1. The insulating resin 13 in this example is formed in a shape that collectively surrounds a plurality of semiconductor chips 1 that are joined to the same circuit pattern 3 among the circuit patterns 3. As a result, some sides of the outer periphery of the semiconductor chip 1 and the under-chip solder 7 are exposed without being covered by the insulating resin 13. Note that the same circuit pattern 3 means that they are integrally connected, and are in an electrically connected state.

[0041] According to this embodiment, even if the solder 7 under the chip remelts and part of the solder 7 under the chip spurts out, the direction of the solder spurting out can be controlled to the exposed part not covered by the insulating resin 13. Furthermore, since the insulating resin 13 is formed in a shape that collectively surrounds a plurality of semiconductor chips 1 bonded to the same circuit pattern 3, even if the spurted solder splashes, it will not splash onto parts that should be insulated, thereby preventing poor insulation.

[0042] Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each embodiment may be combined and applied. [Explanation of symbols]

[0043] 1. Semiconductor chip 2 electrodes 3 Circuit Pattern 4 Wires (Chip to Chip) 5 Wire (between chip circuit patterns) 6 Insulating Substrate 7. Chip Underside Solder 8 metal layer 9 Under-board soldering 10 Base material 11 Insulating resin (circuit pattern periphery) 12 Insulating resin (between circuit patterns) 13 Insulating resin (around the chip) 14 Insulating resin (on chip) 15 Insulating resin (bonds wires together) 16 Insulating resin (bonds wires together) 17 Sealing resin 18 cases 19 droplets 20 Semiconductor Devices

Claims

1. A plurality of semiconductor chips; An insulating substrate; A circuit pattern formed on a front surface side of the insulating substrate; under-chip solder that joins the semiconductor chip and the circuit pattern; a metal layer formed on a back surface side of the insulating substrate; A base member; an under-substrate solder that joins the base member and the metal layer; a plurality of wires connecting the semiconductor chips to each other or connecting the semiconductor chips to the circuit pattern; a first insulating resin that bonds the plurality of wires that connect the semiconductor chips together or the plurality of wires that connect the semiconductor chip and the circuit pattern together; a sealing resin that seals at least the plurality of semiconductor chips, the plurality of wires, and the first insulating resin, said semiconductor device comprising:

2. In claim 1, A semiconductor device comprising: a second insulating resin made of the same material as the first insulating resin, formed in an area that at least partially overlaps with the first insulating resin and that covers at least one of the outer periphery of the semiconductor chip, the solder under the chip, the spaces between the semiconductor chips, and the spaces between the circuit patterns.

3. In claim 1, a third insulating resin that covers the outer periphery of the semiconductor chip and the solder under the chip; a fourth insulating resin that covers the outer periphery of the circuit pattern or the space between the circuit patterns; The semiconductor device according to claim 1, wherein the third insulating resin has a strength higher than that of the fourth insulating resin.

4. In claim 3, The semiconductor device according to claim 1, wherein the third insulating resin has a thickness greater than that of the fourth insulating resin.

5. In claim 3, The third insulating resin has a higher elastic modulus than the fourth insulating resin.

6. In claim 3, The semiconductor device is characterized in that the third insulating resin is formed in a shape that collectively surrounds a plurality of the semiconductor chips bonded to the same one of the circuit patterns.

7. In claim 1, The semiconductor device according to claim 1, wherein the first insulating resin is a polyamide-imide resin.

8. A method for manufacturing the semiconductor device according to claim 1, comprising the steps of: a semiconductor chip bonding step of melting the solder under the chip to bond the semiconductor chip and the circuit pattern; a wire bonding step of bonding the plurality of wires together with the first insulating resin after the semiconductor chip bonding step; a base member bonding step of melting the under-substrate solder to bond the base member and the metal layer after the wire bonding step.

9. A method for manufacturing the semiconductor device according to claim 2, comprising the steps of: A method for manufacturing a semiconductor device, comprising a wire bonding process in which droplets of insulating resin are dripped onto the wires and hardened, thereby bonding the wires together with the first insulating resin and covering them with the second insulating resin in areas that at least partially overlap with the first insulating resin.

10. A method for manufacturing the semiconductor device according to claim 3, comprising the steps of: a semiconductor chip bonding step of melting the solder under the chip to bond the semiconductor chip and the circuit pattern; a semiconductor chip outer periphery covering step of forming the third insulating resin after the semiconductor chip bonding step; a base member bonding step of melting the under-substrate solder to bond the base member and the metal layer after the semiconductor chip outer periphery covering step,

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