Semiconductor device

Abstract

To provide a semiconductor device whose electric characteristics and reliability are improved.SOLUTION: A semiconductor device is described. The device includes lower and upper channel layers on an active region on a substrate. The device further includes an intermediate insulating structure disposed between lower and upper channels. The device includes a gate structure surrounding the channel layers, and lower and upper source / drain regions disposed on the active region on at least one side of the gate structure. Between the lower and upper source / drain regions, a barrier structure exists. Each of the lower and upper source / drain regions can satisfy a lower recess region and an upper recess region. These recess regions are defined by the respective channel layer, gate structure, and barrier structure. Side surface inclinations inside the upper and lower recess regions can change and the respective side surface inclinations of the recess regions can be different from each other.SELECTED DRAWING: Figure 2b

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] There is a high demand for reducing the size of semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical objectives of the implementation of the present invention is to provide a semiconductor device having improved electrical characteristics and reliability. [Means for solving the problem]

[0004] In general, in some aspects, the subject matter of the present application relates to a semiconductor device comprising: an active region extending in a first direction on a substrate; an isolation film disposed on the substrate and defining the active region; lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; upper channel layers disposed on the lower channel layers and spaced apart from each other in the vertical direction; intermediate insulating structures disposed between a top lower channel layer of the lower channel layers and a bottom upper channel layer of the top channel layers; a gate structure extending in a second direction across the active region and surrounding the lower channel layer and the top channel layer, respectively; lower source / drain regions disposed on at least one side of the gate structure on the active region and each coupled to the lower channel layer; the upper source / drain region is vertically spaced from the lower source / drain region, the upper source / drain region being connected to the upper channel layer on at least one side of the structure, and a barrier structure disposed between the lower source / drain region and the upper source / drain region, wherein the lower source / drain region fills a lower recess region defined by a side surface of the lower channel layer, a side surface of the gate structure, and an upper surface of the active region, and the upper source / drain region fills an upper recess region defined by a side surface of the upper channel layer, a side surface of the gate structure, and a lower surface and a side surface of the barrier structure, and a slope of a side surface of the lower recess region and a slope of a side surface of the upper recess region may have opposite signs to each other.

[0005] In general, in some aspects, the subject matter of the present application is a semiconductor device comprising: an active region extending in a first direction on a substrate; an isolation film disposed on the substrate and defining the active region; lower channel layers spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate; upper channel layers disposed on the lower channel layers and spaced apart in the vertical direction; intermediate insulating structures disposed between a top lower channel layer of the lower channel layers and a bottom upper channel layer of the upper channel layers; lower gate structures intersecting the active region and surrounding the lower channel layers, extending in a second direction, and positioned below a lower surface of the intermediate insulating structures; upper gate structures surrounding the upper channel layers, extending in the second direction, and positioned above an upper surface of the intermediate insulating structures; and a barrier structure disposed between the lower source / drain region and the upper source / drain region, wherein a width of an upper portion of the lower source / drain region in the first direction is greater than a width of a lower portion of the barrier structure in the first direction, and the width of the lower gate structure in the first direction decreases toward an upper surface of the substrate, and the width of the upper gate structure in the first direction increases toward an upper surface of the substrate.

[0006] In general, in some aspects, the subject matter of the present application is directed to a semiconductor device including an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from one another in a vertical direction perpendicular to an upper surface of the substrate, gate structures extending in a second direction intersecting the active region and surrounding each of the plurality of channel layers, a lower source / drain region disposed on the active region on at least one side of the gate structure and coupled to a portion of the plurality of channel layers, an upper source / drain region coupled to a remaining portion of the plurality of channel layers on at least one side of the gate structure and spaced apart from the lower source / drain region in the vertical direction, and a barrier structure disposed between the lower source / drain region and the upper source / drain region, wherein the lower source / drain region may include a first lower sloped surface having a first slope and a second lower sloped surface having a second slope different from the first slope. Effect of the Invention

[0007] By including a first lower inclined surface that is inclined such that the width in the first direction increases as the lower source / drain region moves from the bottom to the top of the lower source / drain region, and a second lower inclined surface that has a different inclination from the first lower inclined surface, a cross section of the lower source / drain region in the x-direction has a trapezoidal shape, thereby providing a semiconductor device with improved electrical characteristics.

[0008] The various yet significant advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific implementations of the present invention. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view illustrating an example of a semiconductor device. [Figure 2a] 1 is a cross-sectional view of an example of a semiconductor device. [Figure 2b] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Diagram 3]1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 4] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Diagram 5] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 6] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 7] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 8] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 9] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 10] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 11] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 12] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 13] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 14] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 15] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 16a] 1 is a cross-sectional view of an example of a semiconductor device. [Figure 16b] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 17] 1 is a partially enlarged cross-sectional view of an example of a semiconductor device; [Figure 18] 1 is a partial cross-sectional view of an example of a semiconductor device. [Figure 19a] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19b] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19c] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19d] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19e] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19f] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19g] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 19h] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20a] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20b] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20c] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20d] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20e] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Fig. 20f] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20g] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20h] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20i] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 20j] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following, terms such as "top", "upper", "upper surface", "lower", "lower", "lower surface", "side" and the like are indicated by reference numerals and can be understood to be referred to with reference to the drawings unless otherwise specified.

[0011] FIG. 1 is a plan view showing a semiconductor device.

[0012] 2a is a cross-sectional view showing the semiconductor device, taken along lines II', II-II', and III-III' of the semiconductor device shown in FIG.

[0013] Fig. 2b is a partially enlarged cross-sectional view of the semiconductor device, Fig. 2b shows an enlarged view of region "A" of Fig. 2a.

[0014] For ease of explanation, only the main components of the semiconductor device are shown in FIGS. 1 to 2b.

[0015] 1 to 2b, the semiconductor device 100 may include a substrate 101, an active region 105 on the substrate 101, an isolation layer 110 defining the active region 105, a channel structure 140 including a plurality of channel layers 141A, 142A, 141B, and 142B vertically spaced apart from each other on the active region 105, a middle dielectric isolation structure (MDI) disposed between the lower channel layer 141A, 142A and the upper channel layer 141B, 142B, a gate structure 160 extending across the active region 105, a source / drain region 150 in contact with the plurality of channel layers 141A, 142A, 141B, and 142B, and a barrier structure 170 disposed between the lower source / drain region 150A and the upper source / drain region 150B.

[0016] The semiconductor device 100 may further include a contact structure 180 and an interlayer insulating layer 190. Although not shown for ease of explanation, the semiconductor device 100 may further include contact plugs connected to the lower source / drain regions 150A.

[0017] The substrate 101 may have a top surface extending in the x-direction and the y-direction. The substrate 101 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like.

[0018] The active region 105 may be defined by the isolation film 110 in the substrate 101 and may be disposed to extend in a first direction, for example, the x-direction. The active region 105 may have a structure protruding from the substrate 101. An upper end of the active region 105 may be disposed to protrude from an upper surface of the isolation film 110 at a predetermined height. The active region 105 may be formed of a part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. However, on both sides of the gate structure 160, the active region 105 on the substrate 101 may be partially recessed, and the source / drain region 150 may be disposed on the recessed active region 105. The active region 105 may include impurities or may include a doping region including impurities.

[0019] In the semiconductor device 100, the active region 105 has a fin structure, and the gate structure 160 may be disposed between the active region 105 and the channel structure 140, between the lower channel layer 140A and the upper channel layer 140B of the channel structure 140, and on the channel structure 140. As a result, the semiconductor device 100 may include a transistor having a multi-bridge channel FET (MBCFET™) structure, which is a gate-all-around type field effect transistor. According to an exemplary implementation, the semiconductor device may include a transistor having a complementary FET (CFET) structure. According to an exemplary implementation, the present invention may also be applied to a transistor having a three dimensional-stacked FET (3D-SFET) structure in which a plurality of transistors are vertically stacked.

[0020] As shown in FIG. 2a, the semiconductor device 100 according to the present embodiment may include a first transistor structure TR1 and a second transistor structure TR2 stacked on an active region 105. Each of the first and second transistor structures TR1 and TR2 employed in the present embodiment may be a so-called MBCFET™ (Multi Bridge Channel FET) including a gate structure 160 surrounding lower channel layers 141A and 142A and upper channel layers 141B and 142B disposed on the active region 105. The first transistor structure TR1 may be one of an N-type MOSFET and a P-type MOSFET, and the second transistor structure TR2 may be the other of a P-type MOSFET and an N-type MOSFET. In some implementations, the first and second transistor structures TR1 and TR2 may be P-type MOSFET and N-type MOSFET, respectively.

[0021] The isolation layer 110 may define an active region 105 in the substrate 101. The isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. Depending on the implementation, the isolation layer 110 may further include a region that has a step at the bottom of the substrate 101 and extends deeper. The isolation layer 110 may partially expose the top of the active region 105. Depending on the implementation, the isolation layer 110 may have a curved top surface that has a higher level adjacent to the active region 105. The isolation layer 110 may be made of an insulating material. The isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0022] In this implementation, the first and second transistor structures TR1, TR2 can be configured to share one gate structure 160.

[0023] Specifically, the first transistor structure TR1 may include lower channel layers 141A, 142A stacked on the active region 105, a gate electrode 165 surrounding the lower channel layers 141A, 142A, a lower source / drain region 150A connected to the lower channel layers 141A, 142A on one side of the gate electrode 165, and a gate dielectric layer 162 between the lower channel layers 141A, 142A and the gate electrode 165.

[0024] Similarly, the second transistor structure TR2 may include upper channel layers 141B, 142B, a gate electrode 165 surrounding the upper channel layers 141B, 142B, upper source / drain regions 150B connected to the upper channel layers 141B, 142B on both sides of the gate electrode 165, and a gate dielectric layer 162 between the upper channel layers 141B, 142B and the gate electrode 165.

[0025] The channel structure 140 may include two or more channel layers 141A, 142A, 141B, 142B arranged on the active region 105 in a direction perpendicular to the upper surface of the active region 105, for example, in the z-direction, spaced apart from each other, for example, a lower channel structure 140A including lower channel layers 141A, 142A and an upper channel structure 140B including upper channel layers 141B, 142B. The channel layers 141A, 142A, 141B, 142B may be connected to the source / drain regions 150 and spaced apart from the upper surface of the active region 105. The upper channel layers 141B, 142B may be arranged on intermediate insulating structures MDI, respectively, and spaced apart from each other in the Z-direction.

[0026] The multiple channel layers 141A, 142A, 141B, 142B may have the same or similar width as the active region 105 in the y direction. According to an exemplary implementation, the multiple channel layers 141A, 142A, 141B, 142B may have a decreasing width along the y direction as they move away from the top surface of the substrate 101 in the y direction. The multiple channel layers 141A, 142A, 141B, 142B may increase and decrease in width along the x direction as they move closer to the top surface of the substrate 101 in the x direction. For example, the width along the x direction of the upper channel layers 141B, 142B may increase as they move closer to the top surface of the substrate 101, and the width along the x direction of the lower channel layers 141A, 142A may decrease as they move closer to the top surface of the substrate 101. This may be due to the shape of the lower recess region RCB and the upper recess region RCU.

[0027] The channel layers 141A, 142A, 141B, and 142B may be made of a semiconductor material, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel layers 141A, 142A, 141B, and 142B may be made of the same material as the substrate 101. The channel layers 141A, 142A, 141B, and 142B may be disposed vertically spaced apart from each other on the active region 105. The number and shape of the channel layers 141A, 142A, 141B, and 142B constituting one channel structure 140 may be variously changed depending on the implementation form.

[0028] The intermediate insulating structure MDI may be disposed between the uppermost lower channel layer 142A of the lower channel layers 141A and 142A and the lowermost upper channel layer 141B of the upper channel layers 141B and 142B. The intermediate insulating structure MDI may include an intermediate insulating pattern 300. The intermediate insulating pattern 300 may include an insulating material, such as an oxide, a nitride, or an oxynitride. The intermediate insulating structure MDI may separate the lower channel layers 141A and 142A from the upper channel layers 141B and 142B. The intermediate insulating structure MDI may include a protrusion 300P protruding toward the barrier structure 170. In this specification, the "protrusion 300P" may also be referred to as a "middle portion 300P". The protrusion 300P may have, but is not limited to, a tip shape. According to another implementation, the protrusion 300P may have a rounded shape toward the barrier structure 170.

[0029] The gate structure 160 may cross the active region 105 to surround the lower channel layers 141A, 142A and the upper channel layers 141B, 142B, respectively, and extend in the second direction y. The lower gate structure 160A may cross the active region 105 to surround the lower channel layers 141A, 142A, respectively, and extend in the second direction y, and be located below the lower surface of the intermediate insulating structure MDI. The upper gate structure 160B may cross the upper channel layers 141B, 142B, respectively, and extend in the second direction y, and be located above the upper surface of the intermediate insulating structure MDI. In this embodiment, as described above, the first and second transistor structures TR1, TR2 may share one gate structure 160. The gate electrode 165 employed in this embodiment may be provided as a common gate electrode surrounding the plurality of channel layers 141A, 142A, 141B, 142B. The gate dielectric layer 162 may be provided between the lower channel layer 141A, 142A and the gate electrode 165 as well as between the upper channel layer 141B, 142B and the gate electrode 165. The gate dielectric layer 162 may surround the intermediate insulating pattern 300 in a second direction (e.g., Y direction). The gate structure 160 may further include a gate spacer layer 164. The gate spacer layer 164 may be disposed on both side walls of an electrode portion of the gate electrode 165 extending in the second direction (e.g., Y direction) on the uppermost upper channel layer 141B, 142B. A gate capping layer 166 may be formed on the gate spacer layer 164 and the gate electrode 165.

[0030] The gate electrode 165 employed in this embodiment may include a conductive material. For example, the gate electrode 165 may include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. The gate electrode 165 may include a semiconductor material such as doped polysilicon. Each of the common gate electrodes 165 may be composed of two or more multilayers. Although not shown, in another embodiment, an inter-gate insulating layer may be further included that separates the upper gate structure 160B and the lower gate structure 160A at substantially the same level as the intermediate insulating structure MDI. At least a portion of the inter-gate insulating layer may be disposed to overlap the intermediate insulating structure MDI in the horizontal direction. The gate electrode 165 of the upper gate structure 160B and the gate electrode 165 of the lower gate structure 160A may include different conductive materials due to the inter-gate insulating layer. The gate electrode 165 of the upper gate structure 160B and the gate electrode 165 of the lower gate structure 160A may be made of a material having an appropriate work function in consideration of a desired threshold voltage. Similarly, the gate dielectric layer 162 of the upper gate structure 160B and the gate dielectric layer 162 of the lower gate structure 160A may include different dielectric layers or a combination thereof.

[0031] For example, the gate dielectric layer 162 may include an oxide, a nitride, or a high-k material. The high-k material refers to a dielectric material having a higher dielectric constant than silicon dioxide (SiO2), and the high-k material may be, for example, any one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3).

[0032] For example, the gate spacer layer 164 can include at least one of a silicon oxide, a silicon nitride, and a silicon oxynitride. In some implementations, the gate spacer layer 164 can include a multi-layer structure. The gate capping layer 166 can include, for example, a silicon nitride, a silicon oxynitride, a silicon carbonitride, or a silicon oxycarbonitride.

[0033] According to an exemplary implementation, the slope of the side of the lower source / drain region 150A and the slope of the side of the upper source / drain region 150B may have slopes of opposite signs to each other. For example, the first lower inclined surface 150A1 and the second lower inclined surface 150A2 may have a positive slope and a negative slope, respectively, and the first upper inclined surface 150B1 and the second upper inclined surface 150B2 may have a negative slope and a positive slope, respectively. As a result, the width of the lower gate structure 160A in the first direction x decreases as it approaches the top surface of the substrate 101, and the width of the upper gate structure 160B in the first direction x decreases as it moves away from the top surface of the substrate 101.

[0034] The lower source / drain region 150A may be disposed on the active region 105 on at least one side of the gate structure 160 and connected to the side surfaces of the lower channel layers 141A and 142A. The lower source / drain region 150A may be provided as a source region or a drain region of a first (lower) transistor structure TR1. The lower source / drain region 150A may include epitaxial layers grown on the surfaces of the recessed portions of the active region 105 and both side surfaces of the lower channel layers 141A and 142A. Similarly, the upper source / drain region 150B may be connected to the side surfaces of the upper channel layers 141B and 142B on at least one side of the gate structure 160 and may be vertically separated from the lower source / drain region 150A. The upper source / drain region 150B may be provided as a source region or a drain region of a second (upper) transistor structure TR2. The upper source / drain regions 150B may include epitaxial layers grown using both side surfaces of the upper channel layers 141B and 142B as seed layers.

[0035] The lower and upper source / drain regions 150A, 150B may include a semiconductor epitaxial layer such as silicon (Si). The lower and upper source / drain regions 150A, 150B may include different types and / or concentrations of impurities. For example, if the first transistor structure TR1 is a P-type MOSFET, the upper source / drain region 150A may include p-type doped silicon germanium (SiGe), and if the second transistor structure TR2 is an N-type MOSFET, the upper source / drain region 150B may include n-type doped silicon (Si). Thus, the cross sections of the lower and upper source / drain regions 150A, 150B along the second direction (e.g., Y direction) may have different shapes. For example, the cross sections of the lower and upper source / drain regions 150A, 150B may have a circular, elliptical, pentagonal, hexagonal, or similar shape. According to an exemplary implementation, the lower source / drain region 150A is formed between the gate spacer layer 164 and the first barrier pattern 171, so that the cross-section of the lower source / drain region 150A along the Y direction can be a trapezoidal shape whose width increases as it approaches the top surface of the substrate 101.

[0036] The lower source / drain region 150A may fill a lower recess region RCB defined by side surfaces of the lower channel layers 141A and 142A, a side surface of the gate structure 160, and an upper surface of the active region 105. The upper source / drain region 150B may fill an upper recess region RCU defined by side surfaces of the upper channel layers 141B and 142B, a side surface of the gate structure 160, and a lower surface and a side surface of the barrier structure 170. For example, the middle portion 300P may be a portion where a side surface of the lower recess region RCB and a side surface of the upper recess region RCU are in contact with each other. The middle portion 300P may be a portion where a side surface of the lower source / drain region 150A and a side surface of the upper source / drain region 150B are extended and in contact with each other. The middle portion 300P may be a switching portion where the sign of the slope of the side surface of the lower recess region RCB and the slope of the side surface of the upper recess region RCU are changed. According to an exemplary implementation, the slope of the side of the lower recess region RCB and the slope of the side of the upper recess region RCU may have slopes of opposite signs to each other. Specifically, the middle portion 300P may be a portion where the slope of the side of the lower recess region RCB switches to a positive slope or a negative slope, and the slope of the side of the upper recess region RCU switches to a negative slope or a positive slope. The level of the middle portion 300P may be substantially the same as or lower than the level 300UL of the upper surface of the intermediate insulating structure MDI and substantially the same as or higher than the level 300BL of the lower surface of the intermediate insulating structure MDI. The level of the middle portion 300P may be substantially the same as or higher than the level of the top surface of the lower gate structure 160A located below the lower surface of the intermediate insulating structure MDI and substantially the same as or lower than the level of the bottom surface of the upper gate structure 160B located above the upper surface of the intermediate insulating structure MDI. The level 150BL of the bottom end of the upper source / drain region 150B may be lower than the level 300UL of the top surface of the intermediate insulating structure MDI. The level 150AL of the top end of the lower source / drain region 150A may be located at a level substantially equal to or higher than the level 300BL of the lower surface of the intermediate insulating structure MDI. The top of the lower source / drain region 150A may horizontally overlap the intermediate insulating structure MDI.

[0037] According to an exemplary implementation, the lower source / drain region 150A may include a first lower inclined surface 150A1 inclined so that the width in the first direction x increases from the top to the bottom of the lower source / drain region 150A, and a second lower inclined surface 150A2 having a different inclination from the first lower inclined surface 150A1. The upper source / drain region 150B may include a first upper inclined surface 150B1 inclined so that the width in the first direction x decreases from the top to the bottom of the upper source / drain region 150B, and a second upper inclined surface 150B2 inclined in a different direction from the first upper inclined surface 150B1. As a result, the cross sections of the lower and upper source / drain regions 150A and 150B in the x direction may be trapezoidal (the longer base side of the trapezoid is closer to the substrate than the shorter base side of the trapezoid) and inverted trapezoidal (the longer base side of the trapezoid is farther from the substrate than the shorter base side of the trapezoid).

[0038] The barrier structure 170 may be disposed between the lower source / drain region 150A and the upper source / drain region 150B. The barrier structure 170 may vertically overlap the lower source / drain region 150A and the upper source / drain region 150B. The upper surface of the barrier structure 170 may have a downward convex shape, but is not limited thereto. Although the lower surface of the barrier structure 170 is illustrated as having a flat shape as in FIG. 2a, this is not limited thereto. According to other implementations, the lower surface of the barrier structure 170 may have an upward convex shape or a downward convex shape. The barrier structure 170 may include a first barrier pattern 171 formed along the lower and lower surfaces of the side of the upper recess region RCU, and a second barrier pattern 172 on the first barrier pattern 171. The first and second barrier patterns 171 and 172 may include an insulating material, for example, an oxide, a nitride, or an oxynitride. The first and second barrier patterns 171 and 172 may include, but are not limited to, different materials from each other. The barrier structure 170 may separate the lower source / drain region 150A and the upper source / drain region 150B from each other in the vertical direction Z.

[0039] The contact structure 180 may contact the source / drain region 150 through at least a portion of the interlayer insulating layer 190, and may apply an electrical signal to the source / drain region 150. The contact structure 180 may contact an upper portion of the upper source / drain region 150B. Although not shown for convenience of explanation, the contact plug connected to the lower source / drain region 150A may further include a horizontal contact portion extending in a horizontal direction (e.g., Y direction) with respect to the upper surface of the substrate 101, and a vertical contact portion connected to the horizontal contact portion and extending in a direction perpendicular to the upper surface of the substrate 101 (e.g., Z direction). The horizontal contact portion may be disposed on the upper surface of the lower source / drain region 150A, and the vertical contact portion may be disposed to penetrate the interlayer insulating layer 190. The contact plug may include substantially the same material as the contact structure 180. However, the contact plug is not limited to the above structure and may be formed in various forms. For example, the contact plug may have a structure similar to a backside contact structure 210 of a semiconductor device 100p in FIG. 18, which will be described later.

[0040] The contact structure 180 may be disposed on the source / drain region 150 and may be disposed to have a length longer along the y direction than the source / drain region 150 depending on the implementation. The contact structure 180 may have, but is not limited to, a sloping side such that the width at the bottom is narrower than the width at the top due to an aspect ratio. The contact structure 180 may be disposed to recess the source / drain region 150 to a predetermined depth.

[0041] The contact structure 180 may include a first metal-semiconductor compound layer 182 located at a lower end, a barrier layer 184 disposed along a sidewall, and a plug conductive layer 186. The first metal-semiconductor compound layer 182 may be, for example, a metal silicide layer. The barrier layer 184 may include a metal nitride, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The plug conductive layer 186 may include a metal material, such as, for example, aluminum (Al), tungsten (W), or molybdenum (Mo). In an exemplary implementation, the contact structure 180 may be disposed to penetrate at least a portion of the source / drain region 150. In an exemplary implementation, the number and arrangement of conductive layers constituting the contact structure 180 may be variously changed. In addition, a wiring structure, such as a contact structure, may be further disposed on the gate electrode 165, and a wiring structure connected to the contact structure 180 may be further disposed on the contact structure 180.

[0042] The interlayer insulating layer 190 may be disposed to cover the source / drain regions 150, the gate structures 160, and the device isolation film 110. The interlayer insulating layer 190 may include, for example, at least one of an oxide, a nitride, an oxynitride, and a low-k dielectric.

[0043] 3 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0044] 3, in the semiconductor device 100a, the lower source / drain region 150A may include a lower source / drain protrusion region 150AP protruding toward the lower gate structure 160A by recessing a portion of the active region 105, and the upper source / drain region 150B may include an upper source / drain protrusion region 150BP protruding toward the upper gate structure 160B. The upper source / drain protrusion region 150BP may be formed by forming an upper recess region RCU in the process of FIG. 19c described below, and then further forming an upper recess region RCU in the horizontal direction through a wet etching process, and forming the upper source / drain region 150B in the upper recess region RCU. The lower source / drain protrusion region 150AP may be formed by forming a lower recess region RCB, and then further forming a lower recess region RCB in the horizontal direction through a wet etching process, and forming the lower source / drain region 150A in the lower recess region RCB. Forming the lower source / drain protrusion region 150AP and the upper source / drain protrusion region 150BP can be independent of each other.

[0045] 4 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0046] 4, in the semiconductor device 100b, the intermediate insulating structure MDI may include a plurality of intermediate insulating patterns 300 and a semiconductor pattern 140S between the plurality of intermediate insulating patterns 300. The semiconductor pattern 140S may include silicon (Si) or silicon germanium (SiGe). The semiconductor pattern 140S may have an etching selectivity with respect to the lower sacrificial layer 120A, the intermediate sacrificial layer 120B, and the upper sacrificial layer 120C of the plurality of channel layers 141A, 142A, 141B, and 142B. The semiconductor pattern 140S may remain when the intermediate sacrificial layer 120B is removed in the process of FIG. 19b described below. Thus, the semiconductor pattern 140S may be disposed between the intermediate insulating patterns 300.

[0047] 5 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0048] Referring to FIG. 5, the intermediate insulating structure MDI in the semiconductor device 100c may include a first air gap AG1. The first air gap AG1 may vertically overlap the lower gate structure 160A and the upper gate structure 160B. The first air gap AG1 may be formed in a region corresponding to the semiconductor pattern 140S in FIG. 19a. According to an exemplary implementation, the semiconductor pattern 140S is not replaced with the intermediate insulating pattern 300, and the first air gap AG1 may be formed by selectively removing the semiconductor pattern 140S in a subsequent process. The first air gap AG1 may include air or a gas composed of a material used in the manufacturing process of the semiconductor device 100c. This may also be applied to other implementations.

[0049] 6 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0050] 6, the semiconductor device 100d may include a second air gap AG2 in the semiconductor device 100c of FIG. 5. For example, the barrier structure 170 may not include the first barrier pattern 171 and the second barrier pattern 172, but may include the second air gap AG2. The second air gap AG2 may vertically overlap the lower source / drain region 150A and the upper source / drain region 150B. The second air gap AG2 may be formed by selectively removing the first barrier pattern 171 and the second barrier pattern 172 through the first air gap AG1 in addition to the manufacturing process of the semiconductor device 100b of FIG. 5. Thus, the first air gap AG1 and the second air gap AG2 may be connected to each other. The second air gap AG2 may include air or a gas composed of a material used in the manufacturing process of the semiconductor device 100d. This may also be applied to other implementations.

[0051] 7 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0052] 7, in the semiconductor device 100e, the second barrier pattern 172 may cover the upper surface of the lower source / drain region 150A. In the process of performing the process of FIG. 19f described below, the process of the first barrier pattern 171 covering the upper surface of the lower source / drain region 150A may be omitted, and the second barrier pattern 172 may be formed to contact the upper surface of the lower source / drain region 150A. Thus, the first barrier pattern 171 may be disposed on a side of the second barrier pattern 172.

[0053] 8 is a partial enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0054] 8, the semiconductor device 100f may further include an inner spacer layer 130 disposed on both sides of the gate structure 160 along the first direction x on the lower surface of each of the plurality of channel layers 141A, 142A, 141B, 142B and the lower surface of the intermediate insulating structure MDI in the implementation of FIG. 2a. According to an exemplary implementation, the inner spacer layer 130 may contact at least one of the lower source / drain region 150A and the upper source / drain region 150B. The inner spacer layer 130 may be disposed alongside the gate electrode 165 between the plurality of channel layers 141A, 142A, 141B, 142B. The inner spacer layer 130 may contact the gate dielectric layer 162. The inner spacer layer 130 may be disposed between the gate structure 160 and the source / drain region 150. The side of the inner spacer layer 130 may contact the source / drain region 150. The gate electrode 165 may be separated and electrically isolated from the source / drain region 150 by the inner spacer layer 130. The inner spacer layer 130 may have a convex shape in which a side surface facing the gate electrode 165 is rounded inward toward the gate electrode 165. The inner spacer layer 130 may be made of an oxide, a nitride, or an oxynitride, and in particular may be made of a low dielectric constant film.

[0055] The inner spacer layer 130 can be formed of, but is not limited to, the same material as the gate spacer layer 164. For example, the inner spacer layer 130 can include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN. The inner spacer layer 130 can also be applied to other implementations.

[0056] 9 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0057] 9, in the semiconductor device 100g, the shape of the lower source / drain region 150A may be symmetrical to the shape of the intermediate insulating structure MDI and the upper source / drain region 150B with respect to a plane CL where the barrier structure 170 and the lower source / drain region 150A meet. According to an exemplary implementation, the upper recess region RCU and the lower recess region RCB may be symmetrical based on the plane CL where the barrier structure 170 and the lower source / drain region 150A meet. This may be due to, but is not limited to, forming the thickness of the top channel layer 142B of the upper channel layers 141B, 142B thicker than the thickness of the upper channel layer 141B excluding the lower channel layers 141A, 142A and the top channel layer 142B.

[0058] 10 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0059] Referring to FIG. 10, in the semiconductor device 100h, the barrier structure 170 may be formed in a structure in which the first barrier pattern 171 surrounds the second barrier pattern 172. The first barrier pattern 171 may surround the upper surface, lower surface, and side surface of the second barrier pattern 172. The first barrier pattern 171 may be disposed between the upper surface of the second barrier pattern 172 and the lower surface of the upper source / drain region 150B. The first barrier pattern 171 may be formed on the second barrier pattern 172 before forming the upper source / drain region 150A of FIG. 19g, which will be described later, but is not limited thereto. After forming the upper source / drain region 150A, if there is a space between the second barrier pattern 172 and the upper source / drain region 150A, the first barrier pattern 171 may be formed to fill the space. The structure of the barrier structure 170 as described above may be applied to other implementation forms.

[0060] 11 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0061] 11, the semiconductor device 100i may further include a third air gap AG3 between the second barrier pattern 172 and the first barrier pattern 171. If the second barrier pattern 172 is formed to have a downward convex shape, the third air gap AG3 may be formed if the first barrier pattern 171 cannot completely fill the space between the second barrier pattern 172 and the upper source / drain region 150B. The third air gap AG3 may include air or a gas made of a material used in the manufacturing process of the semiconductor device 100i. This may be applied to other implementations.

[0062] 12 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0063] 12, the semiconductor device 100j does not include the second barrier pattern 172, but may include a third air gap AG3 surrounded by the first barrier pattern 171. The third air gap AG3 surrounded by the first barrier pattern 171 may be formed by removing the second barrier pattern 172 and forming the first barrier pattern 171. The first barrier pattern 171 and the third air gap AG3 may electrically insulate the upper source / drain region 150B from the lower source / drain region 150A.

[0064] 13 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0065] 13, the semiconductor device 100k may have a different shape of the barrier structure 170 from the semiconductor device 100h of FIG. 10. The upper surface of the barrier structure 170 may be convex upward toward the upper source / drain region 150B, and the lower surface of the barrier structure 170 may be convex downward toward the lower source / drain region 150A. However, the shapes are not limited to this. According to another implementation, the upper surface of the barrier structure 170, i.e., the upper surface of the first barrier pattern 171, may have a wavy shape, and the lower surface of the barrier structure 170, i.e., the lower surface of the first barrier pattern 171, may also have a wavy shape. This may be due to the shapes of the upper surface of the lower source / drain region 150A and the lower surface of the upper source / drain region 150B.

[0066] 14 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0067] 14, the semiconductor device 100l may further include a third air gap AG3 between an upper surface of the second barrier pattern 172 and a lower surface of the upper source / drain region 150B. The description of the shape of the first barrier pattern 171 in FIG. 13 may be similarly applied to the shape of the first barrier pattern 171. In the implementation of FIG. 14, the description of the third air gap AG3 may be substantially the same as the description of the third air gap AG3 in FIG.

[0068] 15 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to FIG.

[0069] 15, the semiconductor device 100m does not include a second barrier pattern 172, but may include a third air gap AG3 surrounded by a first barrier pattern 171. The description of the shape of the first barrier pattern 171 in FIG. 13 may be similarly applied to the shape of the first barrier pattern 171. In the implementation form of FIG. 15, substantially the same description as the third air gap AG3 in FIG. 12 may be applied to the third air gap AG3.

[0070] Fig. 16a is a cross-sectional view of the semiconductor device. Fig. 16b is a partially enlarged cross-sectional view of the semiconductor device. Fig. 16a shows a region corresponding to Fig. 2a, and Fig. 16b shows an enlarged view of region "B" of Fig. 16a.

[0071] 16a and 16b, the cross section of the lower source / drain region 150A in the x direction in the semiconductor device 100n may have an inverted trapezoid (i.e., the shorter base of the trapezoid is closer to the substrate than the longer base of the trapezoid). According to an exemplary implementation, the upper width of the lower source / drain region 150A in the x direction may be larger than the lower width. In order to further form a recess region in the horizontal direction (e.g., the x direction and the y direction) in the process of forming the lower source / drain region 150A, the width of the upper part of the lower source / drain region 150A in the x direction may be larger than the lower width of the barrier structure 170 in the x direction. In order to further form a recess region in the horizontal direction, the cross section of the lower source / drain region 150A in the y direction on the active region 105 may have a hexagonal or pentagonal shape. A bend may be formed at a portion where the upper surface of the lower source / drain region 150A and the side of the barrier structure 170 are connected.

[0072] According to an exemplary implementation, the width of the lower gate structure 160A along the x-direction may gradually increase toward the upper surface of the substrate 101. The width of the lower channel layers 141A, 142A along the x-direction may gradually increase toward the upper surface of the substrate 101. The width of the second lower channel layer 142A, which is the uppermost channel layer of the lower channel layers 141A, 142A along the x-direction may be substantially equal to or smaller than the width of the first upper channel layer 141B, which is the lowermost channel layer of the upper channel layers 141B, 142B along the x-direction. In the process of forming the lower source / drain region 150A, the length of the lower channel layers 141A, 142A may be adjusted by further forming a recess region in the horizontal direction, thereby improving the process of forming the epitaxial layer.

[0073] Fig. 17 is a partially enlarged cross-sectional view of a semiconductor device according to an exemplary implementation, showing the area corresponding to Fig. 16b.

[0074] 17, in the semiconductor device 100n of FIG. 16b, when a recess region is further formed in a horizontal direction (e.g., in the x-direction and y-direction) to form the lower source / drain region 150A, the lower source / drain region 150A may include a lower source / drain protrusion region 150AP. According to an exemplary implementation, in the process of FIG. 19c described below, the lower source / drain protrusion region 150AP may be formed by forming the lower recess region RCB, further forming the lower recess region RCB in the horizontal direction through a wet etching process, and forming the lower source / drain region 150A in the lower recess region RCB. The upper source / drain protrusion region 150BP may be formed by forming the upper recess region RCU in the process of FIG. 19c described below, further forming the upper recess region RCU in the horizontal direction through a wet etching process, and forming the upper source / drain region 150B in the upper recess region RCU. 17 shows the upper source / drain protrusion region 150BP also formed, it is possible to form only the lower source / drain protrusion region 150AP or to form only the upper source / drain protrusion region 150BP. The formation of the lower source / drain protrusion region 150AP and the upper source / drain protrusion region 150BP can be independent of each other.

[0075] Figure 18 shows a partial cross-sectional view of a semiconductor device, showing the area corresponding to Figure 2a.

[0076] 18, the semiconductor device 100p of FIG. 18 may further include, in addition to the configuration of the semiconductor device 100 of FIG. 2a, a wiring structure including a via VA and a metal wiring ML, a bottom dielectric isolation structure (BDI), a backside contact structure 210, a backside power structure 195, and a bottom insulating layer 196.

[0077] The via VA may penetrate the first upper insulating layer 192. The via VA may be connected to the contact structure 180. The via VA may be made of a conductive material.

[0078] The metal wiring ML may constitute a back end of line (BEOL) together with the via VA. The metal wiring ML and the via VA may be provided as a wiring section for signal transmission. According to an exemplary implementation, a signal network may be configured by connecting the metal wiring ML and the via VA to an element region (e.g., a source / drain region 150 and a gate electrode 165) through a contact structure 180. The via VA and the metal wiring ML may also be applied to the semiconductor device 100 of FIG. 2a, but are omitted for convenience of explanation.

[0079] The lower insulating structure BDI may be disposed between a bottom surface of the lower gate structure 160A and an upper surface of the active region 105. The lower insulating structure BDI may include, but is not limited to, substantially the same material as the middle insulating structure MDI.

[0080] The backside contact structure 210 may be connected to the lower source / drain region 150A by penetrating the substrate 101 below the lower source / drain region 150A. The backside contact structure 210 may extend vertically through the substrate 101. A side surface of the backside contact structure 210 and a side surface of the substrate 101 may contact each other. The backside contact structure 210 may be a self-aligned contact (SAC) aligned by the lower insulating structure BDI. This may ensure a contact margin between the backside contact structure 210 and the lower source / drain region 150A. The backside contact structure 210 may be disposed to recess a portion of a lower region of the lower source / drain region 150A and contact the recessed lower surface of the lower source / drain region 150A.

[0081] The backside contact structure 210 may include a liner layer 214, a second metal-semiconductor compound layer 212, and a conductive layer 216. Although not shown, the backside contact structure 210 may further include an insulating liner for insulation from the substrate 101. The liner layer 214 may form an outer surface of the backside contact structure 210 and may form a part of an upper surface of the backside contact structure 210. However, the extension range of the liner layer 214 may be variously changed depending on the implementation. The liner layer 214 may include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0082] The second metal-semiconductor compound layer 212 may be located at the top of the backside contact structure 210 and may form at least a portion of the top surface of the backside contact structure 210. The second metal-semiconductor compound layer 212 may be located at a surface where the backside contact structure 210 contacts the source / drain region 150. However, in implementations, the scope of the second metal-semiconductor compound layer 212 is not limited to that shown in the drawings. The second metal-semiconductor compound layer 212 may be, for example, a metal silicide layer. The conductive layer 216 may be disposed to fill the contact hole surrounded by the liner layer 214 and the second metal-semiconductor compound layer 212. The conductive layer 216 may include, for example, a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). In exemplary implementations, the number and arrangement of the conductive layers constituting the backside contact structure 210 may be variously changed. In some implementations, the liner layer 214 and / or the second metal-semiconductor compound layer 212 may be omitted.

[0083] The backside power structure 195 may be coupled to a lower end or a lower surface of the backside contact structure 210. The backside power structure 195 may form a backside power delivery network (BSPDN) for applying a power or ground voltage together with the backside contact structure 210, and may also be referred to as a rear power rail or a buried power rail. For example, the backside power structure 195 may be a buried wiring line extending in one direction, for example, in the Y direction, from below the backside contact structure 210, but the form of the backside power structure 195 is not limited thereto. For example, in some implementations, the backside power structure 195 may include a via region and / or a line region. The backside power structure 195 may include at least one of a conductive material, for example, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo).

[0084] A lower insulating layer 196 can be disposed over the substrate 101. The lower insulating layer 196 can include at least one of an oxide, a nitride, and an oxynitride, and can include, for example, a low-k material. Depending on the implementation, the lower insulating layer 196 can include multiple insulating layers.

[0085] Figures 19a to 19h are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device. Figures 19a to 19h explain an embodiment of the method for manufacturing the semiconductor device 100 of Figures 1 to 2b, and show cross sections corresponding to Figure 2a.

[0086] Referring to FIG. 19a, a sacrificial layer 120, lower channel layers 141A, 142A, semiconductor pattern 140S, and upper channel layers 141B, 142B are alternately stacked on a substrate 101 to form an active structure, and then a sacrificial gate structure 200 can be formed in a second direction y to intersect with the active structure.

[0087] The sacrificial layer 120 may include a lower sacrificial layer 120A, a middle sacrificial layer 120B, and an upper sacrificial layer 120C. The lower sacrificial layer 120A and the upper sacrificial layer 120C may be layers that are changed into a gate dielectric layer 162 and a gate electrode 165 as shown in Fig. 2a through a subsequent process. The middle sacrificial layer 120B and the semiconductor pattern 140S may be layers that are changed into an intermediate insulating structure MDI as shown in Fig. 2a through a subsequent process.

[0088] The sacrificial layer 120 may be made of a material having etch selectivity to the lower channel layers 141A, 142A, the semiconductor patterns 140S, and the upper channel layers 141B, 142B. The lower channel layers 141A, 142A, the semiconductor patterns 140S, and the upper channel layers 141B, 142B may include a material different from the sacrificial layer 120. According to an exemplary implementation, the lower channel layers 141A, 142A, the semiconductor patterns 140S, and the upper channel layers 141B, 142B may include, but are not limited to, silicon (Si), and the sacrificial layer 120 may include silicon germanium (SiGe).

[0089] The sacrificial layer 120, the lower channel layers 141A, 142A, and the upper channel layers 141B, 142B may be formed by performing an epitaxial growth process using the substrate 101 as a seed. Each of the sacrificial layer 120, the lower channel layers 141A, 142A, the semiconductor pattern 140S, and the upper channel layers 141B, 142B may have a thickness in the range of about 1 Å to 100 nm. The number of layers of the lower channel layers 141A, 142A, the semiconductor pattern 140S, and the upper channel layers 141B, 142B alternately stacked with the sacrificial layer 120 may be variously changed depending on the implementation form.

[0090] Next, the sacrificial layer 120, the lower channel layers 141A, 142A, the semiconductor pattern 140S, the upper channel layers 141B, 142B, and a portion of the substrate 101 may be removed to form an active structure, and a sacrificial gate structure 200 may be formed on the active structure.

[0091] The active structure may include a sacrificial layer 120, lower channel layers 141A, 142A, a semiconductor pattern 140S, and upper channel layers 141B, 142B, which are alternately stacked with each other, and may further include an active region 105 formed by removing a portion of the substrate 101 and protruding from the upper surface of the substrate 101. The active structures may be formed in the form of lines extending in one direction, for example, the x direction, and may be spaced apart from each other in the y direction.

[0092] In the region where the portion of the substrate 101 is removed, an insulating material may be filled and then recessed so that the active region 105 protrudes, thereby forming an isolation film 110. The top surface of the isolation film 110 may be formed lower than the top surface of the active region 105.

[0093] The sacrificial gate structure 200 may be a sacrificial structure formed in a region where the gate dielectric layer 162 and the gate electrode 165 are disposed on the upper portion of the channel structure 140 as shown in FIG. 2a through a subsequent process. The sacrificial gate structure 200 may include first and second sacrificial gate layers 202 and 205, which are sequentially stacked, and a mask pattern layer 206. The first and second sacrificial gate layers 202 and 205 may be patterned using the mask pattern layer 206. The first and second sacrificial gate layers 202 and 205 may be an insulating layer and a conductive layer, respectively. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon nitride. The sacrificial gate structure 200 may have a line shape extending in one direction crossing the active structure. For example, the sacrificial gate structures 200 may extend in the y direction and be spaced apart from each other in the x direction.

[0094] Referring to FIG. 19b, an intermediate insulating structure MDI may be formed, and a gate spacer layer 164 may be formed to cover the top and side surfaces of the sacrificial gate structure 200 and the active structure.

[0095] The intermediate sacrificial layer 120B and the semiconductor pattern 140S may be selectively removed because they have etching selectivity with respect to the lower sacrificial layer 120A, the upper sacrificial layer 120C, the lower channel layers 141A and 142A, and the upper channel layers 141B and 142B. The intermediate insulating structure MDI may be formed by filling the intermediate insulating pattern 300 in the area from which the intermediate sacrificial layer 120B and the semiconductor pattern 140S have been removed. The intermediate insulating pattern 300 may include, for example, an oxide or a nitride. In another implementation, the semiconductor pattern 140S may not be removed. In yet another implementation, the semiconductor pattern 140S may have etching selectivity with respect to the intermediate sacrificial layer 120B. The first air gap AG1 of the semiconductor device 100c of FIG. 5 may be formed by removing the intermediate sacrificial layer 120B, filling the intermediate insulating pattern 300 in the area from which the intermediate sacrificial layer 120B has been removed, and then removing the semiconductor pattern 140S.

[0096] The gate spacer layer 164 may be formed to cover both sidewalls and an upper surface of the sacrificial gate structure 200. The gate spacer layer 164 may be formed to a uniform thickness along the upper surface and side surfaces of the sacrificial gate structure 200 and the active structure. The gate spacer layer 164 may cover an upper surface of the device isolation film 110. The gate spacer layer 164 may be made of a low dielectric constant material, and may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0097] Referring to FIG. 19c, a portion of the gate spacer layer 164, the upper channel layers 141B and 142B, the upper sacrificial layer 120C, and a portion of the intermediate insulating structure MDI may be removed to form a first barrier pattern 171.

[0098] A portion of the gate spacer layer 164 may be removed by anisotropic etching, thereby removing the gate spacer layer 164 present on the top surface of the isolation film 110, the top surface of the sacrificial gate structure 200, and the top surface of the active structure. The gate spacer layer 164 present on the side surface of the active structure may also be partially removed to reduce its thickness.

[0099] Between the sacrificial gate structures 200, the exposed upper sacrificial layer 120C, the upper channel layers 141B, 142B, and portions of the intermediate insulating structure MDI may be removed to form upper recess regions RCU.

[0100] The upper recess region RCU may have an inclined side surface since the width of the upper recess region RCU is narrowed along the first direction x. The upper recess region RCU may penetrate at least a portion of the intermediate insulating structure MDI. The level of the lower end of the upper recess region RCU may be substantially the same as or lower than the level of a surface where the intermediate insulating structure MDI and the upper sacrificial layer 120C contact each other, and may be substantially the same as or higher than the level of a surface where the intermediate insulating structure MDI and the lower sacrificial layer 120A contact each other. According to another implementation, in order to manufacture the semiconductor device 100a of FIG. 3, after forming the upper recess region RCU, the upper recess region RCU may be further formed in a horizontal direction through a wet etching process.

[0101] A first barrier pattern 171 may be formed to cover the sacrificial gate structure 200, the gate spacer layer 164, the active structure, and the upper recess region RCU. The first barrier pattern 171 may be formed as a film with a uniform thickness along the upper and side surfaces of the sacrificial gate structure 200, the upper and side surfaces of the gate spacer layer 164, the upper and side surfaces of the active structure, the side and lower surfaces of the upper recess region RCU, and the upper surface of the device isolation film 110. The first barrier pattern 171 may be formed along a surface of the intermediate insulating structure MDI exposed by the upper recess region RCU. The first barrier pattern 171 may include an oxide or a nitride.

[0102] Referring to FIG. 19d, the first barrier pattern 171 may be partially removed, and the lower channel layers 141A and 142A, the lower sacrificial layer 120A, and the intermediate insulating structure MDI may be partially removed to form a lower recess region RCB.

[0103] The first barrier pattern 171 exposed between the sacrificial gate structures 200 can be partially removed through an anisotropic etching process, and the lower channel layers 141A, 142A, the lower sacrificial layer 120A, and portions of the intermediate insulating structure MDI can be removed to form a lower recess region RCB.

[0104] The lower recess region RCB may have a side surface such that the width in the first direction x gradually increases as the lower recess region RCB approaches the upper surface of the substrate 101. The lower recess region RCB may be, but is not limited to, a portion of the upper portion of the active region 105. The upper recess region RCU may have a width gradually decreasing in the first direction x as the upper surface of the substrate 101 is approached. The lower recess region RCB may have a width increasing or decreasing in the first direction x as the upper surface of the substrate 101 is approached. A portion where the side surface of the lower recess region RCB and the side surface of the upper recess region RCU contact each other may be defined as an intermediate portion 300P. The intermediate portion 300P may be a portion where the slope of the side surface of the lower recess region RCB changes to a positive slope or a negative slope, and the slope of the side surface of the upper recess region RCU changes to a negative slope or a positive slope. According to another embodiment, in order to manufacture the semiconductor device 100a of FIG. 3, after forming the lower recess region RCB, a lower recess region RCB can be further formed in the horizontal direction through a wet etching process.

[0105] Referring to FIG. 19e, an epitaxial layer may be formed in lower recess region RCB to form lower source / drain regions 150A.

[0106] The lower source / drain region 150A may be formed by epitaxial growth and may extend to contact the lower channel layers 141A, 142A and the lower sacrificial layer 120A in the lower recess region RCB. The upper surface of the lower source / drain region 150A may have a downward convex shape, but is not limited thereto. The lower source / drain region 150A may contain impurities by in-situ doping. The level 150AL (see FIG. 2b) of the upper end of the lower source / drain region 150A may be higher than the level of the surface where the intermediate insulating structure MDI and the lower sacrificial layer 120A contact each other. The upper surface of the lower source / drain region 150A may be formed flat or convex upward depending on the type of impurity. This may change the shape of the lower surface of the intermediate insulating structure MDI formed in a subsequent process.

[0107] Referring to FIG. 19f, a first barrier pattern 171 and a second barrier pattern 172 may be formed to form an intermediate insulating structure MDI.

[0108] A first barrier pattern 171 may be formed to cover an upper surface of the lower source / drain region 150A. A second barrier pattern 172 may be formed to fill a portion of the upper recess region RCU. The second barrier pattern 172 may have an upper surface that is convex downward. The first barrier pattern 171 exposed on the sidewall of the upper recess region RCU and the gate structure 160 may be removed to form an intermediate insulating structure MDI. The second barrier pattern 172 may protect the first barrier pattern 171. During the process of removing the first barrier pattern 171, the first barrier pattern 171 on the device isolation film 110 may also be removed.

[0109] Referring to FIG. 19g, upper source / drain regions 150B may be formed on the intermediate insulating structure MDI to fill the upper recessed region RCU.

[0110] The upper source / drain region 150B may be formed by epitaxial growth and may extend to contact the upper channel layer 141B, 142B and the upper sacrificial layer 120C in the upper recess region RCU. The upper surface of the upper source / drain region 150B may have an upward convex shape, and the lower surface of the upper source / drain region 150B may have a downward convex shape, but is not limited thereto. The upper source / drain region 150B may contain impurities by in-situ doping.

[0111] Referring to FIG. 19h, the interlayer insulating layer 190 may be formed, and the sacrificial gate structure 200, the upper sacrificial layer 120C, and the lower sacrificial layer 120A may be removed.

[0112] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 200 and the source / drain regions 150 and performing a planarization process.

[0113] The sacrificial gate structure 200, the upper sacrificial layer 120C, and the lower sacrificial layer 120A may be selectively removed with respect to the gate spacer layer 164, the interlayer insulating layer 190, the lower channel layers 141A and 142A, the upper channel layers 141B and 142B, and the intermediate insulating structure MDI. First, the sacrificial gate structure 200 is removed to form the upper gap region UR, and then the lower sacrificial layer 120A and the upper sacrificial layer 120C exposed through the upper gap region UR may be removed to form the lower gap region LR. For example, if the lower sacrificial layer 120A and the upper sacrificial layer 120C contain silicon germanium (SiGe) and the lower channel layers 141A, 142A and the upper channel layers 141B, 142B contain silicon (Si), the lower sacrificial layer 120A and the upper sacrificial layer 120C can be selectively removed by performing a wet etching process using peracetic acid and / or a solution used in an SC1 (Standard clean-1) cleaning process (NH4OH:H2O2:H2O=1:1:5) as an etchant.

[0114] 2a, a gate dielectric layer 162 and a gate electrode 165 may be formed in the upper gap region UR and the lower gap region LR. A gate capping layer 166 may be formed in the upper gap region UR. Also, by forming a contact structure 180, the semiconductor device 100 shown in FIGS. 1 to 2b may be manufactured.

[0115] 20a to 20j are schematic cross-sectional views for explaining a method for manufacturing a semiconductor device according to an exemplary implementation. FIG. 20a to 20j explain an implementation of a manufacturing method for manufacturing the semiconductor device 100p of FIG. 18, and show cross sections corresponding to FIG. 18.

[0116] Referring to FIG. 20a, a sacrificial barrier layer 120D is formed on a substrate 101, and similar to the process of FIG. 19a, a sacrificial layer 120, lower channel layers 141A, 142A, semiconductor patterns 140S, and upper channel layers 141B, 142B are alternately stacked to form an active structure, and then a sacrificial gate structure 200 can be formed in a second direction y to intersect with the active structure.

[0117] The sacrificial barrier layer 120D may be made of a material having an etching selectivity with respect to the sacrificial layer 120, the lower channel layers 141A and 142A, the semiconductor pattern 140S, and the upper channel layers 141B and 142B. The sacrificial barrier layer 120D may include silicon (Si) or silicon germanium (SiGe). When the sacrificial barrier layer 120D includes silicon germanium (SiGe), the sacrificial barrier layer 120D may have an etching selectivity due to a difference in concentration of germanium (Ge) from the sacrificial layer 120. The sacrificial barrier layer 120D may be replaced with a lower insulating structure BDI through a subsequent process.

[0118] Substantially the same steps as in Figure 19a can then be performed.

[0119] Referring to FIG. 20b, a middle insulating structure MDI and a lower insulating structure BDI may be formed, and a gate spacer layer 164 may be formed.

[0120] After selectively removing the intermediate sacrificial layer 120B and the semiconductor pattern 140S, the intermediate insulating structure MDI may be formed by filling the intermediate insulating pattern 300. The sacrificial barrier layer 120D may be selectively removed and the lower insulating structure BDI may be formed by filling the removed area with the lower insulating pattern 310. However, the process is not limited to the above, and the intermediate insulating structure MDI and the lower insulating structure BDI may be formed simultaneously by simultaneously removing the sacrificial barrier layer 120D, the intermediate sacrificial layer 120B, and the semiconductor pattern 140S and filling the area with an insulating material. According to another implementation, the intermediate insulating structure MDI and the lower insulating structure BDI may be formed in the process of forming the gate structure 160. Next, the gate spacer layer 164 may be formed by performing substantially the same process as that of FIG. 19b.

[0121] Next, substantially the same steps as in Figures 19c and 19d can be performed.

[0122] Referring to FIG. 20c, the lower insulating structure BDI and the active region 105 may be partially removed to form a dummy recess region DRC.

[0123] The etching process may be used to remove a portion of the lower insulating structure BDI and the upper portion of the active region 105 to form a dummy recess region DRC. The dummy recess region DRC may have a shape that narrows toward the upper surface of the substrate 101, but is not limited thereto.

[0124] Referring to FIG. 20d, a sacrificial epitaxial layer 150S may be formed to fill the dummy recessed region DRC, and lower source / drain regions 150A may be formed to fill the lower recessed region RCB.

[0125] The sacrificial epitaxial layer 150S may be formed on the active region 105 between the gate spacer layers 164. The sacrificial epitaxial layer 150S may be formed by filling the dummy recess regions DRC with a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In one implementation, the sacrificial epitaxial layer 150S may include silicon germanium (SiGe).

[0126] Next, the lower source / drain regions 150A can be formed by performing substantially the same steps as in FIG. 19e.

[0127] Referring to FIG. 20e, an intermediate insulating structure MDI can be formed by performing substantially the same steps as in FIG. 19f.

[0128] Referring to FIG. 20f, by performing substantially the same process as in FIG. 19g, the upper source / drain regions 150B can be formed to fill the upper recess regions RCU.

[0129] 20g, by performing substantially the same process as in FIG. 19h, the interlayer insulating layer 190 can be formed, and the sacrificial gate structure 200, the upper sacrificial layer 120C, and the lower sacrificial layer 120A can be removed, thereby forming the upper gap region UR and the lower gap region LR.

[0130] Referring to FIG. 20h, a gate structure 160 may be formed in the upper and lower gap regions UR and LR.

[0131] The gate dielectric layer 162 may be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 may be formed to fill the upper gap region UR and the lower gap region LR. The gate electrode 165 and the gate spacer layer 164 may be removed from the top to a predetermined depth in the upper gap region UR. A gate capping layer 166 may be formed in the region in the upper gap region UR from which the gate electrode 165 and the gate spacer layer 164 have been removed. As a result, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166 may be formed.

[0132] Referring to FIG. 20i, contact structures 180, vias VA, and metal lines ML may be formed.

[0133] A contact hole connected to the source / drain region 150 may be formed in the interlayer insulating layer 190, and a barrier layer 184 and a plug conductive layer 186 may be sequentially formed to fill the contact hole. In particular, a material forming the barrier layer 184 may be deposited in the contact hole, and then a silicide process may be performed to form a first metal-semiconductor compound layer 182 such as a silicide layer at the bottom. Then, a planarization process such as CMP may be performed so that the top surface of the contact structure 180 and the top surface of the interlayer insulating layer 190 may be substantially coplanar.

[0134] A first upper insulating layer 192 may be formed to cover the contact structure 180 and the gate structure 160, and a via VA may be formed through the first upper insulating layer 192 to be connected to the contact structure 180. A second upper insulating layer 193 may be formed to cover the first upper insulating layer 192 and the via VA, and the second upper insulating layer 193 may be patterned and filled with a conductive material to form a metal wiring ML. The metal wiring ML is not limited to the above-mentioned process, and may also be formed by a subtractive process.

[0135] Referring to FIG. 20j, the entire structure formed with reference to FIGS. 20a to 20i may be attached to a carrier substrate SUB, and a backside contact hole BCH may be formed.

[0136] A carrier substrate SUB may be attached onto the second upper insulating layer 193 or the metal wiring ML for performing processes on the underside of the substrate 101 in Fig. 20i. In Fig. 20j, for ease of understanding, the entire structure is shown rotated or inverted in a manner that is a mirror image of the structure shown in Fig. 20i.

[0137] The sacrificial epitaxial layer 150S may be selectively removed after penetrating the substrate 101 to expose the sacrificial epitaxial layer 150S. After removing the sacrificial epitaxial layer 150S, a backside contact hole BCH may be formed to penetrate a portion of the lower source / drain region 150A, but is not limited to this.

[0138] According to another implementation, after removing the substrate 101 from the top surface of the substrate 101 and forming an insulating layer, a backside contact hole BCH can be formed through the insulating layer.

[0139] A backside contact structure 210 may be formed to fill the backside contact hole BCH. The second metal-semiconductor compound layer 212 may be formed by performing a metal-semiconductor process, such as a silicide process, using the lower source / drain region 150A exposed by the backside contact hole BCH. A liner layer 214 may be formed on the side of the backside contact hole BCH, and a conductive layer 216 may be formed to fill the inside of the backside contact hole BCH, to form the backside contact structure 210.

[0140] Next, and with further reference to FIG. 18, the backside power structure 195 may be formed.

[0141] After forming the lower insulating layer 196, a part of the lower insulating layer 196 may be removed to form the backside power structure 195, and the carrier substrate SUB may be removed. In this manner, the semiconductor device 100h of Fig. 18 may be manufactured. The semiconductor device 100h may be packaged with the backside power structure 195 located at the top, but is not limited thereto.

[0142] Although the present disclosure includes many specific implementation details, these should not be construed as limiting the scope of the claims. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any suitable subcombination. Furthermore, even if a feature may be described above as operating in a combination, or even initially claimed as such, in some cases one or more features from the combination may be cut out, and the combination may be directed to a subcombination or a variation of the subcombination.

[0143] The present invention is not limited by the above-described implementation form and the accompanying drawings, but is limited by the scope of the accompanying claims. Therefore, within the scope of the claims, various substitutions, modifications, and changes are possible by a person having ordinary knowledge in the art, and these also belong to the scope of the present invention. [Explanation of symbols]

[0144] 101 Substrate 105 Active region 110 Element isolation film TR1 First transistor TR2 Second transistor 120 Sacrificial layer 141A, 142A Lower channel layer 141B, 142B Upper channel layer 150A lower source / drain region 150B Top source / drain region 160 Gate structure 162 Gate dielectric layer 164 Gate spacer layer 165 Gate electrode 166 Gate capping layer 170 Barrier structure 180 contact structure 190 interlayer insulating layer 191, 192 First and second upper insulating layers 195 Backside Power Structure 196 Lower Insulation Layer 210 Backside contact structure MDI Intermediate insulation structure BDI Lower insulation structure RCB Lower recess area RCU Upper recess area DRC Dummy Recess Area BCH Backside Contact Hole

Claims

1. an active region extending in a first direction on a substrate; an isolation film disposed on the substrate and defining the active region; vertically spaced apart lower channel layers perpendicular to an upper surface of the substrate; an upper channel layer disposed on the lower channel layer and spaced apart from each other in the vertical direction; an intermediate insulating structure disposed between the uppermost lower channel layer of the lower channel layers and the lowermost upper channel layer of the upper channel layers; a gate structure extending in a second direction, intersecting the active region and surrounding each of the lower channel layers and each of the upper channel layers; a lower source / drain region disposed on at least one side of the gate structure and over the active region, the lower source / drain region being coupled to the lower channel layer; upper source / drain regions each connected to the upper channel layer on at least one side of the gate structure and vertically spaced apart from the lower source / drain region; a barrier structure disposed between the lower source / drain region and the upper source / drain region; the lower source / drain region fills a lower recess region defined by a side of the lower channel layer, a side of the gate structure, and a top surface of the active region; the upper source / drain region fills an upper recess region defined by a side of the upper channel layer, a side of the gate structure, and a bottom surface and a side of the barrier structure; a side surface of the lower recess region and a side surface of the upper recess region having opposite signs to each other;

2. a middle portion where a side surface of the lower recess region and a side surface of the upper recess region are in contact with each other, 2. The semiconductor device according to claim 1, wherein the intermediate portion is a portion where the inclination of the side surface of the lower recess region changes to a positive inclination or a negative inclination, and the inclination of the side surface of the upper recess region changes to a negative inclination or a positive inclination.

3. The semiconductor device according to claim 2 , wherein the level of the intermediate portion is the same as or lower than the level of the upper surface of the intermediate insulating structure and the same as or higher than the level of the lower surface of the intermediate insulating structure.

4. 3. The semiconductor device according to claim 2, wherein the intermediate portion is a portion where a side surface of the lower source / drain region and a side surface of the upper source / drain region are extended and contact each other.

5. 3. The semiconductor device of claim 2, wherein the level of the intermediate portion is the same as or higher than the level of a top surface of the gate structure located below the lower surface of the intermediate insulating structure, and is the same as or lower than the level of a bottom surface of the gate structure located above the upper surface of the intermediate insulating structure.

6. 2. The semiconductor device of claim 1, further comprising an inner spacer layer in contact with at least one of the lower source / drain region and the upper source / drain region and disposed on both sides of the gate structure along the first direction.

7. a thickness of a top channel layer among the upper channel layers is greater than a thickness of each of the lower channel layers and is also greater than a thickness of each of the upper channel layers excluding the top channel layer; 2 . The semiconductor device of claim 1 , wherein the lower recess region is symmetrical to the upper recess region with respect to a surface where the barrier structure and the lower source / drain region contact each other.

8. a lower insulating structure disposed between a bottom surface of the gate structure and a top surface of the active region; 2. The semiconductor device of claim 1, further comprising a backside contact structure below the lower source / drain region, passing through a portion of the lower source / drain region and the lower insulating structure and connected to the lower source / drain region.

9. 2. The semiconductor device of claim 1, wherein the level of the bottom step of the upper source / drain region is lower than the level of the top surface of the intermediate insulating structure.

10. The semiconductor device of claim 1 , wherein an upper portion of said lower source / drain region horizontally overlaps said intermediate insulating structure.

11. an active region extending in a first direction on a substrate; an isolation film disposed on the substrate and defining the active region; vertically spaced apart lower channel layers perpendicular to an upper surface of the substrate; an upper channel layer disposed on the lower channel layer and spaced apart from each other in the vertical direction; an intermediate insulating structure disposed between a top lower channel layer of the lower channel layers and a bottom upper channel layer of the upper channel layers; a lower gate structure extending in a second direction across the active region and surrounding the lower channel layer, the lower gate structure being located below a lower surface of the intermediate insulating structure; upper gate structures each surrounding the upper channel layer, extending in the second direction and positioned above an upper surface of the intermediate insulating structure; a lower source / drain region disposed on at least one side of the lower gate structure and over the active region, the lower source / drain region being coupled to each of the lower channel layers; upper source / drain regions each connected to the upper channel layer on at least one side of the upper gate structure and vertically spaced apart from the lower source / drain region; a barrier structure disposed between the lower source / drain region and the upper source / drain region; a width of an upper portion of the lower source / drain region in the first direction is greater than a width of a lower portion of the barrier structure in the first direction; the lower gate structure has a width along the first direction that decreases toward an upper surface of the substrate, The upper gate structure has a width in the first direction that increases toward an upper surface of the substrate.

12. the lower channel layer has a width along the first direction that decreases toward the upper surface of the substrate; The semiconductor device according to claim 11 , wherein the upper channel layer has a width along the first direction that increases toward the top surface of the substrate.

13. The semiconductor device of claim 11 , wherein the intermediate insulating structure includes a plurality of intermediate insulating patterns and a semiconductor pattern between the plurality of intermediate insulating patterns.

14. the intermediate insulating structure includes a first air gap; The semiconductor device of claim 11 , wherein the first air gap vertically overlaps the lower gate structure and the upper gate structure.

15. the barrier structure includes a second air gap; the second air gap vertically overlaps the lower source / drain region and the upper source / drain region; The semiconductor device according to claim 14 , wherein the first air gap and the second air gap are connected to each other.

16. the lower source / drain region includes a lower source / drain protrusion region recessed into a portion of the active region and protruding toward the lower gate structure; The semiconductor device of claim 11 , wherein the upper source / drain regions include upper source / drain protrusion regions protruding toward the upper gate structure.

17. a cross section of the upper source / drain region along the first direction has an inverted trapezoidal shape, The semiconductor device according to claim 11 , wherein a cross section of said lower source / drain region along said first direction is trapezoidal.

18. The barrier structure comprises: a first barrier pattern formed along a top surface of the lower source / drain region, a bottom surface of the upper source / drain region, and a side surface of the intermediate insulating structure; The semiconductor device according to claim 11 , comprising at least one of a second barrier pattern or a third air gap surrounded by the first barrier pattern.

19. an active region extending in a first direction on a substrate; a plurality of channel layers spaced apart from one another in a vertical direction perpendicular to a top surface of the substrate; gate structures extending in a second direction, intersecting the active region and surrounding each of the plurality of channel layers; a lower source / drain region disposed on at least one side of the gate structure and over the active region, the lower source / drain region being connected to a portion of the plurality of channel layers; an upper source / drain region connected to a remaining portion of the plurality of channel layers on at least one side of the gate structure and vertically spaced apart from the lower source / drain region; a barrier structure disposed between the lower source / drain region and the upper source / drain region; The lower source / drain region includes a first lower sloped surface having a first slope and a second lower sloped surface having a second slope different from the first slope of the first lower sloped surface.

20. 20. The semiconductor device of claim 19, wherein the upper source / drain region includes a first upper inclined surface that is inclined such that a width in the first direction decreases from a top to a bottom of the upper source / drain region, and a second upper inclined surface in which a width in the first direction decreases at a different rate than the first upper inclined surface from a top to a bottom of the upper source / drain region.

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