Semiconductor device

Abstract

To provide a semiconductor device whose electric characteristics and reliability are improved.SOLUTION: A semiconductor device 100 includes a substrate 101, an active region 105 on the substrate, a first active pattern with a first width, a second active pattern with a second width that is smaller than the first width, a switch active pattern connecting between the first active pattern and the second active pattern, a plurality of sets of channel layers 140 surrounded by respective gate structures 160 on the active region, first and second source / drain regions 150A, 150B, and a transformation source / drain region 150T. Each of the source / drain regions is disposed on the active region and includes a first epitaxial layer 151 and a second epitaxial layer 152. The first epitaxial layer of the transformation source / drain region includes a first side wall with a first transformation side wall thickness Tt1 in an X direction, and a second side wall with a second transformation side wall thickness Tt2, which is smaller than the first transformation side wall thickness, in the X direction.SELECTED DRAWING: Figure 2a

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] As demands for semiconductor devices to have higher performance, higher speed, and / or more functionality increase, the integration degree of the semiconductor devices is increasing. In response to the trend toward higher integration of semiconductor devices, it is required to realize patterns having fine widths or fine separation distances when manufacturing semiconductor devices with fine patterns. In addition, efforts are being made to develop semiconductor devices including FinFETs having channels with three-dimensional structures in order to overcome limitations in operational characteristics caused by size reduction of planar metal oxide semiconductor FETs (MOSFETs). Summary of the Invention [Problem to be solved by the invention]

[0003] One of the technical objects to be achieved by the present invention is to provide a semiconductor device with improved reliability. [Means for solving the problem]

[0004] A semiconductor device according to an exemplary embodiment includes a substrate, an active region on the substrate, the active region including a first active pattern extending in a first direction (first horizontal direction) on the substrate, the first active pattern having a first width in a second direction (second horizontal direction) perpendicular to the first direction at a first height in a third vertical direction on a lower surface of the substrate, a second active pattern extending in the first direction and having a second width in the second direction at the first height that is smaller than the first width, and a switching active pattern extending in the first direction and connecting the first active pattern and the second active pattern. a gate structure extending in the second direction across the active region on the substrate; a plurality of sets of channel layers extending in the first direction and disposed continuously from the active region, spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, the sets including a channel layer surrounded by each gate structure on the active region; and source / drain regions disposed on sides of the gate structures and including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a switching source / drain region disposed on the switching active pattern, the active regions being symmetrical in the second direction with respect to a central axis of the active region extending in the first direction, each of the source / drain regions being disposed on the active region, a first epitaxial layer disposed on the first set and the second set of the plurality of set channel layers and extending, and a second epitaxial layer disposed on the first epitaxial layer, At a second height above a bottom surface of the substrate, a first sidewall thickness along the first direction of the first epitaxial layer of the first source / drain region may be greater than a second sidewall thickness along the first direction of the first epitaxial layer of the second source / drain region, and at the second height, the first epitaxial layer of the conversion source / drain region may have a first sidewall having a first conversion sidewall thickness in the first direction and a second sidewall having a second conversion sidewall thickness in the first direction that is smaller than the first conversion sidewall thickness.

[0005] A semiconductor device according to an exemplary embodiment includes a substrate, an active region including a first active pattern extending in a first direction on the substrate, the first active pattern having a first height in a vertical direction on a lower surface of the substrate and a first width in a second direction, a second active pattern having a second width in the second direction different from the first width, and a switching active pattern connecting the first active pattern and the second active pattern, a gate structure including respective gate structures intersecting the active region on the substrate and extending in the second direction, and source / drain regions disposed on sides of the gate structure, the source / drain regions including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a conversion source / drain region disposed on the switching active pattern, each of the source / drain regions being disposed on the active region and having a recess. a first epitaxial layer having a curved top surface and a second epitaxial layer disposed on the first epitaxial layer, wherein at a second height above a bottom surface of the substrate in the vertical direction, a first sidewall thickness of the first epitaxial layer of the first source / drain region along the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source / drain region along the first direction, at the second height, thicknesses of opposing sidewalls of the first epitaxial layer of the transition source / drain region along the first direction are different from each other, and a vertical level of a bottom end of the second epitaxial layer of the first source / drain region, a vertical level of a bottom end of the second epitaxial layer of the second source / drain region, and a vertical level of a bottom end of the second epitaxial layer of the transition source / drain region may be different from each other.

[0006] A semiconductor device according to an exemplary embodiment includes a substrate, an active region including a first active pattern extending in a first direction on the substrate and having a first width in a second direction intersecting the first direction, a second active pattern having a second width in the second direction smaller than the first width, and a switching active pattern connecting the first active pattern and the second active pattern, a gate structure extending in the second direction intersecting the active region on the substrate, a plurality of sets of channel layers extending in the first direction and continuously disposed from the active region, spaced apart from each other in a third direction perpendicular to an upper surface of the substrate, each set including a channel layer surrounded by each gate structure on the active region, each of the plurality of sets of channel layers being arranged spaced apart from each other in the first direction and disposed between the gate structures adjacent to each other in the first direction, a first source / drain region disposed on the first active pattern, the second active pattern, and a gate structure extending in the second direction intersecting the active region. and a source / drain region including a second source / drain region disposed on the switching active pattern, and a conversion source / drain region disposed on the switching active pattern, each of the source / drain regions being disposed on the active region and including a first epitaxial layer disposed between adjacent sets of channel layers and a second epitaxial layer disposed on the first epitaxial layer, at a first vertical height above a bottom surface of the substrate, the conversion source / drain region has a first conversion sidewall thickness along the first direction of the first epitaxial layer of the conversion source / drain region and a second conversion sidewall thickness smaller than the first conversion sidewall thickness, and a vertical level of a bottom end of the second epitaxial layer of the conversion source / drain region is higher than a vertical level of a bottom end of the second epitaxial layer of the first source / drain region and lower than a vertical level of a bottom end of the second epitaxial layer of the second source / drain region. Effect of the Invention

[0007] A switching source / drain region is disposed on a switching active pattern connecting first and second active patterns having different widths, and the sidewalls of the first epitaxial layer of the switching source / drain region have different thicknesses, and the symmetrical structure of the active region prevents contact between the second epitaxial layer and the gate structure, thereby providing a semiconductor device with improved electrical characteristics and reliability.

[0008] The various and beneficial advantages and effects of the present invention are not limited to the above-mentioned contents, but will be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0009] [Figure 1] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment; [Figure 2a] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 2b] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 2c] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Diagram 3] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment; [Figure 4] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment; [Diagram 5] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment. [Figure 6a] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment; [Figure 6b] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 7a] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment; [Figure 7b] 1 is a cross-sectional view illustrating a semiconductor device according to an exemplary embodiment. [Figure 8] 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment; [Figure 9a]2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 9b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 9c] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 10a] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 10b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 10c] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 11a] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 11b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 12a] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 12b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 13a] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 13b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 14a] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 14b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 15a]2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 15b] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 15c] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; [Figure 16] 2 is a diagram illustrating a process sequence for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. In the following, terms such as "top", "upper", "upper surface", "lower", "lower surface", "side" and the like may be understood to refer to the drawings unless otherwise indicated by drawing reference numbers.

[0011] FIG. 1 is a plan view illustrating a semiconductor device according to an exemplary embodiment. As used herein, a semiconductor device can refer to, for example, a semiconductor chip (e.g., a memory chip and / or logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a package-on-package device including multiple packages. Such devices can be formed using ball grid arrays, wire bonding, through-substrate vias, or other electrical interconnects, and can include memory devices, such as volatile or non-volatile memory devices. The semiconductor package can include a package substrate, one or more semiconductor chips, and an encapsulant formed on the package substrate and covering the semiconductor chips. The semiconductor device disclosed in various embodiments herein can include a gate-all-around transistor, also described as a gate-all-around or nanosheet transistor including a nanosheet channel region.

[0012] 2a to 2c are cross-sectional views showing a semiconductor device according to an exemplary embodiment. Fig. 2a shows a cross section of the semiconductor device of Fig. 1 cut along the cutting line I-I', Fig. 2b shows a cross section of the semiconductor device of Fig. 1 cut along the cutting lines II1-II1', II2-II2', and II3-II3', and Fig. 2c shows a cross section of the semiconductor device of Fig. 1 cut along the cutting lines III1-III1', III2-III2', and III3-III3'. For convenience of explanation, Fig. 1 shows only some components of the semiconductor device.

[0013] 1 to 2c, the semiconductor device 100 may include a substrate 101, an active region 105 including a first active pattern 105A, a second active pattern 105B, and a switching active pattern 105T, a gate structure 160 extending across the active region 105 and including a gate electrode 165, a channel structure 140 including first to fourth channel layers 141, 142, 143, and 144 arranged vertically spaced apart from each other on the active region 105, a source / drain region 150 in contact with the channel structure 140, and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 may further include an isolation layer 110, a gate dielectric layer 162, a gate spacer layer 164, a gate capping layer 166, and an interlayer insulating layer 190.

[0014] In the semiconductor device 100, the active region 105 has a fin structure, and the gate electrode 165 may be disposed between the active region 105 and the channel structure 140, between the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140, and on the channel structure 140. This allows the semiconductor device 100 to include a transistor with an MBCFET™ (Multi Bridge Channel FET) structure, which is a gate-all-around type field effect transistor.

[0015] The substrate 101 may have a top surface extending in an X direction and a Y direction. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like.

[0016] The substrate 101 may include an active region 105 disposed on top of the substrate 101. The active region 105 may be defined by an isolation layer 110 within the substrate 101 and may be disposed extending in a first direction, e.g., the X-direction. An item, layer, or portion of an item or layer described as extending in a particular direction "lengthwise" has a length in the particular direction and a width perpendicular to that direction, where the length may be greater than the width. In one example, the active region 105 may be described as being separate from the substrate 101.

[0017] The active area 105 extends in a first direction (e.g., X-direction) on the substrate 101 and may include a first active pattern 105A having a first width Wa in a second direction (e.g., Y-direction), a second active pattern 105B having a second width Wb different from the first width Wa in the second direction, and a switching active pattern 105T connecting the first active pattern 105A and the second active pattern 105B. The first width Wa and the second width Wb may indicate the width of each active pattern at a particular vertical level (e.g., at a particular height above the bottom surface of the substrate). Although an exemplary bottom surface is shown in FIGS. 2a-2c, the embodiment is not limited thereto. According to an exemplary embodiment, the second width Wb may be smaller than the first width Wa. The switching active pattern 105T may provide non-parallel sides due to a portion where the width in the second direction (e.g., Y-direction) changes. The first active pattern 105A and the second active pattern 105B each have a constant width at a specific vertical level, and the width Wt of the switching active pattern 105T along the second direction (e.g., Y direction) may gradually decrease or increase as it moves toward the first direction (e.g., X direction) at a specific vertical level.

[0018] The active region 105 may protrude partially above the isolation layer 110, and the upper surface of the active region 105 may be located at a higher level than the upper surface of the isolation layer 110. The upper surface of the active region 105 may be convex downward. According to an exemplary embodiment, the upper surfaces of the first active pattern 105A, the second active pattern 105B, and the switching active pattern 105T may be convex downward (e.g., concave). The active region 105 may be a part of the substrate 101 (e.g., formed by etching another part of the substrate 101) or may include an epitaxial layer grown from the substrate 101. In an embodiment, the active region 105 is provided together with the substrate 101. However, the active region 105 may be partially recessed on both sides of the gate structure 160 to form recessed regions, and the source / drain regions 150 may be disposed in the recessed regions. The source / drain regions 150 may extend from a lower surface of an interlayer insulating layer 190 disposed between gate structures 160 and disposed within the active region 105 .

[0019] In an exemplary embodiment, the active region 105 may or may not include a well region containing an impurity. For example, in the case of a p-type transistor (pFET), the well region may contain an n-type impurity such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an n-type transistor (nFET), the well region may contain a p-type impurity such as boron (B), gallium (Ga), or indium (In). The well region may be located at a predetermined depth from the top surface of the active region 105, for example.

[0020] According to an example embodiment, the active region 105 may be symmetrical in a second direction (e.g., Y direction) with respect to a central axis CL of the active region 105 extending in a first direction (e.g., X direction). Such a structure may be effective in preventing contact between the second epitaxial layer 152 and the gate structure 160, thereby providing a semiconductor device with improved electrical characteristics and reliability.

[0021] The isolation layer 110 may define the active region 105 in the substrate 101. The isolation layer 110 may be formed, for example, by a shallow trench isolation (STI) process. The isolation layer 110 may expose a top surface of the active region 105, or may have a partially exposed top portion. In some embodiments, the isolation layer 110 may have a curved top surface having a higher level adjacent to the active region 105. The isolation layer 110 may be made of an insulating material. The isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0022] The gate structure 160 may be disposed on the active region 105 and the channel structure 140, and may extend in a second direction, for example, the Y direction, intersecting the active region 105 and the channel structure 140. A functional channel region of a transistor may be formed in the active region 105 and / or the channel structure 140 intersecting the gate electrode 165 of the gate structure 160. Each of the gate structures 160 may include a gate electrode 165, a gate dielectric layer 162 between the gate electrode 165 and the first to fourth channel layers 141, 142, 143, 144, and a gate spacer layer 164 on a side of the gate electrode 165. In an exemplary embodiment, each of the gate structures 160 may further include a gate capping layer 166 on an upper surface of the gate electrode 165.

[0023] The gate dielectric layer 162 may be disposed between the active region 105 and the gate electrode 165 and between the channel structure 140 and the gate electrode 165, and may be disposed to cover at least a portion of a surface of the gate electrode 165. For example, the gate dielectric layer 162 may be disposed to surround all surfaces of the gate electrode 165 except for a top surface thereof. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but is not limited thereto. The gate dielectric layer 162 may include an oxide, a nitride, or a high-k material. The high-k material may refer to a dielectric material having a higher dielectric constant than silicon oxide (SiO2). The high dielectric constant material may be, for example, any one of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), and praseodymium oxide (Pr2O3). According to an embodiment, the gate dielectric layer 162 may be formed of a multi-layer film.

[0024] The gate electrode 165 may be disposed to extend over the active region 105 while filling the gaps between the first to fourth channel layers 141, 142, 143, and 144 on the active region 105. The gate electrode 165 may be separated from the first to fourth channel layers 141, 142, 143, and 144 by a gate dielectric layer 162. The gate electrode 165 may include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to an embodiment, the gate electrode 165 may be configured of two or more multi-layers.

[0025] The gate spacer layer 164 may be disposed on both sides (e.g., opposite sides) of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. The gate spacer layer 164 may have a multi-layer structure depending on the embodiment. The gate spacer layer 164 may be made of an oxide, a nitride, or an oxynitride, and may in particular be made of a low dielectric constant film.

[0026] The gate capping layer 166 may be disposed on top of the gate electrode 165 and may be surrounded on the bottom by the gate electrode 165 and the gate spacer layer 164 .

[0027] The channel structure 140 may be disposed on the active region 105 in a region where the active region 105 intersects with the gate structure 160. Each of the channel structures 140 may include first to fourth channel layers 141, 142, 143, and 144, which are a plurality of channel layers disposed at a distance from each other in a third direction (e.g., Z direction) perpendicular to the upper surface of the substrate 101. The first to fourth channel layers 141, 142, 143, and 144 may be disposed sequentially from the active region 105. For example, a plurality of channel layer sets (e.g., a first channel layer 141 pattern, a second channel layer 142 pattern, a third channel layer 143 pattern, and a fourth channel layer 144 pattern) including channel layers extending in the first direction may be disposed in a continuous sequence from the active region 105 and disposed at a distance from each other in the third direction (e.g., Z direction). Each channel layer set may be surrounded by a respective gate structure 160 on the active region 105. The channel structure 140 may be connected to the source / drain region 150. The channel structure 140 may have a width in the X direction that is the same as or similar to that of the gate structure 160, and may have a width in the Y direction that is the same as or smaller than that of the active region 105. In a cross section along the Y direction, the channel layer disposed at the lower part among the first to fourth channel layers 141, 142, 143, and 144 may have a width that is the same as or larger than that of the channel layer disposed at the upper part.

[0028] According to an exemplary embodiment, the plurality of channel layers 141, 142, 143, 144 disposed on the first active pattern 105A may have a first channel width CHa along a second direction (e.g., Y direction), the plurality of channel layers 141, 142, 143, 144 disposed on the second active pattern 105B may have a second channel width CHb along the second direction (e.g., Y direction) that is smaller than the first channel width CHa, and the plurality of channel layers 141, 142, 143, 144 disposed on the switching active pattern 105T may have a switching channel width CHt along the second direction (e.g., Y direction) that is smaller than the first channel width CHa and larger than the second channel width CHb. For example, for any given vertical level (e.g., height above the bottom surface of the substrate 101), the width of the channel layers disposed on the first active pattern 105A in the second direction (e.g., Y direction) may be larger than the width of the channel layers disposed on the second active pattern 105B in the second direction (e.g., Y direction). The width in the second direction (e.g., Y direction) of the channel layer arranged on the switching active region 105T may be larger than the width in the second direction (e.g., Y direction) of the channel layer arranged on the second active pattern 105B and smaller than the width in the second direction (e.g., Y direction) of the channel layer arranged on the first active pattern 105A.

[0029] In other words, each set of channel layers arranged on the first active pattern 105A may include continuously aligned channel layers and may have a first set of widths, and each set of channel layers arranged on the second active pattern 105B may include continuously aligned channel layers and may have a second set of widths in a second direction, each of the second set of widths may be smaller than each of the first set of widths. In a plan view, each of the first channel width CHa and the second channel width CHb may have a constant width, and the transition channel width CHt may gradually increase or decrease in the first direction (e.g., X direction). In one embodiment, each set of channel layers arranged on the active pattern 105T may include continuously aligned channel layers and may have a third set of widths in the second direction. Each of the third set of widths may be smaller than each of the first set of widths and larger than each of the second set of widths.

[0030] The number and shape of the channel layers constituting one channel structure 140 may be changed in various ways in the embodiment. As shown in FIG. 2a, the first to third channel layers 141, 142, and 143 have a side surface along the X direction that is convex outward, and the uppermost fourth channel layer 144 may have a side surface that is inclined so that the width decreases toward the active region 105. The channel structure 140 may have a shape in which the width in the X direction increases as the channel layer is closer to the active region 105 (e.g., compared to the width in the X direction of an adjacent channel layer farther from the active region 105). At least one of the first to fourth channel layers 141, 142, 143, and 144 may have a reduced width so that the side surface is located under the gate structure 160 in the X direction (e.g., vertically overlapping at least one of the gate structures 160). However, in embodiments, the shapes and relative widths of the side surfaces of the first to fourth channel layers 141, 142, 143, and 144 may be variously changed and are not limited to the shapes shown in Figures 2a to 2c. For example, in some embodiments, the first to fourth channel layers 141, 142, 143, and 144 may have side surfaces that extend vertically along a third direction (e.g., Z direction).

[0031] The channel structure 140 may be made of a semiconductor material, such as at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The channel structure 140 may be made of the same material as the active region 105. In some embodiments, the channel structure 140 may include an impurity region located adjacent to the source / drain region 150.

[0032] The source / drain regions 150 may be disposed in recess regions that partially recess an upper portion of the active region 105 on both sides of the gate structure 160 in the first direction. The source / drain regions 150 may be disposed to cover side surfaces of the first to fourth channel layers 141, 142, 143, and 144 of the channel structure 140 along the X direction. The top surface of the source / drain region 150 may be located at a height that is the same as or similar to a lower surface of the gate electrode 165 on the channel structure 140, and the height may be variously changed depending on the embodiment. The source / drain region 150 may include at least one of a semiconductor material, for example, silicon (Si) and germanium (Ge), and may further include an impurity.

[0033] According to an illustrative embodiment, the source / drain region 150 may include a first source / drain region 150A disposed on the first active pattern 105A, a second source / drain region 150B disposed on the second active pattern 105B, and a switching source / drain region 150T disposed on the switching active pattern 105T.

[0034] Each of the source / drain regions 150 may include a first epitaxial layer 151 and a second epitaxial layer 152 on the first epitaxial layer 151. According to other embodiments, the source / drain regions 150 may further include multiple epitaxial layers in addition to the first epitaxial layer 151 and the second epitaxial layer 152.

[0035] For each set of the first, second, third and fourth channel layers 141, 142, 143 and 144, the first epitaxial layer 151 may cover the side surfaces of the first to fourth channel layers 141, 142, 143 and 144 along the X direction, and may cover the side surfaces of the gate structures 160 under the channel structures 140 along the X direction. The first epitaxial layer 151 may cover the inner side surfaces and bottom surfaces of the recessed regions in which the source / drain regions 150 are disposed, and may extend as one layer within one source / drain region 150. The first epitaxial layer 151 may have a side surface that protrudes convexly toward the gate structures 160 under the channel structures 140, and thus may have a bend on the side surface. The entire surface of the first epitaxial layer 151 in contact with the alternating channel structures 140 may have a wave shape that may also be described as uneven. The first epitaxial layer 151 may be grown with a relatively small thickness on the side of the fourth channel layer 144 by the gate spacer layer 164 of the gate structure 160 during fabrication. In a plan view, at least some of the outer surfaces of the first epitaxial layer 151 and the second epitaxial layer 152 may be facets along a crystal plane, but are not limited thereto. The source / drain region 150 is not limited to the shape shown in the figure. The source / drain region 150 may have different materials or different shapes depending on whether it is an N-type or P-type transistor. The cross section of the source / drain region 150 along the second direction (e.g., Y direction) may be, but is not limited to, a pentagonal, hexagonal, or polygonal shape with gentle corners.

[0036] Since the first epitaxial layer 151 is formed by epitaxial growth from the sidewalls of the multiple channel layers 141, 142, 143, 144, the thickness of the sidewall of the first epitaxial layer 151 may be determined by the width of the multiple channel layers 141, 142, 143, 144 along the second direction (e.g., Y direction). As shown in FIG. 2a, at a certain vertical level, the first sidewall thickness Ta of the first epitaxial layer 151 of the first source / drain region 150A along the first direction (e.g., X direction) may be different from the second sidewall thickness Tb of the first epitaxial layer 151 of the second source / drain region 150B along the first direction (e.g., X direction). According to an exemplary embodiment, the first channel width CHa can be greater than the second channel width CHb, so that at one level, a first sidewall thickness Ta along a first direction (e.g., the X direction) of the first epitaxial layer 151 of the first source / drain region 150A can be greater than a second sidewall thickness Tb along the first direction (e.g., the X direction) of the first epitaxial layer 151 of the second source / drain region 150B.

[0037] Since the widths of the channel layers 141, 142, 143, 144 in contact with both sides of the converted source / drain region 150T along the second direction (e.g., Y direction) may be different, the thicknesses of the opposing sidewalls of the first epitaxial layer 151 of the converted source / drain region 150T along the first direction (e.g., X direction) may be different from each other at a particular vertical level. According to an exemplary embodiment, at a particular vertical level, the converted source / drain region 150T may have a first converted sidewall thickness Tt1 along the first direction (e.g., X direction) of the first epitaxial layer 151 of the converted source / drain region 150T and a second converted sidewall thickness Tt2 smaller than the first converted sidewall thickness Tt1. This may be because the first channel width CHa is larger than the second channel width CHb. According to an exemplary embodiment, the first sidewall thickness Ta may be substantially the same as the first converted sidewall thickness Tt1, and the second sidewall thickness Tb may be substantially the same as the second converted sidewall thickness Tt2, but is not limited thereto.

[0038] The second epitaxial layer 152 may cover the first epitaxial layer 151 and fill the recessed regions. The second epitaxial layer 152 may be surrounded by the first epitaxial layer 151 in regions other than the top surface. At a certain height, the widths Pa, Pb, and Pt of the second epitaxial layer 152 along the X direction between the first epitaxial layers 151 may be greater than the thicknesses Ta, Tb, Tt1, and Tt2 of the first epitaxial layer 151 at the sidewalls. According to an illustrative embodiment, at a particular height, a width Pt along a first direction (e.g., X-direction) of the second epitaxial layer 152 of the conversion source / drain region 150T may be greater than a width Pa along the first direction (e.g., X-direction) of the second epitaxial layer 152 of the first source / drain region 150A and less than a width Pb along the first direction (e.g., X-direction) of the second epitaxial layer 152 of the second source / drain region 150B.

[0039] The second epitaxial layer 152 may include the same material as the first epitaxial layer 151, but may have a different composition and / or doping concentration than the first epitaxial layer 151. When the semiconductor device 100 is a pFET, the source / drain region 150 may include silicon germanium (SiGe), and the germanium (Ge) concentration of the second epitaxial layer 152 may be higher than the germanium (Ge) concentration of the first epitaxial layer 151. For example, the germanium (Ge) concentration of the first epitaxial layer 151 may be in the range of about 1 at% to about 15 at%, and the germanium (Ge) concentration of the second epitaxial layer 152 may be in the range of about 20 at% to about 100 at%. In addition, the second epitaxial layer 152 may have a higher dopant, i.e., impurity, doping concentration than the first epitaxial layer 151. When the semiconductor device 100 is a pFET, the impurity may be at least one of boron (B), gallium (Ga), and indium (In), and when the semiconductor device 100 is an nFET, the impurity may be at least one of phosphorus (P), arsenic (As), and antimony (Sb). Thus, according to various embodiments, the first epitaxial layer 151 has a different material composition than the second epitaxial layer 152.

[0040] According to an exemplary embodiment, in a cross section along a first direction (e.g., X direction), a level La of the bottom end of the second epitaxial layer 152 of the first source / drain region 150A, a level Lb of the bottom end of the second epitaxial layer 152 of the second source / drain region 150B, and a level Lt of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T may be different from each other. For example, in a cross section along the first direction (e.g., X direction), a level Lt of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T may be higher than a level La of the bottom end of the second epitaxial layer 152 of the first source / drain region 150A and lower than a level Lb of the bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0041] According to an exemplary embodiment, in a cross section along a first direction (e.g., the X direction), a thickness Dt from the bottom end of the first epitaxial layer 151 of the conversion source / drain region 150T to the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T may be greater than a thickness Da from the bottom end of the first epitaxial layer 151 of the first source / drain region 150A to the bottom end of the second epitaxial layer 152 of the first source / drain region 150A and less than a thickness Db from the bottom end of the first epitaxial layer 151 of the second source / drain region 150B to the bottom end of the second epitaxial layer 152 of the second source / drain region 150B. This may be because the first width Wa of the first active pattern 105A along the second direction (e.g., the Y direction) is larger than the second width Wb of the second active pattern 105B along the second direction (e.g., the Y direction), and the width Wt of the switching active pattern 105T along the second direction (e.g., the Y direction) is smaller than the first width Wa and larger than the second width Wb.

[0042] With the above-described structure, the second epitaxial layer 152 of the conversion source / drain region 150T can be disposed apart from the gate structure 160 (e.g., the gate dielectric 162 and the gate electrode 165 of the gate structure 160), thereby preventing leakage current from occurring when the second epitaxial layer 152 and the gate structure 160 come into contact with each other. As a result, a semiconductor device with improved electrical characteristics and reliability can be provided.

[0043] The interlayer insulating layer 190 may be disposed to cover the source / drain regions 150 and the gate structures 160, and to cover the isolation layer 110. The interlayer insulating layer 190 may include at least one of an oxide, a nitride, and an oxynitride, and may include, for example, a low-k material. According to an embodiment, the interlayer insulating layer 190 may include a plurality of insulating layers.

[0044] The contact plug 180 may be connected to the source / drain region 150 through the interlayer insulating layer 190 and may apply an electrical signal to the source / drain region 150. The contact plug 180 may have, but is not limited to, a slanted side such that the width at the bottom is narrower than the width at the top according to an aspect ratio. The contact plug 180 may extend from the top to, for example, below the bottom surface of the fourth channel layer 144 at the top of the channel structure 140, but is not limited to this. The contact plug 180 may contact the second epitaxial layer 152 of the source / drain region 150. According to another embodiment, the contact plug 180 may be disposed to contact along the top surface of the source / drain region 150 without recessing the source / drain region 150.

[0045] Each of the contact plugs 180 may include a metal silicide layer located at a lower end including a lower surface, and may further include a barrier layer extending onto an upper surface of the metal silicide layer while forming a side surface of the contact plug 180. The barrier layer may include a metal nitride such as, for example, a titanium nitride film (TiN), a tantalum nitride film (TaN), or a tungsten nitride film (WN). The contact plugs 180 may include a metal material such as, for example, aluminum (Al), tungsten (W), or molybdenum (Mo). In an exemplary embodiment, the number and arrangement of conductive layers constituting the contact plugs 180 may be variously changed.

[0046] An interconnect structure such as a contact plug may also be disposed on the gate electrode 165 , and an interconnect structure connected to the contact plug 180 may also be disposed on the contact plug 180 .

[0047] In the following description of the embodiment, the description overlapping with that described above with reference to FIGS. 1 to 2c will be omitted.

[0048] FIG. 3 is a plan view illustrating a semiconductor device according to an exemplary embodiment.

[0049] 3, in the semiconductor device 100a, the outer surfaces of the first epitaxial layer 151 and the second epitaxial layer 152 may be rounded. According to an exemplary embodiment, in a plan view, the outer surface of the first epitaxial layer 151 may be rounded toward the second epitaxial layer 152. For example, in a plan view, a surface where the first epitaxial layer 151 and the second epitaxial layer 152 contact each other may be rounded. The outer surface of the second epitaxial layer 152 may not be formed along a crystal plane and may be rounded without facets.

[0050] FIG. 4 is a plan view illustrating a semiconductor device according to an exemplary embodiment.

[0051] 4, in the semiconductor device 100b, the first active pattern 105A may be symmetrical in a second direction (e.g., Y direction) with respect to a central axis CLa of the first active pattern 105A extending in a first direction (e.g., X direction), and the second active pattern 105B may be symmetrical in a second direction (e.g., Y direction) with respect to a central axis CLb of the second active pattern 105B extending in the first direction (e.g., X direction). According to an exemplary embodiment, the central axis CLa of the first active pattern 105A and the central axis CLb of the second active pattern 105B may be shifted from each other. However, in a plan view, the second active pattern 105B may be disposed within an extension line of the first active pattern 105A.

[0052] FIG. 5 is a plan view illustrating a semiconductor device according to an exemplary embodiment.

[0053] 5, in the semiconductor device 100c, the switching active pattern 105T may extend in a first direction (e.g., X direction) and vertically overlap two or more gate structures 160. According to an exemplary embodiment, the channel structure 140 contacting both sidewalls of the transition source / drain region 150T may have a transition channel width CHt, CHt'. According to an exemplary embodiment, the transition channel width CHt of the channel structure 140 located near the channel structure 140 having the first channel width CHa may be larger than the transition channel width CHt' of the channel structure 140 located near the channel structure 140 having the second channel width CHb. The transition channel widths CHt, CHt' of the channel structures 140 may gradually increase or decrease in the first direction (e.g., X direction).

[0054] FIG. 6a is a plan view illustrating a semiconductor device according to an exemplary embodiment.

[0055] Figure 6b shows a cross-sectional view of the semiconductor device according to an exemplary embodiment, taken along the line I1-I1' of Figure 6a.

[0056] 6a and 6b, in the semiconductor device 100d, the active region 105 may further include a third active pattern 105C having a third width Wc different from the first width Wa and the second width Wb. According to an exemplary embodiment, the first width Wa may be greater than the second width Wb and the third width Wc, and the third width Wc may be greater than the second width Wb. Between the first active pattern 105A and the second active pattern 105B, a switching active pattern 105T connecting the first active pattern 105A and the second active pattern 105B may be disposed, and between the second active pattern 105B and the third active pattern 105C, a switching active pattern 105T' connecting the second active pattern 105B and the third active pattern 105C may be disposed. The switching active patterns 105T and 105T' may provide inclined sides by a portion where the width in the second direction (e.g., Y direction) changes. The first channel width CHa, the second channel width CHb, and the third channel width CHc of the channel structure 140 may be constant in a region where the first active pattern 105A and the gate structure 160 vertically overlap, a region where the second active pattern 105B and the gate structure 160 vertically overlap, and a region where the third active pattern 105C and the gate structure 160 vertically overlap. In a region where the switching active patterns 105T, 105T' and the gate structure 160 vertically overlap, the channel structure 140 may have transition channel widths CHt, CHt'. The transition channel widths CHt, CHt' of the channel structure 140 may gradually increase or decrease in a first direction (e.g., X direction).

[0057] The source / drain region 150 may further include a third source / drain region 150C on the third active pattern 105C. The first width Wa of the first active pattern 105A, the second width Wb of the second active pattern 105B, and the third width Wc of the third active pattern 105C are different from each other, and the first channel width CHa, the second channel width CHb, and the third channel width CHc are different from each other, so that a third sidewall thickness Tc along a first direction (e.g., X direction) of the first epitaxial layer 151 of the third source / drain region 150C may be different from the first sidewall thickness Ta and the second sidewall thickness Tb. According to an exemplary embodiment, the first sidewall thickness Ta may be greater than the second sidewall thickness Tb and the third sidewall thickness Tc, and the third sidewall thickness Tc may be greater than the second sidewall thickness Tb.

[0058] A conversion source / drain region 150T may be disposed on a switching active pattern 105T connecting the first active pattern 105A and the second active pattern 105B, and a conversion source / drain region 150T' may be disposed on a switching active pattern 105T' connecting the second active pattern 105B and the third active pattern 105C.

[0059] According to an exemplary embodiment, at a certain vertical level, the converted source / drain region 150T between the first source / drain region 150A and the second source / drain region 150B may have a first converted sidewall thickness Tt1 along a first direction (e.g., X-direction) of the first epitaxial layer 151 of the converted source / drain region 150T and a second converted sidewall thickness Tt2 smaller than the first converted sidewall thickness Tt1. This may be because the first channel width CHa is larger than the second channel width CHb. According to an exemplary embodiment, the first sidewall thickness Ta may be substantially equal to the first converted sidewall thickness Tt1, and the second sidewall thickness Tb may be substantially equal to the second converted sidewall thickness Tt2, but is not limited thereto.

[0060] According to an exemplary embodiment, at a certain vertical level, the converted source / drain region 150T' between the second source / drain region 150B and the third source / drain region 150C may have a first converted sidewall thickness Tt1' along a first direction (e.g., X-direction) of the first epitaxial layer 151 of the converted source / drain region 150T' and a second converted sidewall thickness Tt2' that is greater than the first converted sidewall thickness Tt1'. This may be because the third channel width CHc is greater than the second channel width CHb. According to an exemplary embodiment, the second sidewall thickness Tb may be substantially equal to the first converted sidewall thickness Tt1', and the third sidewall thickness Tc may be substantially equal to the second converted sidewall thickness Tt2', but is not limited thereto.

[0061] According to an illustrative embodiment, a width Pt along a first direction (e.g., X direction) of the second epitaxial layer 152 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may be greater than a width Pa along the first direction (e.g., X direction) of the second epitaxial layer 152 of the first source / drain region 150A and less than a width Pb along the first direction (e.g., X direction) of the second epitaxial layer 152 of the second source / drain region 150B.

[0062] According to an illustrative embodiment, a width Pt' along a first direction (e.g., X direction) of the second epitaxial layer 152 of the transition source / drain region 150T' between the second source / drain region 150B and the third source / drain region 150C may be smaller than a width Pb along the first direction (e.g., X direction) of the second epitaxial layer 152 of the second source / drain region 150B and larger than a width Pc along the first direction (e.g., X direction) of the second epitaxial layer 152 of the third source / drain region 150C.

[0063] According to an exemplary embodiment, in a cross section along a first direction (e.g., the X direction), a level Lt of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may be higher than a level La of the bottom end of the second epitaxial layer 152 of the first source / drain region 150A and lower than a level Lb of the bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0064] According to an exemplary embodiment, in a cross section along the first direction (e.g., the X direction), the level Lt' of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T' arranged between the second source / drain region 150B and the third source / drain region 150C may be higher than the level Lc of the bottom end of the second epitaxial layer 152 of the third source / drain region 150C and lower than the level Lb of the bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0065] In FIG. 6b, the level Lc of the bottom end of the second epitaxial layer 152 of the third source / drain region 150C and the level Lt of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B are shown to be at the same level, but are not limited to this.

[0066] According to an exemplary embodiment, in a cross section along a first direction (e.g., the X direction), a thickness Dt from a bottom end of the first epitaxial layer 151 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B to a bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T may be greater than a thickness Da from a bottom end of the first epitaxial layer 151 of the first source / drain region 150A to a bottom end of the second epitaxial layer 152 of the first source / drain region 150A and less than a thickness Db from a bottom end of the first epitaxial layer 151 of the second source / drain region 150B to a bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0067] According to an illustrative embodiment, in a cross section along the first direction (e.g., the X direction), a thickness Dt' from the bottom end of the first epitaxial layer 151 of the conversion source / drain region 150T' disposed between the second source / drain region 150B and the third source / drain region 150C to the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T' may be greater than a thickness Dc from the bottom end of the first epitaxial layer 151 of the third source / drain region 150C to the bottom end of the second epitaxial layer 152 of the third source / drain region 150C, and may be smaller than a thickness Db from the bottom end of the first epitaxial layer 151 of the second source / drain region 150B to the bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0068] In FIG. 6b, the thickness Dt from the bottom end of the first epitaxial layer 151 of the conversion source / drain region 150T arranged between the first source / drain region 150A and the second source / drain region 150B to the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T is shown to be the same as the thickness Dc from the bottom end of the first epitaxial layer 151 of the third source / drain region 150C to the bottom end of the second epitaxial layer 152 of the third source / drain region 150C, but is not limited to this.

[0069] In the following description of the embodiment, the description overlapping with that described above with reference to FIGS. 6a and 6b will be omitted.

[0070] FIG. 7a is a plan view illustrating a semiconductor device according to an exemplary embodiment.

[0071] Figure 7b shows a cross-sectional view of the semiconductor device according to an exemplary embodiment, taken along the line I2-I2' of Figure 7a.

[0072] 7a and 7b, in the semiconductor device 100e, the active region 105 may further include a third active pattern 105C having a third width Wc different from the first width Wa and the second width Wb. According to an exemplary embodiment, the first width Wa may be greater than the second width Wb, and the second width Wb may be greater than the third width Wc. Between the first active pattern 105A and the second active pattern 105B, a switching active pattern 105T connecting the first active pattern 105A and the second active pattern 105B may be disposed, and between the second active pattern 105B and the third active pattern 105C, a switching active pattern 105T' connecting the second active pattern 105B and the third active pattern 105C may be disposed.

[0073] The source / drain region 150 may further include a third source / drain region 150C on the third active pattern 105C. A third sidewall thickness Tc along a first direction (e.g., X-direction) of the first epitaxial layer 151 of the third source / drain region 150C may be different from the first sidewall thickness Ta and the second sidewall thickness Tb. According to an exemplary embodiment, the first sidewall thickness Ta may be greater than the second sidewall thickness Tb and the third sidewall thickness Tc, and the second sidewall thickness Tb may be greater than the third sidewall thickness Tc.

[0074] According to an exemplary embodiment, at a certain vertical level, the converted source / drain region 150T between the first source / drain region 150A and the second source / drain region 150B may have a first converted sidewall thickness Tt1 along a first direction (e.g., X-direction) of the first epitaxial layer 151 of the converted source / drain region 150T and a second converted sidewall thickness Tt2 smaller than the first converted sidewall thickness Tt1. This may be because the first channel width CHa is larger than the second channel width CHb. According to an exemplary embodiment, the first sidewall thickness Ta may be substantially equal to the first converted sidewall thickness Tt1, and the second sidewall thickness Tb may be substantially equal to the second converted sidewall thickness Tt2, but is not limited thereto.

[0075] According to an exemplary embodiment, at a certain vertical level, the converted source / drain region 150T' between the second source / drain region 150B and the third source / drain region 150C may have a first converted sidewall thickness Tt1' along a first direction (e.g., X-direction) of the first epitaxial layer 151 of the converted source / drain region 150T' and a second converted sidewall thickness Tt2' smaller than the first converted sidewall thickness Tt1'. This may be because the third channel width CHc is smaller than the second channel width CHb. According to an exemplary embodiment, the second sidewall thickness Tb may be substantially the same as the first converted sidewall thickness Tt1', and the third sidewall thickness Tc may be substantially the same as the second converted sidewall thickness Tt2', but is not limited thereto.

[0076] According to an illustrative embodiment, a width Pt along a first direction (e.g., X direction) of the second epitaxial layer 152 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may be greater than a width Pa along the first direction (e.g., X direction) of the second epitaxial layer 152 of the first source / drain region 150A and less than a width Pb along the first direction (e.g., X direction) of the second epitaxial layer 152 of the second source / drain region 150B.

[0077] According to an illustrative embodiment, a width Pt' along a first direction (e.g., X direction) of the second epitaxial layer 152 of the transition source / drain region 150T' between the second source / drain region 150B and the third source / drain region 150C may be greater than a width Pb along the first direction (e.g., X direction) of the second epitaxial layer 152 of the second source / drain region 150B and less than a width Pc along the first direction (e.g., X direction) of the second epitaxial layer 152 of the third source / drain region 150C.

[0078] According to an exemplary embodiment, in a cross section along a first direction (e.g., the X direction), a level Lt of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B may be higher than a level La of the bottom end of the second epitaxial layer 152 of the first source / drain region 150A and lower than a level Lb of the bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0079] According to an exemplary embodiment, in a cross section along the first direction (e.g., the X direction), the level Lt' of the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T' arranged between the second source / drain region 150B and the third source / drain region 150C may be higher than the level Lb of the bottom end of the second epitaxial layer 152 of the second source / drain region 150B and lower than the level Lc of the bottom end of the second epitaxial layer 152 of the third source / drain region 150C.

[0080] According to an exemplary embodiment, in a cross section along a first direction (e.g., the X direction), a thickness Dt from a bottom end of the first epitaxial layer 151 of the conversion source / drain region 150T disposed between the first source / drain region 150A and the second source / drain region 150B to a bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T may be greater than a thickness Da from a bottom end of the first epitaxial layer 151 of the first source / drain region 150A to a bottom end of the second epitaxial layer 152 of the first source / drain region 150A and less than a thickness Db from a bottom end of the first epitaxial layer 151 of the second source / drain region 150B to a bottom end of the second epitaxial layer 152 of the second source / drain region 150B.

[0081] According to an illustrative embodiment, in a cross section along the first direction (e.g., the X direction), a thickness Dt' from the bottom end of the first epitaxial layer 151 of the conversion source / drain region 150T' disposed between the second source / drain region 150B and the third source / drain region 150C to the bottom end of the second epitaxial layer 152 of the conversion source / drain region 150T' may be greater than a thickness Db from the bottom end of the first epitaxial layer 151 of the second source / drain region 150B to the bottom end of the second epitaxial layer 152 of the second source / drain region 150B and less than a thickness Dc from the bottom end of the first epitaxial layer 151 of the third source / drain region 150C to the bottom end of the second epitaxial layer 152 of the third source / drain region 150C.

[0082] FIG. 8 is a plan view illustrating a semiconductor device according to an exemplary embodiment.

[0083] 8, the semiconductor device 100c may further include an inner spacer layer 130 disposed under the fourth channel layer 144 and on both side surfaces of the gate structure 160 in the X direction.

[0084] The inner spacer layer 130 may be disposed in parallel with the gate electrode 165 and the gate dielectric layer 162 between the first to fourth channel layers 141, 142, 143, and 144 along the third direction (e.g., Z direction). A side surface of the inner spacer layer 130 may contact the source / drain region 150. The gate electrode 165 may be stably separated from the source / drain region 150 by the inner spacer layer 130 and electrically isolated. The inner spacer layer 130 may have a round shape (e.g., a convex surface toward the gate electrode 165) on a side surface facing the gate electrode 165, but is not limited thereto. The inner spacer layer 130 may be made of an oxide, a nitride, or an oxynitride, and may be made of a low dielectric constant film in particular.

[0085] In some embodiments, the inner spacer layer 130 may be applied to only some elements of the semiconductor device 100c. For example, the inner spacer layer 130 may be applied to an nFET, and the inner spacer layer 130 may be omitted to improve the crystallinity of silicon germanium (SiGe) in the source / drain regions 150 in a pFET.

[0086] 9a to 16 are drawings showing a process sequence to explain a method for manufacturing a semiconductor device according to an exemplary embodiment. In FIG. 9a to FIG. 16, one embodiment of a manufacturing method for manufacturing the semiconductor device of FIG. 2a to FIG. 2c is explained. FIG. 9a, FIG. 10a, FIG. 11a, FIG. 12a, FIG. 13a, FIG. 14a, FIG. 15a, and FIG. 16 show cross sections corresponding to FIG. 2a, FIG. 9b, FIG. 10b, FIG. 11b, and FIG. 15b show cross sections corresponding to FIG. 2b, and FIG. 9c, FIG. 10c, FIG. 12b, FIG. 13b, FIG. 14b, and FIG. 15c show cross sections corresponding to FIG. 2c.

[0087] 9a to 9c, a sacrificial layer 120 and first to fourth channel layers 141, 142, 143, and 144 may be alternately stacked on a substrate 101. As shown in FIG.

[0088] The sacrificial layer 120 may be a layer that is replaced with the gate dielectric layer 162 and the gate electrode 165 under the fourth channel layer 144 through a subsequent process as shown in FIG. 2a. The sacrificial layer 120 may be made of a material having an etching selectivity with respect to the first to fourth channel layers 141, 142, 143, and 144, respectively. The first to fourth channel layers 141, 142, 143, and 144 may include a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 include a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), for example, but may include different materials from each other and may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the first to fourth channel layers 141, 142, 143, and 144 may include silicon (Si).

[0089] The sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, 144 may be formed by performing an epitaxial growth process from the stacked structure. Each of the sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, 144 may have a thickness in the range of about 1 nm to about 20 nm. The number of layers of the channel layers alternately stacked with the sacrificial layer 120 may be variously changed depending on the embodiment.

[0090] 10a to 10c, the sacrificial layer 120, the first to fourth channel layers 141, 142, 143, and 144, and the substrate 101 may be partially removed to form an active structure including an active region 105, and an isolation layer 110 may be formed.

[0091] The active structure may include an active region 105, a sacrificial layer 120, and first to fourth channel layers 141, 142, 143, and 144. The active structures may be formed in a line shape extending in one direction, for example, the X direction, and may be formed spaced apart from adjacent active structures in the Y direction. The active region 105, the sacrificial layer 120, and the first to fourth channel layers 141 to 144 may be sequentially stacked in the vertical direction (for example, the Z direction). The width of the active structures in the second direction (Y direction) may gradually narrow along the vertical direction (for example, the Z direction).

[0092] An insulating material may be filled in the regions where the active region 105, the sacrificial layer 120, and the first to fourth channel layers 141, 142, 143, and 144 have been partially removed, and then the insulating material may be partially removed so that the active region 105 protrudes, thereby forming an isolation layer 110. The upper surface of the isolation layer 110 may be formed lower than the upper surface of the active region 105.

[0093] When forming the active structure, the active patterns 105A, 105B, and 105T may be formed with different widths in a second direction (e.g., Y direction) for each region. The active region 105 may include a first active pattern 105A having a first width Wa, a second active pattern 105B having a second width Wb different from the first width Wa, and a switching active pattern 105T connecting the first active pattern 105A and the second active pattern 105B. Since the switching active pattern 105T connects the first active pattern 105A and the second active pattern 105B having different widths, the width Wt of the switching active pattern 105T along the second direction (e.g., Y direction) may gradually decrease or increase as it goes toward the first direction (e.g., X direction).

[0094] 11a and 11b, a sacrificial gate structure 170 and a gate spacer layer 164 may be formed over the active structure.

[0095] The sacrificial gate structure 170 may be a sacrificial structure formed in a region where the gate dielectric layer 162 and the gate electrode 165 are disposed on the first to fourth channel layers 141, 142, 143, and 144 through a subsequent process as shown in FIG. 2a. The sacrificial gate structure 170 may include first and second sacrificial gate layers 172 and 175, which are sequentially stacked, and a mask pattern layer 176. The first and second sacrificial gate layers 172 and 175 may be patterned using the mask pattern layer 176. The first and second sacrificial gate layers 172 and 175 may be an insulating layer and a conductive layer, respectively. For example, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The mask pattern layer 176 may include silicon nitride. The sacrificial gate structure 170 may have a line shape extending in one direction across the active structure. The sacrificial gate structures 170 may, for example, extend in the Y direction and be spaced apart from one another in the X direction.

[0096] The gate spacer layer 164 may be formed on both side walls of the sacrificial gate structure 170. The gate spacer layer 164 may be formed by forming a film of uniform thickness along the top and side surfaces of the sacrificial gate structure 170 and the active structure, and then anisotropically etching the film. The gate spacer layer 164 may be made of a low dielectric constant material, and may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0097] 12a and 12b, the sacrificial layer 120 and the first to fourth channel layers 141, 142, 143, and 144 exposed from the sacrificial gate structure 170 may be partially removed to form a recess region RC, and the sacrificial layer 120 may be partially removed.

[0098] A recess region RC may be formed by removing a portion of the exposed sacrificial layer 120 and a portion of the first to fourth channel layers 141, 142, 143, and 144 using the sacrificial gate structure 170 and the gate spacer layer 164 as a mask. As a result, the first to fourth channel layers 141, 142, 143, and 144 may form a channel structure 140 having a limited length along the X direction.

[0099] The sacrificial layer 120 may be selectively etched with respect to the channel structure 140 by, for example, a wet etching process, and removed from a side along the X direction to a predetermined depth. The sacrificial layer 120 may have a concave side surface on the inside due to the side etching as described above. However, the specific shape of the side surface of the sacrificial layer 120 is not limited to that shown in FIGS. 12a and 12b.

[0100] 13a and 13b, a first epitaxial layer 151 may be formed in the recessed region RC.

[0101] The first epitaxial layer 151 may extend to contact the first to fourth channel layers 141, 142, 143, 144 and the sacrificial layer 120 in the recess region RC. Thus, an upper surface of the first epitaxial layer 151 may be formed in a recessed shape, and may be formed to have a substantially U-shape. A surface of the first epitaxial layer 151 in contact with the first to fourth channel layers 141, 142, 143, 144 and the sacrificial layer 120 may have a wavy shape. An inner surface of the first epitaxial layer 151 may have a smooth shape rather than a wavy pattern.

[0102] The first epitaxial layer 151 may include silicon germanium (SiGe) doped with a group 3 element. According to an embodiment, the first epitaxial layer 151 may include any one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The first epitaxial layer 151 may be formed by supplying silicon (Si) and germanium (Ge) source gases under the supply of a carrier gas. In an exemplary embodiment, the carrier gas may be hydrogen (H2) gas, the silicon (Si) source gas may be, for example, silane (SiH4), dichlorosilane (SiH2Cl2; DCS) or monochlorosilane (SiH3Cl; MCS), and the germanium (Ge) source gas may be, for example, germanium tetrahydride (GeH4). A second epitaxial layer 152 (see Figures 14a and 14b), described below, may be formed in a similar manner.

[0103] Since the first epitaxial layer 151 is formed by epitaxial growth on the sidewalls of the multiple channel layers 141, 142, 143, 144 and on the active region 105, the sidewall thicknesses Ta, Tb, Tt1, Tt2 and the lower thicknesses Da, Db, Dt of the first epitaxial layer 151 may be different from each other.

[0104] The sidewall thicknesses Ta, Tb, Tt1, and Tt2 of the first epitaxial layer 151 may be determined by the widths of the channel layers 141, 142, 143, and 144 along the second direction (e.g., Y direction). As shown in FIG. 11b, the widths of the channel layers 141, 142, 143, and 144 along the second direction (e.g., Y direction) on the first active pattern 105A are greater than the widths of the channel layers 141, 142, 143, and 144 along the second direction (e.g., Y direction) on the second active pattern 105B, so that at one level, the first sidewall thickness Ta of the first epitaxial layer 151 of the first source / drain region 150A along the first direction (e.g., X direction) may be greater than the second sidewall thickness Tb of the first epitaxial layer 151 of the second source / drain region 150B along the first direction (e.g., X direction). A first converted sidewall thickness Tt1 along a first direction (e.g., the X direction) of the first epitaxial layer 151 of the converted source / drain region 150T located near the first source / drain region 150A may be greater than a second converted sidewall thickness Tt2 along the first direction (e.g., the X direction) of the first epitaxial layer 151 of the converted source / drain region 150T located near the second source / drain region 150B.

[0105] The thicknesses Da, Db, and Dt of the lower portion of the first epitaxial layer 151 may be affected by the first width Wa of the first active pattern 105A, the second width Wb of the second active pattern 105B, and the width Wt of the switching active pattern 105T along the second direction (e.g., Y direction). According to an exemplary embodiment, in a cross section along the first direction (e.g., X direction), the thickness Dt of the lower portion of the first epitaxial layer 151 along the vertical direction of the switching source / drain region 150T may be greater than the thickness Da of the lower portion of the first epitaxial layer 151 along the vertical direction of the first source / drain region 150A and less than the thickness Db of the lower portion of the first epitaxial layer 151 along the vertical direction of the second source / drain region 150B.

[0106] 8 may be fabricated at this stage by forming the inner spacer layer 130 prior to the formation of the first epitaxial layer 151. The inner spacer layer 130 may be formed by filling the areas where the sacrificial layer 120 has been removed with an insulating material and removing the insulating material deposited outside the channel structure 140.

[0107] 14a and 14b, a second epitaxial layer 152 may be formed on a first epitaxial layer 151 to form source / drain regions 150. As shown in FIG.

[0108] The second epitaxial layer 152 may include silicon (Si) doped with a group 3 element. For example, the second epitaxial layer 152 may include any one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl). The second epitaxial layer 152 may be formed to a level higher than the top surface of the fourth channel layer 144, but is not limited thereto. According to an exemplary embodiment, a plurality of epitaxial layers may be further formed on the second epitaxial layer 152. A width Pt along the first direction (e.g., the X direction) of the second epitaxial layer 152 of the conversion source / drain region 150T may be greater than a width Pa along the first direction (e.g., the X direction) of the second epitaxial layer 152 of the first source / drain region 150A and less than a width Pb along the first direction (e.g., the X direction) of the second epitaxial layer 152 of the second source / drain region 150B.

[0109] 15a to 15c, an interlayer insulating layer 190 may be formed between adjacent sacrificial gate structures 170 on the second epitaxial layer 152, and the sacrificial layer 120 and the sacrificial gate structures 170 may be removed.

[0110] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 170 and the source / drain regions 150 and performing a planarization process.

[0111] The sacrificial layer 120 and the sacrificial gate structure 170 may be selectively removed with respect to the gate spacer layer 164, the interlayer insulating layer 190, and the first to fourth channel layers 141, 142, 143, and 144. First, the sacrificial gate structure 170 may be removed to form an upper gap region UR, and then the sacrificial layer 120 exposed through the upper gap region UR may be removed to form a lower gap region LR. For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the first to fourth channel layers 141, 142, 143, and 144 include silicon (Si), the sacrificial layer 120 may be selectively removed with respect to the first to fourth channel layers 141, 142, 143, and 144 by performing a wet etching process using peracetic acid as an etchant.

[0112] Referring to FIG. 16, a gate structure 160 may be formed in the upper gap region UR and the lower gap region LR.

[0113] The gate dielectric layer 162 may be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 may be formed to completely fill the upper gap region UR and the lower gap region LR. The gate electrode 165 and the gate spacer layer 164 may be removed from the top to a predetermined depth in the upper gap region UR. A gate capping layer 166 may be formed in the region in the upper gap region UR from which the gate electrode 165 and the gate spacer layer 164 have been removed. Thus, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166 may be formed.

[0114] Next, referring together to FIGS. 2a-2c, contact plugs 180 may be formed.

[0115] The interlayer insulating layer 190 may be patterned to form contact holes exposing the source / drain regions 150. Then, the contact holes may be filled with a conductive material to form contact plugs 180.

[0116] Specifically, a material forming a barrier layer may be deposited in the contact hole, and then a silicide process may be performed to form a metal-semiconductor compound layer such as a silicide layer at the bottom. Then, a conductive material may be deposited to fill the contact hole, forming a contact plug 180. In this manner, the semiconductor device 100 of FIGS. 1 to 2c may be manufactured.

[0117] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the appended claims. Therefore, various substitutions, modifications and changes can be made by a person skilled in the art without departing from the technical spirit of the present invention described in the claims, and these also belong to the scope of the present invention. [Explanation of symbols]

[0118] 101: Substrate 105: Active region 110: element isolation layer 120: sacrificial layer 130: Inner spacer layer 140: Channel structure 141, 142, 143, 144: 1st to 4th channel layers 150: source / drain region 150A: first source / drain region 150B: second source / drain region 150T: conversion source / drain region 151: First epitaxial layer 152: Second epitaxial layer 160: Gate structure 162: Gate dielectric layer 164: Gate spacer layer 165: Gate electrode 180: Contact plug 190: Interlayer insulating layer

Claims

1. A substrate; an active region on the substrate; a first active pattern extending in a first direction on the substrate and having a first height in a third vertical direction on a lower surface of the substrate and a first width in a second direction perpendicular to the first direction; a second active pattern extending in the first direction and having a second width in the second direction at the first height that is smaller than the first width; a switching active pattern extending in the first direction and connecting the first active pattern and the second active pattern, a gate structure on the substrate, the gate structure intersecting the active region and extending in the second direction; a plurality of sets of channel layers extending in the first direction and disposed contiguously from the active region, each set including a channel layer disposed spaced apart from one another in a third direction perpendicular to the top surface of the substrate, the channel layers being surrounded by respective ones of the gate structures on the active region; a source / drain region disposed on a side of the gate structure, the source / drain region including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a switching source / drain region disposed on the switching active pattern; the active region is symmetric in the second direction with respect to a central axis of the active region extending in the first direction; Each of the source / drain regions is disposed on the active region, and includes a first epitaxial layer disposed and extending on the first set of the plurality of set channel layers and the second set of the plurality of set channel layers, and a second epitaxial layer disposed on the first epitaxial layer; At a second height above a bottom surface of the substrate in the third direction, a first sidewall thickness of the first epitaxial layer of the first source / drain region along the first direction is greater than a second sidewall thickness of the first epitaxial layer of the second source / drain region along the first direction; At the second elevation, the first epitaxial layer of the converted source / drain region has a first sidewall having a first converted sidewall thickness in the first direction and a second sidewall having a second converted sidewall thickness in the first direction less than the first converted sidewall thickness.

2. the first sidewall thickness is the same as the first transition sidewall thickness at the second height; The semiconductor device of claim 1 , wherein the second sidewall thickness is the same as the second transition sidewall thickness at the second height.

3. In a cross section along the first direction, 2. The semiconductor device of claim 1, wherein a thickness in the third direction from a bottom edge of the first epitaxial layer of the conversion source / drain region to a bottom edge of the second epitaxial layer of the conversion source / drain region is greater than a thickness in the third direction from a bottom edge of the first epitaxial layer of the first source / drain region to a bottom edge of the second epitaxial layer of the first source / drain region and is smaller than a thickness in the third direction from a bottom edge of the first epitaxial layer of the second source / drain region to a bottom edge of the second epitaxial layer of the second source / drain region.

4. In a cross section along the first direction, 2. The semiconductor device of claim 1, wherein a vertical level of a bottom end of the second epitaxial layer of the conversion source / drain region is higher than a vertical level of a bottom end of the second epitaxial layer of the first source / drain region and lower than a vertical level of a bottom end of the second epitaxial layer of the second source / drain region.

5. 2. The semiconductor device of claim 1, wherein the second epitaxial layer of the conversion source / drain region is spaced apart from a gate electrode and a gate dielectric layer of the gate structure.

6. At the first height, the first active pattern and the second active pattern each have a constant width in the second direction; 2 . The semiconductor device of claim 1 , wherein at the first height, a width of the switching active pattern in the second direction gradually increases or decreases along the first direction.

7. 2. The semiconductor device of claim 1, wherein at the second height, a width of the second epitaxial layer of the conversion source / drain region along the first direction is greater than a width of the second epitaxial layer of the first source / drain region along the first direction and is smaller than a width of the second epitaxial layer of the second source / drain region along the first direction.

8. The semiconductor device according to claim 1 , wherein in a plan view, outer surfaces of at least a portion of the first epitaxial layer and the second epitaxial layer are facets along a crystal plane.

9. 2. The semiconductor device of claim 1, wherein each of the source / drain regions further comprises a contact plug that penetrates a portion of the source / drain region and is connected to the source / drain region.

10. The semiconductor device of claim 1 , further comprising an inner spacer layer disposed on both sides of each of the gate structures along the first direction.

11. Each of the plurality of sets of channel layers disposed on the first active pattern includes a channel layer having the first set width along the second direction and aligned continuously; Each of the plurality of sets of channel layers disposed on the second active pattern includes a second set of widths in the second direction and is continuously aligned, each of the second set of widths being smaller than each of the first set of widths; 2. The semiconductor device of claim 1, wherein each of the plurality of sets of channel layers disposed on the switching active pattern includes continuously aligned channel layers having a third set of widths in the second direction, each of the third set of widths being smaller than each of the first set of widths and larger than each of the second set of widths.

12. At the first height, the first active pattern and the second active pattern each have a constant width in the second direction, 12. The semiconductor device of claim 11, wherein at the first height, a width of the switching active pattern in the second direction gradually increases or decreases along the first direction.

13. A substrate; an active region including a first active pattern extending in a first direction on the substrate, the first active pattern having a first width in a second direction at a first height in a vertical direction on a lower surface of the substrate, a second active pattern having a second width different from the first width in the second direction, and a switching active pattern connecting the first active pattern and the second active pattern; a gate structure including respective gate structures on the substrate intersecting the active region and extending in a second direction; a source / drain region disposed on a side of the gate structure, the source / drain region including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a switching source / drain region disposed on the switching active pattern; each of the source / drain regions includes a first epitaxial layer disposed over the active region and having a recessed upper surface and a second epitaxial layer disposed over the first epitaxial layer; a first sidewall thickness of the first epitaxial layer of the first source / drain region along the first direction is different from a second sidewall thickness of the first epitaxial layer of the second source / drain region along the first direction at a second height above a bottom surface of the substrate in the vertical direction; At the second height, opposing sidewalls of the first epitaxial layer of the conversion source / drain regions have different thicknesses along the first direction; A semiconductor device, wherein a vertical level of a bottom end of the second epitaxial layer of the first source / drain region, a vertical level of a bottom end of the second epitaxial layer of the second source / drain region, and a vertical level of a bottom end of the second epitaxial layer of the conversion source / drain region are different from each other.

14. 14. The semiconductor device of claim 13, wherein a width of the switching active pattern along the second direction at the first height gradually decreases or increases in the first direction.

15. the active region further includes a third active pattern having a third width different from the first width and the second width; the source / drain region further includes a third source / drain region on the third active pattern; an additional switching active pattern connecting the second active pattern and the third active pattern; 14. The semiconductor device of claim 13, wherein at the second height, a third sidewall thickness of the first epitaxial layer of the third source / drain region along the first direction is different from the first sidewall thickness and the second sidewall thickness.

16. The first width is greater than the second width, The second width is greater than the third width, the first sidewall thickness is greater than the second sidewall thickness; The semiconductor device of claim 15 , wherein the second sidewall thickness is greater than the third sidewall thickness.

17. the first width is greater than the second width and the third width; The third width is greater than the second width, the first sidewall thickness is greater than the second sidewall thickness and the third sidewall thickness; The semiconductor device of claim 15 , wherein the third sidewall thickness is greater than the second sidewall thickness.

18. the first active pattern is symmetrical in the second direction with respect to a central axis of the first active pattern extending in the first direction; the second active pattern is symmetrical in the second direction with respect to a central axis of the second active pattern extending in the first direction; The semiconductor device of claim 13 , wherein a central axis of the first active pattern and a central axis of the second active pattern are shifted from each other.

19. A substrate; an active region including a first active pattern extending in a first direction on the substrate and having a first width in a second direction intersecting the first direction, a second active pattern having a second width in the second direction smaller than the first width, and a switching active pattern connecting the first active pattern and the second active pattern; a gate structure on the substrate, the gate structure intersecting the active region and extending in the second direction; a plurality of sets of channel layers extending in the first direction and continuously disposed from the active region, each set including a channel layer surrounded by a respective gate structure on the active region and spaced apart from one another in a third direction perpendicular to an upper surface of the substrate, the channel layers of the plurality of sets being spaced apart from one another in the first direction; a source / drain region disposed between the gate structures adjacent to each other in the first direction, the source / drain region including a first source / drain region disposed on the first active pattern, a second source / drain region disposed on the second active pattern, and a switching source / drain region disposed on the switching active pattern; each of the source / drain regions is disposed on the active region and includes a first epitaxial layer disposed between adjacent ones of the sets of channel layers and a second epitaxial layer disposed on the first epitaxial layer; At a first vertical height above a bottom surface of the substrate, the converted source / drain region has a first converted sidewall thickness along the first direction of the first epitaxial layer of the converted source / drain region and a second converted sidewall thickness less than the first converted sidewall thickness; A semiconductor device, wherein a vertical level of a bottom end of the second epitaxial layer of the conversion source / drain region is higher than a vertical level of a bottom end of the second epitaxial layer of the first source / drain region and lower than a vertical level of a bottom end of the second epitaxial layer of the second source / drain region.

20. a width of the switching active pattern along the second direction at a second vertical height above a bottom surface of the substrate that gradually decreases or increases in the first direction; each set of channel layers disposed on the switching active pattern includes a set of widths in the second direction and contiguously aligned channel layers; 20. The semiconductor device of claim 19, wherein at the first vertical height, the first active patterns and the second active patterns each have a constant width in the second direction.

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