Semiconductor device, power conversion device, and manufacturing method thereof

Abstract

To improve the semiconductor chip mounting capacity.SOLUTION: A semiconductor device includes: a semiconductor chip 20 having a source electrode 21s and a gate electrode 21g on a first surface and a drain electrode 21d on a second surface opposite the first surface; a source terminal 10 having a fourth surface exposed from a third surface SF2 of a package and a fifth surface connected to the source electrode and having a shape different from that of the fourth surface; a gate terminal 11 having a sixth surface exposed from the third surface of the package and a seventh surface connected to the gate electrode and having a shape different from that of the sixth surface; and a drain terminal 12 connected to the drain electrode and having an eighth surface exposed from the third surface of the package.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device, a power conversion device, and a manufacturing method thereof. [Background technology]

[0002] 2. Description of the Related Art As switching elements used in power conversion devices (for example, DC-DC converters), semiconductor devices such as power MOSFETs that are surface-mounted on printed circuit boards are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-145046 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of improving the mounting capacity of a semiconductor chip is provided. [Means for solving the problem]

[0005] The semiconductor device of the embodiment includes a semiconductor chip having a source electrode and a gate electrode on a first surface and a drain electrode on a second surface opposite the first surface, a source terminal having a fourth surface exposed from the third surface of the package and a fifth surface connected to the source electrode and having a shape different from that of the fourth surface, a gate terminal having a sixth surface exposed from the third surface of the package and a seventh surface connected to the gate electrode and having a shape different from that of the sixth surface, and a drain terminal connected to the drain electrode and having an eighth surface exposed from the third surface of the package. [Brief description of the drawings]

[0006] [Figure 1] 1 is a plan view of a package surface of the semiconductor device according to the first embodiment. [Diagram 2]FIG. 2 is a plan view of the back surface of the package of the semiconductor device according to the first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line A1-A2 in FIGS. [Figure 4] FIG. 4 is a cross-sectional view taken along line B1-B2 in FIGS. [Diagram 5] 1 is a plan view of a first surface of a semiconductor chip included in the semiconductor device according to a first embodiment. [Figure 6] FIG. 5 is a plan view taken along line C1-C2 in FIGS. 3 and 4. [Figure 7] FIG. 5 is a plan view taken along line D1-D2 in FIGS. 3 and 4. [Figure 8] 2A to 2C are diagrams showing the flow of an assembly process for the semiconductor device according to the first embodiment. [Figure 9] FIG. 11 is a plan view of a package surface of a semiconductor device according to a second embodiment. [Figure 10] FIG. 11 is a plan view of the back surface of the package of the semiconductor device according to the second embodiment. [Figure 11] 11 is a cross-sectional view taken along line A3-A4 in FIGS. 9 and 10. FIG. [Figure 12] 11 is a cross-sectional view taken along line B3-B4 in FIGS. 9 and 10. FIG. [Figure 13] FIG. 13 is a plan view taken along line C3-C4 in FIGS. 11 and 12. [Figure 14] FIG. 13 is a plan view taken along line D3-D4 in FIGS. 11 and 12. [Figure 15] 10A to 10C are diagrams showing the flow of an assembly process for a semiconductor device according to a second embodiment. [Figure 16] FIG. 11 is a plan view of a package surface of a semiconductor device according to a third embodiment. [Figure 17] A cross-sectional view taken along line A5-A6 in Figure 16. [Figure 18] A cross-sectional view taken along line B5-B6 in Figure 16. [Figure 19] 10A to 10C are diagrams showing the flow of an assembly process for a semiconductor device according to a third embodiment. [Figure 20] FIG. 13 is a plan view of a package surface of a semiconductor device according to a fourth embodiment. [Figure 21] A cross-sectional view taken along line A7-A8 in Figure 20. [Figure 22] A cross-sectional view taken along line B7-B8 in Figure 20. [Diagram 23] 10A to 10C are diagrams showing the flow of an assembly process for a semiconductor device according to a fourth embodiment. [Figure 24] FIG. 13 is a circuit diagram of a power conversion device according to a fifth embodiment. [Diagram 25] FIG. 13 is a plan view of a power conversion device according to a fifth embodiment. [Figure 26] 26 is a cross-sectional view taken along line X1-X2 in FIG. 25. [Figure 27] FIG. 13 is a plan view of a power conversion device according to a sixth embodiment. [Figure 28] 28 is a cross-sectional view taken along line X3-X4 in FIG. 27. [Figure 29] FIG. 13 is a plan view of a power conversion device according to a seventh embodiment. [Diagram 30] 29 along line X5-X6 in FIG. 29 . DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. In the following description, components having the same functions and configurations are given common reference symbols. In addition, the embodiments shown below are examples of devices and methods for embodying the technical ideas of the embodiments, and the materials, shapes, structures, arrangements, etc. of the components are not specified as described below. In addition, in the drawings referred to below, components such as insulating layers, coating films, wiring, contacts, etc. are omitted as appropriate in this specification to make the drawings easier to see.

[0008] 1. First embodiment First, a first embodiment will be described. In the first embodiment, a semiconductor device 1 including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) functioning as a switching element will be described. The MOSFET is used in a power conversion device, for example, a DC-DC converter or an inverter. The substrate on which the MOSFET is formed may be a Si substrate or a SiC substrate. The semiconductor device 1 may include an IGBT (Insulated Gate Bipolar Transistor) formed on the Si substrate instead of the MOSFET.

[0009] 1.1 Structure of semiconductor device 1.1.1 Planar structure of semiconductor device First, an example of the planar configuration of the semiconductor device 1 will be described. FIG. 1 is a plan view of the package front surface of the semiconductor device 1. FIG. 2 is a plan view of the package back surface of the semiconductor device 1. In the following description, when the semiconductor device 1 is surface-mounted on a printed circuit board, for example, the mounting surface that is joined to the printed circuit board is referred to as the "package back surface". Also, the surface of the semiconductor device 1 that faces the package back surface is referred to as the "package front surface". In the examples of FIG. 1 and FIG. 2, the plane along the package front surface and package back surface is referred to as the XY plane. Furthermore, on the package back surface, the direction connecting the drain terminal and the source terminal is referred to as the X direction, and the direction intersecting the X direction is referred to as the Y direction. Also, the direction intersecting the XY plane is referred to as the Z direction. The surface of the semiconductor device 1 facing the X direction or the Y direction is referred to as the "package side surface".

[0010] As shown in FIG. 1 and FIG. 2, the semiconductor device 1 includes a source terminal 10, a gate terminal 11, a drain terminal 12, and a molded resin 13. An etched lead frame (hereinafter, also referred to as an "etched frame") is used for the source terminal 10, the gate terminal 11, and the drain terminal 12. The source terminal 10, the gate terminal 11, and the drain terminal 12 are made of a conductive material, for example, copper. The conductive material may also include a high melting point material. The surface of each terminal exposed from the molded resin 13 (hereinafter, referred to as an "exposed surface") may be covered with tin (Sn), solder, or the like, or may not be covered. The semiconductor device 1 of this embodiment can be applied to surface mounting and vertical mounting. For example, in the case of surface mounting, the exposed surface is covered with tin, solder, or the like. Also, for example, in the case of vertical mounting, the exposed surface of each terminal is not covered with tin, solder, or the like. For example, when the semiconductor device 1 is embedded in a printed circuit board by vertical mounting, Cu-plated wiring is formed. For this reason, it is preferable that the exposed surfaces of the terminals are not covered with tin, solder, etc. Although Fig. 1 and Fig. 2 show a structure in which each terminal (lead terminal) does not protrude from the molded resin 13 (i.e., package), such as DFN (Dual Flatpack Non-leaded), the present invention is not limited to this. Each terminal may protrude from the molded resin 13.

[0011] The source terminal 10 and the gate terminal 11 have exposed surfaces on the back surface of the package. The exposed surfaces of the source terminal 10 and the gate terminal 11 are electrically connected to a printed circuit board via solder or the like. The exposed surfaces of the source terminal 10 and the gate terminal 11 may have any shape. In the example of FIG. 2, four protrusions are provided on one end of the source terminal 10 facing the X direction. For example, the four protrusions extend to an end of the molded resin 13 (package) facing the X direction. The four protrusions are exposed on the side of the package facing the X direction on the extending side. Note that, in the assembly process of the semiconductor device 1, when a plurality of semiconductor devices 1 are diced into individual pieces, the cut surface of the etching frame forming the source terminal 10 may be exposed from the side of the package.

[0012] The exposed surface of the gate terminal 11 has, for example, a rectangular shape. For example, one end of the gate terminal 11 facing the Y direction extends to an end of the molding resin 13 facing the Y direction. The gate terminal 11 is exposed on a package side surface facing the Y direction.

[0013] The exposed surface of the drain terminal 12 is provided on the front surface and the back surface of the package. For example, the drain terminal 12 can be electrically connected to a printed circuit board on the front surface or the back surface of the package. The shape of the exposed surface of the drain terminal 12 is arbitrary. In the example of FIG. 1, the exposed surface of the drain terminal 12 on the front surface of the package is rectangular. For example, one end of the drain terminal 12 facing the X direction extends to an end of the molded resin 13 facing the X direction. Also, in the example of FIG. 2, the exposed surface of the drain terminal 12 on the back surface of the package faces the source terminal 10 in the X direction. Four protrusions are provided on one end of the drain terminal 12 facing the X direction. For example, the four protrusions extend to an end of the molded resin 13 facing the X direction. The drain terminal 12 is exposed on a package side surface facing the X direction.

[0014] The mold resin 13 seals the semiconductor device 1. The mold resin 13 stably maintains the insulating state and arrangement between a semiconductor chip (not shown), a source terminal 10, a gate terminal 11, and a drain terminal 12 in the semiconductor device 1. For example, an epoxy resin is used for the mold resin 13. The mold resin 13 may contain a filler such as silicon oxide.

[0015] 1.1.2 Cross-sectional structure of semiconductor device Next, an example of the cross-sectional configuration of the semiconductor device 1 will be described. Fig. 3 is a cross-sectional view taken along line A1-A2 in Fig. 1 and Fig. 2. Fig. 4 is a cross-sectional view taken along line B1-B2 in Fig. 1 and Fig. 2. Fig. 5 is a plan view of the first surface of the semiconductor chip 20. Note that in the example of Fig. 5, conductive layers 23s and 23g, which will be described later, are omitted.

[0016] As shown in FIGS. 3 and 4, the semiconductor device 1 further includes a semiconductor chip 20, and mounting materials 31s, 31g, and 31g.

[0017] The semiconductor chip 20 is, for example, a MOSFET. The semiconductor chip 20 is disposed between the source terminal 10 and the gate terminal 11 and the drain terminal 12. In the following description, the surface of the semiconductor chip 20 that intersects with the Z direction and faces the source terminal 10 and the gate terminal 11 is referred to as the "first surface." In addition, the surface of the semiconductor chip 20 that faces the first surface and faces the drain terminal 12 is referred to as the "second surface."

[0018] The semiconductor chip 20 includes a source electrode 21s, a gate electrode 21g, a drain electrode 21d, a passivation film 22, and conductive layers 23s and 23g.

[0019] A source electrode 21s and a gate electrode 21g are provided on the first surface of the semiconductor chip 20. As shown in Fig. 5, a passivation film 22 is provided so as to surround the source electrode 21s and the gate electrode 21g. A conductive layer 23s and a conductive layer 23g are provided on the source electrode 21s and the gate electrode 21g, respectively. A configuration in which the second surface of the semiconductor chip 20 on which the source electrode 21s and the like are provided faces the package back surface SF2 may also be referred to as a "source-down package."

[0020] As shown in FIGS. 3 and 4, a drain electrode 21d is provided on the second surface of the semiconductor chip 20.

[0021] The source electrode 21s is connected to the source of the MOSFET. The gate electrode 21g is connected to the gate of the MOSFET. The drain electrode 21d is connected to the drain of the MOSFET. The source electrode 21s, the gate electrode 21g, and the drain electrode 21d are made of a conductive material. The source electrode 21s and the gate electrode 21g include, for example, aluminum. The drain electrode 21d includes, for example, any one of a titanium / nickel / gold stacked film, an alloy of gold and silver, or silver.

[0022] The passivation film 22 physically and electrically separates the source electrode 21s and the gate electrode 21g. The passivation film 22 is made of, for example, a resin material such as polyimide.

[0023] The conductive layers 23s and 23g are formed by, for example, a dry process such as sputtering or vapor deposition, or a wet process such as electrolytic plating or electroless plating. The conductive layers 23s and 23g include, for example, at least one of copper, nickel, silver, gold, and palladium.

[0024] The mounting material 31s bonds the conductive layer 23s to the source terminal 10. The mounting material 31g bonds the conductive layer 23g to the gate terminal 11. The mounting material 31d bonds the drain electrode 21d to the drain terminal 12. Hereinafter, the surfaces of the source terminal 10, the gate terminal 11, and the drain terminal 12 that are bonded to the semiconductor chip 20 are referred to as "chip bonding surfaces". The mounting materials 31s, 31g, and 31d are made of a conductive material. For example, solder is used for the mounting materials 31s, 31g, and 31d. Note that a sintered material that is difficult to melt (for example, any of copper, silver, lead, a tin-copper compound, a tin-silver compound, or a tin-nickel compound) may be used instead of the solder. In that case, a pressure sintered material that has excellent pressure resistance may be used.

[0025] The source terminal 10 and the gate terminal 11 are formed of the same etching frame, and therefore the thickness (height in the Z direction) of the source terminal 10 and the gate terminal 11 are approximately the same.

[0026] The source terminal 10 has a half-etched region HE that is half-etched in the Z direction from the exposed surface of the package back surface SF2. In other words, the source terminal 10 has a protruding portion on the chip bonding surface side that protrudes from the exposed surface in the X direction and / or Y direction. A part of the end of the chip bonding surface of the source terminal 10 protrudes from the exposed surface. The height of the half-etched region HE in the Z direction is arbitrary. In the example of FIG. 3 and FIG. 4, the half-etched region HE is provided from the exposed surface of the package back surface SF2 (the lower side of the paper) toward the chip bonding surface with the semiconductor chip 20 at both ends in the X direction. Therefore, the area and shape of the exposed surface of the source terminal 10 are different from the area and shape of the chip bonding surface. Also, in the example of FIG. 3 and FIG. 4, the protruding portion on the chip bonding surface side of the source terminal 10 in the X direction is exposed from the side of the package. By expanding the chip bonding surface to the side of the package, the chip size of the semiconductor chip 20 that can be mounted on the semiconductor device 1 can be increased.

[0027] As shown in FIG. 4, the gate terminal 11 has a half-etched region HE that is half-etched from the exposed surface in the Z direction, and a half-etched region HE that is half-etched from the chip bonding surface in the Z direction. That is, the gate terminal 11 has a shape that is half-etched from both the exposed surface and the chip bonding surface. In other words, the gate terminal 11 has a protrusion that protrudes from the exposed surface in the X direction and / or Y direction on the chip bonding surface side, and a protrusion that protrudes from the chip bonding surface in the X direction and / or Y direction on the exposed surface side. The height in the Z direction of the half-etched region HE that is half-etched from the exposed surface of the gate terminal 11 in the Z direction is approximately the same as the height in the Z direction of the half-etched region HE of the source terminal 10. The area and shape of the exposed surface of the gate terminal 11 are different from the area and shape of the chip bonding surface. This allows the exposed surface of the gate terminal 11 to be provided at any position on the package back surface SF2 regardless of the position of the gate electrode 21g of the semiconductor chip 20.

[0028] For example, the etching frame constituting the drain terminal 12 is formed by etching a lead frame that is thicker than the etching frames constituting the source terminal 10 and the gate terminal 11. For example, the etching frame used for the drain terminal 12 has the same thickness as the package. The etching frame is etched from the rear surface side of the package to form areas on which the semiconductor chip 20, the source terminal 10, and the gate terminal 11 are mounted.

[0029] The drain terminal 12 includes a first portion 12a and a second portion 12b. The first portion 12a is a plate-like portion extending on the XY plane. The surface of the first portion 12a facing the package front surface is exposed from the package front surface SF1. The surface of the first portion 12a facing the package back surface is a chip bonding surface to which the drain electrode 21d is bonded via a mounting material 31d. One end of the second portion 12b is connected to an end of the first portion 12a in the X direction. The second portion 12b extends in the Z direction. The other end of the second portion 12b is exposed to the package back surface SF2.

[0030] The second portion 12b of the drain terminal 12 has a half-etched region HE that is half-etched in the Z direction from the exposed surface of the package back surface SF2 on the package side surface facing the X direction. In other words, the drain terminal 12 has a protrusion that protrudes in the X direction from the exposed surface. The height in the Z direction of the half-etched region HE of the drain terminal 12 may be different from the height in the Z direction of the half-etched regions HE of the source terminal 10 and the gate terminal 11. For example, the length in the Z direction of the half-etched region HE of the drain terminal 12 is longer than the length in the Z direction of the half-etched regions HE of the source terminal 10 and the gate terminal 11. In the X direction, the end (protrusion) of the drain terminal that is not half-etched is exposed from the package side surface.

[0031] In the example of Figures 3 and 4, the half-etched regions HE of the source terminal 10 and the drain terminal 12 on the side surface of the package are sealed with molded resin 13, but the molded resin 13 in this region may be omitted. That is, the half-etched regions HE of each terminal may be exposed on the side surface of the package. The same applies to the Y-direction end of the gate terminal 11 (not shown). This allows the semiconductor device 1 to be compatible with wettable flanks. For example, when the semiconductor device 1 is surface-mounted on a printed circuit board, it can be confirmed that the soldering operation has been performed correctly by seeing that the solder has flowed around the half-etched regions HE exposed on the side surface of the package.

[0032] Similarly to the gate terminal 11, the source terminal 10 may have a half-etched region HE that is half-etched in the Z direction from the chip bonding surface. In order to improve the mounting accuracy of the semiconductor chip 20, a slit (half-etched region HE) that matches the chip size may be formed in the chip bonding surface of the source terminal 10.

[0033] 1.1.3 Planar configuration of each terminal Next, an example of the planar configuration of each terminal will be described. FIG. 6 is a plan view taken along the C1-C2 line in FIG. 3 and FIG. 4. FIG. 7 is a plan view taken along the D1-D2 line in FIG. 3 and FIG. 4. FIG. 6 shows the shape of the chip bonding surface of the source terminal 10 and the gate terminal 11, and the part of the drain terminal 12 that does not include the half-etched region HE. FIG. 7 shows the shape of the exposed surface of the package back surface SF2 of the source terminal 10, the gate terminal 11, and the drain terminal 12. FIG. 6 and FIG. 7 show the plan view seen from the package front surface side. In FIG. 6 and FIG. 7, the chip region where the semiconductor chip 20 is arranged is indicated by a dashed line. The following description will be focused on the source terminal 10 and the gate terminal 11.

[0034] 6 and 7, the shape of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 is different from the shape of the exposed surface of the package back surface SF2. For example, the area of ​​the chip bonding surfaces of the source terminal 10 and the gate terminal 11 is larger than the area of ​​the exposed surface of the package back surface SF2. For example, the position of the bonding surface of the gate terminal 11 on the XY plane is different from the position of the exposed surface of the gate terminal 11 on the XY plane.

[0035] The shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 are designed based on the semiconductor chip 20 to be mounted on the semiconductor device 1. For example, the end of the chip bonding surface of the source terminal 10 extends to the side surface of the package. This improves the degree of freedom in the layout of the source electrode 21s and the gate electrode 21g of the compatible semiconductor chip 20. In addition, the chip size of the mountable semiconductor chip 20 can be made larger than the layout of the exposed surfaces of the source terminal 10 and the gate terminal 11. This improves the mounting capacity of the semiconductor chip 20.

[0036] The shapes of the exposed surfaces of the source terminal 10, the gate terminal 11, and the drain terminal 12 on the package back surface SF2 can be made compatible with the layout of, for example, an existing DFN, etc. This improves the versatility (compatibility) of the semiconductor device 1.

[0037] 1.2 Manufacturing method of semiconductor device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Fig. 8 is a diagram showing the flow of an assembly process. Note that, for the sake of simplicity, the example of Fig. 8 shows a cross section of the semiconductor device 1 taken along line A1-A2 in Figs. 1 and 2, and the gate terminal 11 is omitted. Also, in the example of Fig. 8, the source electrode 21s, the gate electrode 21g, the drain electrode 21d, the passivation film 22, and the conductive layers 23s and 23g are omitted.

[0038] As shown in FIG. 8(a), first, a first etching frame is prepared on which a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 are provided. A semiconductor chip 20 is mounted on the source terminal 10 and the gate terminal 11 with a mounting material 31s and a mounting material 31g, respectively, so that the source terminal 10 is connected to the source electrode 21s and the gate terminal 11 is connected to the gate electrode 21g (S1). Next, a second etching frame on which a drain terminal 12 is provided is mounted on the drain electrode 21d of the semiconductor chip 20 with a mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. If the residue of the mounting material 31 does not cause defects such as poor insulation or peeling, cleaning may be omitted. Alternatively, the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame provided with the source terminal 10 and the gate terminal 11 may be mounted in this order on the second etching frame provided with the drain terminal 12.

[0039] 8(b), the multiple semiconductor devices 1 sharing the first and second etching frames are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed. During molding, the etching frames may be covered with a release film to prevent the molding resin from getting into the half-etched portions.

[0040] 8(c), the molding resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6), thereby dividing the semiconductor device 1 into individual pieces. The cut surfaces of the first etching frame and the second etching frame cut by dicing may be exposed on the side surface of the package.

[0041] With the configuration according to this embodiment, a half-etched etching frame can be applied to the source terminal 10, the gate terminal 11, and the drain terminal 12 of the semiconductor device 1. This allows the exposed surfaces of the source terminal 10 and the gate terminal 11 to have a different shape from the chip bonding surface. The layout of the chip bonding surface is not limited to the layout of the exposed surface. This improves the degree of freedom in the layout of the semiconductor chip 20. In addition, the mountable chip size can be increased. This improves the mounting capacity of the semiconductor chip 20.

[0042] Furthermore, the exposed surfaces of the source terminal 10 and the gate terminal 11 can be made to have the same layout as that of a ready-made product, thereby improving the compatibility and versatility of the semiconductor device 1.

[0043] Furthermore, with the configuration according to this embodiment, the drain terminal 12 can be exposed on both the package front surface SF1 and the package back surface SF2, thereby improving the heat dissipation performance of the semiconductor device 1.

[0044] Furthermore, the drain terminal 12 can be electrically connected to the printed circuit board from either the package front surface SF1 or the package back surface SF2. That is, the semiconductor device 1 has two mounting surfaces. Therefore, the semiconductor device 1 can be applied not only to surface mounting, but also to vertical mounting, such as embedding the semiconductor device in a printed circuit board. That is, the degree of freedom in mounting the semiconductor device 1 can be improved.

[0045] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a configuration of the semiconductor device 1 different from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0046] 2.1 Configuration of semiconductor device 2.1.1 Planar structure of semiconductor device First, there will be described an example of the planar configuration of the semiconductor device 1. Fig. 9 is a plan view of a package front surface SF1 of the semiconductor device 1. Fig. 10 is a plan view of a package back surface SF2 of the semiconductor device 1.

[0047] As shown in Fig. 9 and Fig. 10, in this embodiment, exposed surfaces of the drain terminal 12 are provided at both ends in the X direction on the package back surface SF2. In the example of Fig. 9, the exposed surface of the drain terminal 12 on the package front surface SF1 has a rectangular shape. For example, both ends of the drain terminal 12 facing the X direction extend to both ends of the molded resin 13 facing the X direction. Also, in the example of Fig. 10, four protrusions are provided on each of the two exposed surfaces of the drain terminal 12 provided at both ends in the X direction. For example, the four protrusions extend to the ends of the molded resin 13 facing the X direction.

[0048] The exposed surface of the source terminal 10 is provided in the center of the back surface SF2 of the package, and is not in contact with any end of the molded resin 13. Note that the end of the exposed surface of the source terminal 10 facing the Y direction may extend to the end of the molded resin 13 facing the Y direction.

[0049] The exposed surface of the gate terminal 11 is similar to that described with reference to FIG. 2 in the first embodiment.

[0050] 2.1.2 Cross-sectional structure of semiconductor device Next, a description will be given of an example of a cross-sectional configuration of the semiconductor device 1. Fig. 11 is a cross-sectional view taken along line A3-A4 in Fig. 9 and Fig. 10. Fig. 12 is a cross-sectional view taken along line B3-B4 in Fig. 9 and Fig. 10.

[0051] 11 and 12, the source terminal 10 has a half-etched region HE that is half-etched in the Z direction from the exposed surface, similarly to the description of the first embodiment. In the example of Fig. 11, the half-etched region HE is formed at one end of the source terminal 10 facing the X direction, but the half-etched regions HE may be formed at both ends facing the X direction.

[0052] The gate terminal 11 is the same as that described with reference to FIG. 4 in the first embodiment.

[0053] The drain terminal 12 includes a first portion 12a, a second portion 12b, and a third portion 12c. The first portion 12a is a plate-like portion extending on the XY plane. The surface of the first portion 12a facing the package front surface is exposed from the package front surface SF1. The surface of the first portion 12a facing the package back surface is a chip bonding surface to which the drain electrode 21d is bonded via a mounting material 31d. One end of the second portion 12b is connected to one end of the first portion 12a in the X direction. The second portion 12b extends in the Z direction. The other end of the second portion 12b is exposed to the package back surface SF2. One end of the third portion 12c is connected to the other end of the first portion 12a in the X direction. The third portion 12c extends in the Z direction. The other end of the third portion 12c is exposed to the package back surface SF2. The third portion 12c faces the second portion 12b in the X direction, with the semiconductor chip 20 interposed therebetween.

[0054] The second portion 12b and the third portion 12c of the drain terminal 12 have half-etched regions HE at both ends facing the X direction, which are half-etched in the Z direction from the exposed surface of the package back surface SF2. In the X direction, two ends of the drain terminal that are not half-etched are exposed from the side surfaces of the package.

[0055] 2.1.3 Terminal layout Next, an example of the planar configuration of each terminal will be described. FIG. 13 is a plan view taken along the C3-C4 line in FIG. 11 and FIG. 12. FIG. 14 is a plan view taken along the D3-D4 line in FIG. 11 and FIG. 12. FIG. 13 shows the shape of the chip bonding surface of the source terminal 10 and the gate terminal 11, and the part of the drain terminal 12 that does not include the half-etched region HE. FIG. 14 shows the shape of the exposed surface of the package back surface SF2 of the source terminal 10, the gate terminal 11, and the drain terminal 12. FIG. 13 and FIG. 14 show plan views seen from the package front surface side. The following description will be focused on the source terminal 10 and the gate terminal 11.

[0056] 13 and 14, the shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 are different from the shape of the exposed surface of the package back surface SF2. The shapes of the chip bonding surfaces of the source terminal 10 and the gate terminal 11 do not correspond to the shape of the exposed surface. The semiconductor chip 20 is disposed between two drain terminals 12 provided at both ends in the X direction.

[0057] 2.2 Manufacturing method of semiconductor device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Fig. 15 is a diagram showing the flow of an assembly process. Note that, for the sake of simplicity, the example of Fig. 15 shows a cross section of the semiconductor device 1 taken along line A3-A4 in Figs. 9 and 10, and the gate terminal 11 is omitted. Also, in the example of Fig. 15, the source electrode 21s, the gate electrode 21g, the drain electrode 21d, the passivation film 22, and the conductive layers 23s and 23g are omitted.

[0058] As shown in (a) of FIG. 15, similarly to the description using FIG. 8 of the first embodiment, first, a first etching frame provided with a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 is prepared. A semiconductor chip 20 is mounted on the source terminal 10 and the gate terminal 11 with a mounting material 31s and a mounting material 31g interposed therebetween, respectively, so that the source terminal 10 is connected to the source electrode 21s and the gate terminal 11 is connected to the gate electrode 21g (S1). Next, a second etching frame provided with a drain terminal 12 is mounted on the drain electrode 21d of the semiconductor chip 20 with a mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Note that the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame provided with the source terminal 10 and the gate terminal 11 may be mounted in order on the second etching frame provided with the drain terminal 12.

[0059] 15(b), the plurality of semiconductor devices 1 sharing the first etching frame and the second etching frame are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed.

[0060] 15(c), the molding resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6), thereby dividing the semiconductor device 1 into individual pieces. The cut surfaces of the first etching frame and the second etching frame cut by dicing may be exposed on the side surface of the package.

[0061] With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0062] In the second embodiment, the case where the exposed surfaces of the drain terminal 12 are provided at both ends in the X direction on the package back surface SF2 has been described, but the present invention is not limited to this. For example, the exposed surfaces of the drain terminal 12 may be provided at four ends or four corners of the package back surface SF2.

[0063] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a configuration of the semiconductor device 1 different from those of the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0064] 3.1 Configuration of semiconductor device 3.1.1 Planar structure of semiconductor device First, a description will be given of an example of the planar configuration of the semiconductor device 1. Fig. 16 is a plan view of the package surface SF1 of the semiconductor device 1.

[0065] As shown in Fig. 16, the semiconductor device 1 of this embodiment further includes a heat sink 40 in addition to the configuration described in the first embodiment. The heat sink 40 is made of a conductive material with excellent thermal conductivity. For example, copper is used for the heat sink 40. For example, the heat sink 40 is provided on the entire surface of the package front surface SF1. Note that the configuration of the exposed surfaces of the source terminal 10, gate terminal 11, and drain terminal 12 on the package back surface SF2 is the same as that described with reference to Fig. 2 of the first embodiment.

[0066] 3.1.2 Cross-sectional structure of semiconductor device Next, a description will be given of an example of a cross-sectional configuration of the semiconductor device 1. Fig. 17 is a cross-sectional view taken along line A5-A6 in Fig. 16. Fig. 18 is a cross-sectional view taken along line B5-B6 in Fig. 16.

[0067] As shown in FIGS. 17 and 18, the cross-sectional configurations of the source terminal 10, the gate terminal 11, and the drain terminal 12 are similar to those described with reference to FIGS. 3 and 4 in the first embodiment.

[0068] A heat sink 40 is provided on the package surface SF1 (upper side of the paper in FIGS. 17 and 18). A molded resin 13 is provided between the heat sink 40 and the surface of the drain terminal 12 facing the package surface SF1. The heat sink 40 is not in contact with the drain terminal 12 due to the molded resin 13 being interposed therebetween. In other words, the heat sink 40 is insulated from the source terminal 10, the gate terminal 11, and the drain terminal 12.

[0069] 3.2 Manufacturing method of semiconductor device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Figure 19 is a diagram showing the flow of an assembly process. Note that, for the sake of simplicity, the example of Figure 19 shows a cross section of the semiconductor device 1 taken along line A5-A6 in Figure 16, and the gate terminal 11 is omitted. Also, in the example of Figure 19, the source electrode 21s, the gate electrode 21g, the drain electrode 21d, the passivation film 22, and the conductive layers 23s and 23g are omitted.

[0070] As shown in (a) of FIG. 19, similarly to the description using FIG. 8 of the first embodiment, first, a first etching frame provided with a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 is prepared. A semiconductor chip 20 is mounted on the source terminal 10 and the gate terminal 11 with a mounting material 31s and a mounting material 31g interposed therebetween, respectively, so that the source terminal 10 is connected to the source electrode 21s and the gate terminal 11 is connected to the gate electrode 21g (S1). Next, a second etching frame provided with a drain terminal 12 is mounted on the drain electrode 21d of the semiconductor chip 20 with a mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Note that the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame provided with the source terminal 10 and the gate terminal 11 may be mounted in order on the second etching frame provided with the drain terminal 12.

[0071] 19(b), after the heat sink 40 is mounted (S11), the multiple semiconductor devices 1 sharing the first etching frame and the second etching frame are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed.

[0072] 19(c), the heat sink 40, the molded resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6). This separates the semiconductor device 1. The cut surfaces of the first etching frame, the second etching frame, and the heat sink 40 cut by dicing may be exposed on the side surface of the package.

[0073] The configuration according to this embodiment can improve the mounting capacity of the semiconductor chip 20, similarly to the first embodiment.

[0074] Furthermore, with the configuration according to this embodiment, when the drain terminal 12 is not electrically connected on the package surface SF1, a heat sink 40 can be provided on the package surface SF1. This makes it possible to improve the heat dissipation performance of the semiconductor device 1.

[0075] The structure of the third embodiment can also be applied to the second embodiment.

[0076] 4. Fourth embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a configuration of the semiconductor device 1 different from those of the first to third embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0077] 4.1 Configuration of semiconductor device 4.1.1 Planar structure of semiconductor device First, a description will be given of an example of the planar configuration of the semiconductor device 1. Fig. 20 is a plan view of the package surface SF1 of the semiconductor device 1.

[0078] 20, the semiconductor device 1 of this embodiment further includes an insulating resin 50 in addition to the configuration described in the first embodiment. An insulating material having a higher thermal conductivity than the molded resin 13 is used for the insulating resin 50. The insulating resin 50 preferably has a dielectric strength equal to or higher than that of the molded resin 13, but may have a lower dielectric strength than the molded resin 13. The configuration of the exposed surfaces of the source terminal 10, the gate terminal 11, and the drain terminal 12 on the package back surface SF2 is the same as that described with reference to FIG. 2 of the first embodiment.

[0079] 4.1.2 Cross-sectional structure of semiconductor device Next, a description will be given of an example of a cross-sectional configuration of the semiconductor device 1. Fig. 21 is a cross-sectional view taken along line A7-A8 in Fig. 20. Fig. 22 is a cross-sectional view taken along line B7-B8 in Fig. 20.

[0080] As shown in FIGS. 21 and 22, the cross-sectional configurations of the source terminal 10, the gate terminal 11, and the drain terminal 12 are similar to those described with reference to FIGS. 3 and 4 in the first embodiment.

[0081] For example, insulating resin 50 is provided on the entire surface of package surface SF1 (upper side of the paper in FIGS. 21 and 22). The insulating resin 50 contacts the surface of the drain terminal 12 facing the package surface SF1. Note that mold resin 13 may be provided between the insulating resin 50 and the surface of the drain terminal 12 facing the package surface SF1.

[0082] 4.2 Manufacturing method of semiconductor device Next, an example of a manufacturing method of the semiconductor device 1 will be described. Figure 23 is a diagram showing the flow of an assembly process. Note that, for the sake of simplicity, the example of Figure 23 shows a cross section of the semiconductor device 1 taken along line A7-A8 in Figure 20, and the gate terminal 11 is omitted. Also, in the example of Figure 23, the source electrode 21s, the gate electrode 21g, the drain electrode 21d, the passivation film 22, and the conductive layers 23s and 23g are omitted.

[0083] As shown in (a) of FIG. 23, similarly to the description using FIG. 8 of the first embodiment, first, a first etching frame provided with a plurality of source terminals 10 and a plurality of gate terminals 11 corresponding to a plurality of semiconductor devices 1 is prepared. A semiconductor chip 20 is mounted on the source terminal 10 and the gate terminal 11 with a mounting material 31s and a mounting material 31g interposed therebetween, respectively, so that the source terminal 10 is connected to the source electrode 21s and the gate terminal 11 is connected to the gate electrode 21g (S1). Next, a second etching frame provided with a drain terminal 12 is mounted on the drain electrode 21d of the semiconductor chip 20 with a mounting material 31d interposed therebetween (S2). The second etching frame is thicker than the first etching frame. In this state, reflow (S3) and cleaning (S4) are performed. Note that the mounting material 31d, the semiconductor chip 20, the mounting materials 31s and 31g, and the first etching frame provided with the source terminal 10 and the gate terminal 11 may be mounted in order on the second etching frame provided with the drain terminal 12.

[0084] 23(b), after the insulating resin 50 is formed (S21), the multiple semiconductor devices 1 sharing the etching frame are collectively sealed with the molding resin 13 (S5). That is, a molding process is performed.

[0085] 23(c), the insulating resin 50, the molded resin 13, the first etching frame, and the second etching frame are cut by blade dicing (S6). This separates the semiconductor device 1. The cut surfaces of the first etching frame, the second etching frame, and the insulating resin 50 cut by dicing may be exposed on the side surface of the package.

[0086] The configuration according to this embodiment can improve the mounting capacity of the semiconductor chip 20, similarly to the first embodiment.

[0087] Furthermore, in the configuration according to this embodiment, when the drain terminal 12 is not electrically connected on the package surface SF1, the insulating resin 50 having a higher thermal conductivity than the mold resin 13 can be provided on the package surface SF1. This can improve the heat dissipation performance of the semiconductor device 1.

[0088] The structure of the fourth embodiment can also be applied to the second embodiment.

[0089] 5. Fifth embodiment Next, a fifth embodiment will be described. In the fifth embodiment, a power conversion device 100 including a plurality of the semiconductor devices 1 described in the first embodiment will be described. In the following description, a DC-DC converter will be shown as an example of the power conversion device 100. The following description will focus on the differences from the first embodiment. Note that any of the semiconductor devices 1 described in the second to fourth embodiments may be applied to the power conversion device 100.

[0090] 5.1 Circuit configuration of power conversion device First, a description will be given of an example of a circuit configuration of the power conversion device 100. FIG.

[0091] The power conversion device 100 includes semiconductor devices 1a and 1b, an inductor L1, capacitors C1 and C2, and a gate driver GD. Each of the semiconductor devices 1a and 1b corresponds to the semiconductor device 1 of the first embodiment and includes a MOSFET. The power conversion device 100 also has an input terminal TIN and an output terminal TOUT.

[0092] The input terminal TIN is connected to the drain of the semiconductor device 1a. The input terminal TIN is also connected to a ground voltage node (grounded to the ground GND) via a capacitor C1. For example, the ground voltage node is supplied with a ground voltage VSS.

[0093] The source of the semiconductor device 1a is connected to the drain of the semiconductor device 1b and a first end of the inductor L1.

[0094] The gates of the semiconductor devices 1a and 1b are connected to a gate driver GD.

[0095] The source of the semiconductor device 1b is connected to a ground voltage node.

[0096] A second end of the inductor L1 is connected to the output terminal TOUT and to the ground voltage node via the capacitor C2.

[0097] 5.2 Planar configuration of the power conversion device Next, an example of the planar configuration of the power conversion device 100 will be described. FIG. 25 is a plan view of the power conversion device 100. The example of FIG. 25 is a plan view seen from the upper surface side of the printed circuit board 101. In the following description, the surface on which the inductor L1 and the like are surface-mounted and on which the input terminal TIN and the output terminal TOUT and the like are provided will be referred to as the "upper surface of the printed circuit board". Also, the surface opposite to the mounting surface of the printed circuit board 101 will be referred to as the "lower surface of the printed circuit board". In the example of FIG. 25, capacitors C1 and C2 are omitted to simplify the description.

[0098] As shown in Fig. 25, the power conversion device 100 includes semiconductor devices 1a and 1b, a printed circuit board 101, a gate driver GD, an inductor L1, and capacitors C1 and C2. The semiconductor devices 1a and 1b are arranged such that the package back surface SF2 faces the upper surface of the printed circuit board. In other words, the package front surface SF1 of the semiconductor device 1a and the semiconductor device 1b faces the lower surface of the printed circuit board. Hereinafter, such an arrangement is referred to as "drain down".

[0099] The drain terminals 12 of the semiconductor device 1a and the semiconductor device 1b are connected to a wiring layer of the printed circuit board 101 on the respective package surfaces SF1.

[0100] 5.3 Cross-sectional configuration of power conversion device Next, an example of a cross-sectional configuration of the power conversion device 100 will be described. Fig. 26 is a cross-sectional view of the power conversion device 100 taken along line X1-X2 in Fig. 25. In the example of Fig. 26, not only the cross section but also a part of the contact plugs and wiring layers visible through the cross section are indicated by dashed lines. In the example of Fig. 26, the capacitors C1 and C2 are omitted to simplify the description.

[0101] 26, the power conversion device 100 has a structure in which the semiconductor devices 1a and 1b are embedded in a printed circuit board 101 so as to be drain-down. For example, the gate driver GD and the inductor L1 are surface-mounted on the upper surface of the printed circuit board 101.

[0102] The printed circuit board 101 is a multilayer wiring board having a plurality of wiring layers, a plurality of insulating plates (or insulating layers), and a core material. More specifically, the printed circuit board 101 includes a core material (or insulating material) 102, insulating plates (or insulating layers) 103 and 104, contact plugs 110a, 110b, 110c, 110d, and 110e, wiring layers 111a, 111b, 112a, 112b, 112c, 112d, 112f, 113a, 113b, and 113c, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND (i.e., a ground voltage node).

[0103] Each of the insulating plates 103 and 104 has, for example, a sheet shape and is made of an insulating material in which carbon fiber is impregnated with a thermosetting resin. The contact plugs 110a, 110b, 110c, 110d, and 110e and the wiring layers 111a, 111b, 112a, 112b, 112c, 112d, 112f, 113a, 113b, and 113c are made of a conductive material, for example, including copper.

[0104] The semiconductor devices 1a and 1b are embedded in a printed circuit board 101. More specifically, the semiconductor devices 1a and 1b are provided between insulating plates 103 and 104 in the Z direction. The semiconductor devices 1a and 1b are also provided between core materials 102 in the X and Y directions. The semiconductor devices 1a and 1b are arranged such that their respective package surfaces SF1 face the insulating plate 103. The exposed surfaces of the source terminals 10 and gate terminals 11 of the semiconductor devices 1a and 1b face the insulating plate 104 (the upper surface of the printed circuit board).

[0105] In other words, the drain-down semiconductor devices 1a and 1b are provided at a distance from each other on the insulating plate 103. An insulating plate 104 is provided on top of the semiconductor devices 1a and 1b (on the back surface side of the package). The sides of the semiconductor devices 1a and 1b contact the core material 102. That is, the semiconductor devices 1a and 1b are provided in the same layer as the core material 102.

[0106] On the insulating plate 104, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND are provided.

[0107] Contact plugs 110a and 110b are provided in the insulating plate 104 and the core material 102. Each of the contact plugs 110a and 110b extends in the insulating plate 104 and the core material 102 in the Z direction.

[0108] Contact plugs 110c, 110d, and 110e are provided in the insulating plate 104. The contact plugs 110c, 110d, and 110e extend within the insulating plate 104 in the Z direction.

[0109] A wiring layer 111a is provided between the drain terminal 12 of the semiconductor device 1a and the insulating plate 103. The wiring layer 111a extends on the XY plane. A wiring layer 112a is provided between the gate terminal 11 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112a extends on the XY plane. Wiring layers 112b and 112c are provided between the source terminal 10 of the semiconductor device 1a and the insulating plate 104. The wiring layers 112b and 112c extend on the XY plane.

[0110] A wiring layer 111b is provided between the drain terminal 12 of the semiconductor device 1b and the insulating plate 103. The wiring layer 111b extends on the XY plane. A wiring layer 112d is provided between the gate terminal 11 of the semiconductor device 1b and the insulating plate 104. Wiring layers 112e and 112f are provided between the source terminal 10 of the semiconductor device 1b and the insulating plate 104. The wiring layers 112e and 112f extend on the XY plane.

[0111] Wiring layers 113a, 113b, and 113c are provided on the insulating plate 104. The wiring layers 113a, 113b, and 113c extend on the XY plane.

[0112] The input terminal TIN is connected to a contact plug 110a. The contact plug 110a is connected to a wiring layer 111a. The wiring layer 111a is connected to the drain terminal 12 of the semiconductor device 1a on the package surface SF1 of the semiconductor device 1a (the lower side of the paper surface of FIG. 26).

[0113] The gate terminal 11 of the semiconductor device 1a is connected to a contact plug 110c via a wiring layer 112a. The contact plug 110c is connected to a gate driver terminal TG.

[0114] The source terminal 10 of the semiconductor device 1a is connected to a contact plug 110b via wiring layers 112b and 112c.

[0115] Furthermore, the contact plug 110b is connected to the wiring layer 111b and the wiring layer 113b. The wiring layer 111b is connected to the drain terminal 12 of the semiconductor device 1b on the package surface SF1 (the lower side of the paper surface in FIG. 26) of the semiconductor device 1b. The wiring layer 113b is connected to a first end of the inductor L1. A second end of the inductor L1 is connected to the output terminal TOUT via the wiring layer 113c. The inductor L1 is, for example, surface-mounted on the printed circuit board 101.

[0116] The gate terminal 11 of the semiconductor device 1b is connected to a contact plug 110d via a wiring layer 112d. The contact plug 110d is connected to a gate driver terminal TG via a wiring layer 113a. The gate driver terminal TG is connected to a gate driver GD.

[0117] The source terminal 10 of the semiconductor device 1b is connected to a contact plug 110e via wiring layers 112e and 112f. The contact plug 110e is connected to a ground terminal TGND.

[0118] According to the configuration of this embodiment, the semiconductor devices 1a and 1b can be easily embedded in the printed circuit board 101, and the power conversion device 100, for example, a DC-DC converter, can be formed in a small area. Other effects are similar to those of the first embodiment.

[0119] 6. Sixth embodiment Next, a sixth embodiment will be described. In the sixth embodiment, a configuration of the power conversion device 100 different from that of the fifth embodiment will be described. The following description will focus on the differences from the fifth embodiment.

[0120] 6.1 Planar configuration of the power conversion device First, an example of the planar configuration of the power conversion device 100 will be described. Fig. 27 is a plan view of the power conversion device 100. The example of Fig. 27 is a plan view seen from the top surface side of the printed circuit board 101. In the example of Fig. 27, capacitors C1 and C2 are omitted for the sake of simplicity of explanation.

[0121] As shown in FIG. 27, the power conversion device 100 includes semiconductor devices 1a and 1b, a printed circuit board 101, a gate driver GD, an inductor L1, and capacitors C1 and C2. The semiconductor device 1a is arranged so as to be drain-down. The semiconductor device 1b is arranged so that the package front surface SF1 faces the upper surface of the printed circuit board. In other words, the package back surface SF2 of the semiconductor device 1b faces the lower surface of the printed circuit board. That is, the exposed surfaces of the source terminal 10 and the gate terminal 11 face the lower surface of the printed circuit board. Hereinafter, such an arrangement will be referred to as "source-down".

[0122] The drain terminals 12 of the semiconductor device 1a and the semiconductor device 1b are connected to a wiring layer of the printed circuit board 101 on the respective package surfaces SF1.

[0123] 6.2 Cross-sectional configuration of power conversion device Next, an example of a cross-sectional configuration of the power conversion device 100 will be described. Fig. 28 is a cross-sectional view of the power conversion device 100 taken along line X3-X4 in Fig. 27. In the example of Fig. 28, not only the cross section but also a part of the contact plugs and wiring layers visible through the cross section are indicated by dashed lines. In the example of Fig. 28, the capacitors C1 and C2 are omitted to simplify the description.

[0124] As shown in FIG. 28, the printed circuit board 101 includes a core material 102, insulating plates 103 and 104, contact plugs 110a, 110b, 110c, 110d, and 110e, wiring layers 111a, 111b, 111c, 111d, 112a, 112b, 112c, 112d, 112e, 113a, 113b, and 113c, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND.

[0125] The semiconductor devices 1a and 1b are embedded in a printed circuit board 101. In this embodiment, the semiconductor device 1a is disposed so that the package front surface SF1 faces the insulating plate 103. The semiconductor device 1b is disposed so that the package back surface SF2 faces the insulating plate 103. That is, the exposed surfaces of the source terminal 10 and the gate terminal 11 of the semiconductor device 1a face the insulating plate 104 (the upper surface of the printed circuit board). The exposed surfaces of the source terminal 10 and the gate terminal 11 of the semiconductor device 1b face the insulating plate 103 (the lower surface of the printed circuit board).

[0126] In other words, the drain-down semiconductor device 1a and the source-down semiconductor device 1b are provided separately on an insulating plate 103. An insulating plate 104 is provided on the semiconductor devices 1a and 1b. The sides of the semiconductor devices 1a and 1b are in contact with the core material 102. That is, the semiconductor devices 1a and 1b are provided in the same layer as the core material 102.

[0127] On the insulating plate 104, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND are provided.

[0128] Contact plugs 110a, 110d, and 110e are provided in the insulating plate 104 and the core material 102. Each of the contact plugs 110a, 110d, and 110e extends in the insulating plate 104 and the core material 102 in the Z direction.

[0129] Contact plugs 110b and 110c are provided in the insulating plate 104. The contact plugs 110b and 110c extend within the insulating plate 104 in the Z direction.

[0130] A wiring layer 111a is provided between the drain terminal 12 of the semiconductor device 1a and the insulating plate 103. The wiring layer 111a extends on the XY plane. A wiring layer 112a is provided between the gate terminal 11 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112a extends on the XY plane. Wiring layers 112b and 112c are provided between the source terminal 10 of the semiconductor device 1a and the insulating plate 104. The wiring layers 112b and 112c extend on the XY plane.

[0131] Between the gate terminal 11 of the semiconductor device 1b and the insulating plate 103, wiring layers 111b and 111c are provided. The wiring layers 111b and 111c extend on the XY plane. Between the source terminal 10 of the semiconductor device 1b and the insulating plate 103, wiring layer 111d is provided. Between the drain terminal 12 of the semiconductor device 1b and the insulating plate 104, wiring layers 112d and 112e are provided. The wiring layers 112d and 112e extend on the XY plane.

[0132] Wiring layers 113a, 113b, and 113c are provided on the insulating plate 104. The wiring layers 113a, 113b, and 113c extend on the XY plane.

[0133] The input terminal TIN is connected to a contact plug 110a. The contact plug 110a is connected to a wiring layer 111a. The wiring layer 111a is connected to the drain terminal 12 of the semiconductor device 1a on the package surface SF1 of the semiconductor device 1a (the lower side of the paper surface of FIG. 28).

[0134] The gate terminal 11 of the semiconductor device 1a is connected to a contact plug 110c via a wiring layer 112a. The contact plug 110c is connected to a gate driver terminal TG.

[0135] Furthermore, the gate driver terminal TG is connected to a contact plug 110d via a wiring layer 113a. The contact plug 110d is connected to the gate terminal 11 of the semiconductor device 1b via wiring layers 111c and 111b.

[0136] The source terminal 10 of the semiconductor device 1a is connected to a contact plug 110b via wiring layers 112b and 112c.

[0137] Furthermore, the contact plug 110b is connected to the wiring layer 112e and the wiring layer 113b. The wiring layer 112e is connected to the wiring layer 112d. The wiring layer 112d is connected to the drain terminal 12 of the semiconductor device 1b on the package surface SF1 (the upper side of the paper surface of FIG. 28) of the semiconductor device 1b. The wiring layer 113b is connected to a first end of the inductor L1. A second end of the inductor L1 is connected to the output terminal TOUT via the wiring layer 113c.

[0138] The source terminal 10 of the semiconductor device 1b is connected to a contact plug 110e through a wiring layer 111d. The contact plug 110e is connected to a ground terminal TGND.

[0139] The configuration according to this embodiment provides the same effects as those of the fifth embodiment, and the other effects are the same as those of the first embodiment.

[0140] 7. Seventh embodiment Next, a seventh embodiment will be described. In the seventh embodiment, a configuration of the power conversion device 100 different from the fifth and sixth embodiments will be described. The following description will focus on the differences from the fifth and sixth embodiments.

[0141] 7.1 Planar configuration of power conversion equipment First, an example of the planar configuration of the power conversion device 100 will be described. Fig. 29 is a plan view of the power conversion device 100. The example of Fig. 29 is a plan view seen from the top surface side of the printed circuit board 101. In the example of Fig. 29, capacitors C1 and C2 are omitted for the sake of simplicity of explanation.

[0142] 29, the power conversion device 100 includes semiconductor devices 1a and 1b, a printed circuit board 101, a gate driver GD, an inductor L1, and capacitors C1 and C2. The semiconductor devices 1a and 1b are arranged so as to be drain-down, as in the description of the fifth embodiment.

[0143] In this embodiment, the drain terminals 12 of the semiconductor device 1a and the semiconductor device 1b are connected to a wiring layer of the printed circuit board 101 on the rear surface SF2 of each package.

[0144] 7.2 Cross-sectional structure of power conversion device Next, an example of a cross-sectional configuration of the power conversion device 100 will be described. Fig. 30 is a cross-sectional view of the power conversion device 100 taken along line X5-X6 in Fig. 29. In the example of Fig. 30, not only the cross section but also a part of the contact plugs and wiring layers visible through the cross section are indicated by dashed lines. In the example of Fig. 30, the capacitors C1 and C2 are omitted to simplify the description.

[0145] As shown in FIG. 30, the printed circuit board 101 includes a core material 102, insulating plates 103 and 104, contact plugs 110a, 110b, 110c, 110d, and 110e, wiring layers 112a, 112b, 112c, 112d, 112e, 112f, 112g, 113a, 113b, and 113c, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND.

[0146] The semiconductor devices 1a and 1b are embedded in a printed circuit board 101. In this embodiment, similarly to the description of the fifth embodiment, the semiconductor devices 1a and 1b are arranged so as to be drain-down.

[0147] In other words, the drain-down semiconductor devices 1a and 1b are provided at a distance from each other on an insulating plate 103. An insulating plate 104 is provided on the semiconductor devices 1a and 1b. The sides of the semiconductor devices 1a and 1b contact the core material 102. That is, the semiconductor devices 1a and 1b are provided in the same layer as the core material 102.

[0148] On the insulating plate 104, an input terminal TIN, an output terminal TOUT, a gate driver terminal TG, and a ground terminal TGND are provided.

[0149] Contact plugs 110a, 110b, 110c, 110d, and 110e are provided in the insulating plate 104. The contact plugs 110a, 110b, 110c, 110d, and 110e extend within the insulating plate 104 in the Z direction.

[0150] A wiring layer 112a is provided between the drain terminal 12 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112a extends on the XY plane. A wiring layer 112b is provided between the gate terminal 11 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112b extends on the XY plane. A wiring layer 112c is provided between the source terminal 10 of the semiconductor device 1a and the insulating plate 104. The wiring layer 112c extends on the XY plane.

[0151] A wiring layer 112d is provided between the drain terminal 12 of the semiconductor device 1b and the insulating plate 104. The wiring layer 112d extends on the XY plane. A wiring layer 112e is provided between the gate terminal 11 of the semiconductor device 1b and the insulating plate 104. The wiring layer 112e extends on the XY plane. Wiring layers 112f and 112g are provided between the source terminal 10 of the semiconductor device 1b and the insulating plate 104. The wiring layers 112f and 112g extend on the XY plane.

[0152] Wiring layers 113a, 113b, and 113c are provided on the insulating plate 104. The wiring layers 113a, 113b, and 113c extend on the XY plane.

[0153] The input terminal TIN is connected to a contact plug 110a. The contact plug 110a is connected to a wiring layer 112a. The wiring layer 112a is connected to the drain terminal 12 of the semiconductor device 1a on the back surface SF2 of the package of the semiconductor device 1a (the upper side of the paper in FIG. 30).

[0154] The gate terminal 11 of the semiconductor device 1a is connected to a contact plug 110c via a wiring layer 112b. The contact plug 110c is connected to a gate driver terminal TG.

[0155] Furthermore, the gate driver terminal TG is connected to a contact plug 110d via a wiring layer 113a. The contact plug 110d is connected to the gate terminal 11 of the semiconductor device 1b via a wiring layer 112e.

[0156] The source terminal 10 of the semiconductor device 1a is connected to a contact plug 110b via a wiring layer 112c.

[0157] Furthermore, the contact plug 110b is connected to the wiring layer 112d and the wiring layer 113b. The wiring layer 112d is connected to the drain terminal 12 of the semiconductor device 1b on the package back surface SF2 (upper side of the paper in FIG. 30) of the semiconductor device 1b. The wiring layer 113b is connected to a first end of the inductor L1. A second end of the inductor L1 is connected to the output terminal TOUT via the wiring layer 113c.

[0158] The source terminal 10 of the semiconductor device 1b is connected to a contact plug 110e via wiring layers 112f and 112g. The contact plug 110e is connected to a ground terminal TGND.

[0159] The configuration according to this embodiment provides the same effects as those of the fifth embodiment, and the other effects are the same as those of the first embodiment.

[0160] 8. Modifications, etc. In the fifth to seventh embodiments, the semiconductor devices 1a and 1b are embedded in the printed circuit board 101, but the configuration of the power conversion device 100 is not limited thereto. For example, at least one of the semiconductor devices 1a and 1b may be surface-mounted on the printed circuit board 101.

[0161] The semiconductor devices 1a and 1b may be embedded in the printed circuit board 101 so as to be source down.

[0162] The semiconductor device 1 of the second embodiment may be applied to the fifth to seventh embodiments.

[0163] The semiconductor device 1 of the third or fourth embodiment may be applied to the seventh embodiment.

[0164] In the above embodiment, "connected" also includes a state of being indirectly connected via another conductive material.

[0165] In the above embodiment, "substantially the same" may include manufacturing variations.

[0166] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0167] 1, 1a, 1b...Semiconductor device 10...Source terminal 11…Gate terminal 12…Drain terminal 13…Mold resin 20...Semiconductor chip 21d…Drain electrode 21g: Gate electrode 21s…Source electrode 22...Passivation film 23g, 23s…conductive layer 31, 31d, 31g, 31s…Mounting material 40...Heat sink 50...Insulating resin 100...Power conversion device 101...Printed circuit board 102…Core material 103, 104...insulating plate 110a, 110b, 110c, 110d, 110e" ... Contact plug 111a, 111b, 111c, 111d, 112a, 112b, 112c, 112d, 112e, 112f, 112g, 113a, 113b, 113c...wiring layer C1, C2…Capacitors L1…inductor

Claims

1. a semiconductor chip having a source electrode and a gate electrode provided on a first surface and a drain electrode provided on a second surface opposite to the first surface; a source terminal having a fourth surface exposed from the third surface of the package and a fifth surface connected to the source electrode and having a shape different from that of the fourth surface; a gate terminal having a sixth surface exposed from the third surface of the package and a seventh surface connected to the gate electrode and having a shape different from that of the sixth surface; a drain terminal connected to the drain electrode and having an eighth surface exposed from the third surface of the package; Equipped with Semiconductor device.

2. When surface-mounted on a printed circuit board, the fourth surface, the sixth surface, and the eighth surface are covered with tin or solder; When vertically mounted on a printed circuit board, the fourth surface, the sixth surface, and the eighth surface are not covered with tin and solder. The semiconductor device according to claim 1 .

3. the source terminal, the gate terminal, and the drain terminal are formed of an etching frame; The semiconductor device according to claim 1 .

4. each of the source terminal, the gate terminal, and the drain terminal has a first region that is half-etched from the third surface side of the package in a first direction; the gate terminal further has a second region half-etched from the seventh surface side; The semiconductor device according to claim 1 .

5. a length in the first direction of the first region of the drain terminal is longer than a length in the first direction of each of the first regions of the source terminal and the gate terminal; The semiconductor device according to claim 4.

6. a length of the first region of the source terminal in the first direction is equal to a length of the first region of the gate terminal in the first direction; The semiconductor device according to claim 4.

7. The length of the drain terminal in the first direction is longer than the lengths of the source terminal and the gate terminal in the first direction. The semiconductor device according to claim 1 .

8. the drain terminal includes a first portion connected to the drain electrode via a mounting material, and a second portion having one end connected to the first portion, extending in a first direction, and the other end having the eighth surface exposed from the third surface of the package. The semiconductor device according to claim 1 .

9. The length of the drain terminal in the first direction is the same as the length of the package in the first direction. The semiconductor device according to claim 7.

10. the first portion of the drain terminal has a tenth surface exposed from a ninth surface facing the third surface of the package; The semiconductor device according to claim 8.

11. the drain terminal further includes a third portion having an eleventh surface, one end of which is connected to the first portion, extending in the first direction, facing the second portion across the semiconductor chip, and the other end of which has an eleventh surface exposed from the third surface of the package. The semiconductor device according to claim 8.

12. the package further includes a conductive heat sink exposed from a ninth surface opposite to the third surface and insulated from the source terminal, the gate terminal, and the drain terminal. The semiconductor device according to claim 1 .

13. an insulating resin exposed from a ninth surface of the package opposite to the third surface, in contact with the drain terminal, and having a higher thermal conductivity than a molding resin; The semiconductor device according to claim 1 .

14. A method for manufacturing a semiconductor device in which a source terminal, a gate terminal, and a drain terminal are exposed from a first surface of a package, the method comprising the steps of: a step of mounting a semiconductor chip on the source terminal and the gate terminal provided on a first etching frame via a mounting material such that a source electrode is connected to the source terminal and a gate electrode is connected to the gate terminal; a step of mounting the drain terminal provided on a second etching frame having a thickness different from that of the first etching frame via the mounting material on a drain electrode provided on a surface of the semiconductor chip opposite to a surface on which the source electrode and the gate electrode are provided; sealing the first etching frame, the semiconductor chip, and the second etching frame with a molding resin; cutting the first etching frame, the second etching frame, and the molding resin; Equipped with A method for manufacturing a semiconductor device.

15. each of the source terminal, the gate terminal, and the drain terminal has a first region that is half-etched in a first direction from the first surface side of the package; The method for manufacturing a semiconductor device according to claim 14.

16. the drain terminal is further exposed from a second surface of the package opposite to the first surface; The method for manufacturing a semiconductor device according to claim 14.

17. The length of the drain terminal in the first direction is the same as the length of the package in the first direction. The method for manufacturing a semiconductor device according to claim 14.

18. The method further includes a step of mounting a conductive heat sink that is exposed from a second surface of the package opposite to the first surface and is insulated from the source terminal, the gate terminal, and the drain terminal. The method for manufacturing a semiconductor device according to claim 14.

19. forming an insulating resin that is exposed from a second surface of the package opposite to the first surface, that is in contact with the drain terminal, and that has a thermal conductivity higher than that of the molding resin; The method for manufacturing a semiconductor device according to claim 14.

20. A first insulating plate; a second insulating plate facing the first insulating plate; The semiconductor device according to claim 1 , which is provided between the first insulating plate and the second insulating plate; A core material provided in the same layer as the semiconductor device; Equipped with Power conversion equipment.

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