Method for manufacturing light-emitting chip, light-emitting chip, exposure head, and image forming device

Abstract

To solve such a problem that an excessive area unrelated to a light-emitting element exists widely in an outer peripheral part of a light-emitting chip.SOLUTION: A method for manufacturing a light-emitting chip is the method for manufacturing a light-emitting chip for use in an exposure head of an image forming device and comprises: a thinning step in which a wafer is thinned by grinding a second surface being a surface opposite to a first surface in a wafer in which multiple light-emitting chips each having multiple light-emitting parts that are arranged along a prescribed direction and emit light to expose a photoreceptor are formed on a first surface with scribe areas left therebetween; a formation step in which irradiation with laser light is performed from the second surface toward the scribe areas so as to be focused inside the wafer to form modified layers within the wafer; and a dividing step in which the wafer is divided into light-emitting chips along the modified layers in the scribe areas.SELECTED DRAWING: Figure 16B

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a light-emitting chip, a light-emitting chip, an exposure head, and an image forming apparatus. [Background technology]

[0002] In an electrophotographic image forming apparatus, an electrostatic latent image is formed on a photoreceptor by exposing the photoreceptor to light as it is rotated, and the electrostatic latent image is developed with toner to form an image. In particular, a solid-state exposure type exposure device that uses a rod lens array to focus light from an array of light-emitting elements on the surface of a photoreceptor has attracted attention because it is easier to reduce the size, noise level, and cost compared to a laser scanning type exposure device.

[0003] For solid-state exposure type exposure devices, since it is difficult to manufacture a monolithic long light-emitting chip, a method is used in which multiple light-emitting chips are joined together to ensure a sufficient image formation width in the axial direction of the photoconductor. Furthermore, by arranging multiple light-emitting chips in a staggered pattern, it is possible to realize an image formation area without gaps at the joints between the light-emitting chips. When the light-emitting chips are arranged in a staggered pattern, the light-capturing efficiency of the rod lens array is improved by arranging the light-emitting chips in the first row and the light-emitting chips in the second row as close as possible. However, a wide margin (hereinafter referred to as the scribe area) remains in the light-emitting chips cut out from the wafer relative to the cutting line.

[0004] Therefore, techniques for reducing the scribe area have been proposed. For example, the techniques described in Patent Documents 1 and 2 focus laser light inside the wafer and form modified layers on the wafer at the positions where the laser light is focused. Furthermore, these techniques form multiple modified layers in the thickness direction of the wafer and separate the wafer along the modified layers. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2014-192339 A [Patent Document 2] Patent Publication No. 2023-032215 Summary of the Invention [Problem to be solved by the invention]

[0006] When cutting out light-emitting chips from a wafer, it is common for chip mapping on a wafer to reserve a wide scribe area, taking into consideration the operating tolerance of the processing device. However, in an exposure head that arranges light-emitting chips in a staggered pattern, if a wide scribe area is reserved, there is a problem that a large excess area unrelated to the light-emitting element exists on the outer periphery of the light-emitting chip. [Means for solving the problem]

[0007] In order to solve this problem, for example, a method for manufacturing a light-emitting chip of the present invention has the following configuration. That is, the method for manufacturing a light-emitting chip is a method for manufacturing a light-emitting chip for use in an exposure head of an image forming apparatus, a thinning step of thinning the wafer by grinding a second surface, which is a surface opposite to the first surface, in a wafer in which a plurality of light-emitting chips, each of which has a plurality of light-emitting portions that emit light to expose a photosensitive body, are formed on a first surface with a scribe region therebetween; a forming step of forming a modified layer inside the wafer by irradiating a laser beam from the second surface toward the scribe region and so as to be focused inside the wafer; and a cutting step of cutting the wafer along the modified layer in the scribe region into the light emitting chips. Effect of the Invention

[0008] According to the present invention, the scribe area can be made smaller, and the extra area that is not related to the light emitting element on the outer periphery of the light emitting chip can be reduced. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing a schematic configuration of an image forming apparatus according to an embodiment; [Diagram 2] FIG. 2 is an explanatory diagram of a configuration of a photoconductor and an exposure head according to the embodiment. [Diagram 3] FIG. 4 is an explanatory diagram of the configuration of a printed circuit board of an exposure head according to an embodiment. [Figure 4] 1A and 1B are explanatory diagrams of a light-emitting chip and a light-emitting element array in the light-emitting chip according to an embodiment. [Diagram 5] FIG. 1 is a plan view showing a schematic configuration of a light-emitting chip according to an embodiment. [Figure 6] FIG. 1 is a cross-sectional view showing a schematic configuration of a light-emitting chip according to an embodiment. [Figure 7] FIG. 4 is a circuit diagram showing a control configuration of an exposure apparatus according to an embodiment. [Figure 8] 6 is a signal chart related to access to a register of a light emitting chip according to an embodiment; [Figure 9] 11 is a signal chart related to the transmission of image data to a light-emitting chip according to an embodiment; [Figure 10] FIG. 2 is a functional block diagram showing a detailed configuration of a light-emitting chip according to an embodiment. [Figure 11] FIG. 13 is an explanatory diagram of multiple exposure using light-emitting elements arranged in a stepped pattern. [Figure 12] FIG. 1 is a plan view of a wafer on which light-emitting chips are mapped. [Figure 13] 1A to 1C are diagrams illustrating a wafer thinning process. [Figure 14A] An enlarged view of the light-emitting chips mapped onto a wafer. [Figure 14B] FIG. 1 is a plan view of a state in which light-emitting chips cut from a wafer are arranged on a printed circuit board. [Figure 15A] FIG. 4 is a first explanatory diagram of a forming step of forming a modified layer by irradiating laser light. [Figure 15B] FIG. 2 is a second explanatory diagram of the forming step of forming a modified layer by irradiating laser light. [Figure 15C]5A to 5C are explanatory views of a cleaving step for cleaving the wafer along the modified layer into light emitting chips. [Figure 16A] 13 is an enlarged view of a light-emitting chip mapped on a wafer in a modified example. [Figure 16B] 13 is a plan view showing a state in which light-emitting chips cut out from a wafer are arranged on a printed circuit board in a modified example. [Figure 17A] FIG. 13 is an enlarged view of light-emitting chips mapped on a wafer in another modified example. [Figure 17B] FIG. 13 is a plan view showing a state in which light-emitting chips cut out from a wafer are arranged on a printed circuit board in another modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0011] <1. Schematic configuration of image forming apparatus> 1 shows an example of a schematic configuration of an image forming apparatus 1 according to an embodiment. The image forming apparatus 1 includes a reading unit 100, an image creating unit 103, a fixing unit 104, and a conveying unit 105. The reading unit 100 optically reads an original placed on a platen and generates read image data. The image creating unit 103 forms an image on a sheet based on the read image data generated by the reading unit 100, or based on print image data received from an external device via a network, for example.

[0012] The image forming unit 103 includes image forming units 101a, 101b, 101c, and 101d. The image forming units 101a, 101b, 101c, and 101d form black, yellow, magenta, and cyan toner images, respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration, and are collectively referred to as the image forming unit 101 below. The photoconductor 102 of the image forming unit 101 is rotated clockwise in the figure during image formation. The charger 107 charges the photoconductor 102. The exposure head 106 exposes the photoconductor 102 to light to form an electrostatic latent image on the surface of the photoconductor 102. The developer 108 develops the electrostatic latent image on the photoconductor 102 with toner to form a toner image. The toner image formed on the surface of the photoconductor 102 is transferred to a sheet transported on a transfer belt 111. By transferring the toner images of the four photoconductors 102 onto a sheet in an overlapping manner, a color image containing four color components, namely black, yellow, magenta, and cyan, can be formed.

[0013] The conveying unit 105 controls the feeding and conveying of the sheet. Specifically, the conveying unit 105 feeds the sheet from a designated unit among the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to the conveying path of the image forming apparatus 1. The fed sheet is conveyed to the registration roller 110. The registration roller 110 conveys the sheet onto the transfer belt 111 at an appropriate timing so that the toner image of each photoconductor 102 is transferred onto the sheet. As described above, the toner image is transferred onto the sheet while the sheet is being conveyed on the transfer belt 111. The fixing unit 104 fixes the toner image onto the sheet by heating and pressing the sheet onto which the toner image has been transferred. After the toner image is fixed, the sheet is discharged to the outside of the image forming apparatus 1 by the discharge roller 112. An optical sensor 113 is disposed at a position opposite the transfer belt 111. Optical sensor 113 optically reads a test chart formed on transfer belt 111 by image forming unit 101. When misregistration is detected in the test chart read by optical sensor 113, image controller 700 (described later) performs control to compensate for the misregistration when a subsequent job is executed.

[0014] Although an example in which a toner image is directly transferred from each photoconductor 102 to a sheet on the transfer belt 111 has been described here, the toner image may be indirectly transferred from each photoconductor 102 to a sheet via an intermediate transfer body. Also, although an example in which a color image is formed using toners of multiple colors has been described here, the technology according to the present disclosure is also applicable to an image forming apparatus that forms a monochrome image using toners of a single color.

[0015] <2. Exposure head configuration example> 2(A) and 2(B) show the photoconductor 102 and the exposure head 106. The exposure head 106 has a light emitting element array 201, a printed circuit board 202 on which the light emitting element array 201 is mounted, a rod lens array 203, and a housing 204 that holds the rod lens array 203 and the printed circuit board 202. The photoconductor 102 has a cylindrical shape. The exposure head 106 is disposed such that its longitudinal direction is parallel to the axial direction D1 of the photoconductor 102, and the surface on which the rod lens array 203 is attached faces the surface of the photoconductor 102. While the photoconductor 102 rotates in the circumferential direction D2, the light emitting element array 201 of the exposure head 106 emits light, and the rod lens array 203 focuses the light on the surface of the photoconductor 102.

[0016] Fig. 3(A) and Fig. 3(B) show an example of the configuration of the printed circuit board 202. Fig. 3(A) shows the surface on which the connector 305 is mounted, and Fig. 3(B) shows the surface on which the light-emitting element array 201 is mounted (the surface opposite to the surface on which the connector 305 is mounted). Fig. 4 shows a schematic diagram of the light-emitting chip 400 and the array of the light-emitting elements 602 in the light-emitting chip 400.

[0017] In this embodiment, the light-emitting element array 201 has a plurality of light-emitting elements arranged two-dimensionally. The light-emitting element array 201 includes, as a whole, N columns of light-emitting elements in the axial direction D1 of the photoconductor and M rows of light-emitting elements in the circumferential direction D2, where M and N are integers of 2 or more. In the example of FIG. 3(B), the light-emitting element array 201 is divided into 20 light-emitting chips 400-1 to 400-20, each of which includes a subset of the entire plurality of light-emitting elements, and the light-emitting chips 400-1 to 400-20 are arranged in a staggered manner along the axial direction D1. The light-emitting chips 400-1 to 400-20 are also collectively referred to as light-emitting chips 400. As shown in FIG. 3(B), the range occupied by all the light-emitting elements of the 20 light-emitting chips in the axial direction D1 is wider than the range occupied by the maximum width W0 of the input image data. Therefore, some light-emitting elements located at both ends in the axial direction D1 may not be used to expose the photoconductor 102 unless a positional deviation of the image is detected. Each light-emitting chip 400 on the printed circuit board 202 is connected to the image controller 700 (FIG. 7) via a connector 305. For convenience of explanation, the side with the smaller branch number of the light-emitting chips 400-1 to 400-20 arranged along the axial direction D1 may be referred to as the "left" and the side with the larger branch number as the "right". For example, the light-emitting chip 400-1 is the leftmost light-emitting chip 400, and the light-emitting chip 400-20 is the rightmost light-emitting chip.

[0018] The number J (J=N / 20) of the light-emitting elements 602 arranged in each row of one light-emitting chip 400 may be equal to, for example, 748 (J=748). Meanwhile, the number M of the light-emitting elements 602 arranged in each column of one light-emitting chip 400 may be equal to, for example, 4 (M=4). That is, in the exemplary embodiment, each light-emitting chip 400 has a total of 2992 (=748×4) light-emitting elements 602, with 748 in the axial direction D1 and 4 in the circumferential direction D2. The interval P between the center points of the light-emitting elements 602 adjacent to each other in the circumferential direction D2 is Cmay be, for example, about 21.16 μm, which corresponds to a resolution of 1200 dpi. The distance between the center points of adjacent light-emitting elements 602 in the axial direction D1 may also be about 21.16 μm, in which case 748 light-emitting elements 602 occupy a length of about 15.8 mm in the axial direction D1. Note that, for convenience of explanation, FIG. 4 shows an example in which the light-emitting elements 602 are completely arranged in a lattice in each light-emitting chip 400, but in reality, M (M=4) light-emitting elements 602 in each row are arranged in a staircase pattern. This point will be further explained later.

[0019] 5 is a plan view showing a schematic configuration of the light emitting chip 400. The light emitting elements 602 of each light emitting chip 400 are formed on a light emitting substrate 402, which is, for example, a silicon substrate. A circuit unit 406 for driving the light emitting elements 602 is provided on the light emitting substrate 402. Signal lines for communicating with the image controller 700, power lines for connecting to a power source, and ground lines for connecting to a ground are connected to the pads 408-1 to 408-9. The signal lines, power lines, and ground lines may be wires made of, for example, gold.

[0020] FIG. 6 shows a part of the cross section taken along line AA in FIG. 5. A plurality of lower electrodes 504 are formed on the light emitting substrate 402. A gap of length d is provided between two adjacent lower electrodes 504. A light emitting layer 506 is provided on the lower electrode 504, and an upper electrode 508 is provided on the light emitting layer 506. The upper electrode 508 is a common electrode for the plurality of lower electrodes 504. When a voltage is applied between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light emitting layer 506 to emit light. Therefore, one lower electrode 504 and a partial region of the light emitting layer 506 and the upper electrode 508 corresponding to the lower electrode 504 constitute one light emitting element 602. That is, in this embodiment, the light emitting substrate 402 includes a plurality of light emitting elements 602.

[0021] The light-emitting layer 506 may be, for example, an organic EL film. The upper electrode 508 is made of, for example, a transparent electrode such as indium tin oxide (ITO) so as to transmit the emission wavelength of the light-emitting layer 506. In this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but the entire upper electrode 508 does not need to transmit the emission wavelength. Specifically, it is sufficient that a partial region through which light from each light-emitting element 602 passes transmits the emission wavelength. In FIG. 6, one continuous light-emitting layer 506 is formed, but multiple light-emitting layers 506 each having a width equivalent to the width W of the lower electrode 504 may be formed on the lower electrode 504. In FIG. 6, the upper electrode 508 is one common electrode for multiple lower electrodes 504, but multiple upper electrodes 508 each having a width equivalent to the width W of the lower electrode 504 may be formed corresponding to each lower electrode 504. Moreover, among the lower electrodes 504 of each light-emitting chip 400, a first plurality of lower electrodes 504 may be covered with a first light-emitting layer 506, and a second plurality of lower electrodes 504 may be covered with a second light-emitting layer 506. Moreover, among the lower electrodes 504 of each light-emitting chip 400, a first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504, and a second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. Even in such a configuration, one lower electrode 504 and a region of the light-emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 configure one light-emitting element 602.

[0022] FIG. 7 is a circuit diagram related to a control configuration for controlling the light-emitting chip 400. The image controller 700 is a control circuit that communicates with the printed circuit board 202 via a plurality of signal lines (wires). The image controller 700 has a CPU 701, a clock generating unit 702, an image data processing unit 703, a register access unit 704, and a light-emitting control unit 705. The light-emitting control unit 705 is a component that configures an exposure device together with the exposure head 106. The light-emitting control unit 705 terminates a signal line between the light-emitting control unit 705 and the printed circuit board 202. The n-th light-emitting chip 400-n (n is an integer from 1 to 20) on the printed circuit board 202 is connected to the light-emitting control unit 705 via a signal line DATAn and a signal line WRITEn. The signal line DATAn is used to transmit image data from the image controller 700 to the light-emitting chip 400-n. The signal line WRITEn is used for the image controller 700 to write control data to the register of the light-emitting chip 400-n.

[0023] One signal line CLK, one signal line SYNC, and one signal line EN are further provided between the light-emitting control unit 705 and each light-emitting chip 400. The signal line CLK is used to transmit a clock signal for transmitting data on the signal lines DATAn and WRITEn. The light-emitting control unit 705 outputs a clock signal generated based on a reference clock signal from the clock generating unit 702 to the signal line CLK. The signals transmitted to the signal lines SYNC and EN will be described later.

[0024] The CPU 701 controls the entire image forming apparatus 1. The image data processing unit 703 performs image processing on image data received from the reading unit 100 or an external device to generate binary bitmap image data for controlling the on / off of the light emission of the light emitting element 602 of the light emitting chip 400 on the printed circuit board 202. The image processing here may include, for example, raster conversion, tone correction, color conversion, and halftone processing. The image data processing unit 703 transmits the generated image data to the light emission control unit 705 as input image data. The register access unit 704 receives control data to be written to the register in each light emitting chip 400 from the CPU 701 and transmits it to the light emission control unit 705.

[0025] FIG. 8 shows the transition of the signal level of each signal line when control data is written to the register of the light-emitting chip 400. An enable signal that is at high level during communication and indicates that communication is in progress is output to the signal line EN. The light-emitting control unit 705 transmits a start bit to the signal line WRITEn in synchronization with the rising edge of the enable signal. Next, the light-emitting control unit 705 transmits a write identification bit indicating a write operation, and then transmits the address of the register to which the control data is to be written (4 bits in this example) and the control data (8 bits in this example). When writing to the register, the light-emitting control unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to, for example, 3 MHz.

[0026] FIG. 9 shows the transition of the signal level of each signal line when image data is transmitted to each light-emitting chip 400. A periodic line synchronization signal indicating the exposure timing of each line on the photoconductor 102 is output to the signal line SYNC. If the circumferential speed of the photoconductor 102 is 200 mm / s and the resolution in the circumferential direction is 1200 dpi (approximately 21.16 μm), the line synchronization signal is output at a period of approximately 105.8 μs. The light-emitting control unit 705 transmits image data to the signal lines DATA1 to DATA20 in synchronization with the rising edge of the line synchronization signal. In this embodiment, since each light-emitting chip 400 has 2992 light-emitting elements 602, it is necessary to transmit image data indicating the light emission / non-light emission of each of the total 2992 light-emitting elements 602 to each light-emitting chip 400 within a period of approximately 105.8 μs. Therefore, in this example, as shown in FIG. 9, when transmitting image data, the light-emitting control unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to 30 MHz.

[0027] FIG. 10 is a functional block diagram showing a detailed configuration of one light-emitting chip 400 (n-th light-emitting chip 400-n). As also shown in FIG. 5, the light-emitting chip 400 has nine pads 408-1 to 408-9. The pads 408-1 and 408-2 are connected to a power supply voltage VCC by a power supply line. Power is supplied from this power supply voltage VCC to each circuit of the circuit unit 406 of the light-emitting chip 400. The pads 408-3 and 408-4 are connected to the ground by a ground line. Each circuit of the circuit unit 406 and the upper electrode 508 are connected to the ground via the pads 408-3 and 408-4. The signal line CLK is connected to the transfer unit 1003, the register 1102, and the latch units 1004-001 to 748 via the pad 408-5. The signal lines SYNC and DATAn are connected to the transfer unit 1003 via the pads 408-6 and 408-7. The signal lines EN and WRITEn are connected via pads 408-8 and 408-9 to a register 1102. The register 1102 stores control data indicating a desired light emission intensity of the light emitting element 602, for example.

[0028] The transfer unit 1003 receives input image data including a series of pixel values ​​each indicating the emission or non-emission of one light emitting element 602 from a signal line DATAn in synchronization with a clock signal from a signal line CLK, starting from a line synchronization signal from a signal line SYNC. The transfer unit 1003 performs serial-to-parallel conversion on the series of pixel values ​​serially received from the signal line DATAn in units of M (for example, M=4) pixel values. For example, the transfer unit 1003 has four cascaded D flip-flops, and parallelizes pixel values ​​DATA-1, DATA-2, DATA-3, and DATA-4 input over four clocks, and outputs the parallelized pixel values ​​to the latch units 1004-0001 to 1004-748. The transfer unit 1003 further has four D flip-flops for delaying the line synchronization signal, and outputs a first latch signal to the latch unit 1004-001 via a signal line LAT1 at a timing delayed by four clocks from the input of the line synchronization signal.

[0029] The kth latch unit 1004-k (k is an integer from 1 to 748) holds the four pixel values ​​DATA-1, DATA-2, DATA-3, and DATA-4 input from the transfer unit 1003 at the same time as the kth latch signal is input, by using a latch circuit. In addition, except for the last-stage latch unit 1004-748, the kth latch unit 1004-k delays the kth latch signal by four clocks and outputs the (k+1)th latch signal to the latch unit 1004-(k+1) via the signal line LAT(k+1). Then, the kth latch unit 1004-k continues to output a drive signal based on the four pixel values ​​held by the latch circuit to the current drive unit 1104 during the signal period of the kth latch signal. For example, there is a delay of four clocks between the timing when the first latch signal is input to the latch unit 1004-1 and the timing when the second latch signal is input to the latch unit 1004-2. Therefore, the latch unit 1004-1 outputs drive signals based on the 1st, 2nd, 3rd and 4th pixel values ​​to the current driver 1104, whereas the latch unit 1004-2 outputs drive signals based on the 5th, 6th, 7th and 8th pixel values ​​to the current driver 1104. Generally speaking, the latch unit 1004-k outputs drive signals based on the (4k-3), (4k-2), (4k-1) and (4k)th pixel values ​​to the current driver 1104. Therefore, in the embodiment shown in FIG. 10, 748 latch units 1004-001 to 1004-748 output 2992 drive signals for controlling the driving of 2992 (=748×4) light emitting elements 602 in approximately parallel to the current driver 1104. Each drive signal is a binary signal indicating a high level or a low level.

[0030] The current driver 1104 has 2992 light emission driver circuits corresponding to the 2992 light emitting elements 602 each including a partial region of the light emitting layer 506. Each light emission driver circuit applies a drive voltage corresponding to the light emission intensity indicated by the control data in the register 1102 to the light emitting layer 506 of the corresponding light emitting element 602 while the corresponding drive signal indicates a high level indicating that light emission is on. This causes a current to flow through the light emitting layer 506, causing the light emitting element 602 to emit light. Note that the control data may indicate one individual light emission intensity for each light emitting element 602, may indicate one light emission intensity for each group of the light emitting elements 602, or may indicate one light emission intensity common to all the light emitting elements 602.

[0031] <3. Control of multiple exposure> FIG. 4 shows an example in which the light-emitting elements 602 are completely arranged in a lattice pattern in each light-emitting chip 400, but in reality, in this embodiment, the M light-emitting elements 602 in each row can be arranged in a stepped pattern at a constant pitch. FIG. 11 is an explanatory diagram of multiple exposure using light-emitting elements arranged in a stepped pattern. Here, an example of the arrangement of light-emitting elements in the light-emitting chip 400-1 when M=4 is partially shown. R in the figure j_m (j={0,1,...,J-1}, m={0,1,2,3}) represents the light emitting element 602 in the j-th column from the left in the axial direction and in the m-th row from the top in the circumferential direction. C As described above, the axial spacing between two adjacent light-emitting elements among the M light-emitting elements in each row, i.e., the axial pitch P A may be approximately 5 μm, which corresponds to a resolution of 4800 dpi.

[0032] By arranging the four light-emitting elements in each row in a stepped manner in this manner, any two adjacent light-emitting elements among the four light-emitting elements occupy areas that partially overlap in the axial direction. Then, the four light-emitting elements in the row corresponding to each pixel position of the input image data sequentially emit light while the photoconductor 102 is rotating, forming spots corresponding to each pixel position on the surface of the photoconductor 102. In the example of Figure 11, when the pixel value at the left end of the i-th line of the input image data indicates that light is on, the light-emitting element R 0_0 , R 0_1 , R 0_2 , R 0_3 is a line L on the surface of the photoconductor 102. i As a result, the line L i In the same manner, when the jth pixel value from the left of the i-th line of the input image data indicates that light is emitted, the light-emitting element R j_0 , R j_1 , R j_2 , R j_3 is a line L on the surface of the photoconductor 102. i As a result, the line L i The jth spot area from the left of is multiplexed and the corresponding spot SP j is formed.

[0033] 11, in this embodiment, the light-emitting elements in two axially adjacent rows also occupy a partially overlapping range in the axial direction. Similarly, of the two axially adjacent light-emitting chips 400, the light-emitting elements in the rightmost row of the left light-emitting chip 400 and the light-emitting elements in the leftmost row of the right light-emitting chip 400 also occupy a partially overlapping range in the axial direction. The axial pitch P of the light-emitting elements across all 20 light-emitting chips 400 is Ais constant at about 5 μm. By sequentially emitting light at appropriate times from the four light-emitting elements in each row of these light-emitting chips 400, a smooth line of an electrostatic latent image can be formed on the surface of the photoconductor 102, which is made up of a series of spots that are partially overlapping each other with a constant spot spacing. As a result of such lines being continuously formed in the circumferential direction, a two-dimensional electrostatic latent image is created.

[0034] <4. Manufacturing of light-emitting chips> Next, a manufacturing process of the light emitting chip 400 will be described. FIG. 12 is a plan view of the light emitting chip 400 mapped on a Si wafer. First, a plurality of light emitting chips 400 each having a light emitting element array consisting of a plurality of light emitting elements 602 and a driving circuit are formed on a wafer 680 by a known semiconductor manufacturing process. The plurality of light emitting elements 602 are an example of a plurality of light emitting units that emit light to expose a photosensitive body. The light emitting element 602 may be an organic EL (Electro-Luminescence). The known semiconductor manufacturing process may be, for example, a VPE (Vapor Phase Epitaxy) method, a CVD (Chemical Vapor Deposition) method, an MBE (Molecular Beam Epitaxy) method, or an MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0035] Next, the wafer thinning process will be described. FIG. 13 is a cross-sectional view for explaining the wafer thinning process. On the surface of the wafer 680, a plurality of light emitting chip regions 651 in which the light emitting chips 400 are formed and a driving circuit region 655 are formed by the above-mentioned semiconductor manufacturing process. Between the adjacent light emitting chip regions 651 and the light emitting chip region 651, a scribe region 650 is formed in order to cleave the wafer 680 in a later cleaving process. In other words, a plurality of light emitting chip regions 651 are formed on the surface of the wafer 680 with the scribe region 650 left open. In the thinning process performed after the plurality of light emitting chips 400 are formed, the back surface of the wafer 680 opposite to the front surface is ground to remove a part 680a of the wafer 680, thereby thinning the wafer 680. The front surface of the wafer 680 is an example of a first surface, and the back surface of the wafer 680 is an example of a second surface.

[0036] Generally, the thickness of a semiconductor wafer is standardized according to the wafer diameter. A wafer with a diameter of 6 inches has a thickness of 625 μm, a wafer with a diameter of 8 inches has a thickness of 725 μm, and so on. If the wafer is processed with the standardized thickness, a large laser output is required, and as a result, the scribe area needs to be enlarged. Therefore, in this embodiment, the thickness of the wafer 680 is thinned by a thinning process, the laser output for forming the modified layer is suppressed, and the diameter of the laser light is reduced.

[0037] In this embodiment, the back surface of the wafer 680 opposite to the surface on which the light emitting chip region 651 is formed is ground. This reduces the thickness of the wafer 680. The thinner the wafer is, the more the laser output for forming the modified layer can be suppressed, and the fewer the number of modified layers required for dicing can be. On the other hand, if the wafer 680 is made too thin, the strength of the wafer 680 and the strength of the chip after being cut out as the light emitting chip 400 are also reduced, so it is necessary to ensure a certain thickness in the wafer 680. In this embodiment, the wafer 680 is ground so that the thickness of the semiconductor wafer 680 after the thinning process is, for example, 400 μm.

[0038] Next, an outline of the forming process and the cutting process for cutting out the individual light emitting chips 400 from the wafer 680 will be described. In the forming process, a laser beam is irradiated from the back surface of the wafer 680 toward the scribe region and so as to be condensed inside the wafer 680. As a result, a modified layer is formed inside the wafer 680. The modified layer is a part where the wafer 680 is partially melted, and is weaker in strength than other parts and more likely to crack. The forming process for forming the modified layer is performed multiple times at different positions in the thickness direction of the wafer 680. As a result, the modified layer is formed at multiple positions in the thickness direction of the wafer 680. Furthermore, the forming process for forming the modified layer is performed multiple times along the scribe region formed between the adjacent light emitting chips 400, so that the modified layer is formed over the entire length of the scribe region. Thereafter, in a cutting step (also called an expanding step), the wafer 680 is cut (stealth dicing) along the modified layer in the scribe region, so that the individual light emitting chips 400 are cut out from the wafer 680 by being cut in the scribe region.

[0039] 14A is an enlarged view of the light emitting chips 400 mapped on the wafer 680. A plurality of light emitting chips 400 are arranged in a matrix at equal intervals in two directions. The longitudinal direction of the light emitting chips 400 is an example of the predetermined direction. A scribe region 650 is formed between adjacent light emitting chips 400. In a dicing process, the wafer 680 is cut at the scribe region. As a result, the light emitting chips 400 are separated, and individual light emitting chips 400 are cut out.

[0040] The dotted line shown in FIG. 14A is a line passing through the center of the strip-shaped scribe region 650. The center line of the scribe region 650 is also called the scribe line to be cut. Usually, the width of the scribe region 650 is set with a sufficient margin for the cutting accuracy of the dicing device and the spread angle of the laser light. The part exposed to the laser light on the wafer 680 and the vicinity of the position where the energy is concentrated when the laser is focused to form the modified layer become hot. Therefore, usually, the laser light is irradiated to a position sufficiently distant from the light emitting element 602 and the control circuit of the light emitting chip 400 to form the modified layer. If the light emitting chip 400 is damaged by the laser light, the light emitting element 602 or the control circuit in the light emitting chip 400 is destroyed, and the light emitting element 602 does not emit light even if a control signal is sent.

[0041] 14B is a diagram showing the light emitting chips 400 cut out from the wafer 680 by irradiating the laser beam along the dotted line in FIG. 14A to form a modified layer, followed by cleaving, and then arranged on the printed circuit board 202. A scribe region 650 is present on the outer periphery of each separated light emitting chip 400. Here, the distance D between the light emitting element 602 of the light emitting chip 400 in the first row and the light emitting element 602 of the light emitting chip 400 in the second row includes the scribe region 650. Therefore, it is desirable that the scribe region 650 between adjacent light emitting chips 400 be as small as possible for the light capture efficiency of the rod lens array.

[0042] 15A and 15B are explanatory diagrams of a forming step (stealth dicing step) in which a laser beam is incident to form a modified layer. FIG. 15A shows the state of incidence of the laser beam in the forming step in a cross section of a wafer 680. A scribe region 650 exists between the light emitting chips 400 adjacent to each other. A laser beam 653 is emitted from a laser beam source 652 and is incident on the back surface of the wafer 680. The laser beam 653 is focused inside the wafer 680 in the scribe region 650. The laser beam source 652 is, for example, a pulsed laser.

[0043] In this embodiment, a dicing tape 656 is attached to the back surface of the wafer 680 opposite to the front surface on which the light emitting chips 400 are formed in order to fix the position of the wafer 680. The laser light 653 is incident on the back surface of the wafer 680 through the dicing tape. The advantage of back surface incidence is that the light emitting chip region 651 and the driving circuit region 655 are not present on the optical path of the laser light 653, so that the risk of the light emitting element 602 and the driving circuit region 655 being damaged by the irradiation of the laser light can be reduced. Therefore, in the case of back surface incidence, compared to the conventional example in which a wider scribe region was required to be secured, it is possible to cut the wafer 680 by irradiating the laser light 653 on a region close to the end of the light emitting chip 400.

[0044] A point where the laser light is focused inside the wafer 680 and in the scribe region 650 is called a focusing point 654. Even if the vicinity of the focusing point 654 is far from the optical path of the laser light 653, the vicinity is damaged by heat because the energy of the laser light 653 when forming the modified layer becomes high temperature. The thermal damage region 657 shown by the elliptical dashed line in FIG. 15A is a region that is damaged by heat when forming the modified layer at the focusing point 654. Therefore, it is better to separate the focusing point 654 from the light emitting chip region 651. In this embodiment, the laser light 653 is focused at a position 30 μm or more away from the surface of the wafer 680 in the thickness direction of the wafer 680. The laser light 653 is focused at a position up to 100 μm from the surface of the wafer 680 in the thickness direction of the wafer 680. The position of the focusing point 654 of the laser light 653 is not particularly limited. Moreover, since the thermal damage area 657 becomes wider in proportion to the laser output, the thermal damage area 657 can be reduced by weakening the laser output, thereby reducing the thermal damage. In order to weaken the laser output, it is effective to lengthen the laser processing time or to reduce the thickness of the wafer 680. In this embodiment, the rear surface of the wafer 680 is ground (back-grinded) to reduce the thickness of the wafer 680, and then the laser beam 653 is irradiated, so that the laser output is suppressed, the irradiation area of ​​the laser beam 653 is reduced, and the range of the thermal damage area 657 is narrowed.

[0045] 15B is an image diagram showing six modified layers formed in the depth direction of a wafer 680. By irradiating the wafer 680 with laser light 653 multiple times while shifting the position of a focusing point 654 of the laser light 653 in the thickness direction of the wafer 680, multiple modified layers are formed at different positions in the thickness direction of the wafer 680 on the same cross section.

[0046] The modified layers are formed in order from the deepest part as viewed from the incident surface of the laser light 653. When forming the deepest first modified layer (the modified layer closest to the light emitting chip region 651), if the distance to the light emitting chip region 651 is close, there is a risk of thermal damage, so it is necessary to determine the position in the thickness direction of the first modified layer 661 so as not to cause thermal damage. Here, the first modified layer 661 is formed at a position 30 μm or more away from the surface (i.e., the distance S′ in the thickness direction from the surface ≧30 μm). In addition, the thinner the thickness (distance S) of the wafer 680 itself is, the weaker the laser output can be, so that when the scribe region 650 is to be narrowed, it is advantageous for the wafer 680 to be thin. Here, an example is shown in which the thickness of the thinned wafer 680 is set to 400 μm and six modified layers are formed. After the first modified layer 661 is formed, the focusing point 654 of the laser light 653 is shifted toward the back surface to which the dicing tape 656 is attached, thereby forming the second modified layer 662, the third modified layer 663, the fourth modified layer 664, the fifth modified layer 665, and the sixth modified layer 666 in this order. Here, the first modified layer 661 to the sixth modified layer 666 are formed by changing the position of the focusing point 654 of the laser light 653 in the thickness direction without moving the laser light source 652 in the planar direction of the wafer 680. The position of the focusing point 654 of the laser light 653 may be moved by moving the position of the lens for focusing the laser light 653 in the thickness direction of the wafer 680, or may be moved by moving the laser light source 652 in the thickness direction of the wafer 680. As a result, the first modified layer 661 to the sixth modified layer 666 are formed at the same position in a plan view, but at different positions in the thickness direction of the wafer 680. Thereafter, the laser light source 652 is moved along the scribe region 650, so that multiple sets of the first modified layer 661 to the sixth modified layer 666 are formed and arranged along the scribe region. When the sets of the first modified layer 661 to the sixth modified layer 666 have been formed along all of the scribe regions 650, the forming process is completed, and the process proceeds to the cleaving process (expanding process).

[0047] 15C is an explanatory diagram of a cleaving step for cleaving the wafer along the modified layers into light-emitting chips. In the cleaving step, the wafer 680 is pulled in the outer circumferential direction. As a result, as shown in FIG. 15C, the multiple modified layers are connected in the thickness direction of the wafer 680 and along the scribe lines, and cracks are generated in the scribe regions 650, and the wafer 680 is cleaved. As a result, the individual light-emitting chips 400 are separated and cut out.

[0048] As described above, in this embodiment, the light-emitting chips 400 are cut out by stealth dicing, in which laser light is incident from the back surface of the wafer 680 thinned in the thinning process, thereby making it possible to suppress the laser output and reduce thermal damage near the focal point 654.

[0049] In a modified example, the position of the first modified layer may be 30 μm away from the surface on which the light emitting chips 400 are formed, a scribe line may be set at a position closer to the end than the center of the scribe region 650, and the wafer may be cleaved along the scribe line. FIGS. 16A and 16B are explanatory diagrams of the modified example. FIG. 16A is an enlarged plan view of a light emitting chip mapped on a wafer in the modified example. FIG. 16B is a plan view showing a state in which the light emitting chips cut out from the wafer are arranged on a printed circuit board in the modified example. In FIG. 16A, the scribe line shown by the dotted line is set at a position closer to the end than the center of the scribe region 650. The wafer is cleaved along the scribe line, the light emitting chips 400 are cut out, and the light emitting chips 400 are arranged in a staggered pattern on the printed circuit board 202, so that the light emitting elements 602 of the light emitting chips 400 in the first and second rows can be brought close to each other as shown in FIG. 16B. Assuming that the width of the scribe region is 100 μm, in the conventional method where cutting was performed by aiming at the center, a scribe region 650 of 50 μm remained on the outer periphery of the light-emitting chip 400, but by using this method, the remaining scribe region 650 can be reduced to 10 μm. Compared to the conventional scribe line, it is possible to bring the light-emitting elements 602 of adjacent light-emitting chips 400 closer to each other by 80 μm (the difference between D and D' in the figure).

[0050] Fig. 17A is an enlarged plan view of the light-emitting chip 400 mapped on the wafer 680 in another modified example. Fig. 17B is a plan view showing the state in which the light-emitting chip 400 cut out from the wafer 680 is arranged on the printed circuit board 202 in another modified example. In the other modified example shown in Fig. 17A, the scribe region 650 on the periphery of the light-emitting chip 400 is narrowed. By mapping in this manner, the number of light-emitting chips 400 that can be manufactured from one wafer 680 can be increased, which has the advantage of reducing material costs.

[0051] 17B , in a modification in which the scribe region 650 is narrowed, the light emitting chips 400 are arranged in a staggered pattern on the printed circuit board 202. By narrowing the scribe region 650 on the periphery of the light emitting chip 400 as in this modification, the light emitting chips 602 of the light emitting chips 400 in the first row and the light emitting chips 400 in the second row can be placed close to each other when the light emitting chips 400 are arranged on the printed circuit board 202.

[0052] <5. Summary> As described above, in this embodiment, the wafer 680 is thinned, and the laser light is incident from the back surface of the wafer 680 where the light emitting chip region 651 is not formed, to form a modified layer, and the wafer 680 is cut. As a result, in this embodiment, the laser output can be reduced to reduce the diameter of the laser light 653, and therefore the scribe region can be reduced. As a result, in this embodiment, the extra portion unrelated to the light emitting element 602 can be reduced on the outer periphery of the light emitting chip 400 taken out of the wafer 680. Therefore, in this embodiment, the light emitting elements 602 of the first row of light emitting chips 400 arranged in a staggered pattern on the printed circuit board 202 and the light emitting elements 602 of the second row of light emitting chips 400 can be brought close to each other, and the light capture efficiency of the rod lens array 203 can be improved.

[0053] In this embodiment, a thinning process is performed to thin the wafer 680 after the light emitting chips 400 are formed. This allows the light emitting chips 400 to be formed in a thick wafer 680, so that the wafer 680 can maintain a sufficient strength during the formation of the light emitting chips 400 and protect the wafer 680 from breakage.

[0054] In this embodiment, the laser light 653 is focused at a position 30 μm or more away from the front surface of the wafer 680 to form the modified layer. This makes it possible to suppress thermal damage caused by the laser light 653 to the light emitting chips 400 formed on the front surface of the wafer 680. The laser light 653 is focused at a position 100 μm away from the front surface of the wafer 680 to form the modified layer. This makes it possible to suppress damage to the dicing tape 656 attached to the rear surface of the wafer 680.

[0055] In this embodiment, a plurality of modified layers are formed at different positions in the thickness direction of the wafer 680. This makes it possible to more reliably cleave the wafer 680 along the scribe lines formed by the plurality of modified layers.

[0056] In this embodiment, the modified layer is formed by irradiating the laser light 653 through the dicing tape 656, so that damage to the light emitting chips 400 due to dropping or the like can be suppressed when the wafer 680 is cut.

[0057] <6. Other Examples> The examples described in the embodiment are merely examples, and are not limited to the numerical values ​​used in the description. For example, the width of the scribe region 650, the thickness of the wafer 680, the position where the first modified layer is formed, and the like may be changed depending on the conditions.

[0058] In the above-described embodiment, an example was given of forming six modified layers at different positions in the thickness direction of the wafer 680, but the number of modified layers is not particularly limited to the above-described example and may be, for example, three or more layers.

[0059] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0060] 106... exposure head, 201... light-emitting element array, 202... printed circuit board, 400... light-emitting chip, 602... light-emitting element, 680... wafer, 651... light-emitting chip area, 650... scribe area, 652... laser light source, 653... laser light, 656... dicing tape, 654... focusing point, 661~666... ​​modified layer.

Claims

1. 1. A method for manufacturing a light emitting chip for use in an exposure head of an image forming apparatus, comprising: a thinning step of thinning the wafer by grinding a second surface, which is a surface opposite to the first surface, in a wafer in which a plurality of light-emitting chips, each of which has a plurality of light-emitting portions that emit light to expose a photosensitive body, are formed on a first surface with a scribe region therebetween; a forming step of forming a modified layer inside the wafer by irradiating a laser beam from the second surface toward the scribe region and so as to be focused inside the wafer; a cleaving step of cleaving the wafer along the modified layer in the scribe region into the light emitting chips.

2. The thinning step is performed after the plurality of light emitting chips are formed on the first surface. The method for manufacturing the light-emitting chip according to claim 1 .

3. In the forming step, the laser light is focused at a position 30 μm or more away from the first surface of the wafer in the thickness direction of the wafer. The method for manufacturing the light-emitting chip according to claim 1 .

4. In the forming step, the laser light is focused at a position up to 100 μm from the first surface of the wafer in the thickness direction of the wafer. The method for manufacturing a light-emitting chip according to claim 3 .

5. In the forming step, a plurality of modified layers are formed at different positions in the thickness direction of the wafer. The method for manufacturing the light-emitting chip according to claim 1 .

6. In the forming step, three or more modified layers are formed at different positions in the thickness direction of the wafer. The method for manufacturing a light-emitting chip according to claim 5 .

7. In the forming step, the position where the laser light is focused is changed to form the plurality of modified layers. The method for manufacturing a light-emitting chip according to claim 5 .

8. In the forming step, the laser light is irradiated through a dicing tape attached to the scribe region to form the modified layer. The method for manufacturing the light-emitting chip according to claim 1 .

9. A light-emitting chip manufactured by the manufacturing method according to claim 1.

10. The light-emitting chip according to claim 9 , and a substrate on which the light emitting chip is mounted.

11. An image forming apparatus comprising the exposure head according to claim 10.

12. 2. The method for manufacturing a light-emitting chip according to claim 1, wherein the plurality of light-emitting parts are organic electroluminescent (EL) parts.

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