Switch circuit to suppress inrush current

Abstract

SOLUTION: In a switch circuit 1, a first terminal (source) and a second terminal (drain) of a first switch Q1 are electrically connected to the input terminal 11 and the output terminal 12, respectively, and both ends of a bypass resistor R1 are electrically connected to the input terminal and the output terminal, respectively, and both ends of an output capacitor Co are electrically connected to the output terminal and the ground terminal, respectively, and the anode of a diode D is electrically connected to the input terminal, and the first terminal (source) and the second terminal (drain) of a second switch Q2 are electrically connected to the cathode of the diode D and the third terminal (gate) of the first switch, respectively, and both ends of a discharge resistor R2 are electrically connected to the third terminal and the ground terminal of the first switch, respectively, and voltage dividing resistors R3 and R4 are connected in series between the output terminal and the ground terminal, and the intermediate node of the voltage dividing resistors is electrically connected to the third terminal (gate) of the second switch.EFFECT: An inrush current in a switch circuit is suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a switch circuit, and more particularly to a switch circuit capable of suppressing inrush current. [Background technology]

[0002] In the conventional switch control method, the inrush current is suppressed by slow starting of the switch, but the switch on time is longer, so the switch element has to endure more heat loss, which not only reduces efficiency but also makes the switch more likely to be damaged. In addition, the longer the switch on time, the longer the switch off time, so when the system triggers a protection mechanism, the switch cannot be turned off immediately to achieve immediate protection.

[0003] Therefore, there is currently an urgent need to invent a switch circuit that can improve upon the above-mentioned conventional technology. Summary of the Invention [Problem to be solved by the invention]

[0004] The object of the present invention is to provide a switch circuit that reduces the voltage change when the switch is turned on by pre-charging, suppresses inrush current, and avoids problems that occur in conventional methods, such as a decrease in efficiency due to an increase in the on / off time of the switch, damage to the switch, and the inability to immediately turn off the switch when protection is activated. Furthermore, the switch circuit of the present invention can achieve zero voltage switching and has a short circuit protection function. [Means for solving the problem]

[0005] In order to achieve the above object, the present invention provides a switch circuit including an input terminal, an output terminal, a first switch, a bypass resistor, an output capacitor, a diode, a second switch, a discharge resistor, a first voltage dividing resistor, and a second voltage dividing resistor. The first terminal and the second terminal of the first switch are electrically connected to the input terminal and the output terminal, respectively. Both ends of the bypass resistor are electrically connected to the input terminal and the output terminal, respectively. Both ends of the output capacitor are electrically connected to the output terminal and the ground terminal, respectively. The anode of the diode is electrically connected to the input terminal. The first terminal and the second terminal of the second switch are electrically connected to the cathode of the diode and the third terminal of the first switch, respectively. Both ends of the discharge resistor are electrically connected to the third terminal of the first switch and the ground terminal, respectively. The first voltage dividing resistor and the second voltage dividing resistor are connected in series between the output terminal and the ground terminal, and a connection node between the first voltage dividing resistor and the second voltage dividing resistor is electrically connected to the third terminal of the second switch. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic circuit diagram of a switch circuit according to a first embodiment of the present invention;

[0007] [Diagram 2] FIG. 6 is a schematic circuit diagram of a switch circuit according to a second embodiment of the present invention.

[0008] [Figure 3A] 2 shows the main voltage and current waveforms of the switch circuit of FIG. 1 when suppressing inrush current. [Figure 3B] 2 shows the main voltage and current waveforms of the switch circuit of FIG. 1 when suppressing inrush current.

[0009] [Figure 4A] 2 shows main voltage and current waveforms of the switch circuit of FIG. 1 when the first switch is turned on early in response to the operation of the post-stage converter. [Figure 4B]2 shows main voltage and current waveforms of the switch circuit of FIG. 1 when the first switch is turned on early in response to the operation of the post-stage converter.

[0010] [Figure 5A] 2 shows the main voltage and current waveforms of the switch circuit of FIG. 1 to achieve short-circuit protection when the output is short-circuited. [Figure 5B] 2 shows the main voltage and current waveforms of the switch circuit of FIG. 1 to achieve short-circuit protection when the output is short-circuited. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Some exemplary embodiments illustrating the features and advantages of the present invention are described in detail in the following description. It should be understood that the present invention can be modified in various ways in different aspects, all without departing from the scope of the present invention.

[0012] Fig. 1 is a schematic circuit diagram of a switch circuit according to a first embodiment of the present invention. As shown in Fig. 1, the switch circuit 1 includes an input terminal 11, an output terminal 12, a first switch Q1, a bypass resistor R1, an output capacitor Co, a diode D, a second switch Q2, a discharge resistor R2, a first voltage dividing resistor R3, a second voltage dividing resistor R4, an input capacitor Cin, and a post-stage voltage detection circuit 13. The first voltage dividing resistor R3 and the second voltage dividing resistor R4 form a voltage divider.

[0013] Structurally, the input terminal 11 is configured to receive an input voltage Vin, and the output terminal 12 is configured to supply an output voltage Vo. The first and second terminals of the first switch Q1 are electrically connected to the input terminal 11 and the output terminal 12, respectively. The bypass resistor R1 has both ends electrically connected to the input terminal 11 and the output terminal 12, respectively. The output capacitor Co has both ends electrically connected to the output terminal 12 and the ground terminal, respectively. The anode of the diode D is electrically connected to the input terminal 11 and is configured to prevent a reverse current flow. The first and second terminals of the second switch Q2 are electrically connected to the cathode of the diode D and the third terminal of the first switch Q1, respectively. The discharge resistor R2 has both ends electrically connected to the third terminal of the first switch Q1 and the ground terminal, respectively. The first and second voltage dividing resistors R3 and R4 are connected in series between the output terminal 12 and the ground terminal. The first and second voltage dividing resistors R3 and R4 are connected to the output terminal 12 and the ground terminal, respectively, and a connection node between the first and second voltage dividing resistors R3 and R4 is electrically connected to the third terminal of the second switch Q2. Both ends of an input capacitor Cin for decoupling are electrically connected to the input terminal 11 and the ground terminal, respectively.

[0014] In operation, immediately after power-on, the first switch Q1 is turned off, and the input voltage Vin charges the output capacitor Co through the bypass resistor R1, gradually increasing the output voltage Vo at the output terminal 12. At the same time, the second switch Q2 is turned on, and the input voltage Vin generates a voltage Vg across the discharge resistor R2. Next, the first voltage dividing resistor R3 and the second voltage dividing resistor R4 divide the output voltage Vo to generate a voltage Vsen. When the voltage Vsen rises and reaches a threshold sufficient to turn off the second switch Q2, the voltage Vg is discharged to the ground terminal through the discharge resistor R2, turning on the first switch Q1. Thus, when the first switch Q1 is turned on, the input voltage Vin is transmitted to the output terminal 12 as the output voltage Vo.

[0015] Since the voltage of the output terminal 12 is increased by charging the output capacitor Co through the bypass resistor R1, when the first switch Q1 is turned on, the voltage difference between the input terminal 11 and the output terminal 12 is reduced, thereby making it possible to avoid an inrush current caused by a large voltage difference. In addition, when the voltage of the output terminal 12 gradually increases, the voltage of the second terminal of the first switch Q1 also gradually increases, so that when the first switch Q1 is turned on, the voltage difference between the first terminal and the second terminal of the first switch Q1 is reduced, effectively suppressing the inrush current and preventing damage to the body diode of the first switch Q1 caused by the electromotive force generated by Faraday's law of electromagnetic induction.

[0016] The switch circuit 1 further includes a rear-stage voltage detection circuit 13. The rear-stage voltage detection circuit 13 is electrically connected to the voltage divider and configured to supply a rear-stage voltage V2nd to the voltage Vsen to adjust the on-time of the first switch Q1. The rear-stage voltage detection circuit 13 includes a detection capacitor C1, a detection resistor R5, and a detection terminal 14. Both ends of the detection capacitor C1 are electrically connected to the third terminal of the second switch Q2 and the detection terminal 14, respectively, and both ends of the detection resistor R5 are electrically connected to the detection terminal 14 and the ground terminal, respectively. The detection terminal 14 is configured to detect the output of the rear-stage power supply. For example, when the output terminal 12 is electrically connected to a rear-stage converter (not shown), the rear-stage converter converts the output voltage Vo supplied by the output terminal 12 of the switch circuit 1 into a rear-stage voltage V2nd, and the detection terminal 14 is electrically connected to the rear-stage voltage V2nd to detect the output of the rear-stage converter. The rear stage voltage V2nd causes an instantaneous voltage change in the detection capacitor C1, and at the same time, the voltage Vsen changes, which causes the second switch Q2 to turn off early and the first switch Q1 to turn on early.

[0017] In a multilevel power conversion system, a switch circuit is provided in the first level power protector to avoid inrush current when the power supply is turned on. In order to speed up the power-on speed of the entire system, when the output voltage Vo reaches a reference voltage (e.g., 80% or 90% of the input voltage Vin), the post-converter draws the output voltage Vo for voltage conversion. Therefore, it is necessary to turn on the first switch Q1 early so as to provide a sufficient output voltage Vo to match the operation of the post-converter.

[0018] In the first embodiment, the first switch Q1 may be a P-type MOSFET (metal oxide semiconductor field effect transistor), and the first terminal, the second terminal, and the third terminal of the first switch Q1 are a source, a drain, and a gate, respectively. The second switch Q2 may be a P-type BJT (bipolar junction transistor), and the first terminal, the second terminal, and the third terminal of the second switch Q2 are an emitter, a collector, and a base, respectively.

[0019] Fig. 2 is a schematic circuit diagram of a switch circuit according to a second embodiment of the present invention. A second switch Q3 in Fig. 2 can replace the second switch Q2 in Fig. 1. The second switch Q3 is a P-type MOSFET, and the first terminal, the second terminal, and the third terminal of the second switch Q3 are a source, a drain, and a gate, respectively.

[0020] Please refer to FIG. 1, FIG. 3A, and FIG. 3B. FIG. 3A and FIG. 3B show main voltage and current waveforms of the switch circuit 1 of FIG. 1 when suppressing inrush current. In FIG. 3A, Vg is the voltage of the third terminal of the first switch Q1, and Vsen is the voltage of the third terminal of the second switch Q2. In FIG. 3B, Iin, I1, and Io are the currents flowing through the first switch Q1, the bypass resistor R1, and the output capacitor Co, respectively. As shown in FIG. 1, FIG. 3A, and FIG. 3B, when the input voltage Vin starts to be input to the input terminal 11 (i.e., when the input voltage Vin rises), the input voltage Vin is supplied to the second switch Q2 via the diode D, and the second switch Q2 is turned on, so that the voltage Vg of the third terminal of the first switch Q1 becomes high level, and the first switch Q1 is turned off. At this time, the input voltage Vin charges the output capacitor Co via the bypass resistor R1, gradually increasing the output voltage Vo of the output capacitor Co. When the output voltage Vo is lower than the threshold voltage, the first switch Q1 is maintained in the off state, the second switch Q2 is maintained in the on state, and the output capacitor Co continues to be charged, causing the output voltage Vo to gradually increase. When the output voltage Vo increases and reaches the threshold voltage, the second switch Q2 is turned off, and the voltage Vg at the third terminal of the first switch Q1 is discharged to zero through the discharge resistor R2, causing the first switch Q1 to be turned on, and the input voltage Vin is supplied to the output terminal 12 through the first switch Q1. Note that those skilled in the art can select the resistance values ​​of the first voltage dividing resistor R3 and the second voltage dividing resistor R4 according to application requirements, and can determine the time when the second switch Q2 is turned off by changing the resistance values ​​of the first voltage dividing resistor R3 and the second voltage dividing resistor R4. In addition, in this embodiment, the post-stage converter does not operate, so the post-stage voltage V2nd is fixed to zero.

[0021] This achieves zero-voltage conduction of the first switch Q1 and reduces switching loss. Furthermore, when the first switch Q1 is turned on, the output voltage Vo is already at a relatively high level, so that the voltage change amount can be reduced and the inrush current can be reduced, thereby realizing suppression of the inrush current.

[0022] Please refer to FIG. 1, FIG. 4A, and FIG. 4B. FIG. 4A and FIG. 4B show the main voltage and current waveforms of the switch circuit 1 of FIG. 1 when the first switch Q1 is turned on early according to the operation of the post-stage converter. As shown in FIG. 1, FIG. 4A, and FIG. 4B, when the input voltage Vin starts to be input to the input terminal 11 (i.e., when the input voltage Vin rises), the second switch Q2 is turned on and the first switch Q1 is turned off, and the input voltage Vin charges the output capacitor Co through the bypass resistor R1, gradually increasing the output voltage Vo of the output capacitor Co. When the output voltage Vo rises and reaches the reference voltage, the post-stage converter converts the output voltage Vo into the post-stage voltage V2nd, and the post-stage voltage V2nd is transmitted to the third terminal of the second switch Q2 through the post-stage voltage detection circuit 13, and further, the voltage Vsen of the third terminal of the second switch Q2 rises, and the second switch Q2 is triggered to be turned off. Then, the voltage Vg at the third terminal of the first switch Q1 is discharged to zero through the discharge resistor R2, turning on the first switch Q1, and the input voltage Vin is supplied to the output terminal 12 through the first switch Q1. Generally, the reference voltage is lower than the threshold voltage, so that in this embodiment, compared with the embodiment shown in FIG. 3A and FIG. 3B, the second switch Q2 is turned off early according to the operation of the post-converter, so that the first switch Q1 is turned on early to supply electric energy to the post-converter through the first switch Q1, so that the post-converter can maintain a stable output. The reference voltage may be, for example, 80% or 90% of the input voltage Vin, but is not limited thereto.

[0023] Please refer to Figures 1, 5A, and 5B. Figures 5A and 5B show main voltage and current waveforms of the switch circuit 1 in Figure 1 for realizing short circuit protection when the output is short circuited. As shown in Figures 1, 5A, and 5B, when an input voltage Vin is input to the input terminal 11 and the output terminal 12 is short circuited to the ground terminal, the output voltage Vo becomes zero, the second switch Q2 is maintained in an ON state, and the voltage Vg of the third terminal of the first switch Q1 is maintained at a high level, so that the first switch Q1 is not triggered to be ON and is maintained in an OFF state, thereby achieving short circuit protection.

[0024] As described above, the present invention provides a switch circuit that suppresses inrush current by reducing the amount of voltage change when the switch is turned on by pre-charging, and avoids problems that occur in conventional methods, such as reduced efficiency due to increased on / off time of the switch, damage to the switch, and the inability to immediately turn off the switch when protection is activated. In addition, the switch circuit of the present invention can achieve zero voltage switching and has a short-circuit protection function, and can ensure stable output of the post-stage converter.

[0025] It should be noted that the above are only preferred embodiments proposed to explain the present invention, the present invention is not limited to the above embodiments, and the scope of the present invention is determined by the scope of the attached patent application. The present invention can be modified by those skilled in the art, but it does not deviate from the scope defined by the claims. [Explanation of symbols]

[0026] 1: Switch circuit 11: Input terminal 12: Output terminal Q1: First switch R1: Bypass resistor Co: Output capacitor D: Diode Q2, Q3: Second switch R2: discharge resistance R3: 1st voltage divider resistor R4: Second voltage divider resistor Cin: Input capacitor 13: Rear voltage detection circuit Vin: Input voltage Vo: Output voltage C1: Detection capacitor R5: Detection resistor 14: Detection terminal V2nd: Rear voltage Vg, Vsen: Voltage Iin, I1, Io: Current

Claims

1. A switch circuit including an input terminal, an output terminal, a first switch, a bypass resistor, an output capacitor, a diode, a second switch, a discharge resistor, a first voltage dividing resistor, and a second voltage dividing resistor, a first terminal and a second terminal of the first switch are electrically connected to the input terminal and the output terminal, respectively; both ends of the bypass resistor are electrically connected to the input terminal and the output terminal, both ends of the output capacitor are electrically connected to the output terminal and a ground terminal, respectively; the anode of the diode is electrically connected to the input terminal; a first terminal and a second terminal of the second switch are electrically connected to the cathode of the diode and the third terminal of the first switch, respectively; both ends of the discharge resistor are electrically connected to the third terminal and the ground terminal of the first switch, respectively; the first voltage dividing resistor and the second voltage dividing resistor are connected in series between the output terminal and the ground terminal, and a connection node between the first voltage dividing resistor and the second voltage dividing resistor is electrically connected to a third terminal of the second switch. Switch circuit.

2. 2. The switch circuit according to claim 1, wherein, when an input voltage is input to the input terminal, the first switch is turned off and the second switch is turned on, and the input voltage charges the output capacitor through the bypass resistor, thereby increasing the output voltage of the output capacitor.

3. 3. The switch circuit according to claim 2, wherein when the output voltage increases and reaches a threshold voltage, the second switch is turned off, the voltage of the third terminal of the first switch is discharged through the discharge resistor to zero, turning on the first switch, and the input voltage is supplied to the output terminal through the first switch.

4. Further including a post-stage voltage detection circuit, the rear stage voltage detection circuit includes a detection terminal, a detection capacitor, and a detection resistor; the detection terminal is configured to receive a post-stage voltage, the output terminal is electrically connected to a post-stage converter, and the post-stage converter is configured to convert an output voltage provided by the output terminal into the post-stage voltage; both ends of the detection capacitor are electrically connected to the third terminal and the detection terminal of the second switch, respectively; Both ends of the detection resistor are electrically connected to the detection terminal and the ground terminal, respectively.

2. The switch circuit according to claim 1.

5. 5. The switch circuit according to claim 4, wherein, when an input voltage is input to the input terminal, the first switch is turned off and the second switch is turned on, and the input voltage charges the output capacitor through the bypass resistor, thereby increasing the output voltage of the output capacitor.

6. 6. The switch circuit according to claim 5, wherein when the output voltage rises and reaches a reference voltage, the post-stage converter converts the output voltage to the post-stage voltage, the post-stage voltage detection circuit turns off the second switch by the post-stage voltage, the voltage of the third terminal of the first switch is discharged through the discharge resistor to zero to turn on the first switch, and the input voltage is supplied to the output terminal through the first switch.

7. 7. The switch circuit according to claim 6, wherein the reference voltage is 80% or 90% of the input voltage.

8. 6. The switch circuit according to claim 5, wherein the latter stage voltage changes a voltage of the third terminal of the second switch via the detection capacitor to turn off the second switch early and to turn on the first switch early.

9. 2. The switch circuit according to claim 1, wherein the time point at which the second switch is turned off can be adjusted by changing a resistance value of the first voltage dividing resistor and a resistance value of the second voltage dividing resistor.

10. 2. The switch circuit of claim 1, wherein the first switch is a P-type metal oxide semiconductor field effect transistor, and the first terminal, the second terminal, and the third terminal of the first switch are a source, a drain, and a gate, respectively.

11. 2. The switch circuit of claim 1, wherein the second switch is a bipolar junction transistor, and the first terminal, the second terminal, and the third terminal of the second switch are an emitter, a collector, and a base, respectively.

12. 2. The switch circuit of claim 1, wherein the second switch is a P-type metal oxide semiconductor field effect transistor, and the first terminal, the second terminal, and the third terminal of the second switch are a source, a drain, and a gate, respectively.

13. The switch circuit according to claim 1 , further comprising an input capacitor for decoupling, both ends of the input capacitor being electrically connected to the input terminal and the ground terminal, respectively.

14. 2. The switch circuit according to claim 1, wherein when an input voltage is input to the input terminal and the output terminal is shorted to the ground terminal, the output voltage becomes zero, the second switch is maintained in an on state, the voltage of the third terminal of the first switch is maintained at a high level, and the first switch is maintained in an off state.

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