Wiring board and method for manufacturing wiring board

Abstract

To enhance connection reliability.SOLUTION: A wiring board includes: a wiring layer; an insulating layer 130 that is stacked on the wiring layer; an opening portion that penetrates the insulating layer 130 to the wiring layer; and a conductor film that is formed in the opening portion of the insulating layer 130. The surface of the insulating layer 130 includes: a smooth portion 130b that is exposed from the conductive film; and a roughened portion 130a that includes an inner wall of the opening portion covered with the conductive film and has a larger surface roughness than the smooth portion 130b.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, for example, wiring boards on which semiconductor chips are mounted have a multilayer wiring structure formed by using a semi-additive method. Specifically, a wiring layer is formed on an insulating layer by electroless plating and electrolytic plating, and an insulating layer is further formed to cover the wiring layer. In this way, a wiring board having a multilayer wiring structure is formed by repeatedly stacking insulating layers and wiring layers.

[0003] In such a wiring board, vias are provided through the insulating layer as necessary, and wiring patterns of different wiring layers are electrically connected. The outermost wiring layer of the multilayer wiring structure is covered with an insulating solder resist layer. Then, connection terminals are provided through the solder resist layer as necessary, so that the outermost wiring layer can be electrically connected to electronic components such as semiconductor chips mounted on the solder resist layer.

[0004] These vias and connection terminals are formed by forming an opening in an insulating layer or a solder resist layer, forming a seed layer by electroless plating on the surface of the insulating layer or the solder resist layer including the inner wall surface of the opening, and then performing electrolytic plating on the seed layer. The electrolytic plating is performed by masking the areas other than the areas where the vias and connection terminals are to be formed with, for example, a dry film resist (DFR). After the electrolytic plating is performed, the DFR is removed, and the seed layer exposed in the unnecessary areas is removed by etching. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-125709 A [Patent Document 2] JP 2019-186243 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, the above-mentioned wiring board has a problem that the connection reliability of the vias and the connection terminals is not sufficient. Specifically, when the unnecessary part of the seed layer is removed by etching, the seed layer at the base of the vias and the connection terminals is etched from the side by side etching, and undercuts occur. This is because the etching solution used for etching the seed layer is isotropic, and the unnecessary part of the seed layer is etched in the thickness direction and at the same time, it is also etched in the direction along the surface, and the vicinity of the base of the vias and the connection terminals is dissolved from the side.

[0007] Since the amount of undercut varies depending on the etching time, it is possible to reduce the undercut by shortening the etching time. However, in this case, the unnecessary seed layer may not be sufficiently removed, which may cause a short circuit in the wiring pattern. Therefore, the etching time is generally set longer than the time required to completely remove the unnecessary seed layer in the thickness direction to reliably prevent a short circuit in the wiring pattern. As a result, side etching increases and the undercut becomes larger.

[0008] If the undercut becomes large, the range of movement of the vias and the connection terminals becomes large, and the electrical connection between the vias and the connection terminals and the wiring layer becomes unstable, which reduces the connection reliability with the wiring layer of the wiring board.

[0009] The disclosed technology has been made in view of the above points, and has an object to provide a wiring board and a method for manufacturing a wiring board that can improve connection reliability. [Means for solving the problem]

[0010] In one aspect, the wiring board disclosed in the present application has a wiring layer, an insulating layer stacked on the wiring layer, an opening penetrating the insulating layer to the wiring layer, and a conductor film formed in the opening of the insulating layer, and the surface of the insulating layer has a smooth portion exposed from the conductor film and a roughened portion including an inner wall surface of the opening covered by the conductor film and having a surface roughness greater than that of the smooth portion. Effect of the Invention

[0011] According to one aspect of the wiring board and the method for manufacturing the wiring board disclosed in the present application, it is possible to obtain an effect of improving connection reliability. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing a configuration of a wiring board according to an embodiment. [Diagram 2] FIG. 2 is an enlarged view of a portion of the connection terminal. [Diagram 3] FIG. 3 is an enlarged view of the periphery of the via. [Figure 4] FIG. 4 is a flow diagram showing a method for manufacturing a semiconductor device according to an embodiment. [Diagram 5] FIG. 5 is a diagram showing a specific example of a core substrate forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of the insulating layer forming step. [Figure 7] FIG. 7 is a diagram showing a specific example of the opening forming step. [Figure 8] FIG. 8 is a diagram showing a specific example of a wiring layer forming step. [Figure 9] FIG. 9 is a diagram showing a specific example of a multi-layer wiring structure. [Figure 10] FIG. 10 is a diagram showing a specific example of the solder resist layer forming step. [Figure 11] FIG. 11 is a diagram showing a specific example of a connection terminal forming step. [Figure 12] FIG. 12 is a diagram showing a specific example of a semiconductor chip mounting process. [Figure 13]FIG. 13 is a flow chart showing the connection terminal forming step. [Figure 14] FIG. 14 is an enlarged view of a part of the solder resist layer. [Figure 15] FIG. 15 is a diagram showing a specific example of the opening forming step. [Figure 16] FIG. 16 is a diagram showing a specific example of the desmear treatment process. [Figure 17] FIG. 17 is a diagram showing a specific example of an electroless plating process. [Figure 18] FIG. 18 is a diagram showing the appearance of the surface of the seed layer. [Figure 19] FIG. 19 is a diagram showing a specific example of a DFR layer forming step. [Figure 20] FIG. 20 is a diagram showing a specific example of an electrolytic plating process. [Figure 21] FIG. 21 is a diagram showing a specific example of the DFR layer removing step. [Figure 22] FIG. 22 is a diagram showing a specific example of the etching process. [Figure 23] FIG. 23 is a diagram showing a specific example of the mask process. [Figure 24] FIG. 24 is a diagram showing a specific example of a dry desmear treatment process. [Diagram 25] FIG. 25 is a diagram showing a specific example of a mask removal process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, an embodiment of a wiring board and a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiment.

[0014] Fig. 1 is a diagram showing a configuration of a wiring board 100 according to an embodiment. Fig. 1 shows a schematic cross section of the wiring board 100. The wiring board 100 shown in Fig. 1 can be used, for example, as a substrate for a semiconductor device on which a semiconductor chip is mounted.

[0015] The wiring board 100 has a layered structure, and includes a core substrate 110, a multilayer wiring structure 120, and solder resist layers 130 and 140. In the following description, the solder resist layer 140 is the bottom layer and the solder resist layer 130 is the top layer as shown in Fig. 1, but the wiring board 100 may be used, for example, upside down, or in any position.

[0016] Core substrate 110 has wiring layers 113 formed by metal plating on both sides of base material 111, which is a plate-shaped insulator. Wiring layers 113 on both sides are connected by through-wires 112 that penetrate base material 111 as necessary.

[0017] The multilayer wiring structure 120 is a laminate of layers including an insulating layer 121 and a conductive wiring layer 122. The insulating layer 121 is formed of a heat-resistant, non-photosensitive and thermosetting insulating resin, such as epoxy resin, polyimide resin, and cyanate resin. The wiring layer 122 is formed of a metal, such as copper or a copper alloy. In FIG. 1, two layers are laminated in the multilayer wiring structure 120 above the core substrate 110, and two layers are laminated in the multilayer wiring structure 120 below the core substrate 110, but the number of layers to be laminated may be one layer or three or more layers. The adjacent wiring layers 113 and 122 are connected via the insulating layer 121 by a via 123 that penetrates the insulating layer 121 as necessary. Since the insulating layer 121 is formed of a non-photosensitive thermosetting resin, it is possible to form an opening for forming the via 123 by laser processing. As will be described later, the surface of the insulating layer 121 is roughened on the inner wall surface of the opening where the via 123 is formed and in the vicinity of the via 123.

[0018] The solder resist layer 130 is a layer that covers the uppermost wiring layer 122 of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 130 is a layer made of a heat-resistant, non-photosensitive and thermosetting insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin, and is one of the insulating layers.

[0019] The solder resist layer 130 side of the wiring board 100 is a surface on which electronic components such as semiconductor chips are mounted. At the position where the semiconductor chip is to be mounted, an opening 131 is formed in the solder resist layer 130. Since the solder resist layer 130 is formed using a non-photosensitive thermosetting resin, the opening 131 can be formed by laser processing. Then, in the opening 131, a connection terminal 150 is formed to connect the wiring layer 122 of the multilayer wiring structure 120 and the electrode of the semiconductor chip. As will be described later, the surface of the solder resist layer 130 is roughened on the inner wall surface of the opening 131 and in the vicinity of the connection terminal 150.

[0020] The solder resist layer 140, like the solder resist layer 130, is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of a heat-resistant, non-photosensitive and thermosetting insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin, and is one of the insulating layers.

[0021] The solder resist layer 140 side of the wiring board 100 is the surface to be connected to external components, devices, etc. At positions where external connection terminals for electrically connecting to external components or devices are to be formed, openings 141 are formed in the solder resist layer 140, and the wiring layer 122 of the multilayer wiring structure 120 is exposed from the openings 141. External connection terminals, such as solder balls, are formed in the openings 141. Since the solder resist layer 140 is formed using a non-photosensitive thermosetting resin, the openings 141 can be formed by laser processing.

[0022] Fig. 2 is an enlarged view of part A in Fig. 1. In this figure, the vicinity of the boundary between the connection terminal 150 and the solder resist layer 130 is shown in an enlarged manner.

[0023] As shown in FIG. 2, the connection terminal 150 has a seed layer 151 which is an electroless plated film formed by electroless plating, and a post 152 which is an electrolytic plated film formed on the seed layer 151 by electrolytic plating. In addition, in the vicinity of the position where the connection terminal 150 is formed, the surface of the solder resist layer 130 is roughened to form a roughened portion 130a. In other positions, the surface of the solder resist layer 130 is smooth to form a smooth portion 130b. The seed layer 151 which forms the connection terminal 150 is formed in the roughened portion 130a by electroless plating. Compared to the smooth portion 130b, the roughened portion 130a has a longer creepage distance per unit length in a direction parallel to the surface of the solder resist layer 130, so the amount of side etching of the seed layer 151 is smaller, and the undercut around the post 152 is also smaller.

[0024] That is, the unnecessary portion of the seed layer is formed on the smooth portion 130b, and when this seed layer is removed by etching, the seed layer 151 forming the connection terminal 150 is side-etched. At this time, since the creeping distance of the roughened portion 130a on which the seed layer 151 is formed is long, the side etching proceeds relatively slowly in a direction parallel to the surface of the solder resist layer 130, and only a small amount of the lower portion of the post 152 and the seed layer 151 is dissolved. As a result, the undercut of the connection terminal 150 is small, and the connection reliability between the connection terminal 150 and the wiring layer 122 can be improved.

[0025] Although the structure of the connection terminal 150 has been described here, the via 123 penetrating the insulating layer 121 and the surrounding wiring layer 122 are also composed of a seed layer and an electrolytic plating layer, similar to the connection terminal 150. Specifically, as shown in FIG. 3, for example, at the position where the via 123 is to be formed, the wiring layer 122 is composed of a seed layer 122a and an electrolytic plating layer 122b. The via 123 is formed by filling the seed layer 122a with electrolytic plating in the opening of the insulating layer 121. Such wiring layer 122 and via 123 are formed, for example, by a semi-additive method.

[0026] A roughened portion is formed on the surface of the insulating layer 121 near the position where the via 123 is to be formed. That is, the inner wall surface of the opening of the insulating layer 121 where the via 123 is to be formed is roughened, and the seed layer 122a is formed so as to cover the roughened portion. Since the via 123 is formed by subjecting the seed layer 122a to electrolytic plating, the undercut of the via 123 can be reduced, and the connection reliability between the via 123 and the wiring layer 113 (or the underlying wiring layer 122) can be improved.

[0027] Next, a method for manufacturing a semiconductor device having wiring board 100 configured as described above will be described with reference to a specific example and a flow chart of FIG.

[0028] First, a core substrate 110 that becomes a support member of the wiring substrate 100 is formed (step S101). Specifically, for example, as shown in FIG. 5, a through-wire 112 that penetrates a base material 111 that is a plate-shaped insulator is formed, and a wiring layer 113 of a metal such as copper or a copper alloy is formed on both sides of the base material 111 by, for example, copper foil or copper plating. The wiring layers 113 on both sides of the base material 111 are connected by through-wires 112 formed by plating of a metal such as copper or a copper alloy as necessary. As the base material 111, for example, a reinforcing material such as a woven glass fabric impregnated with an insulating resin such as an epoxy resin can be used. As the reinforcing material, in addition to the woven glass fabric, a nonwoven glass fabric, an aramid woven fabric, or an aramid nonwoven fabric can be used. In addition to the epoxy resin, a polyimide resin or a cyanate resin can be used as the insulating resin.

[0029] Then, a multilayer wiring structure 120 is formed by a build-up method on the upper and lower surfaces of the core substrate 110. Specifically, for example, as shown in Fig. 6, first, an insulating layer 121 is formed on the upper and lower surfaces of the core substrate 110 (step S102). That is, an insulating layer 121 made of a heat-resistant, non-photosensitive, thermosetting resin such as an epoxy resin, a polyimide resin, or a cyanate resin is laminated on the wiring layer 113 of the core substrate 110.

[0030] An opening is formed at a position where the via 123 of the insulating layer 121 is to be formed (step S103). That is, for example, as shown in FIG. 7, an opening 121a is formed that penetrates the insulating layer 121 and exposes the wiring layer 113 at the bottom. At this time, since the insulating layer 121 is formed of a non-photosensitive resin, the opening 121a is formed by laser processing. For example, a CO2 laser or a UV laser is used for the laser processing, and the surface of the insulating layer 121 is irradiated with a laser so that the surface temperature of the insulating layer 121 is at least equal to or higher than the glass transition temperature of the resin constituting the insulating layer 121. That is, when the opening 121a is formed, a laser having energy that changes the material of the insulating layer 121 is irradiated to the inner wall surface and the periphery of the opening 121a, and the inner wall surface and the periphery of the opening 121a are embrittled.

[0031] When the opening 121a is formed in the insulating layer 121, a desmear process is performed to remove the resin residue. That is, the resin residue remaining in and around the opening 121a is removed using, for example, a potassium permanganate solution. At this time, since the inner wall surface and the periphery of the opening 121a are embrittled, when these parts are immersed in a chemical solution used for the desmear process, the surface of the insulating layer 121 is roughened and the surface roughness increases. The surface roughness of the inner wall surface and the periphery of the opening 121a is, for example, about 3 to 10 times larger than the surface roughness of the part that is not embrittled by the laser irradiation.

[0032] Then, the wiring layer 122 is formed on the insulating layer 121 with the opening 121a formed therein (step S104). The wiring layer 122 is formed by, for example, a semi-additive method. In this case, a seed layer is formed on the surface of the insulating layer 121 including the inner wall surface of the opening 121a by, for example, electroless copper plating. Next, a plating resist layer having an opening in a wiring pattern forming portion is formed on the seed layer. Next, for example, electrolytic copper plating is applied to the seed layer exposed from the opening of the plating resist layer to form an electrolytic plating layer. Next, the plating resist layer is removed. Thereafter, the seed layer exposed from the electrolytic plating layer is removed by etching to form the wiring layer 122 having the desired wiring pattern.

[0033] At this time, as shown in FIG. 8, for example, the opening 121a of the insulating layer 121 is filled with electrolytic copper plating to form a via 123 penetrating the insulating layer 121, and the wiring layer 113 of the core substrate 110 and the wiring layer 122 are electrically connected. After the wiring pattern is formed by electrolytic copper plating, the seed layer of the unnecessary portion where the wiring pattern is not formed is removed by etching. However, since the surface of the insulating layer 121 is roughened around the via 123, the amount of side etching of the seed layer forming the via 123 is small. Therefore, the undercut around the via 123 is small, and the connection reliability by the via 123 can be improved. The seed layer may be formed by sputtering a metal such as copper. The seed layer by electroless plating or sputtering and the electrolytic plating layer are examples of the conductor film.

[0034] By repeating the formation of the insulating layer 121, the formation of the openings 121a, and the formation of the wiring layer 122 as described above a desired number of times, the insulating layers 121 and the wiring layers 122 are sequentially stacked to form the multilayer wiring structure 120. In the following, the explanation will be continued assuming that two insulating layers 121 and two wiring layers 122 are formed on the top and bottom surfaces of the core substrate 110, for example, as shown in Fig. 9. Around each via 123 shown in Fig. 9, the surface of the insulating layer 121 is roughened, so that undercuts around the vias 123 are small and connection reliability is improved.

[0035] When the multilayer wiring structure 120 is formed by the build-up method, the wiring layer 122 on the surface of the multilayer wiring structure 120 is covered with the solder resist layers 130, 140 (step S105). That is, the wiring layer 122 on the surface of the multilayer wiring structure 120 laminated on the upper surface of the core substrate 110 is covered with the solder resist layer 130, and the wiring layer 122 on the surface of the multilayer wiring structure 120 laminated on the lower surface of the core substrate 110 is covered with the solder resist layer 140. The solder resist layers 130, 140 are formed from a heat-resistant, non-photosensitive, thermosetting resin material such as epoxy resin, polyimide resin, and cyanate resin.

[0036] 10, for example, openings 131 are formed in the solder resist layer 130 on the side on which the semiconductor chip is mounted at positions where connection terminals 150 for connecting to the semiconductor chip are to be provided (step S106). The top wiring layer 122 of the multilayer wiring structure 120 is exposed at the bottom of the openings 131. Meanwhile, openings 141 are formed in the solder resist layer 140 on the side connected to external components or devices at positions where external connection terminals are to be provided. The bottom of the openings 141 is exposed at the bottom of the openings 141.

[0037] Since the solder resist layers 130, 140 are formed of a non-photosensitive resin, the openings 131, 141 are formed by laser processing. For example, a CO2 laser or a UV laser is used for the laser processing, and the surfaces of the solder resist layers 130, 140 are irradiated with a laser so that the surface temperature of the solder resist layers 130, 140 is at least equal to or higher than the glass transition temperature of the resin constituting the solder resist layers 130, 140. In other words, when the openings 131, 141 are formed, the inner wall surfaces and peripheries of the openings 131, 141 are irradiated with a laser having energy that alters the material of the solder resist layers 130, 140, and the inner wall surfaces and peripheries of the openings 131, 141 become embrittled.

[0038] When the openings 131, 141 are formed in the solder resist layers 130, 140, a desmear process is performed to remove the resin residue. That is, the resin residue remaining in and around the openings 131, 141 is removed using, for example, a potassium permanganate solution. At this time, since the inner wall surfaces and periphery of the openings 131, 141 are embrittled, when these parts are immersed in a chemical solution used for the desmear process, the surfaces of the solder resist layers 130, 140 are roughened and the surface roughness increases. The surface roughness of the inner wall surfaces and periphery of the openings 131, 141 is, for example, about 3 to 10 times larger than the surface roughness of the parts that are not embrittled by the laser irradiation.

[0039] Then, the connection terminals 150 are formed in the openings 131 of the solder resist layer 130 (step S107). That is, a seed layer is formed on the surface of the solder resist layer 130 by, for example, electroless copper plating, and the seed layer is subjected to, for example, electrolytic copper plating at the positions of the openings 131 to form the connection terminals 150 consisting of the seed layer 151 and the posts 152. The connection terminals 150 are connected to the uppermost wiring layer 122 of the multilayer wiring structure 120 at the positions of the openings 131 of the solder resist layer 130, as shown in, for example, FIG. 11. The seed layer may be formed by sputtering a metal such as copper. The seed layer formed by electroless plating or sputtering, and the electrolytic plating layer are examples of the conductor film.

[0040] When forming the connection terminal 150, the post 152 is formed on the seed layer 151 by electrolytic copper plating, and then the unnecessary portion of the seed layer is removed by etching, but since the surface of the solder resist layer 130 is roughened around the opening 131, the amount of side etching of the seed layer 151 is small. Therefore, the undercut around the connection terminal 150 is small, and the connection reliability by the connection terminal 150 can be improved. The formation of the connection terminal 150 will be described in detail later.

[0041] The formation of connection terminals 150 completes wiring board 100. Then, a semiconductor chip is mounted on the solder resist layer 130 side of wiring board 100 (step S108), and connection terminals 150 and electrodes of the semiconductor chip are connected.

[0042] Specifically, as shown in FIG. 12, for example, the semiconductor chip 180 is mounted above the connection terminal 150. The semiconductor chip 180 is mounted on the wiring board 100 by bonding the electrodes 181 to the connection terminal 150 by, for example, solder, and sealing the bonding portions between the electrodes 181 and the connection terminal 150 by underfill resin 182. Next, external connection terminals such as solder balls 170 are formed in the openings 141 of the solder resist layer 140 (step 109). The above-mentioned process of mounting the semiconductor chip 180 and the process of forming the external connection terminals may be performed in reverse order. Also, the solder balls 170 may not be provided, and the portions of the wiring layer 122 exposed from the openings 141 of the solder resist layer 140 may serve as the external connection terminals.

[0043] Next, the process of forming the connection terminal 150 will be described more specifically with reference to the flow diagram shown in Fig. 13. Here, a method of forming the connection terminal 150 on the solder resist layer 130 that covers the uppermost wiring layer 122 of the multilayer wiring structure 120 will be described, for example, as shown in Fig. 14. However, a similar method can also be applied to the case of forming a via 123 in the insulating layer 121.

[0044] When the solder resist layer 130 is formed using a non-photosensitive insulating resin, an opening 131 is formed in the solder resist layer 130 (step S201). Specifically, as shown in FIG. 15, for example, a laser such as a CO2 laser or a UV laser is irradiated at a position where the wiring pattern of the wiring layer 122 is to be arranged, thereby forming the opening 131 in the solder resist layer 130. At this time, a relatively high-energy laser is irradiated so that the surface temperature of the solder resist layer 130 is at least equal to or higher than the glass transition temperature of the resin constituting the solder resist layer 130, so that the inner wall surface 131a of the opening 131 and the resin around it are altered and embrittled. In FIG. 15, the part where the resin is altered is indicated by a thick line.

[0045] Then, a desmear process is performed to remove resin residue remaining on the bottom surface and inner wall surface 131a of opening 131 and their periphery (step S202). That is, the inside of opening 131 and its periphery are cleaned with a chemical solution such as a potassium permanganate solution. Since inner wall surface 131a of opening 131 and its periphery are embrittled by laser irradiation, they are roughened when immersed in the chemical solution, for example, as shown in FIG. 16. That is, around opening 131, roughened portion 130a is formed on the surface of solder resist layer 130, and the surface roughness is larger than that of other smooth portions 130b.

[0046] Specifically, the arithmetic mean roughness Ra representing the surface roughness of the smooth portion 130b is, for example, about 60 to 100 nm, whereas the arithmetic mean roughness Ra of the roughened portion 130a is, for example, about 300 to 600 nm. Therefore, the surface roughness of the roughened portion 130a is, for example, about 3 to 10 times larger than the surface roughness of the smooth portion 130b. Although such a ratio of the surface roughness of the roughened portion 130a and the smooth portion 130b is an example, the surface roughness of the roughened portion 130a is preferably in the range of about 1.5 to 50 times the surface roughness of the smooth portion 130b. As the surface roughness of the roughened portion 130a increases, the creepage distance per unit length in the direction parallel to the surface of the solder resist layer 130 becomes longer in the roughened portion 130a. That is, the creepage distance per unit length in the roughened portion 130a is, for example, 3 to 10 times the creepage distance per unit length in the smooth portion 130b.

[0047] When the roughened portion 130a is thus formed around the opening 131, a seed layer 151 is formed by electroless plating (step S203). Specifically, as shown in Fig. 17, for example, electroless copper plating is applied to the surface of the solder resist layer 130 including the roughened portion 130a and the smooth portion 130b to form the seed layer 151. The thickness of the seed layer 151 is, for example, about 0.5 to 1.5 µm.

[0048] The seed layer 151 covers the upper surface, roughened portion 130a, and smooth portion 130b of the wiring layer 122. The appearance of this seed layer 151 when viewed from above is, for example, as shown in Fig. 18. That is, a portion covering the roughened portion 130a including the inner wall surface of the opening 131 extends around the portion covering the upper surface of the central wiring layer 122, and a portion covering the smooth portion 130b extends around that portion. The seed layer 151 may be formed by sputtering a metal such as copper.

[0049] After the seed layer 151 is formed, a dry film resist (DFR) layer that serves as a mask for electrolytic plating is formed (step S204). That is, the DFR is laminated on the seed layer 151, and exposure and development are performed according to the positions of the connection terminals 150, thereby forming a DFR 210 on the seed layer 151 except for the positions where the connection terminals 150 are to be formed, as shown in FIG.

[0050] Then, electrolytic plating is performed to form posts 152 on seed layer 151 (step S205). Specifically, for example, electrolytic copper plating is performed using a copper sulfate plating solution, whereby copper is deposited in the portion where DFR 210 is not formed, and posts 152 are formed on seed layer 151, as shown in Fig. 20. At this time, openings 131 are filled with electrolytic plating.

[0051] After the posts 152 are formed, the DFR 210 is removed (step S206). For example, an alkaline stripping solution such as caustic soda or an amine is used to remove the DFR 210. By removing the DFR 210, the posts 152 protrude from the solder resist layer 130 and are connected to the wiring layer 122 via the seed layer 151, as shown in FIG. 21 for example. At this stage, the seed layer 151 remains over the entire surface, and the posts 152 are short-circuited with other posts, so that it is necessary to remove the unnecessary portions of the seed layer 151 that do not overlap with the posts 152.

[0052] Therefore, the seed layer 151 is etched using the posts 152 as a mask (step S207). Specifically, the seed layer 151 formed on the upper surface of the solder resist layer 130 is immersed in an etching solution that selectively dissolves copper, for example, and unnecessary portions of the seed layer 151 that do not overlap with the posts 152 are removed, for example, as shown in Fig. 22. As a result, a connection terminal 150 that is connected to the wiring layer 122 and is made up of the seed layer 151 and the posts 152 is formed.

[0053] In the etching of the seed layer 151, the unnecessary portion of the seed layer 151 is dissolved, and at the same time, the side etching proceeds and the seed layer 151 overlapping the post 152 is dissolved from the side. However, in the region overlapping the post 152, the seed layer 151 is formed on the roughened portion 130a of the surface of the solder resist layer 130, so the side etching proceeds relatively slowly. That is, since the creeping distance of the roughened portion 130a is long, the etching solution is prevented from entering the seed layer 151 on the roughened portion 130a, and the amount of side etching of the seed layer 151 is reduced. As a result, the amount of the seed layer 151 overlapping the post 152 that is dissolved is reduced, and the undercut of the connection terminal 150 is reduced. Therefore, the connection terminal 150 is reliably fixed to the surface of the solder resist layer 130, and the connection reliability between the connection terminal 150 and the wiring layer 122 can be improved.

[0054] As described above, according to the present embodiment, when an opening is formed in an insulating layer made of resin by laser processing, the resin around the opening is altered by laser irradiation, and when the resin residue is removed by desmearing, the altered opening periphery is roughened. Then, a seed layer is formed on the surface of the insulating layer including the opening periphery, electrolytic plating is performed on the seed layer to form a connection terminal or a via, and an unnecessary portion of the seed layer is removed by etching. Therefore, when the unnecessary portion of the seed layer is etched, the intrusion of the etching solution into the roughened opening periphery is hindered, and the amount of side etching of the seed layer in the portion overlapping with the electrolytic plating can be reduced. As a result, the connection terminal or via can be reliably fixed to the surface of the insulating layer, and the connection reliability of the connection terminal or via can be improved.

[0055] In the above embodiment, the resin around the opening of the insulating layer is altered by laser irradiation, and the surface of the insulating layer is roughened by desmearing around the altered opening. However, the method of roughening the surface of the insulating layer is not limited to the above method. For example, after forming an opening in the insulating layer, the part to be smooth other than the opening periphery may be masked with, for example, DFR, and the unmasked opening periphery may be subjected to, for example, dry desmearing, to roughen the opening periphery.

[0056] In this case, when the solder resist layer 130 is formed using, for example, an insulating resin, an opening 131 is formed in the solder resist layer 130, and a mask is formed around the opening 131 using, for example, a DFR. That is, for example, as shown in Fig. 23, the surface of the solder resist layer 130 except for the inner wall surface 131a of the opening 131 and its periphery is masked by a DFR 220.

[0057] Then, a dry desmear process is performed to remove resin residue remaining on the bottom surface and inner wall surface 131a of opening 131 and their surroundings. The dry desmear process is a type of plasma process, and uses, for example, CF4 (carbon tetrafluoride) gas to finely etch the resin on the surface of the insulating layer. Therefore, the dry desmear process roughens the surface of solder resist layer 130 on inner wall surface 131a of opening 131 exposed from DFR 220 and its surroundings, for example, as shown in FIG.

[0058] 25, for example, when the mask made of DFR 220 is removed, roughened portion 130a and smooth portion 130b are formed on the surface of solder resist layer 130. That is, around opening 131, roughened portion 130a is formed on the surface of solder resist layer 130, and the surface roughness is greater than that of other smooth portions 130b.

[0059] Although this method adds the steps of masking using DFR and removing the mask, it makes it possible to roughen the area around the opening even when forming an opening in an insulating layer by exposure and development, and a photosensitive resin can be used as the material for the insulating layer.

[0060] Furthermore, in the above embodiment, the connection terminal 150 is composed of the seed layer 151 and the post 152, but a surface treatment layer, such as nickel / palladium / gold plating, may be formed on the upper surface of the connection terminal 150. By forming a surface treatment layer on the upper surface of the connection terminal 150, for example, when the electrode 181 of the semiconductor chip 180 is joined to the connection terminal 150 by solder, the wettability of the solder can be improved.

[0061] In the above embodiment, the wiring board 100 in which the multilayer wiring structure 120 is formed by a build-up method on the core substrate 110 has been described as an example. However, the present invention may be applied to a coreless wiring board that does not have the core substrate 110. [Explanation of symbols]

[0062] 110 Core Board 111 Base material 112 Through Wiring 113, 122 wiring layer 120 Multilayer wiring structure 121 Insulating layer 121a, 131, 141 opening 123 Beer 130, 140 Solder resist layer 130a Roughening section 130b Smooth part 150 Connection terminal 151 Seed Layer 152 Posts 180 Semiconductor Chips

Claims

1. A wiring layer; an insulating layer laminated on the wiring layer; an opening penetrating the insulating layer to the wiring layer; a conductive film formed in the opening of the insulating layer, The surface of the insulating layer is a smooth portion exposed from the conductive film; a roughened portion including an inner wall surface of the opening covered with the conductor film and having a surface roughness greater than that of the smooth portion; having The roughening portion is a conductive layer is provided on a surface of the insulating layer around the opening, surrounding the entire periphery of the opening and on an inner wall surface of the opening; The smooth portion is a surface of the insulating layer that surrounds the entire periphery of the roughened portion, The conductive film is The roughened portion and the surface of the wiring layer exposed from the opening are covered, and the smooth portion is exposed. A wiring board comprising:

2. The conductive film is a first conductor film covering an inner wall surface of the opening and a surface of the wiring layer exposed from the opening; a second conductor film laminated on the first conductor film; 2. The wiring board according to claim 1, further comprising:

3. The side surface of the first conductive film is 3. The wiring board according to claim 2, wherein the second conductive film is positioned radially inward of a side surface of the opening.

4. The roughening portion is 2. The wiring board according to claim 1, wherein the surface roughness of the smooth portion is 1.5 to 50 times greater than the surface roughness of the smooth portion.

5. The side surface of the conductor film on the surface of the insulating layer is 2 . The wiring board according to claim 1 , wherein the roughened portion is located radially inward of the opening with respect to a periphery of the roughened portion on the surface of the insulating layer.

6. The conductive film is 2. The wiring board according to claim 1, wherein a connection terminal is formed by connecting to the wiring layer and protruding from an opening in the insulating layer.

7. The conductive film is 2. The wiring board according to claim 1, further comprising a via formed to connect the wiring layer to another wiring layer formed on the insulating layer.

8. laminating an insulating layer on the wiring layer; forming an opening in the insulating layer that penetrates to the wiring layer; roughening a portion of a surface of the insulating layer including an inner wall surface of the opening; forming a conductor film on a surface of the insulating layer; removing unnecessary portions of the conductor film by etching; having The roughening step includes: a surface of the insulating layer is roughened to form a roughened portion on the surface of the insulating layer around the opening, the roughened portion being provided on an inner wall surface of the opening and surrounding the entire periphery of the opening, and a smooth portion being provided on the surface of the insulating layer, the smooth portion being provided on the entire periphery of the roughened portion; The conductor film after the removing step is The roughened portion and the surface of the wiring layer exposed from the opening are covered, and the smooth portion is exposed.

4. A method for manufacturing a wiring board comprising the steps of:

9. The step of forming the opening includes: forming the opening by irradiating the insulating layer with a laser and modifying a part of a surface of the insulating layer including an inner wall surface of the opening; The roughening step includes: A part of the surface of the altered insulating layer is roughened by a desmear treatment using a chemical solution.

9. The method for manufacturing a wiring board according to claim 8.

10. The roughening step includes: forming a mask on the surface of the insulating layer excluding the portion; a step of micro-etching the surface of the insulating layer by a dry desmear treatment using plasma to roughen the portion; removing the mask; 9. The method for manufacturing a wiring board according to claim 8, further comprising the steps of:

11. The side surface of the conductor film on the surface of the insulating layer is 9. The method for manufacturing a wiring board according to claim 8, wherein the roughened portion on the surface of the insulating layer is located radially inward of the opening with respect to a periphery of the roughened portion.

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