Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

To stabilize the electrical properties of the 2DEG.SOLUTION: A nitride semiconductor device 10 includes an electron transit layer 16, an electron supply layer 18, a gate layer 22 formed on the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, and a passivation layer 26 having a source opening 26A and a drain opening 26B. The electron transit layer 16 includes a first portion 41 located below the gate layer 22 and a second portion 42 located between the gate layer 22 and the source opening 26A and between the gate layer 22 and the drain opening 26B. The electron supply layer 18 includes a first electron supply layer 51 formed on the first portion 41 and located below the gate layer 22, and a second electron supply layer 52 formed on the second portion 42 and connected to the first electron supply layer 51.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes an electron transit layer made of a gallium nitride (GaN) layer and an electron supply layer made of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer.

[0004] In addition, in the nitride semiconductor device of Patent Document 1, a gate layer (e.g., a p-type GaN layer) containing acceptor-type impurities is provided on an electron supply layer, and a gate electrode is disposed on the gate layer. In this configuration, in the region directly below the gate layer, the gate layer raises the band energy of the conduction band in the vicinity of the heterojunction interface between the electron transit layer and the electron supply layer, thereby eliminating the channel directly below the gate layer, thereby realizing a normally-off state. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2017-73506 A

[0006] [overview] In the above nitride semiconductor device, the gate layer is formed as a remaining portion after selectively removing a part of the nitride semiconductor layer formed on the electron supply layer by etching. At this time, in the portion where the gate layer is not formed, the nitride semiconductor layer is etched until the electron supply layer is exposed. At this time, etching damage occurs in the electron supply layer located in that portion. The etching damage in the electron supply layer becomes a factor that changes the electrical characteristics of the 2DEG generated in the electron transit layer.

[0007] A nitride semiconductor device according to one aspect of the present disclosure includes an electron transport layer made of a nitride semiconductor, an electron supply layer formed on the electron transport layer and made of a nitride semiconductor having a band gap larger than that of the electron transport layer, a gate layer formed on a part of the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity, a gate electrode formed on the gate layer, and a passivation layer covering the electron supply layer, the gate layer, and the gate electrode and having a source opening and a drain opening spaced apart from each other with the gate layer in between. the electron transit layer includes a first portion located below the gate layer and a second portion located, in a plan view, between the gate layer and the source opening and between the gate layer and the drain opening, and the electron supply layer includes a first electron supply layer formed on the first portion and located below the gate layer, and a second electron supply layer formed on the second portion and connected to the first electron supply layer.

[0008] A method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes forming an initially formed electron supply layer on an electron transit layer made of a nitride semiconductor; forming a gate layer made of a nitride semiconductor containing acceptor-type impurities on the initially formed electron supply layer; removing a part of the initially formed electron supply layer by etching to expose the electron transit layer while leaving a part under the gate layer, thereby forming a first electron transit layer which is a remaining part of the initially formed electron supply layer; forming a reformed electron supply layer connected to the first electron supply layer on the electron transit layer exposed by the etching; forming a passivation layer on the reformed electron supply layer; forming a gate electrode on the gate layer; and forming a source electrode and a drain electrode on the reformed electron supply layer, wherein the initially formed electron supply layer and the reformed electron supply layer are made of nitride semiconductors having a larger band gap than the electron transit layer. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. [Diagram 3] FIG. 3 is an enlarged cross-sectional view showing an example of a structure around a gate layer. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating exemplary manufacturing steps of the nitride semiconductor device according to the embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 16] FIG. 16 is an enlarged cross-sectional view showing a structure around the gate layer in the modified example. [Figure 17] FIG. 17 is an enlarged cross-sectional view showing a structure around the gate layer in the modified example. [Figure 18] FIG. 18 is an enlarged cross-sectional view showing a structure around the gate layer in the modified example.

[0010] [Detailed Description] Hereinafter, embodiments of a nitride semiconductor device according to the present disclosure will be described with reference to the accompanying drawings.

[0011] For simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0012] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0013] [Schematic structure of nitride semiconductor device] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10, taken along line 2-2 in FIG. 1. For convenience, in the nitride semiconductor device 10 shown in FIG. 1 and FIG. 2, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless otherwise expressly specified, "plan view" refers to the nitride semiconductor device 10 viewed from above along the Z axis. Furthermore, unless otherwise expressly specified, thickness refers to the dimension along the Z direction.

[0014] As an example, the nitride semiconductor device 10 may be a HEMT using GaN. In the following, a cross-sectional structure of the nitride semiconductor device 10 will be described with reference to Fig. 2, and then a planar structure of the nitride semiconductor device 10 will be described with reference to Fig. 1.

[0015] 2, the nitride semiconductor device 10 may be configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16. The nitride semiconductor device 10 further includes a gate layer 22 formed on a part of the electron supply layer 18 with the electron supply layer 18 sandwiched therebetween, and a gate electrode 24 formed on the gate layer 22.

[0016] The substrate 12 can be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. The substrate 12 is, for example, a Si substrate. The thickness of the substrate 12 is, for example, 200 μm or more and 1500 μm or less. The Z direction of the mutually orthogonal XYZ axes shown in FIG. 1 and FIG. 2 is the thickness direction of the substrate 12, which can also be said to be the thickness direction of the electron supply layer 18.

[0017] The buffer layer 14 is formed on the substrate upper surface 12A of the substrate 12. The buffer layer 14 may be located between the substrate 12 and the electron transport layer 16. In one example, the buffer layer 14 may be composed of any material that can facilitate epitaxial growth of the electron transport layer 16. The buffer layer 14 may include one or more nitride semiconductor layers.

[0018] The buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. In order to suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the concentration of the impurity may be, for example, 4×10 16 cm -3 That's all.

[0019] The electron transit layer 16 is, for example, a GaN layer. The thickness of the electron transit layer 16 is, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 16, an impurity may be introduced into a part of the electron transit layer 16 to include a semi-insulating region other than the surface region of the electron transit layer 16. In this case, the impurity may be, for example, C, and the peak concentration of the impurity in the electron transit layer 16 may be, for example, 1×10 19 cm -3 That's all.

[0020] In one example, the electron transport layer 16 includes a first semiconductor layer formed on the buffer layer 14, a second semiconductor layer formed on the first semiconductor layer, and a third semiconductor layer formed on the second semiconductor layer. It can be said that the first semiconductor layer is formed above the substrate 12 or on the substrate 12. The third semiconductor layer is in contact with the electron supply layer 18. The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are GaN layers with different impurity concentrations. The first semiconductor layer and the third semiconductor layer are non-doped GaN layers, and the second semiconductor layer is a C-doped GaN layer containing C as an impurity.

[0021] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, since the larger the Al composition, the larger the bandgap, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably, 0.2 < x < 0.3. The thickness of the electron supply layer 18 is, for example, 5 nm or more and 20 nm or less.

[0022] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the stress received by the electron supply layer 18 near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0023] The electron supply layer 18 includes a first electron supply layer 51 and a second electron supply layer 52. The first electron supply layer 51 and the second electron supply layer 52 will be described in detail later. The nitride semiconductor device 10 further includes a gate layer 22 formed on a part of the electron supply layer 18 (on the electron supply layer 18 with a first electron supply layer 51 described later sandwiched therebetween), a gate electrode 24 formed on the gate layer 22, and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18, the gate layer 22, and the gate electrode 24, and includes a source opening 26A and a drain opening 26B. The nitride semiconductor device 10 further includes a source electrode 28 in contact with the electron supply layer 18 via the source opening 26A, and a drain electrode 30 in contact with the electron supply layer 18 via the drain opening 26B.

[0024] The gate layer 22 is located between the source opening 26A and the drain opening 26B of the passivation layer 26 and is spaced apart from each of the source opening 26A and the drain opening 26B. The gate layer 22 is located closer to the source opening 26A than to the drain opening 26B.

[0025] The gate layer 22 has a smaller band gap than the electron supply layer 18 and is made of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can be made of any material having a smaller band gap than the electron supply layer 18, which is, for example, an AlGaN layer. The gate layer 22 is, for example, a GaN layer doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of the acceptor-type impurities in the gate layer 22 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0026] As described above, the gate layer 22 contains acceptor-type impurities, which raises the energy levels of the electron transit layer 16 and the electron supply layer 18. Therefore, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 24, the 2DEG 20 is not formed in the electron transit layer 16 in the region immediately below the gate layer 22. On the other hand, the 2DEG 20 is formed in the electron transit layer 16 in regions other than the region immediately below the gate layer 22.

[0027] In this way, the presence of the gate layer 22 doped with acceptor-type impurities causes the 2DEG 20 to disappear in the region directly below the gate layer 22. As a result, the transistor operates normally off. When an appropriate on-voltage is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region directly below the gate electrode 24, providing electrical continuity between the source and drain.

[0028] The gate electrode 24 is composed of one or more metal layers. The gate electrode 24 is, for example, a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer formed of a material containing Ti, and a second metal layer formed of a material containing TiN and laminated on the first metal layer. The thickness of the gate electrode 24 is, for example, 50 nm or more and 200 nm or less.

[0029] The passivation layer 26 is formed on the electron supply layer 18. It can also be said that the passivation layer 26 covers the electron supply layer 18. The passivation layer 26 can be made of a material including any one of silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON), for example.

[0030] The thickness of the passivation layer 26 is thicker than the thickness of the electron supply layer 18. The thickness of the passivation layer 26 is, for example, 300 nm or more and 1000 nm or less. The thickness of the passivation layer 26 can be changed as desired. The passivation layer 26 includes a first passivation layer 61 and a second passivation layer 62. The detailed structures of the first passivation layer 61 and the second passivation layer 62 will be described later.

[0031] The source electrode 28 and the drain electrode 30 are disposed on the upper surface of the electron supply layer 18 so as to sandwich the gate layer 22 therebetween. Hereinafter, the direction (X direction) in which the source electrode 28 and the drain electrode 30 are arranged with the gate layer 22 sandwiched therebetween in a plan view may be referred to as a first direction. The first direction may also be referred to as the direction in which the source opening 26A and the drain opening 26B in the passivation layer 26 are arranged with the gate layer 22 sandwiched therebetween.

[0032] The source electrode 28 and the drain electrode 30 may be composed of one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be composed of a combination of two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a part of the source electrode 28 is filled in the source opening 26A and is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the source opening 26A. Similarly, at least a part of the drain electrode 30 is filled in the drain opening 26B and is in ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the drain opening 26B.

[0033] An example of the source electrode 28 includes a source contact portion 28A filled in the source opening 26A and a source field plate portion 28B formed on the passivation layer 26. The source field plate portion 28B is continuous with the source contact portion 28A and is formed integrally with the source contact portion 28A. The source field plate portion 28B includes an end portion 28C located between the drain opening 26B and the gate layer 22 in a plan view. The source field plate portion 28B is spaced apart from the drain electrode 30. The source field plate portion 28B plays a role in mitigating electric field concentration near the end portion of the gate electrode 24 and near the end portion of the gate layer 22 when a drain voltage is applied to the drain electrode 30 in a zero bias state in which no gate voltage is applied to the gate electrode 24.

[0034] [Detailed structure of the electron transport layer, electron supply layer, gate layer, and passivation layer] The detailed structures of the electron transport layer, the electron supply layer, the gate layer, and the passivation layer 26 will be described with reference to FIGS.

[0035] 2, the electron transit layer 16 includes a first portion 41, a second portion 42, and a third portion 43. The first portion 41 is a portion of the electron transit layer 16 located below the gate layer 22. The second portion 42 is a portion of the electron transit layer 16 located between the gate layer 22 and the source opening 26A and between the gate layer 22 and the drain opening 26B in a plan view. The third portion 43 is a portion located below the source opening 26A and the drain opening 26B.

[0036] The first portion 41 has a protruding portion 44 that protrudes upward from the second portion 42. The protruding portion 44 includes an upper surface 44A and a side surface 44B connected to the upper surface 44A. The upper surface 44A of the protruding portion 44 is located above the upper surface 42A of the second portion 42 and is formed in a flat surface parallel to the upper surface 42A. The protruding portion 44 of this embodiment is formed over the entire first portion 41 in a planar view. Therefore, it can be said that the first portion 41 protrudes upward from the second portion 42. In this case, the upper surface 41A of the protruding portion 44 is synonymous with the upper surface 41A of the first portion 41.

[0037] Fig. 3 is an enlarged view of the peripheral region (area A) of the gate layer 22 in Fig. 2. The details of the protruding portion 44 will be described with reference to Fig. 3. The protruding height H1 of the protruding portion 44 is, for example, 1 nm or more, and preferably 2 nm or more. The protruding height H1 of the protruding portion 44 is, for example, 10 nm or less, and preferably 5 nm or less. The protruding height H1 of the protruding portion 44 is the difference between the position of the upper surface 44A (upper surface 41A of the first portion 41) of the protruding portion 44 and the position of the upper surface 42A of the second portion 42 in the thickness direction.

[0038] The width W1 of the protruding portion 44 is, for example, 630 nm or more and 750 nm or less. The width W1 of the protruding portion 44 is the length of the protruding portion 44 in the first direction. The protruding portion 44 may have a rectangular cross-sectional shape with a constant width, or may have a cross-sectional shape that varies partially or entirely. When the protruding portion 44 has a cross-sectional shape with a varying width, for example, the average value of the width of the protruding portion 44 is set to the width W1.

[0039] An example of the width W1 of the protruding portion 44 is shorter than the width W2 of the gate layer 22 formed on the protruding portion 44. The width W2 of the gate layer 22 is, for example, not less than 640 nm and not more than 760 nm. The difference (W2-W1) between the width W1 of the protruding portion 44 and the width W2 of the gate layer 22 is, for example, not less than 1 nm and not more than 10 nm. Furthermore, the width W1 of the protruding portion 44 may be the same as the width W2 of the gate layer 22.

[0040] The protruding portion 44 in the example shown in FIG. 3 has a shape in which the width in the first direction gradually increases or the width in the first direction gradually decreases toward the top. The side surface 44B of the protruding portion 44 is inclined or curved intersecting the thickness direction. The width of the protruding portion 44 is shorter than the width W2 of the gate layer 22 over the entire thickness direction. In the example shown in FIG. 3, the side surface 44B is an inclined plane in which the width of the protruding portion 44 in the first direction gradually increases toward the top. The side surface 44B may be an inclined plane in which the width of the protruding portion 44 in the first direction gradually decreases toward the top. The side surface 44B may be a curved surface in which the width of the protruding portion 44 in the first direction gradually increases toward the top, or a curved surface in which the width of the protruding portion 44 in the first direction gradually decreases toward the top. In FIG. 3, the side surface 44B of the protruding portion 44 is exaggerated and shown to be greatly recessed in the first direction in order to make it easier to understand the shape of the side surface 44B of the protruding portion 44.

[0041] 2, the electron supply layer 18 includes a first electron supply layer 51, a second electron supply layer 52, and a third electron supply layer 53. The first electron supply layer 51 is formed on an upper surface 41A (upper surface 44A of the protruding portion 44) of the first portion 41 of the electron transit layer 16, and is located below the gate layer 22. The second electron supply layer 52 is formed on the second portion 42 of the electron transit layer 16, and is connected to the first electron supply layer 51. The third electron supply layer 53 is formed on the third portion 43 of the electron transit layer 16, and is located below the source opening 26A and the drain opening 26B, and is connected to the second electron supply layer 52.

[0042] 3, the first electron supply layer 51 has a thickness T1 of, for example, 5 nm or more and 20 nm or less, and the second electron supply layer 52 has a thickness T2 of, for example, 5 nm or more and 20 nm or less. The material constituting the second electron supply layer 52 is, for example, the same as the material constituting the first electron supply layer 51. Also, the material constituting the second electron supply layer 52 may be different from the material constituting the first electron supply layer 51. In one example, the first electron supply layer 51 is an AlGaN layer, and the second electron supply layer 52 is an AlGaN layer having a smaller Al composition than the first electron supply layer 51. In this case, the gate threshold voltage can be increased. Therefore, the gate leakage current can be suppressed by increasing the gate threshold voltage. In another example, the first electron supply layer 51 is an AlGaN layer, and the second electron supply layer 52 is an AlGaN layer having a larger Al composition than the first electron supply layer 51. In this case, the amount of 2DEG 20 formed between the gate and source and between the gate and drain increases, so that the on-resistance can be reduced.

[0043] The thickness T2 of the second electron supply layer 52 is, for example, the same as the thickness T1 of the first electron supply layer 51. The thickness T2 of the second electron supply layer 52 may be thicker than the thickness T1. In this case, the amount of 2DEG 20 formed between the gate and the source and between the gate and the drain increases, so that the on-resistance can be reduced. The thickness T2 of the second electron supply layer 52 may be thinner than the thickness T1.

[0044] 3 is equal to or thinner than the protruding height H1 of the protruding portion 44 of the electron transit layer 16. In other words, in the thickness direction, the upper surface 52A of the second electron supply layer 52 is at the same position as the upper surface 44A of the protruding portion 44 or is located lower than the upper surface 44A of the protruding portion 44. In this case, the second electron supply layer 52 includes a connection portion 52B that is partially formed thick along the side surface 44B of the protruding portion 44, and is connected to the first electron supply layer 51 at the connection portion 52B.

[0045] Furthermore, the thickness T2 of the second electron supply layer 52 may be greater than the protruding height H1 of the protruding portion 44 of the electron transit layer 16. In other words, in the thickness direction, the upper surface 52A of the second electron supply layer 52 may be located higher than the upper surface 44A of the protruding portion 44. In this case, the second electron supply layer 52 does not require the connection portion 52B, and therefore is easy to manufacture.

[0046] The material constituting the third electron supply layer 53 is, for example, the same as the material constituting the second electron supply layer 52. The thickness (not shown) of the third electron supply layer 53 is, for example, 5 nm or more and 20 nm or less. The thickness of the third electron supply layer 53 is, for example, the same as the thickness T2 of the second electron supply layer 52.

[0047] As shown in FIG. 2, the electron supply layer 18 further includes a covering portion 54 that covers the upper surface 22A and the side surface 22B of the gate layer 22 and is connected to the second electron supply layer 52. As shown in FIG. 3, the covering portion 54 includes an upper portion 54A that covers the upper surface 22A of the gate layer 22 and a side portion 54B that covers the side surface 22B of the gate layer 22. The upper portion 54A of the covering portion 54 is sandwiched between the gate layer 22 and the gate electrode 24. The gate electrode 24 is in contact with the gate layer 22 via the upper portion 54A of the covering portion 54. The covering portion 54 is connected to the second electron supply layer 52 at the lower end of the side portion 54B. The upper portion 54A of the covering portion 54 located between the gate layer 22 and the gate electrode 24 plays a role in increasing the Schottky barrier between the gate layer 22 and the gate electrode 24.

[0048] The material constituting the covering portion 54 is, for example, the same as the material constituting the second electron supply layer 52. The thickness T3 of the covering portion 54 is, for example, 5 nm or more and 20 nm or less. The thickness T3 of the covering portion 54 is, for example, the same as the thickness T2 of the second electron supply layer 52. In one example, the thickness T3 of the covering portion 54 is thicker than the thickness T1 of the first electron supply layer 51. In this case, the Schottky barrier between the gate layer 22 and the gate electrode 24 can be made higher. Furthermore, the thickness T3 of the covering portion 54 may be the same as the thickness T1, or may be thinner than the thickness T1.

[0049] Here, in the electron supply layer 18, the first electron supply layer 51 and the second electron supply layer 52 are layers formed at different times. More specifically, the first electron supply layer 51 is a layer formed prior to the gate layer 22 (hereinafter referred to as an initially formed electron supply layer), and the second electron supply layer 52 is a layer formed after the gate layer 22 (hereinafter referred to as a reformed electron supply layer). In this drawing, the portion constituted by the initially formed electron supply layer is indicated by thick dot hatching, and the portion constituted by the reformed electron supply layer is indicated by thin dot hatching.

[0050] As shown in FIG. 3, an example of the electron supply layer 18 has an interface 18A between a first electron supply layer 51, which is an initially formed electron supply layer, and a second electron supply layer 52, which is a reformed electron supply layer. The interface 18A is formed on an end face of the first electron supply layer 51 in the first direction. The interface 18A may also be formed on a lower face of an end of the first electron supply layer 51 in the first direction, in addition to the end face. The electron supply layer 18 may not have the interface 18A. For example, when the first electron supply layer 51 and the second electron supply layer 52 are made of the same material, the interface 18A may not be formed.

[0051] The third electron supply layer 53 and the covering portion 54 are configured of a reformed electron supply layer. That is, the second electron supply layer 52, the third electron supply layer 53, and the covering portion 54 are a continuous reformed electron supply layer formed at the same time.

[0052] 2, the passivation layer 26 includes a first passivation layer 61 and a second passivation layer 62. The first passivation layer 61 is formed on the second electron supply layer 52 and the gate layer 22. It can be said that the first passivation layer 61 covers the second electron supply layer 52 and the gate layer 22.

[0053] The first passivation layer 61 includes a gate opening 61A formed in a portion located on the gate layer 22. At least a portion of the gate electrode 24 is filled in the gate opening 61A and is in contact with the electron supply layer 18 (upper portion 54A of the covering portion 54) through the gate opening 61A. The first passivation layer 61 is a layer for protecting the second electron supply layer 52 from etching damage during etching to form the gate electrode 24.

[0054] The second passivation layer 62 is formed on the first passivation layer 61 and the gate electrode 24. It can be said that the second passivation layer 62 covers the first passivation layer 61 and the gate electrode 24. The source field plate portion 28B of the source electrode 28 is formed on the second passivation layer 62.

[0055] The material constituting the first passivation layer 61 and the material constituting the second passivation layer 62 may be the same or different. In one example, the first passivation layer 61 is a layer having a structure with a relatively high density, and the second passivation layer 62 is a layer having a structure with a relatively low density. Since the passivation layer 26 includes the first passivation layer 61 and the second passivation layer 62, a layer having a structure with a low density can be adopted for the second passivation layer 62 that is not in contact with the electron supply layer 18, thereby simplifying the manufacturing process.

[0056] The first passivation layer 61 has a thickness of, for example, 95 nm or more and 105 nm or less. The second passivation layer 62 has a thickness of, for example, 95 nm or more and 105 nm or less. The second passivation layer 62 is thicker than the first passivation layer 61. The second passivation layer 62 may have a thickness equal to or thinner than the first passivation layer 61. The passivation layer 26 may have an interface (not shown) between the first passivation layer 61 and the second passivation layer 62.

[0057] [Planar structure of nitride semiconductor devices] Next, the planar structure of the nitride semiconductor device 10 will be described with reference to Fig. 1. In Fig. 1, the passivation layer 26 and the source electrode 28 are omitted, and the source opening 26A, drain opening 26B, and gate opening 61A of the passivation layer 26, and the end 28C of the source electrode 28 are depicted by dashed lines.

[0058] The nitride semiconductor device 10 has, for example, active regions that contribute to transistor operation and inactive regions (not shown) that do not contribute to transistor operation. In one example, the active regions and the inactive regions are arranged alternately in the Y direction.

[0059] In the active region of the nitride semiconductor device 10, the source electrode 28 (see FIG. 2), the gate electrode 24, and the drain electrode 30 are arranged adjacent to each other in a first direction (X direction) on the electron supply layer 18 (see FIG. 2). A combination of the source electrode 28, the gate electrode 24, and the drain electrode 30 adjacent to each other in the first direction constitutes one HEMT cell HC. In the example of FIG. 1, two HEMT cells HC are arranged in the X direction in the active region. Note that in practice, more HEMT cells HC may be arranged in each active region.

[0060] [Method of manufacturing a nitride semiconductor device] An exemplary method for manufacturing the nitride semiconductor device 10 will be described with reference to Figures 4 to 15. In Figures 4 to 15, components similar to those in Figure 2 are denoted by the same reference numerals.

[0061] 4, the method for manufacturing the nitride semiconductor device 10 includes sequentially forming a buffer layer 14 and an electron transit layer 16 on a substrate 12. The substrate is, for example, a Si substrate. The buffer layer 14 and the electron transit layer 16 can be epitaxially grown by, for example, a metal organic chemical vapor deposition (MOCVD) method.

[0062] Although detailed illustration is omitted, in one example, the buffer layer 14 is a multi-layer buffer layer, in which an AlN layer (first buffer layer) is formed on the substrate 12, and then a graded AlGaN layer (second buffer layer) is formed on the AlN layer. The graded AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in that order from the side closest to the AlN layer.

[0063] Next, an electron transit layer 16 is formed on the buffer layer 14. The electron transit layer 16 is formed on the substrate 12 via the buffer layer 14. The electron transit layer 16 is, for example, a GaN layer. Although detailed illustration is omitted, in one example, after a non-doped GaN layer (first semiconductor layer) is formed on the buffer layer 14, a C-doped GaN layer (second semiconductor layer) is formed on the non-doped GaN layer. Furthermore, a non-doped GaN layer (third semiconductor layer) is formed on the C-doped GaN layer.

[0064] The manufacturing method of the nitride semiconductor device 10 includes forming an initially formed electron supply layer 70 on the electron transit layer 16 made of a nitride semiconductor. The manufacturing method of the nitride semiconductor device 10 also includes forming a gate layer 22 made of a nitride semiconductor containing acceptor-type impurities on the initially formed electron supply layer 70, and forming a first electron supply layer 51 by removing a part of the initially formed electron supply layer 70 by etching so as to expose the electron transit layer 16 while leaving a part located under the gate layer 22.

[0065] 4, an initially formed electron supply layer 70 is formed on the electron transit layer 16. The initially formed electron supply layer 70 is a layer for forming the first electron supply layer 51, and is, for example, an AlGaN layer. The initially formed electron supply layer 70 is made of a nitride semiconductor having a larger band gap than the electron transit layer 16. The initially formed electron supply layer 70 can be epitaxially grown by, for example, the MOCVD method.

[0066] Next, a first nitride semiconductor layer 71 is formed on the initially formed electron supply layer 70. The first nitride semiconductor layer 71 is a layer for forming the gate layer 22, and is, for example, a GaN layer containing Mg as an acceptor-type impurity. The first nitride semiconductor layer 71 can be epitaxially grown using an MOCVD method. As an example, the first nitride semiconductor layer 71 is formed by doping GaN with Mg while growing GaN on the initially formed electron supply layer 70.

[0067] Next, as shown in Fig. 5, a mask 72 is formed on a portion of the first nitride semiconductor layer 71. Thereafter, as shown in Fig. 6, the first nitride semiconductor layer 71 and the initially formed electron supply layer 70 are selectively removed by etching so as to expose a portion of the upper surface of the electron transit layer 16 in a portion where the mask 72 is not formed in a plan view. Then, the mask 72 is removed. As a result, the gate layer 22 is formed as the remaining portion of the first nitride semiconductor layer 71, and the first electron supply layer 51 is formed as the remaining portion of the initially formed electron supply layer 70.

[0068] When removing a portion of the initially formed electron supply layer 70 by etching, a portion of the upper surface of the electron transit layer 16 where the mask 72 is not formed is also removed. As a result, a protruding portion 44 is formed in a region (first portion 41) of the electron transit layer 16 located below the gate layer 22. The protruding height H1 of the protruding portion 44 can be adjusted by changing the amount of etching of the electron transit layer 16.

[0069] The etching rate of the material (e.g., AlGaN) constituting the initially formed electron supply layer 70 may be higher than the etching rate of the material (e.g., GaN) constituting the electron transit layer 16. In this case, when a part of the upper surface side of the electron transit layer 16 is etched, the part located under the gate layer 22 is cut into and the electron transit layer 16 is removed. As a result, as shown in FIG. 3, the width W1 of the protruding portion 44 becomes shorter than the width W2 of the gate layer 22.

[0070] The manufacturing method for the nitride semiconductor device 10 includes forming a reshaped electron supply layer 73 connected to the first electron supply layer 51 on the electron transit layer 16 exposed by etching, forming a passivation layer 26 on the reshaped electron supply layer 73, and forming a gate electrode 24 on the gate layer 22.

[0071] As shown in FIG. 7, a reformed electron supply layer 73 is formed on the electron transit layer 16 and the gate layer 22. The reformed electron supply layer 73 is a layer that covers a part of the electron transit layer 16 and the gate layer 22, and is, for example, an AlGaN layer. The reformed electron supply layer 73 is a continuous layer in which the second electron supply layer 52, the third electron supply layer 53, and the covering portion 54 are integrally formed. The reformed electron supply layer 73 is made of a nitride semiconductor having a band gap larger than that of the electron transit layer 16. The reformed electron supply layer 73 can be epitaxially grown by, for example, MOCVD.

[0072] In one example, the initially formed electron supply layer 70 is an AlGaN layer, and the reshaped electron supply layer 73 is an AlGaN layer having a smaller Al composition than the initially formed electron supply layer 70. In another example, the initially formed electron supply layer 70 is an AlGaN layer, and the reshaped electron supply layer 73 is an AlGaN layer having a larger Al composition than the initially formed electron supply layer 70.

[0073] Next, as shown in FIG. 8, a first passivation layer 61 is formed on the reformed electron supply layer 73. Thereafter, as shown in FIG. 9, a gate opening 61A is formed in the first passivation layer 61 to expose the reformed electron supply layer 73 located on the gate layer 22. The first passivation layer 61 is, for example, a SiN layer. The first passivation layer 61 can be formed by, for example, a low-pressure chemical vapor deposition (LPCVD) method. The gate opening 61A is formed by selectively removing a part of the portion of the first passivation layer 61 located on the gate layer 22 by lithography and etching using a mask.

[0074] 10, a first metal layer 74 is formed on the first passivation layer 61 and in the gate opening 61A. The first metal layer 74 is a layer for forming the gate electrode 24, and is, for example, a TiN layer. The first metal layer 74 can be formed by using, for example, a sputtering method.

[0075] 11, a portion of the first metal layer 74 is selectively removed. This forms the gate electrode 24 as the remaining portion of the first metal layer 74. The gate electrode 24 is formed so as to contact the reformed electron supply layer 73 (covering portion 54) exposed in the gate opening 61A of the first passivation layer 61. The gate electrode 24 is formed by selectively removing a portion of the first metal layer 74 by lithography and etching using a mask.

[0076] Here, the etching for selectively removing a portion of the first metal layer 74 is performed in a state where the first passivation layer 61 is formed on the reformed electron supply layer 73. Therefore, the reformed electron supply layer 73 is protected from the above-mentioned etching by the first passivation layer 61. This suppresses etching damage to the reformed electron supply layer 73 (particularly, the second electron supply layer 52).

[0077] 12, a second passivation layer 62 is formed on the first passivation layer 61 and the gate electrode 24. The second passivation layer 62 is formed so as to cover a part of the first passivation layer 61 and the gate electrode 24. The second passivation layer 62 is, for example, a SiN layer. The second passivation layer 62 can be formed by using, for example, a low-pressure CVD method. Note that forming the passivation layer 26 on the re-formed electron supply layer 73 as described above includes forming the first passivation layer 61 and forming the second passivation layer 62.

[0078] The method for manufacturing the nitride semiconductor device 10 includes forming the source electrode 28 and the drain electrode 30 on the reformed electron supply layer 73 . 13, a source opening 26A and a drain opening 26B exposing the reformed electron supply layer 73 are formed in the first passivation layer 61 and the second passivation layer 62. The source opening 26A and the drain opening 26B are formed by selectively removing parts of the first passivation layer 61 and the second passivation layer 62 by lithography and etching using a mask.

[0079] 14, a second metal layer 75 is formed on the second passivation layer 62 and in the source opening 26A and the drain opening 26B. The second metal layer 75 is a layer for forming the source electrode 28 and the drain electrode 30, and is, for example, a Ti layer. The second metal layer 75 can be formed by using, for example, a sputtering method.

[0080] Next, as shown in FIG. 15, a part of the second metal layer 75 is selectively removed. As a result, the source electrode 28 and the drain electrode 30 are formed as remaining parts of the second metal layer 75. The source electrode 28 is formed so as to contact the reformed electron supply layer 73 exposed in the source opening 26A of the first passivation layer 61 and the second passivation layer 62. The drain electrode 30 is formed so as to contact the reformed electron supply layer 73 exposed in the drain opening 26B of the first passivation layer 61 and the second passivation layer 62. The source electrode 28 and the drain electrode 30 are formed by selectively removing a part of the second metal layer 75 by lithography and etching using a mask. Through the above steps, the nitride semiconductor device 10 can be obtained.

[0081] [Effect] Next, the operation of the nitride semiconductor device 10 will be described. In a conventional nitride semiconductor device having a gate layer formed on an electron supply layer, etching during gate layer formation causes etching damage to the electron supply layer located between the gate layer and the source electrode and between the gate layer and the drain electrode. The etching damage to the electron supply layer causes fluctuations in the electrical characteristics of the 2DEG generated in the electron transit layer. The electron supply layer with etching damage becomes prone to trapping surrounding electrons. This is believed to be due to the instability of the crystal structure of the electron supply layer. When the electron supply layer has etching damage, some of the electrons moving through the 2DEG are trapped in the electron supply layer when a current flows through the 2DEG as a conductive path, causing fluctuations in the electrical characteristics of the 2DEG.

[0082] The nitride semiconductor device 10 of the above embodiment includes, as the electron supply layer 18, a first electron supply layer 51 located under the gate layer 22, and a second electron supply layer 52 located between the gate layer 22 and the source opening 26A and between the gate layer 22 and the drain opening 26B and connected to the first electron supply layer 51. In this case, by configuring the first electron supply layer 51 and the second electron supply layer 52 as different layers formed at different times, the second electron supply layer 52 can be a damage-free layer that is free from etching damage.

[0083] In more detail, an initially formed electron supply layer 70 is formed on the electron transit layer 16, and then a gate layer 22 is formed on the initially formed electron supply layer 70. In the etching for forming the gate layer 22, a portion of the initially formed electron supply layer 70 that is not located under the gate layer 22 is completely removed. Then, a reformed electron supply layer 73 is formed on the electron transit layer 16 exposed by removing the initially formed electron supply layer 70, and this reformed electron supply layer 73 is used as the second electron supply layer 52. In this case, after the initially formed electron supply layer 70 that is damaged by etching during the formation of the gate layer 22 is removed, the second electron supply layer 52 is formed as the newly formed reformed electron supply layer 73. Therefore, the second electron supply layer 52 becomes a damage-free layer that is not damaged by etching during the formation of the gate layer 22.

[0084] Since the second electron supply layer 52 is a damage-free layer, when a current flows with the 2DEG 20 as a conductive path, electrons moving through the 2DEG 20 are prevented from being trapped in the second electron supply layer 52. As a result, the electrical characteristics of the 2DEG 20 in the nitride semiconductor device 10 are stabilized. Furthermore, when designing a nitride semiconductor device 10 having desired electrical characteristics of the 2DEG 20, it becomes unnecessary to take into account control parameters related to the amount of etching. This also contributes to stabilizing the electrical characteristics of the 2DEG 20 in the nitride semiconductor device 10.

[0085] [effect] The nitride semiconductor device 10 provides the following advantages. (1) The nitride semiconductor device 10 includes an electron transit layer 16, an electron supply layer 18 formed on the electron transit layer 16, a gate layer 22 formed on a part of the electron supply layer 18, a gate electrode 24 formed on the gate layer 22, a passivation layer 26 covering the electron supply layer 18, the gate layer 22, and the gate electrode 24 and having a source opening 26A and a drain opening 26B, a source electrode 28 in contact with the electron supply layer 18 through the source opening 26A, and a drain electrode 30 in contact with the electron supply layer 18 through the drain opening 26B. The electron transit layer 16 includes a first portion 41 located under the gate layer 22, and a second portion 42 located between the gate layer 22 and the source opening 26A and between the gate layer 22 and the drain opening 26B. The electron supply layer 18 includes a first electron supply layer 51 formed on the first portion 41 and located below the gate layer 22, and a second electron supply layer 52 formed on the second portion 42 and connected to the first electron supply layer 51.

[0086] According to the above configuration, the electron supply layer 18 (second electron supply layer 52) that is free from etching damage can be positioned between the gate electrode 24 and the source electrode 28, and between the gate electrode 24 and the drain electrode 30 in a plan view. This stabilizes the electrical characteristics of the 2DEG 20 in the nitride semiconductor device 10.

[0087] (2) The thickness T2 of the second electron supply layer 52 is the same as the thickness T1 of the first electron supply layer 51. In this case, it is possible to reduce the difference between the amount of 2DEG 20 formed between the gate and source and between the gate and drain and the amount of 2DEG 20 formed directly below the gate electrode 24 when an on-voltage is applied to the gate electrode 24.

[0088] (3) The thickness T2 of the second electron supply layer 52 is greater than the thickness T1 of the first electron supply layer 51. In this case, the amount of 2DEG 20 formed between the gate and the source and between the gate and the drain increases, thereby reducing the on-resistance.

[0089] (4) The electron supply layer 18 includes a covering portion 54 that covers the upper surface 22A of the gate layer 22. An upper portion 54A of the covering portion 54 that covers the upper surface 22A of the gate layer 22 is sandwiched between the gate layer 22 and the gate electrode 24. In this case, the presence of the electron supply layer 18 (upper portion 54A of the covering portion 54) between the gate layer 22 and the gate electrode 24 can increase the Schottky barrier between the gate layer 22 and the gate electrode 24. As a result, the gate leakage current through the gate layer 22 can be reduced.

[0090] (5) The covering portion 54 covers the side surface 22B of the gate layer 22 and includes a side portion 54B connected to the second electron supply layer 52. In this case, the second electron supply layer 52, which is a damage-free layer, and the upper portion 54A of the covering portion 54, which serves to increase the Schottky barrier, can be formed as a single layer in a single formation process.

[0091] (6) The thickness T3 of the covering portion 54 is the same as or thinner than the thickness T1 of the first electron supply layer 51. In this case, it is possible to prevent the Schottky barrier from becoming excessively high and the on-resistance from becoming excessively high accordingly.

[0092] (7) The thickness T3 of the covering portion 54 is greater than the thickness T1 of the first electron supply layer 51. In this case, the Schottky barrier can be made higher. As a result, the gate leakage current through the gate layer 22 can be further reduced.

[0093] (8) The first portion 41 of the electron transit layer 16 has a protruding portion 44 that protrudes upward more than the second portion 42. The first electron supply layer 51 of the electron supply layer 18 is formed on the protruding portion 44. In this case, the initially formed electron supply layer 70 that has been damaged by etching can be removed more reliably. Therefore, the effect of (1) described above can be more significantly obtained.

[0094] <Example of change> The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

[0095] 16, the first portion 41 of the electron transit layer 16 may not include a protruding portion 44. In this case, the top surface 41A of the first portion 41 and the top surface 42A of the second portion 42 are at the same position in the thickness direction, that is, the top surfaces 41A and 42A are flush with each other. The electron transit layer 16 having the above-mentioned configuration can be formed as follows. In the step of removing a part of the initially formed electron supply layer 70 by etching (see FIG. 6) in the method for manufacturing the nitride semiconductor device 10, the initially formed electron supply layer 70 is etched so as not to remove a part of the top surface side of the electron transit layer 16. This makes it possible to form the electron transit layer 16 without the protruding portion 44.

[0096] 17, the thickness T4 of the portion 54A1 located under the gate electrode 24 in the upper portion 54A of the covering portion 54 may be partially thinned. The thickness T4 of the portion 54A1 is, for example, 1 nm or more and 10 nm or less. The ratio (T4 / T3) of the thickness T4 of the portion 54A1 to the thickness T3 of the portion of the covering portion 54 other than the portion 54A1 is, for example, 1 or more and 10 or less. In addition, the ratio (T4 / T2) of the thickness T4 of the portion 54A1 to the thickness T2 of the second electron supply layer 52 is, for example, 1 or more and 10 or less. By adjusting the thickness T4 of the portion 54A1, the height of the Schottky barrier between the gate layer 22 and the gate electrode 24 can be controlled. For example, it is considered that the amount of 2DEG 20 generated can be increased by making the thickness T2 of the second electron supply layer thicker than the thickness T1 of the first electron supply layer 51. In this case, by making the thickness T3 of the portion 54A1 thinner than the thickness T2 of the second electron supply layer, the Schottky barrier between the gate layer 22 and the gate electrode 24 can be prevented from becoming excessively high.

[0097] The covering portion 54 having the above configuration can be formed as follows. When part of the first passivation layer 61 is removed by etching in the step of forming the gate opening 61A (see FIG. 8) in the method of manufacturing the nitride semiconductor device 10, part of the upper surface side of the part of the covering portion 54 located below the gate opening 61A is also removed. This allows the thickness T4 of the part 54A1 of the upper part 54A of the covering portion 54 located below the gate electrode 24 to be partially thinned.

[0098] Furthermore, in the step of forming the gate opening 61A (see FIG. 8), when removing a part of the first passivation layer 61 by etching, the part of the covering portion 54 located under the gate opening 61A may be completely removed. In this case, as shown in FIG. 18, the gate electrode 24 contacts the gate layer 22 through the gate opening 61A.

[0099] The electron supply layer 18 may be configured so as to omit the covering portion 54. In this case, the gate electrode 24 contacts the gate layer 22 through the gate opening 61A. In the above embodiment, the nitride semiconductor device 10 is configured as a nitride semiconductor HEMT, but is not limited to a nitride semiconductor HEMT and may be configured as a nitride semiconductor diode.

[0100] The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0101] The Z direction used in this disclosure does not necessarily have to be a vertical direction, nor does it have to be perfectly aligned with the vertical direction. Therefore, the various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X direction may be a vertical direction, or the Y direction may be a vertical direction.

[0102] The terms "first", "second", "third", etc. in this disclosure are used merely to distinguish objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0103] [Appendix 1] an electron transit layer (16) made of a nitride semiconductor; an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a larger band gap than the electron transit layer (16); a gate layer (22) formed on a portion of the electron supply layer (18) and made of a nitride semiconductor containing an acceptor-type impurity; a gate electrode (24) formed on the gate layer (22); a passivation layer (26) covering the electron supply layer (18), the gate layer (22), and the gate electrode (24), and having a source opening (26A) and a drain opening (26B) spaced apart from each other with the gate layer (22) in between; a source electrode (28) in contact with the electron supply layer (18) through the source opening (26A); a drain electrode (30) in contact with the electron supply layer (18) through the drain opening (26B), The electron transport layer (16) is a first portion (41) located under the gate layer (22); a second portion (42) located between the gate layer (22) and the source opening (26A) and between the gate layer (22) and the drain opening (26B) in a plan view; The electron supply layer (18) is a first electron supply layer (51) formed on the first portion (41) and located below the gate layer (22); a second electron supply layer (52) formed on the second portion (42) and connected to the first electron supply layer (51),

[0104] [Appendix 2] 2. The nitride semiconductor device (10) according to claim 1, wherein an interface (18A) is formed between the first electron supply layer (51) and the second electron supply layer (52).

[0105] [Appendix 3] the electron supply layer (18) includes a covering portion (54) that covers an upper surface (22A) and a side surface (22B) of the gate layer (22) and is connected to the second electron supply layer (52); 3. The nitride semiconductor device (10) according to claim 1 or 2, wherein a portion (54A) of the covering portion (54) covering an upper surface (22A) of the gate layer (22) is sandwiched between the gate layer (22) and the gate electrode (24).

[0106] [Appendix 4] the first portion (41) of the electron transit layer (16) has a protruding portion (44) that protrudes upward beyond the second portion (42); The nitride semiconductor device (10) according to any one of appendix 1 to 3, wherein the first electron supply layer (51) of the electron supply layer (18) is formed on the protruding portion (44).

[0107] [Appendix 5] In the direction in which the source electrode (28) and the drain electrode (30) are arranged with the gate layer (22) in between, 5. The nitride semiconductor device (10) according to claim 4, wherein a width (W1) of the protruding portion (44) of the first portion (41) is shorter than a width (W2) of the gate layer (22).

[0108] [Appendix 6] an upper surface (52A) of the second electron supply layer (52) is located at the same position as an upper surface (44A) of the protruding portion (44) or lower than the upper surface (44A) of the protruding portion (44) in a thickness direction; The nitride semiconductor device (10) according to claim 4 or 5, wherein the second electron supply layer (52) covers a side surface (44B) of the protruding portion (44) and includes a connection portion (52B) connected to the first electron supply layer (51).

[0109] [Appendix 7] The nitride semiconductor device (10) according to claim 4 or 5, wherein an upper surface (52A) of the second electron supply layer (52) is located higher than an upper surface (44A) of the protruding portion (44) in a thickness direction.

[0110] [Appendix 8] The nitride semiconductor device (10) according to any one of Appendices 1 to 3, wherein an upper surface (42A) of the second portion (42) of the electron transit layer (16) is flush with an upper surface (41A) of the first portion (41) of the electron transit layer (16).

[0111] [Appendix 9] The nitride semiconductor device (10) according to any one of appendix 1 to 8, wherein a thickness (T2) of the second electron supply layer (52) is the same as a thickness (T1) of the first electron supply layer (51).

[0112] [Appendix 10] The nitride semiconductor device (10) according to any one of Appendices 1 to 9, wherein the passivation layer (26) includes a first passivation layer (61) covering the second electron supply layer (52), and a second passivation layer (62) covering the first passivation layer (61) and the gate electrode (24).

[0113] [Appendix 11] the electron transport layer (16) is a GaN layer, the electron supply layer (18) is an AlGaN layer; The nitride semiconductor device (10) according to any one of appendices 1 to 10, wherein the gate layer (22) is a GaN layer containing the acceptor-type impurity.

[0114] [Appendix 12] forming an initial electron supply layer (70) on an electron transit layer (16) made of a nitride semiconductor; forming a gate layer (22) made of a nitride semiconductor containing an acceptor-type impurity on the initially formed electron supply layer (70); removing a portion of the initially formed electron supply layer (70) by etching so as to expose the electron transit layer (16) while leaving a portion located under the gate layer (22), thereby forming a first electron supply layer (51) which is the remaining portion of the initially formed electron supply layer (70); forming a reformed electron supply layer (73) connected to the first electron supply layer (51) on the electron transit layer (16) exposed by the etching; forming a passivation layer (26, 61, 62) on said reformed electron supply layer (73); forming a gate electrode (24) on the gate layer (22); and forming a source electrode (28) and a drain electrode (30) on the reformed electron supply layer (73); The method for manufacturing a nitride semiconductor device, wherein the initially formed electron supply layer (70) and the re-formed electron supply layer (73) are composed of a nitride semiconductor having a larger band gap than the electron transit layer (16).

[0115] [Appendix 13] the reformed electron supply layer (73) is formed to include a covering portion (54) that covers an upper surface (22A) and a side surface (22B) of the gate layer (22); 13. The method for manufacturing a nitride semiconductor device according to claim 12, wherein the gate electrode (24) is formed on a portion (54A) of the covering portion (54) that covers an upper surface (22A) of the gate layer (22).

[0116] [Appendix 14] 14. The method for manufacturing a nitride semiconductor device according to claim 12 or 13, wherein when removing the portion of the initially formed electron supply layer (70) by etching, a portion of an upper surface side of the electron transit layer (16) is also removed.

[0117] [Appendix 15] forming the gate electrode (24) on the gate layer (22), forming a metal layer (74) on the gate layer (22); and etching away a portion of the metal layer (74) to form the gate electrode (24) which is a remaining portion of the metal layer (74); forming a passivation layer (26, 61, 62) on the reformed electron supply layer (73), 15. A method for manufacturing a nitride semiconductor device according to any one of claims 12 to 14, comprising forming a first passivation layer (61) on the reformed electron supply layer (73) before forming the metal layer (74), and forming a second passivation layer (62) on the first passivation layer (61) after forming the gate electrode (24). [Explanation of symbols]

[0118] H1: Projection height HC…HEMT cell T1~T4…Thickness W1, W2…Width 10...Nitride semiconductor device 12...Substrate 12A...Top surface of board 14…Buffer layer 16...Electron transport layer 18...electron supply layer 18A…Interface 20...Two-dimensional electron gas 22…Gate layer 22A…Top surface 22B…Side 24...Gate electrode 26…Passivation layer 26A…Source opening 26B…Drain opening 28…Source electrode 28A…Source contact section 28B…Source field plate section 28C...end 30...Drain electrode 41…Part 1 41A…Top surface 42…Second part 42A…Top surface 43...Third part 44...Protruding part 44A…Top surface 44B…Side 51...first electron supply layer 52…Second electron supply layer 52A…Top surface 52B…Connection 53…Third electron supply layer 54…Covering part 54A…Upper 54B…Side 61…First passivation layer 61A…Gate opening 62…Second passivation layer 70...Initially formed electron supply layer 71...first nitride semiconductor layer 72...Mask 73…Reformed electron supply layer 74...First metal layer 75…Second metal layer

Claims

1. an electron transit layer made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; a gate layer formed on a portion of the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity; a gate electrode formed on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a source opening and a drain opening spaced apart from each other with the gate layer therebetween; a source electrode in contact with the electron supply layer through the source opening; a drain electrode in contact with the electron supply layer through the drain opening, The electron transport layer is a first portion located below the gate layer; a second portion located between the gate layer and the source opening and between the gate layer and the drain opening in a plan view; The electron supply layer is a first electron supply layer formed on the first portion and positioned below the gate layer; a second electron supply layer formed on the second portion and connected to the first electron supply layer.

2. the electron supply layer includes a covering portion that covers an upper surface and a side surface of the gate layer and is connected to the second electron supply layer; The nitride semiconductor device according to claim 1 , wherein a portion of said covering portion covering an upper surface of said gate layer is sandwiched between said gate layer and said gate electrode.

3. the first portion of the electron transit layer has a protruding portion protruding above the second portion, The nitride semiconductor device according to claim 1 , wherein said first electron supply layer of said electron supply layer is formed on said protruding portion.

4. In a direction in which the source electrode and the drain electrode are arranged with the gate layer in between, The nitride semiconductor device according to claim 3 , wherein a width of said protruding portion of said first portion is shorter than a width of said gate layer.

5. In a thickness direction, an upper surface of the second electron supply layer is located at the same position as an upper surface of the protruding portion or lower than the upper surface of the protruding portion, The nitride semiconductor device according to claim 3 , wherein said second electron supply layer covers a side surface of said protruding portion and includes a connection portion connected to said first electron supply layer.

6. The nitride semiconductor device according to claim 3 , wherein an upper surface of said second electron supply layer is located higher than an upper surface of said protruding portion in a thickness direction.

7. The nitride semiconductor device according to claim 1 , wherein an upper surface of the second portion of the electron transport layer is flush with an upper surface of the first portion of the electron transport layer.

8. The nitride semiconductor device according to claim 1 , wherein a thickness of said second electron supply layer is the same as a thickness of said first electron supply layer.

9. 2. The nitride semiconductor device according to claim 1, wherein said passivation layer includes a first passivation layer covering said second electron supply layer, and a second passivation layer covering said first passivation layer and said gate electrode.

10. the electron transport layer is a GaN layer, the electron supply layer is an AlGaN layer; 10. The nitride semiconductor device according to claim 1, wherein said gate layer is a GaN layer containing said acceptor-type impurities.

11. forming an initial electron supply layer on an electron transit layer made of a nitride semiconductor; forming a gate layer made of a nitride semiconductor containing an acceptor-type impurity on the initially formed electron supply layer; removing a portion of the initially formed electron supply layer by etching so as to expose the electron transit layer while leaving a portion located under the gate layer, thereby forming a first electron supply layer which is the remaining portion of the initially formed electron supply layer; forming a reformed electron supply layer connected to the first electron supply layer on the electron transit layer exposed by the etching; forming a passivation layer over the reformed electron supply layer; forming a gate electrode over the gate layer; and forming a source electrode and a drain electrode on the reformed electron supply layer; The initially formed electron supply layer and the re-formed electron supply layer are made of a nitride semiconductor having a larger band gap than the electron transit layer.

12. the reformed electron supply layer is formed to include a covering portion covering an upper surface and a side surface of the gate layer; The method for manufacturing a nitride semiconductor device according to claim 11 , wherein said gate electrode is formed on a portion of said covering portion covering an upper surface of said gate layer.

13. The method for manufacturing a nitride semiconductor device according to claim 11 , wherein when the portion of the initially formed electron supply layer is removed by etching, a portion of an upper surface side of the electron transit layer is also removed.

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