Power supply controller circuit and electronic device

Abstract

To provide a power supply controller circuit capable of correctly controlling a plurality of lanes.SOLUTION: An oscillator 410 generates a clock signal CLK. A first slot pulse generator 420 generates a first slot pulse SP1 that is asserted every time the clock signal CLK is counted a predetermined number of times in a master mode. In the master mode, a timing reference signal generator 440 generates a timing reference signal TREF having a period corresponding to a period of the first slot pulse SP1 and transmits it to another power supply controller circuit 400 operating in a slave mode. In the slave mode, a second slot pulse generator 450 receives the timing reference signal TREF from the other power supply controller circuit 400 operating in the master mode, measures a time interval of the timing reference signal TREF, stores the measured value of the time interval, and generates a second slot pulse SP2 having a time interval corresponding to the measured value.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to a power supply controller circuit for managing and controlling a plurality of power supplies. [Background technology]

[0002] Mobile phones, tablet terminals, notebook personal computers (PCs), desktop PCs, and game consoles are equipped with microprocessors such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) that perform arithmetic processing.

[0003] Electronic devices incorporating microprocessors are being subdivided into multiple circuit blocks in response to the miniaturization of semiconductor manufacturing processes, the increase in peripheral circuits, and the demand for lower power consumption. Each circuit block is configured so that its power supply voltage can be controlled independently.

[0004] In such devices, a power supply controller circuit is used to control multiple power supply systems corresponding to multiple circuit blocks. The power supply controller circuit is also called a power management integrated circuit (PMIC).

[0005] The power supply controller circuit includes a sequencer that is required to reliably control the on / off of multiple power supply lanes in accordance with a predetermined sequence.

[0006] The power controller circuit controls multiple power lanes in time units called slots. For example, after starting a sequence, it is possible to set up a sequence in which the first power lane is turned on in the third slot, the second power lane is turned on in the fourth slot, the third power lane is turned on in the sixth slot, and so on. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2009-272998 A

[0008] [overview] There are systems in which the number of power supply lanes to be controlled (called the number of lanes or the number of channels) is greater than the number of lanes of a single power supply controller circuit. In such systems, it is necessary to use multiple power supply controller circuits in combination. The following describes the problems that occur in such systems.

[0009] 1 is a diagram for explaining a problem that occurs in a system equipped with a plurality of power supply controller circuits. Consider a system in which two power supply controller circuits PMIC1 and PMIC2 coexist.

[0010] Since the slot time is generated by counting the clock signal, the slot time is affected by the variation in the period of the clock signal. If the period of the clock signal has an accuracy of 10%, the accuracy of the slot time will also be 10%.

[0011] Suppose the design value of one slot time (referred to as slot time Ts) is 0.1 ms (1 MHz). In this case, in the worst case, the slot time Ts1 in one power supply controller circuit PMIC1 is 0.11 ms, and the slot time Ts2 in the other power supply controller circuit PMIC2 is 0.09 ms.

[0012] Consider a sequence in which a power lane X under the control of a first power controller IC is turned on in slot 5, and another power lane Y under the control of a second power controller IC is turned on in slot 6. In this case, it is expected that the power lane X will be turned on first, followed by the power lane Y.

[0013] In response to the start signal START, the two power supply controller circuits PMIC1 and PMIC2 start sequence control. VDDx indicates the output voltage of the power supply lane X, and VDDy indicates the output voltage of the lane Y.

[0014] As shown in FIG. 1, in the worst case, the power supply lane Y may be turned on first, and then the power supply lane X may be turned on later, resulting in a situation in which the order is reversed.

[0015] The present disclosure has been made in this context, and it is an exemplary purpose of an embodiment of the present disclosure to provide a power supply controller circuit capable of correctly controlling multiple lanes.

[0016] An embodiment of the present disclosure relates to a power supply controller circuit switchable between a master mode and a slave mode, the power supply controller circuit including an oscillator for generating a clock signal, a first slot pulse generator for generating a first slot pulse asserted every time the clock signal is counted a predetermined number in the master mode, a timing reference signal generator for generating a timing reference signal having a period corresponding to the period of the first slot pulse in the master mode and transmitting the timing reference signal to another power supply controller circuit operating in the slave mode, a second slot pulse generator for receiving a timing reference signal from the other power supply controller circuit operating in the master mode in the slave mode, measuring a time interval of the timing reference signal, storing the measured value of the time interval, and generating a second slot pulse having a time interval corresponding to the measured value in the slave mode, and a sequencer for controlling a plurality of power supply lanes in response to the first slot pulse in the master mode and for controlling a plurality of power supply lanes in response to the second slot pulse in the slave mode.

[0017] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief description of the drawings]

[0018] [Figure 1]FIG. 1 is a diagram illustrating a problem that occurs in a system having multiple power supply controller circuits. [Diagram 2] FIG. 2 is a block diagram of the power supply system according to the embodiment. [Diagram 3] FIG. 3 is a diagram showing the timing reference signal TREF. [Figure 4] FIG. 4 is a block diagram of the power supply controller IC. [Diagram 5] FIG. 5 is a block diagram of a power supply system configured using the power supply controller IC of FIG. [Figure 6] FIG. 6 is a waveform diagram illustrating the basic operation of the power supply system of FIG. [Figure 7] FIG. 7 is a waveform diagram when the timing reference signal TREF is interrupted in the power supply system of FIG. [Figure 8] FIG. 8 is a block diagram of the power supply controller IC according to the first embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a specific example of the configuration of the second slot pulse generator. [Figure 10] FIG. 10 is a block diagram of a power supply controller IC according to the second embodiment. [Figure 11] FIG. 11 is a waveform diagram illustrating the operation of the second slot pulse generator of FIG. [Figure 12] FIG. 12 is a waveform diagram illustrating another operation of the second slot pulse generator of FIG. [Figure 13] FIG. 13 is a waveform diagram illustrating still another operation of the second slot pulse generator of FIG. [Figure 14] FIG. 14 is a circuit diagram showing an example of the configuration of the second slot pulse generator of FIG. [Figure 15] FIG. 15 is a waveform diagram illustrating the operation of the second slot pulse generator of FIG. [Figure 16] FIG. 16 is a waveform diagram illustrating the operation of the second slot pulse generator of FIG. [Figure 17]FIG. 17 is a waveform diagram illustrating the operation of the second slot pulse generator of FIG.

[0019] [Detailed Description] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0020] A power supply controller circuit according to an embodiment is switchable between a master mode and a slave mode. The power supply controller circuit includes an oscillator that generates a clock signal, a first slot pulse generator that generates a first slot pulse asserted every time the clock signal is counted a predetermined number in the master mode, a timing reference signal generator that generates a timing reference signal having a period corresponding to the period of the first slot pulse in the master mode and transmits the timing reference signal to another power supply controller circuit operating in the slave mode, a second slot pulse generator that receives a timing reference signal from the other power supply controller circuit operating in the master mode in the slave mode, measures a time interval of the timing reference signal, stores the measured value of the time interval, and generates a second slot pulse having a time interval corresponding to the measured value, and a sequencer that controls a plurality of power supply lanes in response to the first slot pulse in the master mode and controls a plurality of power supply lanes in response to the second slot pulse in the slave mode.

[0021] According to this configuration, even if there is a variation in the frequency of the clock signal between the power supply controller circuit operating in the master mode and the power supply controller circuit operating in the slave mode, the power supply controller circuit in the slave mode can generate slots based on the timing reference signal from the power supply controller circuit in the master mode. This allows the power supply controller circuit in the master mode and the power supply controller circuit in the slave mode to control multiple power supply lanes in the correct order. Note that "having a period corresponding to the period of the first slot pulse" includes not only the case where the period of the timing reference signal is the same as the period of the first slot pulse, but also the case where the period of the timing reference signal is an integer multiple or an integer multiple of the period of the first slot pulse.

[0022] Furthermore, by measuring the time interval of the timing reference signal and storing it in memory in the slave mode power supply controller circuit, if the timing reference signal from the master mode power supply controller is temporarily interrupted, the stored time interval can be used to regenerate the second slot pulse.

[0023] In one embodiment, the second slot pulse generator may generate the next second slot pulse at the earlier of a first timing that is a time that has elapsed since the generation timing of the previous second slot pulse according to a measurement value, and a second timing that is the time when a timing reference signal is received.

[0024] In one embodiment, the second slot pulse generator may increment the measurement value when it generates a second slot pulse at the first timing when it does not receive a timing reference signal.

[0025] In one embodiment, the second slot pulse generator may include a counter that counts the number of times a second slot pulse is generated at the first timing when a timing reference signal is not received, and an error detector that asserts an error signal (Node 18) when the count value of the counter reaches a predetermined threshold.

[0026] In one embodiment, the second slot pulse generator may stop incrementing the measurement while the error signal is asserted.

[0027] In one embodiment, the first slot pulse is asserted for one cycle of the clock signal, and the timing reference signal may be asserted for multiple n cycles of the clock signal, where n is an integer greater than or equal to two.

[0028] In one embodiment, 2≦n≦20.

[0029] In one embodiment, the power controller circuit may further include a synchronization circuit that utilizes a clock signal to retime the timing reference signal.

[0030] In one embodiment, the power supply controller circuit may be integrated on a single semiconductor substrate. "Integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are integrated on a single substrate, and some resistors and capacitors for adjusting the circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0031] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0032] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0033] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0034] 2 is a block diagram of a power supply system 100 according to an embodiment. The power supply system 100 includes a first power supply controller IC200, a second power supply controller IC300, and multi-lane (multi-channel) power supply circuits PS1_1 to PS1_m, PS2_1 to PS2_n. m=n may be satisfied, or m≠n may be satisfied. The power supply circuits PS1 and PS2 may be step-up, step-down, or step-up / step-down DC / DC converters, or may be linear regulators (LDO: Low Drop Output).

[0035] The first power supply controller IC200 controls a plurality of power supply circuits PS1_1 to PS1_m. The second power supply controller IC300 controls a plurality of power supply circuits PS2_1 to PS2_n. Note that the main parts of the power supply circuit PS may be integrated into the first power supply controller IC200 and the second power supply controller IC300. The power supply circuit PS1 controlled by the first power supply controller IC200 is referred to as a first power supply lane, and the power supply circuit PS2 controlled by the second power supply controller IC300 is referred to as a second power supply lane.

[0036] The first power supply controller IC200 acts as a master, and the second power supply controller IC300 acts as a slave.

[0037] The first power supply controller IC 200 includes an oscillator 210, a first slot pulse generator 220, a first sequencer 230, and a timing reference signal generator 240. The oscillator 210 generates a clock signal CLK.

[0038] The first slot pulse generator 220 starts operation in response to receiving a start signal START, and generates a first slot pulse SP1 using a clock signal CLK. The first sequencer 230 controls the multiple first power supply lanes PS1_1 to PS1_m in response to the first slot pulse SP1.

[0039] The timing reference signal generator 240 generates a timing reference signal TREF in response to the first slot pulse SP1 and transmits it to the second power supply controller 300.

[0040] FIG. 3 is a diagram showing the timing reference signal TREF. The timing reference signal TREF has the same period as the first slot pulse SP1. The timing reference signal TREF is a signal obtained by widening the pulse width (high section) of the first slot pulse SP1. In this example, the high section of the first slot pulse SP1 is one clock period, and the high section of the timing reference signal TREF is n (n≧2) clock periods. The high section of the timing reference signal TREF may be determined so that the second power supply controller IC300 can reliably receive the timing reference signal TREF, taking into account the variation in the frequency of the clock signal CLK. In this example, n=10, but n is not particularly limited and may be determined in the range of 2≦n≦20. The positive edge of the timing reference signal TREF may coincide with the positive edge of the first slot pulse SP1.

[0041] 2, the second power supply controller 300 includes a second sequencer 330 and a second slot pulse generator 350.

[0042] The second slot pulse generator 350 receives the timing reference signal TREF from the first power supply controller IC 200. The second slot pulse generator 350 starts operation in response to receiving the start signal START, and generates the second slot pulse SP2 using the timing reference signal TREF.

[0043] The second sequencer 330 controls the multiple second power supply lanes PS2_1 to PS2_n in response to the second slot pulse SP2.

[0044] 2, a start signal START is supplied from an external source to the first slot pulse generator 220 and the second slot pulse generator 350, but the present disclosure is not limited to this. For example, a start signal START may be supplied only to the first power supply controller IC200, and the start signal START may be supplied to the second power supply controller IC300 via the first power supply controller IC200.

[0045] The above is the configuration of the power supply system 100. The first power supply controller IC200 and the second power supply controller IC300 may each be a dedicated IC, or as described below, may be a power supply controller IC400 having the same structure.

[0046] 4 is a block diagram of the power supply controller IC 400. When the power supply controller IC 400 is set in the master mode, it functions as the first power supply controller IC 200, and when set in the slave mode, it functions as the second power supply controller IC 300.

[0047] The power supply controller IC400 has a terminal A and a terminal B. The terminal A is a terminal for outputting the timing reference signal TREF when the power supply controller IC400 is in the master mode, and the terminal B is a terminal for receiving the timing reference signal TREF when the power supply controller IC400 is in the slave mode.

[0048] The power supply controller IC 400 includes an oscillator 410 , a first slot pulse generator 420 , a multiplexer 422 , a sequencer 430 , a timing reference signal generator 440 , and a second slot pulse generator 450 .

[0049] 2. Oscillator 410 corresponds to oscillator 210. First slot pulse generator 420 corresponds to first slot pulse generator 220 of FIG. 2. Sequencer 430 corresponds to first sequencer 230 and second sequencer 330 of FIG. 2. Timing reference signal generator 440 corresponds to timing reference signal generator 240 of FIG. 2. Second slot pulse generator 450 corresponds to second slot pulse generator 350 of FIG. 2.

[0050] The oscillator 410 generates a clock signal CLK. The first slot pulse generator 420 is active in the master mode and generates a slot pulse SP1 using the clock signal CLK. Specifically, the first slot pulse generator 420 repeats the operation of asserting (e.g., high) the slot pulse SP1 every time it counts a predetermined number of clock signals CLK (M≧2).

[0051] The second slot pulse generator 450 becomes active in the slave mode, and generates a second slot pulse SP2 based on the timing reference signal TREF input to terminal B. The second slot pulse generator 450 is supplied with the clock signal CLK.

[0052] Specifically, the second slot pulse generator 450 is capable of measuring the time interval of the timing reference signal TREF using the clock signal CLK, and storing the measured value N of the time interval in the memory 452. The second slot pulse generator 450 is capable of generating a second slot pulse SP2 having a time interval corresponding to the measured value N, using the clock signal CLK.

[0053] In one embodiment, the second slot pulse generator 450 may output a second slot pulse SP2 based on the interval of the current timing reference signal TREF when the timing reference signal TREF is input normally, and may output a second slot pulse SP2 having a time interval according to the measurement value N when the timing reference signal TREF is interrupted.

[0054] In one embodiment, the second slot pulse generator 450 may output a second slot pulse SP2 having a time interval according to the measurement value N not only when the timing reference signal TREF is interrupted, but also while the timing reference signal TREF is being input normally.

[0055] The multiplexer 422 is connected to receive the first slot pulse SP1 and the second slot pulse SP2. The multiplexer 422 selects one of them according to the mode control signal MODE. The sequencer 430 operates based on the slot pulse SP1 or SP2 selected by the multiplexer 422.

[0056] The timing reference signal generator 440 is active in the master mode and generates a timing reference signal TREF in response to the first slot pulse SP1 selected by the multiplexer 422. The timing reference signal TREF is a signal in which the high period of the first slot pulse SP1 is extended over a predetermined number of cycles of the clock signal CLK. The timing reference signal TREF is output from terminal A.

[0057] Fig. 5 is a block diagram of a power supply system 100 configured using the power supply controller IC400 of Fig. 4. In Fig. 5, active signal lines are indicated by solid lines, and inactive signal lines are indicated by dashed lines. One power supply controller IC400 is a first power supply controller IC200, which operates in a master mode. The other power supply controller IC400 is a second power supply controller IC300, which operates in a slave mode.

[0058] 6 is a waveform diagram for explaining the basic operation of the power supply system 100 of FIG. 5. In the first power supply controller IC200, a first slot pulse SP1 having a period M times (M≧2) the period of the clock signal CLK1 is repeatedly generated. CLK1 Then, the period of the first slot pulse SP1 (slot period Ts) is T=T CLK1 ×M It is.

[0059] A timing reference signal TREF having the same period (time interval) as the first slot pulse SP1 is supplied from the first power supply controller IC200 to the second power supply controller IC300.

[0060] The second slot pulse generator 450 generates a time interval T i is measured using the clock signal CLK2. i indicates the cycle number (slot number). A digital counter can be used for time measurement, and the measured time interval T i The measured value is given as a count value N. Let the period of the clock signal CLK2 be T CLK2 Then, the count value N is N i =T i / T CLK2 Count value N i is written to memory 452 as a measurement value.

[0061] The second slot pulse generator 450 generates a second slot pulse SP2 by using a digital counter with reference to the measured value N. In the i-th cycle, the memory 452 stores the count value N of the previous cycle i-1. i-1 Therefore, the interval of the second slot pulse SP2 in the i-th cycle is T CLK2 ×N 1-i It becomes.

[0062] The operation of the power supply system 100 has been described above.

[0063] The frequency of the clock signal CLK1 in the power supply controller IC400 operating in master mode (period T CLK1 ) and the frequency of the clock signal CLK2 in the power supply controller IC400 operating in slave mode (period T CLK2 ) has an error. Even in this case, the second slot pulse SP2 reproduced in the slave mode has the same period as the first slot pulse SP1 generated in the master mode. This ensures that the slots progress at the same intervals when multiple power supply controller ICs 400 are operated in cooperation. This makes it possible to prevent the order of control of the power supply lanes from being changed.

[0064] Although it has been assumed here that the second slot pulse SP2 reproduced in the slave mode has no delay with respect to the first slot pulse SP1 generated in the master mode, in reality, the signal may be delayed by several clock cycles. However, since the slot period Ts is several hundred to 1000 times the clock period, this delay does not pose a problem.

[0065] Fig. 7 is a waveform diagram when the timing reference signal TREF is interrupted in the power supply system 100 of Fig. 5. In the i-th cycle, an abnormality such as a ground fault, a short to power, or a break occurs in the wiring connecting between the terminal A of the first power supply controller IC200 and the terminal B of the second power supply controller IC300, and the second slot pulse generator 450 is no longer able to receive the timing reference signal TREF.

[0066] In the i-th cycle, a measurement value indicating the interval of the reference signal TREF measured in the (i-1)-th cycle is stored in the second slot pulse generator 450. The second slot pulse generator 450 continues to generate the second slot pulse SP2 from the i-th cycle onward using this measurement value.

[0067] In this way, according to the power supply system 100 of the embodiment, by measuring the time interval of the timing reference signal TREF and storing it in the memory 452, if the timing reference signal TREF from the power supply controller in the master mode is temporarily interrupted, the second slot pulse SP2 can be reproduced by utilizing the stored time interval.

[0068] Next, specific configuration examples and modifications of the power supply controller IC 400 will be described.

[0069] Example 1 8 is a block diagram of a power supply controller IC 400A according to the first embodiment. The second slot pulse generator 450A includes a memory 452, a synchronization circuit 454, an edge detection circuit 456, and a counter 460. The synchronization circuit 454 synchronizes the timing reference signal TREF with the clock signal CLK (retiming).

[0070] The edge detection circuit 456 receives the output signal TREF' from the synchronization circuit 454 and detects its rising edge (positive edge) to generate a reference pulse REF. The timing reference signal TREF has a pulse width wider than that of the first slot pulse SP1. The edge detection circuit 456 generates a reference pulse REF by extracting the leading one clock cycle of the output signal TREF' from the synchronization circuit 454.

[0071] The counter 460 counts the interval of the reference pulse REF using the clock signal CLK, and writes the count value N as a measured value into the memory 452. The interval of the reference pulse REF is equal to the interval of the timing reference signal TREF'.

[0072] Moreover, counter 460 generates a second slot pulse SP2 by counting the clock signal CLK a number corresponding to the measurement value N. The rest is as described with reference to FIG.

[0073] 9 is a circuit diagram showing a specific example of the configuration of the second slot pulse generator 450. The memory 452 includes flip-flops FF1 and FF2. The edge detection circuit 456 includes a flip-flop FF3, an inverter INV1, and an AND gate AND1. The edge detection circuit 456 extracts one period of the leading clock signal CLK from the timing reference signal TREF'.

[0074] Example 2 10 is a block diagram of a power supply controller IC 450B according to embodiment 2. This power supply controller IC 400B can be considered as a modified example of the power supply controller IC 400A in FIG.

[0075] The second slot pulse generator 450B detects a time T corresponding to the measurement value N from the generation timing of the second slot pulse SP2 in the previous cycle (the cycle before). CLK The next second slot pulse SP2 is generated at the earlier timing between the first timing after ×N has elapsed and the second timing at which the timing reference signal TREF' is received.

[0076] The second slot pulse generator 450B further comprises an OR gate OR1 and a pulse stretcher 458 in addition to a memory 452, a synchronization circuit 454, an edge detection circuit 456, and a counter 460.

[0077] As in the first embodiment, the counter 460 generates a pulse signal (hereinafter referred to as an internal pulse) SP3 by counting. This internal pulse SP3 has a length of one period of the clock signal CLK. The pulse stretcher 458 expands the pulse width (i.e., high period) of the internal pulse SP3 to generate an internal timing reference signal TREFs. A signal based on the timing reference signal TREF supplied from the master (e.g., the output of the synchronization circuit 454) is referred to as an external timing reference signal TREFm.

[0078] The pulse width of the internal timing reference signal TREFs is determined taking into consideration the jitter of the external timing reference signal TREFm. Specifically, the pulse width is determined so that the output signal (logical sum) of the OR gate OR1 becomes one pulse when the timing of the external timing reference signal TREFm and the internal timing reference signal TREFs fluctuates.

[0079] Furthermore, the positive edge of the external timing reference signal TREFm lags behind the positive edge of the internal pulse SP3 by one clock cycle.

[0080] The OR gate OR1 outputs the logical sum of the external timing reference signal TREFm and the internal timing reference signal TREFs. The edge detection circuit 456 detects the positive edge of the output signal SP4 of the OR gate OR1, and outputs a second slot pulse SP2 that is at a high level for one clock period. The positive edge of the second slot pulse SP2 corresponds to the earlier timing of the positive edge of the internal timing reference signal TREFs or the positive edge of the external timing reference signal TREFm.

[0081] The counter 460 measures the interval of the second slot pulse SP 2 , which is the output of the edge detection circuit 456 , and writes the count value N to the memory 452 .

[0082] The above is the configuration of the power supply controller IC 400B. Next, we will explain its operation.

[0083] Fig. 11 is a waveform diagram explaining the operation of the second slot pulse generator 450B in Fig. 10. Fig. 11 shows the state when a timing reference signal TREF with a constant interval is input. In this state, the intervals of the internal pulse SP3, the external timing reference signal TREFm, and the second slot pulse SP2 all match.

[0084] When the operation of FIG. 11 occurs, the interval between second slot pulses SP2 is determined by a time T based on the measurement N stored in memory 452. CLK ×N is the same.

[0085] Moreover, since the second slot pulse SP2 input to the counter 460 has the same time interval as the external timing reference signal TREFm, it can be said that the counter 460 measures the interval of the external timing reference signal TREFm.

[0086] Fig. 12 is a waveform diagram for explaining another operation of the second slot pulse generator 450B of Fig. 10. Fig. 12 shows a state in which the interval of the external timing reference signal TREFm becomes wider in the (i+1)th cycle. t1 is the timing at which the internal pulse SP3 transitions to a high level in the (i+1)th cycle (hereinafter referred to as the first timing). This first timing t1 is a time T corresponding to the measurement value N from the generation timing t0 of the second slot pulse SP2 in the previous i-th cycle. CLK ×N has elapsed. t2 is the timing when the external timing reference signal TREFm is received (hereinafter, referred to as the second timing).

[0087] Since the first timing t1 is earlier than the second timing t2, the occurrence timing of the next second slot pulse SP2 is determined by the first timing t1. When this operation occurs, the interval between the second slot pulses SP2 is the time T CLK Matches ×N.

[0088] When the operations of FIG. 12 occur, counter 460 is measuring the time interval of the internal pulse SP3 it is generating, not the time interval of the external timing reference signal TREFm.

[0089] Fig. 13 is a waveform diagram for explaining still another operation of the second slot pulse generator 450B of Fig. 10. Fig. 13 shows a state in which the interval of the external timing reference signal TREFm narrows in the (i+1)th cycle.

[0090] Since the second timing t2 is earlier than the first timing t1, the generation timing of the next second slot pulse SP2 is determined by the second timing t2. When this operation occurs, the interval between the second slot pulses SP2 is the time T CLK ×N.

[0091] Next, a specific example of the configuration of second slot pulse generator 450B will be described.

[0092] Fig. 14 is a circuit diagram showing a configuration example of the second slot pulse generator 450B of Fig. 9. In this configuration example, the memory 452 is incorporated into a counter 460. The counter 460 includes a digital counter 461, an inverter 462, a coincidence detection circuit 463, and an AND gate 464.

[0093] The digital counter 461 counts up in response to the clock signal CLK while the input IN is high. When a low is input to the negative logic reset terminal RESETB, the count value is reset. The inverter 462 inverts the second slot pulse SP2 and supplies it to the reset terminal RESETB of the digital counter 461. The count value C1 of the digital counter 461 is incremented for each cycle of the clock signal CLK.

[0094] The coincidence detection circuit 463 compares the count value of the digital counter 461 with the value N stored in the memory 452, and when they coincide, generates a high signal at the node Node12. The signal at the node Node12 is the internal pulse NP3.

[0095] The AND gate 464 generates a logical AND of the second slot pulse SP2 and the negative logic error signal ERRB generated by the error detector 470, and supplies the logical AND to the load terminal (LOAD) of the memory 452. The count value C at the time when the transition of the second slot pulse SP2 (Node 6) occurs is written to the memory 452. The value written to the memory 452 is the measured value N.

[0096] The error detector 470 monitors the state of the output node Node5 of the synchronization circuit 454, and detects the absence of an input of the timing reference signal TREF'. The error detector 470 includes an OR gate 472, an AND gate 474, a flip-flop 476, a counter 478, a coincidence detection circuit 480, and an inverter 482.

[0097] The counter 478 holds the output value OUT when the count enable terminal COUNT_EN is low. The counter 478 increments the output value OUT when the input IN goes low while the count enable terminal COUNT_EN is high. The counter 478 counts the number of times the second slot pulse SP2 has been generated at the first timing t1 as shown in FIG. 12 in a state where the timing reference signal TREF is not received.

[0098] The coincidence detection circuit 480 compares the output value OUT of the counter 478 with a threshold value TH. The threshold value TH may be, for example, 11 in binary (3 in decimal). After the output value OUT of the counter 478 reaches the threshold value TH, the counter 478 maintains that value. When the output value OUT of the counter 478 becomes equal to the threshold value TH, the error signal ERR, which is the output of the coincidence detection circuit 480, goes high. The inverter 482 inverts the error signal ERR to generate a negative logic error signal ERRB.

[0099] The operation of second slot pulse generator 450B in FIG. 14 will be described with reference to FIGS.

[0100] Fig. 15 is a waveform diagram for explaining the operation of the second slot pulse generator 450B in Fig. 14. Fig. 15 shows the operation when the timing reference signal TREF is normally received. Each signal shows the waveform or value of each node in Fig. 14.

[0101] The node Node3 corresponds to the timing reference signal TREF. When the node Node3 transitions to high, the node Node6 transitions to high. When the node Node6 transitions to high, the digital counter 461 is reset and starts counting (counting up).

[0102] The count value C (Node 10) of the digital counter 461 is incremented for each period of the clock signal CLK. The count value C when the node Node 6 next transitions to high is loaded into the memory 452 as the measurement value N. This measurement value N indicates the time interval of the signal of the node Node 6, in other words, the time interval of the timing reference signal TREF (Node 3).

[0103] In each cycle, the coincidence detection circuit 463 compares the past count value N (Node 11) stored in the memory 452 with the current count value C (Node 10).

[0104] (1) When C=N is true before node Node3 transitions to high This state can be considered as a state in which the time interval of the external timing reference signal TREFm has become longer than the time interval of the second slot pulse SP2 currently being generated by the second slot pulse generator 450B.

[0105] At time t1 when C=N is established, the internal pulse SP3 (Node 12) which is the output of the coincidence detection circuit 463 is asserted, and the internal timing reference signal TREFs is asserted. Since the positive edge of this internal timing reference signal TREFs precedes the positive edge of the external timing reference signal TREFm, the second slot pulse SP2 is generated based on the internal timing reference signal TREFs and has a time interval based on the past measurement value N.

[0106] As described above, the positive edge of the external timing reference signal TREFm lags behind the positive edge of the internal pulse SP3 by one clock cycle. As a result, when the operation of Fig. 15 occurs, the measurement value N in the memory 452 becomes a value that is 1 larger than the previous value (increment). If the positive edge of the external timing reference signal TREFm coincides with the positive edge of the internal pulse SP3, the measurement value N will continue to maintain the same value, and if the time interval of the external timing reference signal TREFm widens, a problem occurs in that it will not be able to follow it. On the other hand, the second slot pulse generator 450B can solve this problem by incrementing the measurement value N.

[0107] (2) When the external timing reference signal TREFm occurs before C=N is established. At time t2, the second slot pulse SP2 is asserted in response to the positive edge of the external timing reference signal TREFm. The count value C at this time is then loaded into the memory 452 as the measurement value N.

[0108] Fig. 16 is a waveform diagram for explaining the operation of the second slot pulse generator 450B of Fig. 14. Fig. 16 shows the operation when the timing reference signal TREF is interrupted at time t0.

[0109] When the timing reference signal TREF is interrupted, the node Node5 (TREFm) is fixed to low. Then, as shown in Fig. 15, C = N is established before the node Node3 transitions to high, and an internal timing reference signal TREFs based on the past measurement value N is generated, and the measurement value N is incremented every time the internal timing reference signal TREFs is generated.

[0110] The count value of node Node17 represents the number of times an increment has occurred in the measured value N. When the number of increments reaches a predetermined value (3 in this example) at time t1, node Node18 (error signal ERRB) goes low, and it is determined that an abnormal state has occurred.

[0111] Fig. 17 is a waveform diagram for explaining the operation of the second slot pulse generator 450B of Fig. 14. Fig. 17 shows the operation when the timing reference signal TREF returns. At time t0, the timing reference signal TREF returns. At time t1, the error signal ERRB (Node 18) transitions to high.

[0112] When the error signal ERRB is in a high state and the node Node6 transitions to high, a high signal is generated at the load terminal (Node 19) of the memory 452, the count value C of the digital counter 461 at that time is written into the memory 452 as the measurement value N, and the operation returns to that shown in FIG. 15.

[0113] The above is the operation of second slot pulse generator 450B.

[0114] (Modification) In the embodiment, the period of the timing reference signal TREF is the same as the period of the first slot pulse SP1, but the present disclosure is not limited thereto. For example, the period of the timing reference signal TREF may be an integer multiple (for example, 10 times) of the period of the first slot pulse SP1.

[0115] The embodiments are merely examples, and it will be understood by those skilled in the art that there are various modifications in the combination of each component and each treatment process, and that such modifications are also included within the scope of the present disclosure or the present invention.

[0116] (Additional Note) In one aspect, the technology disclosed in this specification is defined as follows.

[0117] (Item 1) A power supply controller circuit switchable between a master mode and a slave mode, comprising: an oscillator for generating a clock signal; a first slot pulse generator that generates a first slot pulse that is asserted every time the clock signal is counted a predetermined number in the master mode; a timing reference signal generator that generates, in the master mode, a timing reference signal having a period corresponding to a period of the first slot pulse and transmits the timing reference signal to another of the power supply controller circuits operating in the slave mode; a second slot pulse generator that, in the slave mode, receives the timing reference signal from the other power controller circuit operating in the master mode, measures a time interval of the timing reference signal, stores the measured value of the time interval, and generates a second slot pulse having a time interval corresponding to the measured value; a sequencer that controls a plurality of power supply lanes in response to the first slot pulse in the master mode and controls the plurality of power supply lanes in response to the second slot pulse in the slave mode; 1. A power supply controller circuit comprising:

[0118] (Item 2) The second slot pulse generator includes: 2. The power supply controller circuit according to item 1, wherein the next second slot pulse is generated at an earlier timing between a first timing at which a time corresponding to the measurement value has elapsed since the previous generation timing of the second slot pulse, and a second timing at which the timing reference signal is received.

[0119] (Item 3) 3. The power supply controller circuit of claim 2, wherein the second slot pulse generator increments the measurement value when it generates the second slot pulse at the first timing when it does not receive the timing reference signal.

[0120] (Item 4) The second slot pulse generator includes: a counter that counts the number of times the second slot pulse is generated at the first timing when the timing reference signal is not received; an error detector that asserts an error signal when the count value of the counter reaches a predetermined threshold; 4. The power supply controller circuit of item 2 or 3, comprising:

[0121] (Item 5) 5. The power supply controller circuit of claim 4, wherein the second slot pulse generator stops incrementing the measurement value while the error signal is asserted.

[0122] (Item 6) the first slot pulse is asserted for one cycle of the clock signal; 6. The power supply controller circuit of any of items 1 to 5, wherein the timing reference signal is asserted for multiple n cycles of the clock signal, where n is an integer greater than or equal to 2.

[0123] (Item 7) 7. The power supply controller circuit of item 6, wherein 2≦n≦20.

[0124] (Item 8) 7. The power supply controller circuit of any of items 1 to 6, further comprising a synchronization circuit that utilizes the clock signal to retime the timing reference signal.

[0125] (Item 9) A first power supply controller circuit operating as a master mode according to any one of items 1 to 8; A second power controller circuit according to any one of items 1 to 8, operating in a slave mode; An electronic device comprising: [Explanation of symbols]

[0126] 100 Power System 200 1st power supply controller IC 210 Oscillator 220 1st slot pulse generator 230 1st sequencer 240 Timing Reference Signal Generator 300 Secondary Power Supply Controller IC 330 Second sequencer 350 Second Slot Pulse Generator 400 Power Supply Controller IC 410 Oscillator 420 1st slot pulse generator 422 Multiplexer 430 Sequencer 440 Timing Reference Signal Generator 450 Second Slot Pulse Generator 452 Memory 454 Synchronous Circuit 456 Edge detection circuit 458 Pulse Stretcher 460 Counter 461 Digital Counter 463 Coincidence Detection Circuit

Claims

1. A power supply controller circuit switchable between a master mode and a slave mode, comprising: an oscillator for generating a clock signal; a first slot pulse generator that generates a first slot pulse that is asserted every time the clock signal is counted a predetermined number in the master mode; a timing reference signal generator that generates, in the master mode, a timing reference signal having a period corresponding to a period of the first slot pulse and transmits the timing reference signal to another of the power supply controller circuits operating in the slave mode; a second slot pulse generator that, in the slave mode, receives the timing reference signal from the other power controller circuit operating in the master mode, measures a time interval of the timing reference signal, stores the measured value of the time interval, and generates a second slot pulse having a time interval corresponding to the measured value; a sequencer that controls a plurality of power supply lanes in response to the first slot pulse in the master mode and controls the plurality of power supply lanes in response to the second slot pulse in the slave mode; 1. A power supply controller circuit comprising:

2. The second slot pulse generator includes:

2. The power supply controller circuit of claim 1, wherein the next second slot pulse is generated at an earlier timing of either a first timing at which a time corresponding to the measurement value has elapsed since the previous generation timing of the second slot pulse, or a second timing at which the timing reference signal is received.

3. 3. The power supply controller circuit of claim 2, wherein said second slot pulse generator increments said measurement value when it generates said second slot pulse at said first timing when said timing reference signal is not received.

4. The second slot pulse generator includes: a counter that counts the number of times the second slot pulse is generated at the first timing when the timing reference signal is not received; an error detector that asserts an error signal when the count value of the counter reaches a predetermined threshold; 4. A power supply controller circuit as claimed in claim 2 or 3, comprising:

5. 5. The power supply controller circuit of claim 4, wherein said second slot pulse generator stops incrementing said measurement value while said error signal is asserted.

6. the first slot pulse is asserted for one cycle of the clock signal; 4. The power supply controller circuit of claim 1, wherein the timing reference signal is asserted for a number n of cycles of the clock signal, where n is an integer equal to or greater than two.

7. 7. The power supply controller circuit of claim 6, wherein 2≦n≦20.

8. 4. The power supply controller circuit of claim 1, further comprising a synchronization circuit for retiming said timing reference signal utilizing said clock signal.

9. A first power supply controller circuit operating in a master mode according to any one of claims 1 to 3; A second power controller circuit according to any one of claims 1 to 8, operating in a slave mode; An electronic device comprising:

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