Nitride semiconductor device

Abstract

To suppress an increase in gate current when a high gate voltage is applied.SOLUTION: A nitride semiconductor device 10 includes: a substrate 12; a nitride semiconductor layer 40 formed on the substrate 12; a gate electrode 24 formed on and in contact with the nitride semiconductor layer 40; and a source electrode 28 and a drain electrode 30 formed on the nitride semiconductor layer 40 and sandwiching the gate electrode 24. At least a part of the gate electrode 24, including a lower surface 24B in contact with the nitride semiconductor layer 40, is composed of a specific metal oxide. The specific metal oxide includes at least one first metal selected from Pd and Pt, at least one second metal selected from Co, Rh, and Cr, and oxygen atoms.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a nitride semiconductor device. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use a two-dimensional electron gas (2DEG) formed near the interface of a semiconductor heterojunction as a conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher speed / frequency operation compared to typical silicon (Si) power devices.

[0003] For example, a nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transit layer formed of a gallium nitride (GaN) layer, and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0005] [overview] In order to increase the power density of nitride semiconductor devices, it is desirable to increase the drain current. One possible method for increasing the drain current is to increase the gate voltage applied to the gate electrode. However, when a high gate voltage is applied, the drain current decreases due to the increased gate current. Therefore, in order to increase the drain current by increasing the gate voltage, it is necessary to suppress the increase in gate current when a high gate voltage is applied.

[0006] A nitride semiconductor device according to one embodiment of the present disclosure includes a substrate, a nitride semiconductor layer formed on the substrate, a gate electrode formed on and in contact with the nitride semiconductor layer, and a source electrode and a drain electrode formed on and between the gate electrode and the nitride semiconductor layer, wherein at least a portion of the gate electrode including a lower surface in contact with the nitride semiconductor layer is composed of a specific metal oxide, and the specific metal oxide includes at least one first metal selected from Pd and Pt, at least one second metal selected from Co, Rh, and Cr, and oxygen atoms. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line 2-2 of FIG. [Figure 3] FIG. 3 is an enlarged cross-sectional view of an example gate electrode. [Figure 4] FIG. 4 is a schematic diagram showing the crystal structure of a specific metal oxide. [Figure 5] FIG. 5 is a graph showing an example relationship between gate voltage and drain current, and an example relationship between gate voltage and gate current. [Figure 6] FIG. 6 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a modified example. [Figure 7] FIG. 7 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a modified example.

[0008] [Detailed explanation] Hereinafter, embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings.

[0009] For simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0011] [Schematic structure of nitride semiconductor device] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device 10 according to an embodiment. FIG. 2 is a schematic cross-sectional view of the nitride semiconductor device 10, taken along line 2-2 in FIG. 1. For convenience, in the nitride semiconductor device 10 shown in FIG. 1, the +Z direction is defined as up, the −Z direction as down, the +X direction as right, and the −X direction as left. Unless otherwise expressly specified, a “plan view” refers to a view of the nitride semiconductor device 10 from above along the Z axis. Furthermore, unless otherwise expressly specified, a thickness refers to the dimension along the Z direction.

[0012] As an example, the nitride semiconductor device 10 may be a HEMT using GaN. Below, a cross-sectional structure of the nitride semiconductor device 10 will be described with reference to Fig. 2, and then a planar structure of the nitride semiconductor device 10 will be described with reference to Fig. 1.

[0013] 2, the nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, and a nitride semiconductor layer 40 formed on the buffer layer 14. The nitride semiconductor layer 40 includes an electron transit layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transit layer 16. The buffer layer 14 and the nitride semiconductor layer 40 are epitaxially grown on the substrate 12.

[0014] The substrate 12 may be formed of silicon (Si), silicon carbide (SiC), GaN, sapphire, or other substrate materials. In one example, the substrate 12 may be a Si substrate. The thickness of the substrate 12 is, for example, 200 μm or more and 1500 μm or less. The Z direction of the mutually orthogonal X, Y, and Z axes shown in FIGS. 1 and 2 is the thickness direction of the substrate 12.

[0015] The buffer layer 14 is formed on the substrate upper surface 12A of the substrate 12. The buffer layer 14 may be located between the substrate 12 and the electron transit layer 16. In one example, the buffer layer 14 may be made of any material that can facilitate epitaxial growth of the electron transit layer 16. The buffer layer 14 may include one or more nitride semiconductor layers.

[0016] In one example, the buffer layer 14 may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure. To suppress leakage current in the buffer layer 14, impurities may be introduced into a portion of the buffer layer 14 to make the buffer layer 14 semi-insulating. In this case, the impurity may be, for example, carbon (C) or iron (Fe), and the impurity concentration may be, for example, 4×10 16 cm -3 That's all.

[0017] The electron transit layer 16 is made of a nitride semiconductor. The electron transit layer 16 is, for example, a GaN layer. The thickness of the electron transit layer 16 is, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 16, impurities may be introduced into a part of the electron transit layer 16 to make the electron transit layer 16 semi-insulating except for the surface region. In this case, the impurity may be, for example, C, and the peak concentration of the impurity in the electron transit layer 16 may be, for example, 1×10 19 cm-3 The above is the case.

[0018] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16. The electron supply layer 18 is, for example, an AlGaN layer. In this case, since the bandgap increases as the Al composition increases, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al x Ga 1-x N, where x satisfies 0.1 < x < 0.4, and more preferably, 0.2 < x < 0.3. The thickness of the electron supply layer 18 is, for example, 5 nm or more and 20 nm or less.

[0019] The electron transport layer 16 and the electron supply layer 18 are composed of nitride semiconductors having different lattice constants. Therefore, the nitride semiconductor (for example, GaN) constituting the electron transport layer 16 and the nitride semiconductor (for example, AlGaN) constituting the electron supply layer 18 form a hetero-junction of a lattice mismatch system. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18 and the piezo-polarization caused by the stress received by the electron supply layer 18 near the hetero-junction interface, the energy level of the conduction band of the electron transport layer 16 near the hetero-junction interface becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads in the electron transport layer 16 at a position close to the hetero-junction interface between the electron transport layer 16 and the electron supply layer 18 (for example, within a range of about several nm from the interface).

[0020] The nitride semiconductor device 10 further includes a gate electrode 24 formed on the electron supply layer 18 and a passivation layer 26. The passivation layer 26 is formed on the electron supply layer 18 and the gate electrode 24 and includes a first opening 26A and a second opening 26B. Further, the nitride semiconductor device 10 further includes a source electrode 28 contacting the electron supply layer 18 through the first opening 26A and a drain electrode 30 contacting the electron supply layer 18 through the second opening 26B.

[0021] The gate electrode 24 will be described in detail later. The passivation layer 26 is formed on the electron supply layer 18. It can also be said that the passivation layer 26 covers the upper surface 18A of the electron supply layer 18. The passivation layer 26 may be made of a material containing one of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON). In one example, the passivation layer 26 is made of a material containing SiN. The portion of the passivation layer 26 covering the gate electrode 24 is formed along the surfaces of the gate layer 22 and the gate electrode 24, and therefore has an uneven surface. The passivation layer 26 has a thickness of, for example, 200 nm or less. Here, the thickness of the passivation layer 26 may be, for example, the thickness of the portion in contact with the electron supply layer 18 or the thickness of the portion in contact with the upper surface 24A of the gate electrode 24.

[0022] The source electrode 28 and the drain electrode 30 are disposed on the upper surface 18A of the electron supply layer 18 in the X direction, sandwiching the gate electrode 24. The source electrode 28 and the drain electrode 30 may be formed of one or more metal layers. For example, the source electrode 28 and the drain electrode 30 may be formed of a combination of two or more metal layers selected from a group including a Ti layer, a TiN layer, an Al layer, an AlSiCu layer, and an AlCu layer. At least a portion of the source electrode 28 is filled in the first opening 26A and makes ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the first opening 26A. Similarly, at least a portion of the drain electrode 30 is filled in the second opening 26B and makes ohmic contact with the 2DEG 20 directly below the electron supply layer 18 through the second opening 26B.

[0023] [Planar structure of nitride semiconductor devices] Next, the planar structure of the nitride semiconductor device 10 will be described with reference to Fig. 1. In Fig. 1, the passivation layer 26 and the source electrode 28 are not shown, and a first opening 26A and a second opening 26B of the passivation layer 26 are depicted by dashed lines.

[0024] The nitride semiconductor device 10 has, for example, active regions that contribute to transistor operation and inactive regions (not shown) that do not contribute to transistor operation. In one example, the active regions and inactive regions are arranged alternately in the Y direction.

[0025] In the active region of the nitride semiconductor device 10, the source electrode 28 (see FIG. 2), the gate electrode 24, and the drain electrode 30 are arranged adjacent to each other in the X direction on the electron supply layer 18 (see FIG. 2). A combination of the source electrode 28, the gate electrode 24, and the drain electrode 30 adjacent to each other in the X direction constitutes one HEMT cell HC. In the example of FIG. 1, two HEMT cells HC are arranged in the X direction in the active region. In practice, more HEMT cells HC may be arranged in each active region.

[0026] [Gate electrode details] Next, the gate electrode 24 will be described in detail with reference to FIGS. 2, the gate electrode 24 is located between the first opening 26A and the second opening 26B of the passivation layer 26 and is spaced apart from each of the first opening 26A and the second opening 26B. The gate electrode 24 is located closer to the first opening 26A than to the second opening 26B.

[0027] The gate electrode 24 has an upper surface 24A and a lower surface 24B. The lower surface 24B is the surface of the gate electrode 24 that contacts the nitride semiconductor layer 40. The lower surface 24B can also be said to be the surface that forms an interface with the nitride semiconductor layer 40. In this embodiment, the lower surface 24B of the gate electrode 24 contacts the upper surface 18A of the electron supply layer 18 and forms an interface with the electron supply layer 18. The upper surface 24A is the surface of the gate electrode 24 that faces the opposite side to the lower surface 24B. The thickness of the gate electrode 24 is, for example, not less than 50 nm and not more than 200 nm.

[0028] At least a portion of the gate electrode 24, including the lower surface 24B, is made of a specific metal oxide, which will be described later. In the example shown in FIG. 2, the entire gate electrode 24, including the lower surface 24B, is made of the specific metal oxide. In this case, the gate electrode 24 may contain other materials in addition to the specific metal oxide. Examples of other materials include inevitable impurities. The inevitable impurities are those present in raw materials or impurities that are inevitably mixed in during the manufacturing process.

[0029] The gate electrode 24 may also be composed of a combination of two or more layers. For example, the example gate electrode 24 shown in FIG. 3 includes a first electrode layer 241 including a lower surface 24B and a second electrode layer 242 formed on the first electrode layer 241. The first electrode layer 241 is composed of a specific metal oxide. The second electrode layer 242 is composed of a conductive material different from that of the first electrode layer 241. An example of the conductive material is at least one selected from gold (Au), platinum (Pt), aluminum (Al), and copper (Cu), with gold (Au) being preferred. In this case, it is possible to suppress the degeneration of the second electrode layer 242 due to a reaction between the specific metal oxide constituting the first electrode layer 241 and the conductive material, for example, oxidation of the conductive material. The conductive material may also be a known material used in gate electrodes, such as a metal material such as titanium (Ti) or titanium nitride (TiN). The first electrode layer 241 may also contain other materials in addition to the specific metal oxide. The other materials include, for example, inevitable impurities.

[0030] The thickness of the first electrode layer 241 is, for example, 1 nm or more and 100 nm or less. The thickness of the second electrode layer 242 is, for example, 100 nm or more and 1000 nm or less. In one example, the thickness of the first electrode layer 241 is thinner than the thickness of the second electrode layer 242. Compared with the second electrode layer 242 made of a metal material or the like, the first electrode layer 241 made of a specific metal oxide requires greater cost and time to form. Therefore, by making the first electrode layer 241 relatively thin, the cost and time required to form the entire gate electrode 24 can be reduced. The thickness of the first electrode layer 241 may be the same as or thicker than the thickness of the second electrode layer 242.

[0031] [Details of specific metal oxides] Next, the specific metal oxide will be described in detail with reference to FIG. The specific metal oxide is a metal oxide containing at least one first metal selected from Pd and Pt, at least one second metal selected from Co, Rh, and Cr, and oxygen atoms. The fact that the lower surface 24B of the gate electrode 24 is made of the specific metal oxide can be confirmed, for example, by detecting the first metal, the second metal, and oxygen atoms when elemental analysis is performed on the portion forming the lower surface 24B of the gate electrode 24.

[0032] As shown in FIG. 4, the specific metal oxide has a metal layer (A + ) and a metal oxide layer consisting of metal oxide ions of the second metal ([BO2] 3- ) and a layered oxide (ABO2) having a crystal structure containing the metal layers and metal oxide layers. In the crystal structure, the metal layers and metal oxide layers extend in the ab-plane direction and are alternately stacked in the c-axis direction. The structure in which the metal layers and metal oxide layers are alternately stacked forms an electric dipole. The crystal structure is a hexagonal system, the same as the nitride semiconductor (e.g., GaN) that constitutes the electron transit layer 16 and the nitride semiconductor (e.g., AlGaN) that constitutes the electron supply layer 18. The crystal structure is sometimes referred to as a delafossite-type crystal structure.

[0033] The metal layer is, for example, Pd + layer, Pt + At least one metal layer is selected from the group consisting of Pd + The layer may contain other components besides Pd. For example, Pd + The layer is Pd + The layer may be a layer in which a part of the Pd constituting the layer is replaced with Pt. + The layer may contain other components besides Pt. For example, Pt + The layer is Pt + The layer may be a layer in which a part of the Pt constituting the layer is substituted with Pd.

[0034] The metal oxide layer may be, for example, CoO2 - layer, RhO2 - layer, CrO2 - At least one metal oxide layer selected from the group consisting of CoO2 - The layer is CoO2 - It may contain other components other than CoO2. - The layer is CoO2 - The layer may be a layer in which a part of the Co constituting the layer is replaced with Rh or Cr, which is a second metal other than Co. Similarly, RhO2 - The layer is RhO2 - It may contain other components other than RhO2. - The layer is RhO2 - The layer may be a layer in which a part of the Rh constituting the layer is replaced with Co or Cr, which is a second metal other than Rh. - The layer is CrO2 - It may contain other components other than CrO2. - The layer is CrO2 - The layer may be a layer in which a portion of the Cr constituting the layer is substituted with Co or Rh, which is a second metal other than Cr.

[0035] The specific metal oxide is, for example, at least one selected from PdCoO2, PtCoO2, PdCrO2, and PdRhO2. These specific metal oxides exhibit electrical conductivity equivalent to that of metals. In particular, PdCoO2 and PtCoO2 exhibit electrical conductivity equivalent to that of Au, a metal with high electrical conductivity.

[0036] In the gate electrode 24, the c-axis direction of the crystal structure of the specific metal oxide (the direction in which the metal layer and the metal oxide layer are stacked) is the thickness direction (z direction) of the gate electrode 24. In the crystal structure of the specific metal oxide, the termination surface forming the lower surface 24B of the gate electrode 24 is a metal oxide layer. The fact that the lower surface 24B of the gate electrode 24 is formed of a metal oxide layer can be confirmed, for example, by analysis using a scanning transmission electron microscope (STEM). For example, a STEM image of a cross section including the interface between the gate electrode 24 and the nitride semiconductor layer 40 (electron supply layer 18) is obtained. Then, from the STEM image, it is confirmed which layer of the alternately stacked metal layers and metal oxide layers is located on the lower surface 24B of the gate electrode 24. It can also be said that the lower surface 24B of the gate electrode 24 contains the second metal and oxygen atoms, but does not contain the first metal.

[0037] In addition, in the gate electrode 24 entirely made of a specific metal oxide (see FIG. 3), the terminal surface forming the upper surface 24A of the gate electrode 24 may be a metal layer or a metal oxide layer. Similarly, in the gate electrode 24 made of a combination of two or more layers (see FIG. 4), the terminal surface forming the upper surface of the first electrode layer 241 may be a metal layer or a metal oxide layer.

[0038] The gate electrode 24 made of the specific metal oxide can be formed by a known method such as sputtering or pulsed laser deposition. For example, a layer of the specific metal oxide is formed by epitaxial growth on the upper surface 18A of the electron supply layer 18 using the sputtering method. Then, part of the layer is selectively removed by lithography and etching to form the gate electrode 24. The first electrode layer 241 can be formed in the same manner.

[0039] Specific metal oxides are substances with a higher work function than metals. The metal with the highest work function is Pt, which has a value of 5.3 eV. Therefore, the work function of specific metal oxides is, for example, greater than 5.3 eV. The work function of specific metal oxides is preferably 5.4 eV or greater. Furthermore, the work function of specific metal oxides is, for example, 10 eV or less. As an example, the work function of PdCoO2, one specific metal oxide, is 7.8 eV. Note that the work function of specific metal oxides is the value when the termination surface is a metal oxide layer. Other specific metal oxides such as PtCoO2, PdCrO2, and PdRhO2 are also layered oxides with a similar crystal structure to PdCoO2, so it can be assumed that they have work functions similar to that of PdCoO2.

[0040] [Effect] Next, the operation of the nitride semiconductor device 10 will be described. First, the relationship between the gate voltage and the drain current in a transistor will be described with reference to the graph in Figure 5. Figure 5 also shows an exemplary relationship between the gate voltage and the drain current, as well as an exemplary relationship between the gate voltage and the gate current. In Figure 5, the solid black plots represent the drain current, and the open white plots represent the gate current. The values ​​of the gate voltage, drain current, and gate current shown on each axis in Figure 5 are merely examples.

[0041] 5, the drain current increases as the gate voltage increases when the gate voltage is below a specific value, and decreases when the gate voltage exceeds the specific value. On the other hand, the gate current remains almost constant when the gate voltage is below the specific value, and increases sharply when the gate voltage exceeds the specific value.

[0042] The gate voltage at which the drain current changes from an increasing trend to a decreasing trend is almost the same as the gate voltage at which the gate current suddenly increases. This indicates that while the drain current can be increased by increasing the gate voltage, if the gate voltage is increased beyond a certain value, the increase in the drain current is suppressed and the drain current decreases due to the increase in the gate current. Therefore, in order to further increase the drain current by increasing the gate voltage, it is important to suppress the increase in the gate current when a high gate voltage is applied.

[0043] Application of a positive voltage to the gate electrode is equivalent to application of a forward bias to the Schottky contact formed at the interface between the metal layer (gate electrode) and the semiconductor layer. Therefore, when a positive voltage is applied to the gate electrode, electrons move from the semiconductor layer to the gate electrode at the interface, causing a forward current to flow. Therefore, by increasing the Schottky barrier at the interface, it is possible to suppress an increase in gate current when a high gate voltage is applied.

[0044] Here, in the nitride semiconductor device 10, the lower surface 24B of the gate electrode 24 is made of the specific metal oxide. In other words, in the gate electrode 24, the interface that forms Schottky contact with the nitride semiconductor layer 40 (electron supply layer 18) is made of the specific metal oxide. As described above, the specific metal oxide is a substance with a work function higher than that of a metal. Therefore, in the nitride semiconductor device 10, the Schottky barrier can be made larger than when a gate electrode made of a metal is used. In other words, the Schottky barrier (φ bn) is the work function (φ m ) and the electron affinity (χ s ) and the difference (φ bn =φ m -χ s Therefore, the Schottky barrier can be increased by using a material with a high work function as the material for the surface of the metal layer that forms the interface.

[0045] Therefore, in the nitride semiconductor device 10, the lower surface 24B of the gate electrode 24 is made of a specific metal oxide, which increases the Schottky barrier at the interface between the gate electrode 24 and the nitride semiconductor layer 40 (electron supply layer 18). This makes it difficult for electrons to move at the interface, thereby suppressing an increase in gate current when a high gate voltage is applied. Furthermore, suppressing an increase in gate current when a high gate voltage is applied makes it possible to further increase the drain current by increasing the gate voltage.

[0046] [effect] The nitride semiconductor device 10 provides the following effects. (1) The nitride semiconductor device 10 includes a substrate 12, a nitride semiconductor layer 40 formed on the substrate 12, a gate electrode 24 formed on and in contact with the nitride semiconductor layer 40, and a source electrode 28 and a drain electrode 30 formed on the nitride semiconductor layer 40 and sandwiching the gate electrode 24. At least a portion of the gate electrode 24, including a lower surface 24B in contact with the nitride semiconductor layer 40, is composed of a specific metal oxide. The specific metal oxide includes at least one first metal selected from Pd and Pt, at least one second metal selected from Co, Rh, and Cr, and oxygen atoms.

[0047] According to the above configuration, an increase in gate current when a high gate voltage is applied is suppressed, thereby enabling a further increase in drain current by increasing the gate voltage. As a result, a nitride semiconductor device 10 with high power density can be realized. Note that an example of a nitride semiconductor device 10 in which the increase in gate current is suppressed is a device having a gate threshold voltage of 4.0 V or higher, defined at a gate current of 1 mA.

[0048] Another method for increasing the Schottky barrier at the interface between the lower surface 24B of the gate electrode 24 and the nitride semiconductor layer 40 is to change the semiconductor material constituting the nitride semiconductor layer 40. In other words, by using a semiconductor material with a small electron affinity, the Schottky barrier (φ bn =φ m -χ s However, the materials constituting the nitride semiconductor layer 40, particularly the materials constituting the electron supply layer 18, are carefully adjusted so that the carrier density (the amount of 2DEG 20 formed in the electron transit layer 16) falls within an appropriate range. Therefore, when changing the semiconductor material constituting the nitride semiconductor layer 40, it is necessary to redesign the materials so that the carrier density falls within an appropriate range.

[0049] In this regard, in the case of the above-described configuration using the gate electrode 24 made of a specific metal oxide, the Schottky barrier can be increased without changing the semiconductor material that constitutes the nitride semiconductor layer 40. Therefore, the above-described configuration also has the effect of allowing the use of a nitride semiconductor layer 40 with an existing material design.

[0050] (2) The specific metal oxide is, for example, at least one selected from PdCoO2, PtCoO2, PdCrO2, and PdRhO2, in which case the effect of (1) above is more pronounced.

[0051] (3) The specific metal oxide is at least one selected from PdCoO2 and PtCoO2. PdCoO2 and PtCoO2 have high electrical conductivity among the specific metal oxides. Therefore, in this case, a low-resistance gate electrode 24 can be obtained.

[0052] (4) The specific metal oxide is a hexagonal metal oxide, which can be easily epitaxially grown on the nitride semiconductor layer 40, which also has a hexagonal crystal system.

[0053] (5) The gate electrode 24 includes a first electrode layer 241 including the lower surface 24B, and a second electrode layer 242 formed on the first electrode layer 241. The first electrode layer 241 is made of a specific metal oxide. The second electrode layer 242 is made of a conductive material different from that of the first electrode layer 241. In this case, the proportion of the portion of the gate electrode 24 made of the specific metal oxide can be reduced. This allows the cost and time required to form the entire gate electrode 24 to be reduced.

[0054] <Example of change> The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0055] The nitride semiconductor layer 40 may include an intermediate layer interposed between the electron supply layer 18 and the gate electrode 24. That is, the nitride semiconductor layer 40 may include an intermediate layer formed on the electron supply layer 18, and the gate electrode 24 may be formed on and in contact with the intermediate layer. An example of this is shown in FIG. 6.

[0056] The nitride semiconductor device 10 shown in FIG. 6 includes an intermediate layer 19 formed on the electron supply layer 18. The intermediate layer 19 is a layer included in the nitride semiconductor layer 40. The intermediate layer 19 is formed in contact with an upper surface 18A of the electron supply layer 18. A lower surface 24B of the gate electrode 24 is in contact with an upper surface 19A of the intermediate layer 19. The source electrode 28 and the drain electrode 30 are formed in contact with the upper surface 19A of the intermediate layer 19, and a passivation layer 26 is formed on the gate electrode 24 and the intermediate layer 19. The intermediate layer 19 is a layer made of a nitride semiconductor, such as a GaN layer.

[0057] The thickness of the intermediate layer 19 is, for example, 3 nm or more and 200 nm or less. In one example, the thickness of the intermediate layer 19 is thinner than the thickness of the electron supply layer 18. The thickness of the intermediate layer 19 may be the same as or thicker than the thickness of the electron supply layer 18. The intermediate layer 19 formed between the source electrode 28 and the electron supply layer 18 and between the drain electrode 30 and the electron supply layer 18 may be omitted. The intermediate layer 19 formed between the passivation layer 26 and the electron supply layer 18 may be omitted.

[0058] The nitride semiconductor device 10 may be a normally-off transistor. An example of a normally-off nitride semiconductor device 10 is shown in FIG. The nitride semiconductor device 10 shown in FIG. 7 includes a gate layer 22 formed on the electron supply layer 18. The gate layer 22 is a layer included in the nitride semiconductor layer 40. The gate layer 22 is located between the first opening 26A and the second opening 26B of the passivation layer 26 and is spaced apart from the first opening 26A and the second opening 26B. The gate layer 22 is located closer to the first opening 26A than to the second opening 26B. The thickness of the gate layer 22 is, for example, not less than 50 nm and not more than 200 nm. The gate electrode 24 is formed on the gate layer 22. A lower surface 24B of the gate electrode 24 is in contact with an upper surface 22A of the gate layer 22.

[0059] The gate layer 22 has a bandgap smaller than that of the electron supply layer 18 and is made of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can be made of any material having a bandgap smaller than that of the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 22 is a GaN layer doped with acceptor-type impurities (a p-type GaN layer).

[0060] The acceptor-type impurities may include at least one of magnesium (Mg), zinc (Zn), and C. An example of the acceptor-type impurity is Mg. The maximum concentration of the acceptor-type impurity in the gate layer 22 is, for example, 1×10 18 cm -3 or more, or 1×10 19 cm -3 The maximum concentration of the acceptor-type impurity in the gate layer 22 is, for example, 1×10 20 cm -3 The following is the result.

[0061] The inclusion of acceptor-type impurities in the gate layer 22 raises the energy levels of the electron transit layer 16 and the electron supply layer 18. As a result, in the region immediately below the gate layer 22, the energy level of the conduction band of the electron transit layer 16 near the heterojunction interface between the electron transit layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Therefore, at zero bias when no voltage is applied to the gate electrode 24, a 2DEG 20 is not formed in the region of the electron transit layer 16 immediately below the gate layer 22. On the other hand, a 2DEG 20 is formed in the region of the electron transit layer 16 other than the region immediately below the gate layer 22.

[0062] In this way, the presence of the gate layer 22 doped with acceptor-type impurities eliminates the 2DEG 20 in the region directly below the gate layer 22. As a result, normally-off operation of the transistor is achieved. When an appropriate on-voltage is applied to the gate electrode 24, a channel is formed by the 2DEG 20 in the electron transit layer 16 in the region directly below the gate electrode 24, thereby establishing conduction between the source and the drain. In the case of a nitride semiconductor device 10 having the gate layer 22, the Schottky barrier at the interface between the lower surface 24B of the gate electrode 24 and the upper surface 22A of the gate layer 22 becomes large. This provides the effect of suppressing an increase in gate current, similar to the above embodiment.

[0063] In the above embodiment, the nitride semiconductor device 10 is configured as a nitride semiconductor HEMT, but is not limited to a nitride semiconductor HEMT and may be configured as a nitride semiconductor diode.

[0064] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0065] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" of the Z direction described herein being "up" and "down" of the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0066] Terms such as "first," "second," and "third" in this disclosure are used merely to distinguish between objects and do not rank the objects. <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0067] [Appendix 1] A substrate (12); a nitride semiconductor layer (40) formed on the substrate (12); a gate electrode (24) formed on and in contact with the nitride semiconductor layer (40); a source electrode (28) and a drain electrode (30) formed on the nitride semiconductor layer (40) and sandwiching the gate electrode (24); At least a portion of the gate electrode (24) including a lower surface (24B) in contact with the nitride semiconductor layer (40) is made of a specific metal oxide; The specific metal oxide is At least one first metal selected from Pd and Pt; at least one second metal selected from Co, Rh, and Cr; and an oxygen atom.

[0068] [Appendix 2] The nitride semiconductor device (10) according to appendix 1, wherein the specific metal oxide is a hexagonal metal oxide.

[0069] [Appendix 3] The nitride semiconductor device (10) according to appendix 1 or 2, wherein the specific metal oxide is a metal oxide having a work function exceeding 5.3 eV.

[0070] [Appendix 4] The nitride semiconductor device (10) according to any one of appendixes 1 to 3, wherein the specific metal oxide is at least one selected from PdCoO2, PtCoO2, PdCrO2, and PdRhO2.

[0071] [Appendix 5] The specific metal oxide is a metal layer containing the first metal; 5. The nitride semiconductor device (10) according to any one of appendices 1 to 4, wherein the nitride semiconductor device is a layered oxide in which the second metal and a metal oxide layer containing oxygen atoms are stacked.

[0072] [Appendix 6] 6. The nitride semiconductor device (10) according to claim 5, wherein the lower surface (24B) of the gate electrode (24) is formed of the metal oxide layer.

[0073] [Appendix 7] 7. The nitride semiconductor device (10) according to claim 6, wherein the lower surface (24B) of the gate electrode (24) contains the second metal and oxygen atoms.

[0074] [Appendix 8] 7. The nitride semiconductor device (10) according to claim 6, wherein the lower surface (24B) of the gate electrode (24) contains the second metal and oxygen atoms, but does not contain the first metal.

[0075] [Appendix 9] the gate electrode (24) includes a first electrode layer (241) including the lower surface (24B) and a second electrode layer (242) formed on the first electrode layer (241); the first electrode layer (241) is made of the specific metal oxide, The nitride semiconductor device (10) according to any one of appendices 1 to 8, wherein the second electrode layer (242) is made of a conductive material different from that of the first electrode layer (241).

[0076] [Appendix 10] The nitride semiconductor layer (40) is an electron transit layer (16) formed on the substrate (12) and made of a nitride semiconductor; an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (16); 10. The nitride semiconductor device (10) according to any one of appendices 1 to 9, wherein the gate electrode (24) is formed on and in contact with the electron supply layer (18).

[0077] [Appendix 11] the electron transit layer (16) is a GaN layer, The nitride semiconductor device (10) according to claim 10, wherein the electron supply layer (18) is an AlGaN layer.

[0078] [Appendix 12] The nitride semiconductor layer (40) is an electron transit layer (16) formed on the substrate (12) and made of a nitride semiconductor; an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (16); an intermediate layer (19) formed on the electron supply layer (18) and made of a nitride semiconductor; 10. The nitride semiconductor device (10) according to any one of appendices 1 to 9, wherein the gate electrode (24) is formed on and in contact with the intermediate layer (19).

[0079] [Appendix 13] the electron transit layer (16) is a GaN layer, the electron supply layer (18) is an AlGaN layer, 13. The nitride semiconductor device (10) according to claim 12, wherein the intermediate layer (19) is a GaN layer.

[0080] [Appendix 14] A nitride semiconductor device (10) according to any one of appendices 10 to 13, wherein a gate threshold voltage defined at a gate current of 1 mA is 4.0 V or more.

[0081] [Appendix 15] The nitride semiconductor layer (40) is an electron transit layer (16) formed on the substrate (12) and made of a nitride semiconductor; an electron supply layer (18) formed on the electron transit layer (16) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer (16); a gate layer (22) formed on the electron supply layer (16) and made of a nitride semiconductor containing acceptor-type impurities; The nitride semiconductor device (10) according to any one of appendices 1 to 9, wherein the gate electrode (24) is formed on and in contact with the gate layer (22).

[0082] [Appendix 16] the electron transit layer (16) is a GaN layer, the electron supply layer (18) is an AlGaN layer, 16. The nitride semiconductor device (10) according to claim 15, wherein the gate layer (22) is a GaN layer containing the acceptor-type impurities. [Explanation of symbols]

[0083] HC…HEMT cell 10...Nitride semiconductor device 12... Circuit board 12A...Top surface of board 14...Buffer layer 16...Electron transit layer 18...electron supply layer 18A…Top surface 19...Middle class 19A…Top surface 20...Two-dimensional electron gas (2DEG) 22...Gate layer 22A…Top surface 24...Gate electrode 24A…Top surface 24B…Bottom surface 241...first electrode layer 242…Second electrode layer 26...passivation layer 26A…1st opening 26B…Second opening 28...Source electrode 30...Drain electrode 40...Nitride semiconductor layer

Claims

1. A substrate; a nitride semiconductor layer formed on the substrate; a gate electrode formed on and in contact with the nitride semiconductor layer; a source electrode and a drain electrode formed on the nitride semiconductor layer and sandwiching the gate electrode; at least a portion of the gate electrode including a lower surface in contact with the nitride semiconductor layer is made of a specific metal oxide; The specific metal oxide is At least one first metal selected from Pd and Pt; At least one second metal selected from Co, Rh, and Cr; and an oxygen atom.

2. The nitride semiconductor device according to claim 1 , wherein the specific metal oxide is a hexagonal metal oxide.

3. The nitride semiconductor device according to claim 1 , wherein the specific metal oxide is a metal oxide having a work function exceeding 5.3 eV.

4. The specific metal oxide is PdCoO ２ , PtCoO ２ , PdCrO ２ , PdRhO ２ 2. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is at least one selected from the following:

5. The specific metal oxide is a metal layer including the first metal; The nitride semiconductor device according to claim 1 , wherein the second metal and a metal oxide layer containing oxygen atoms are laminated to form a layered oxide.

6. The nitride semiconductor device according to claim 5 , wherein said lower surface of said gate electrode is formed by said metal oxide layer.

7. the gate electrode includes a first electrode layer including the lower surface and a second electrode layer formed on the first electrode layer; the first electrode layer is made of the specific metal oxide, The nitride semiconductor device according to claim 1 , wherein said second electrode layer is made of a conductive material different from that of said first electrode layer.

8. The nitride semiconductor layer is an electron transit layer formed on the substrate and made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; The nitride semiconductor device according to claim 1 , wherein said gate electrode is formed on and in contact with said electron supply layer.

9. the electron transport layer is a GaN layer, The nitride semiconductor device according to claim 8 , wherein said electron supply layer is an AlGaN layer.

10. The nitride semiconductor layer is an electron transit layer formed on the substrate and made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; an intermediate layer formed on the electron supply layer and made of a nitride semiconductor; The nitride semiconductor device according to claim 1 , wherein said gate electrode is formed on and in contact with said intermediate layer.

11. the electron transport layer is a GaN layer, the electron supply layer is an AlGaN layer; The nitride semiconductor device according to claim 10 , wherein the intermediate layer is a GaN layer.

12. The nitride semiconductor layer is an electron transit layer formed on the substrate and made of a nitride semiconductor; an electron supply layer formed on the electron transit layer and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; a gate layer formed on the electron supply layer and made of a nitride semiconductor containing an acceptor-type impurity; The nitride semiconductor device according to claim 1 , wherein said gate electrode is formed on and in contact with said gate layer.

13. the electron transport layer is a GaN layer, the electron supply layer is an AlGaN layer; The nitride semiconductor device according to claim 12 , wherein said gate layer is a GaN layer containing said acceptor-type impurities.

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