Chip resistor and electronic circuit device

Abstract

To provide a chip resistor having an improved short-time overload (STOL) characteristic.SOLUTION: A chip resistor 1 includes an insulating substrate 10, a resistor layer 15, a first electrode 30, and a second electrode 40. The insulating substrate 10 includes a back surface 12. The first electrode 30 includes a first back surface electrode 33. The second electrode 40 includes a second back surface electrode 43. The ratio of the sum of a first area of the first back surface electrode 33 and a second area of the second back surface electrode 43 to the area of the back surface 12 of the insulating substrate 10 is 31% or more. In a direction where the first electrode 30 and the second electrode 40 are separated from each other, each of a first length L21 of the first back surface electrode 33 and a second length L22 of the second back surface electrode 43 is 0.8 mm or more.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a chip resistor and an electronic circuit device. [Background technology]

[0002] International Publication No. 2020 / 189217 (Patent Document 1) discloses a chip resistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 189217 [Summary]

[0004] It is an object of the present disclosure to provide a chip resistor having improved short time overload (STOL) characteristics.

[0005] The chip resistor of the present disclosure includes an insulating substrate, a resistor layer, a first electrode, and a second electrode. The insulating substrate has a front surface, a back surface opposite to the front surface, a first end surface connected to the front surface and the back surface, and a second end surface opposite to the first end surface. The resistor layer is disposed on the front surface of the insulating substrate. The first electrode is connected to the resistor layer. The second electrode is connected to the resistor layer. The first end surface and the second end surface are spaced apart from each other in a direction in which the first electrode and the second electrode are spaced apart from each other. The first electrode includes a first back surface electrode disposed on the back surface of the insulating substrate and electrically connected to the resistor layer. The second electrode includes a second back surface electrode disposed on the back surface of the insulating substrate and electrically connected to the resistor layer. The ratio of the sum of the first area of ​​the first back surface electrode and the second area of ​​the second back surface electrode to the area of ​​the back surface of the insulating substrate is 31% or more. The first length of the first back surface electrode in the above direction and the second length of the second back surface electrode in the above direction are each 0.8 mm or more. [Brief description of the drawings]

[0006] [Figure 1]FIG. 1 is a schematic plan view of a chip resistor according to an embodiment. [Diagram 2] FIG. 2 is a schematic cross-sectional view of the chip resistor according to the embodiment taken along the cross-sectional line II-II shown in FIG. [Diagram 3] FIG. 3 is a schematic bottom view of the chip resistor according to the embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view of the chip resistor and the electronic circuit device according to the embodiment. [Diagram 5] FIG. 5 is a schematic cross-sectional view of an electronic circuit device according to a modified example of the embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing one step of the method for manufacturing the chip resistor according to the embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 6 in the method for manufacturing a chip resistor according to the embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 7 in the method for manufacturing a chip resistor according to the embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 8 in the method for manufacturing a chip resistor according to the embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 9 in the method for manufacturing a chip resistor according to the embodiment. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 10 in the method for manufacturing a chip resistor according to the embodiment. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 11 in the method for manufacturing a chip resistor according to the embodiment. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 12 in the method for manufacturing a chip resistor according to the embodiment. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 13 in the method for manufacturing a chip resistor according to the embodiment. [Figure 15]FIG. 15 is a schematic cross-sectional view showing a step subsequent to the step shown in FIG. 14 in the method for manufacturing a chip resistor according to the embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view of a chip resistor and an electronic circuit device of a comparative example. [Figure 17] 17 is a graph showing the relationship between the bonding strength between the chip resistor and the land pattern and the area of ​​the back electrode.

[0007] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are given the same reference numerals, and the description thereof will not be repeated. At least some of the configurations of the embodiments described below may be arbitrarily combined.

[0008] A chip resistor 1 according to an embodiment will be described with reference to Fig. 1 to Fig. 3. The chip resistor 1 mainly includes an insulating substrate 10, a resistor layer 15, a first electrode 30, and a second electrode 40. The chip resistor 1 may further include an intermediate electrode 20, a first insulating protective layer 25, and a second insulating protective layer 26. For convenience, a portion of the first electrode 30, a portion of the second electrode 40, the first insulating protective layer 25, and the second insulating protective layer 26 are omitted from Fig. 1 and Fig. 3.

[0009] The insulating substrate 10 is made of an insulating material such as alumina (Al2O3). The insulating substrate 10 includes a front surface 11, a back surface 12 opposite the front surface 11, a first end surface 13, and a second end surface 14 opposite the first end surface 13.

[0010] The front surface 11 and the back surface 12 each extend along a first direction (x direction) and a second direction (y direction) perpendicular to the first direction. The first direction (x direction) is the longitudinal direction of the insulating substrate 10. The second direction (y direction) is the lateral direction of the insulating substrate 10. The front surface 11 and the back surface 12 are spaced apart from each other in a third direction (z direction) perpendicular to the first direction (x direction) and the second direction (y direction). The third direction (z direction) is the thickness direction of the insulating substrate 10. The front surface 11 and the back surface 12 are both end surfaces of the insulating substrate 10 in the thickness direction. As shown in FIG. 4, when the chip resistor 1 is mounted on a circuit board 50, the back surface 12 faces the circuit board 50.

[0011] The first end surface 13 and the second end surface 14 are connected to the front surface 11 and the back surface 12, respectively. The first end surface 13 and the second end surface 14 extend along the second direction (y direction) and the third direction (z direction), respectively. The first end surface 13 and the second end surface 14 are, for example, both end surfaces in the longitudinal direction of the insulating substrate 10. The first end surface 13 and the second end surface 14 are spaced apart from each other in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)). The distance between the first end surface 13 and the second end surface 14 is, for example, the length L1 of the insulating substrate 10 in the longitudinal direction (first direction (x direction)) of the insulating substrate 10. The length L1 of the insulating substrate 10 is, for example, greater than 3.2 mm. The length L1 may be 4.0 mm or more, 4.0 mm or more, or 6.0 mm or more.

[0012] The resistor layer 15 has, for example, a function of limiting a current or a function of detecting a current. The resistor layer 15 is disposed on the front surface 11 of the insulating substrate 10. The resistor layer 15 is formed of a conductive material including conductive particles, such as ruthenium oxide (RuO2) or a silver-palladium alloy, and glass.

[0013] The resistor layer 15 may include a first resistor layer portion 16 and a second resistor layer portion 17. The first resistor layer portion 16 and the second resistor layer portion 17 are spaced apart from each other in a direction (first direction (x direction)) in which the first electrode 30 and the second electrode 40 are spaced apart from each other. The first resistor layer portion 16 is provided on the first end face 13 side of the insulating substrate 10. The first resistor layer portion 16 is closer to the first end face 13 than the second resistor layer portion 17. The second resistor layer portion 17 is provided on the second end face 14 side of the insulating substrate 10. The second resistor layer portion 17 is closer to the second end face 14 than the first resistor layer portion 16. The first resistor layer portion 16 is connected to the first electrode 30 (first front surface electrode 31, first auxiliary electrode 32) and the intermediate electrode 20. The second resistor layer portion 17 is connected to the second electrode 40 (the second front surface electrode 41 and the second auxiliary electrode 42) and the intermediate electrode 20.

[0014] Trimming grooves 18 and 19 may be formed in the resistor layer 15. By forming the trimming grooves 18 and 19 in the resistor layer 15, the resistance value of the chip resistor 1 can be accurately determined. Specifically, the trimming groove 18 is formed in the first resistor layer portion 16. The trimming groove 19 is formed in the second resistor layer portion 17. One of the trimming groove 18 and the trimming groove 19 may be omitted.

[0015] The intermediate electrode 20 is disposed on the front surface 11 of the insulating substrate 10. The intermediate electrode 20 is disposed between the first front surface electrode 31 and the second front surface electrode 41 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)). The intermediate electrode 20 is connected to the first resistor layer portion 16 and the second resistor layer portion 17. The intermediate electrode 20 electrically connects the first resistor layer portion 16 and the second resistor layer portion 17 to each other in series. The intermediate electrode 20 is formed of a conductive material including, for example, metal particles (for example, silver particles) and glass.

[0016] The first insulating protective layer 25 covers the resistor layer 15 and protects the resistor layer 15. The first insulating protective layer 25 may further cover or further protect the intermediate electrode 20. The first insulating protective layer 25 may further cover a part of the first front surface electrode 31 of the first electrode 30 and a part of the second front surface electrode 41 of the second electrode 40. The first insulating protective layer 25 is formed of an insulating material such as glass, for example.

[0017] The second insulating protective layer 26 covers the first insulating protective layer 25. The second insulating protective layer 26 may further cover a part of the first front surface electrode 31 of the first electrode 30 and a part of the second front surface electrode 41 of the second electrode 40. The second insulating protective layer 26 may be filled in the trimming grooves 18 and 19 of the resistor layer 15. The second insulating protective layer 26 is formed of an insulating resin such as an epoxy resin.

[0018] The first electrode 30 is disposed on the first end face 13 side of the insulating substrate 10. The first electrode 30 is closer to the first end face 13 than the second electrode 40. The first electrode 30 is connected to the resistor layer 15 (first resistor layer portion 16). The first electrode 30 includes a first front surface electrode 31, a first back surface electrode 33, and a first side surface electrode 36. The first electrode 30 may further include a first auxiliary electrode 32, a first inner plating film 37, and a first outer plating film 38.

[0019] The first front surface electrode 31 is disposed on the front surface 11 of the insulating substrate 10. The first front surface electrode 31 is disposed on a portion of the front surface 11 on the first end surface 13 side. The first front surface electrode 31 is disposed on a portion of the front surface 11 close to the first end surface 13. The first front surface electrode 31 is connected to the resistor layer 15 (first resistor layer portion 16). In a plan view of the front surface 11 of the insulating substrate 10, the first front surface electrode 31 has, for example, a rectangular shape. The first front surface electrode 31 is formed of, for example, a conductive material including metal particles (for example, silver particles) and glass.

[0020] The first auxiliary electrode 32 is disposed on the first front surface electrode 31 and is connected to the first front surface electrode 31. The first auxiliary electrode 32 may be further disposed on the second insulating protective layer 26. The first auxiliary electrode 32 is formed of a conductive material including, for example, a binder resin (for example, an epoxy resin) and metal particles (for example, silver particles) dispersed in the binder resin.

[0021] The first back surface electrode 33 is disposed on the back surface 12 of the insulating substrate 10. The first back surface electrode 33 is disposed on a portion of the back surface 12 on the first end surface 13 side. The first back surface electrode 33 is disposed on a portion of the back surface 12 close to the first end surface 13. The first back surface electrode 33 includes an end portion 33e close to the center 10c of the insulating substrate 10 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)). In a plan view of the front surface 11 or the back surface 12, the first back surface electrode 33 overlaps the trimming groove 18. In a plan view of the front surface 11 or the back surface 12, the first back surface electrode 33 overlaps the center 16c of the first resistor layer portion 16 in the above direction (first direction (x direction)). The first back surface electrode 33 includes a first insulating resin layer 34 and a first conductive layer 35. The first back surface electrode 33 may have a two-layer structure formed of a first insulating resin layer and a first conductive layer .

[0022] The first insulating resin layer 34 is disposed on the back surface 12 of the insulating substrate 10. The first insulating resin layer 34 is formed of an insulating resin such as an epoxy resin. The first insulating resin layer 34 improves the adhesive strength of the first back surface electrode 33 to the insulating substrate 10.

[0023] The first conductive layer 35 is disposed on the first insulating resin layer 34. The first conductive layer 35 covers at least a portion of the first insulating resin layer 34. The first conductive layer 35 may cover the entire first insulating resin layer 34. The first conductive layer 35 may also be disposed on the rear surface 12 of the insulating substrate 10. The first conductive layer 35 is formed of a conductive material containing, for example, a binder resin (e.g., epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin.

[0024] The first side electrode 36 is disposed on the first end face 13 of the insulating substrate 10, on the first front surface electrode 31, and on the first back surface electrode 33 (first conductive layer 35). The first side electrode 36 connects the first front surface electrode 31 and the first back surface electrode 33 to each other. The first side electrode 36 may also be disposed on the first auxiliary electrode 32, and may connect the first auxiliary electrode 32 and the first back surface electrode 33 to each other. The first side electrode 36 is formed of, for example, a Ni-Cr alloy. The first side electrode 36 is formed by a sputtering method.

[0025] The first inner plating film 37 is disposed on the first auxiliary electrode 32, the first side electrode 36, and the first back electrode 33 (first conductive layer 35). The first inner plating film 37 covers the first auxiliary electrode 32, the first side electrode 36, and the first back electrode 33 (first conductive layer 35). The first inner plating film 37 protects the first front electrode 31, the first auxiliary electrode 32, the first side electrode 36, and the first back electrode 33 from heat and impact. The first inner plating film 37 may also be disposed on the second insulating protective layer 26. The first inner plating film 37 is, for example, a nickel plating layer.

[0026] The first outer plating film 38 is disposed on the first inner plating film 37. The first outer plating film 38 covers the first inner plating film 37. The first outer plating film 38 may also be disposed on the second insulating protective layer 26. The first outer plating film 38 is formed of a material to which a joining member such as solder is more easily attached than the first inner plating film 37. The first outer plating film 38 is, for example, a tin plating layer. As shown in FIG. 4, when the chip resistor 1 is mounted on a circuit board 50, the first outer plating film 38 is joined to a land pattern 52 of the circuit board 50 via a joining member 54.

[0027] The second electrode 40 is disposed on the second end surface 14 side of the insulating substrate 10. The second electrode 40 is closer to the second end surface 14 than the first electrode 30. The first electrode 30 and the second electrode 40 are spaced apart from each other in the direction in which the first end surface 13 and the second end surface 14 are spaced apart from each other (first direction (x direction)). The second electrode 40 is connected to the resistor layer 15 (second resistor layer portion 17). The second electrode 40 includes a second front surface electrode 41, a second back surface electrode 43, and a second side surface electrode 46. The second electrode 40 may further include a second auxiliary electrode 42, a second inner plating film 47, and a second outer plating film 48.

[0028] The second front surface electrode 41 is disposed on the front surface 11 of the insulating substrate 10. The second front surface electrode 41 is disposed on a portion of the front surface 11 on the second end surface 14 side. The second front surface electrode 41 is disposed on a portion of the front surface 11 close to the second end surface 14. The second front surface electrode 41 is connected to the resistor layer 15 (second resistor layer portion 17). In a plan view of the front surface 11 of the insulating substrate 10, the second front surface electrode 41 has, for example, a rectangular shape. The second front surface electrode 41 is formed of a conductive material including, for example, metal particles (for example, silver particles) and glass.

[0029] The second auxiliary electrode 42 is disposed on the second front surface electrode 41 and is connected to the second front surface electrode 41. The second auxiliary electrode 42 may be further disposed on the second insulating protective layer 26. The second auxiliary electrode 42 is formed of a conductive material including, for example, a binder resin (e.g., epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin.

[0030] The second back surface electrode 43 is disposed on the back surface 12 of the insulating substrate 10. The second back surface electrode 43 is disposed on a portion of the back surface 12 on the second end surface 14 side. The second back surface electrode 43 is disposed on a portion of the back surface 12 close to the second end surface 14. The second back surface electrode 43 includes an end portion 43e close to the center 10c of the insulating substrate 10 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)). In a plan view of the front surface 11 or the back surface 12, the second back surface electrode 43 overlaps the trimming groove 19. In a plan view of the front surface 11 or the back surface 12, the second back surface electrode 43 overlaps the center 17c of the second resistor layer portion 17 in the above direction (first direction (x direction)). The second back surface electrode 43 includes a second insulating resin layer 44 and a second conductive layer 45. The second back surface electrode 43 may have a two-layer structure formed of a second insulating resin layer 44 and a second conductive layer 45.

[0031] The second insulating resin layer 44 is disposed on the back surface 12 of the insulating substrate 10. The second insulating resin layer 44 is formed of an insulating resin such as an epoxy resin. The second insulating resin layer 44 improves the adhesive strength of the second back surface electrode 43 to the insulating substrate 10.

[0032] The second conductive layer 45 is disposed on the second insulating resin layer 44. The second conductive layer 45 covers at least a portion of the second insulating resin layer 44. The second conductive layer 45 may cover the entire second insulating resin layer 44. The second conductive layer 45 may also be disposed on the rear surface 12 of the insulating substrate 10. The second conductive layer 45 is formed of a conductive material containing, for example, a binder resin (e.g., epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin.

[0033] The second side electrode 46 is disposed on the second end surface 14 of the insulating substrate 10, on the second front surface electrode 41, and on the second back surface electrode 43 (second conductive layer 45). The second side electrode 46 connects the second front surface electrode 41 and the second back surface electrode 43 to each other. The second side electrode 46 may also be disposed on the second auxiliary electrode 42, and may connect the second auxiliary electrode 42 and the second back surface electrode 43 to each other. The second side electrode 46 is formed of, for example, a Ni-Cr alloy. The second side electrode 46 is formed by a sputtering method.

[0034] The second inner plating film 47 is disposed on the second auxiliary electrode 42, the second side electrode 46, and the second back electrode 43 (second conductive layer 45). The second inner plating film 47 covers the second auxiliary electrode 42, the second side electrode 46, and the second back electrode 43 (second conductive layer 45). The second inner plating film 47 protects the second front electrode 41, the second auxiliary electrode 42, the second side electrode 46, and the second back electrode 43 from heat and impact. The second inner plating film 47 may also be disposed on the second insulating protective layer 26. The second inner plating film 47 is, for example, a nickel plating layer.

[0035] The second outer plating film 48 is disposed on the second inner plating film 47. The second outer plating film 48 covers the second inner plating film 47. The second outer plating film 48 may also be disposed on the second insulating protective layer 26. The second outer plating film 48 is formed of a material to which a joining member such as solder is more easily attached than the second inner plating film 47. The second outer plating film 48 is, for example, a tin plating layer. As shown in FIG. 4, when the chip resistor 1 is mounted on a circuit board 50, the second outer plating film 48 is joined to a land pattern 53 of the circuit board 50 via a joining member 55.

[0036] The area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is 31% or more. In this specification, the area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 means the ratio of the sum of the first area of ​​the first back surface electrode 33 and the second area of ​​the second back surface electrode 43 to the area of ​​the back surface 12 of the insulating substrate 10. The area of ​​the back surface 12 of the insulating substrate 10, the first area of ​​the first back surface electrode 33, and the second area of ​​the second back surface electrode 43 are all areas in a plan view of the back surface 12. The above ratio may be 38% or more, or may be 44% or more. The first length L of the first back surface electrode 33 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)) 21 and the second length L of the second back surface electrode 43 in the above direction. 22 Each of the first length L 21 and the second length L 22 may each be 1.0 mm or more, or 1.2 mm or more.

[0037] An electronic circuit device 2 of the present embodiment will be described with reference to Fig. 4. The electronic circuit device 2 includes a chip resistor 1, a circuit board 50, a bonding member 54, and a bonding member 55.

[0038] The circuit board 50 includes an insulating circuit board 51, a land pattern 52, and a land pattern 53 spaced apart from the land pattern 52. The first back electrode 33 is joined to the land pattern 52 using a joining member 54 such as solder. The second back electrode 43 is joined to the land pattern 53 using a joining member 55 such as solder. The land pattern 52 includes an end 52e that is proximate to the center 10c of the insulating substrate 10 and proximate to the land pattern 53 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)). The land pattern 53 includes an end 53e that is proximate to the center 10c of the insulating substrate 10 and proximate to the land pattern 52 in the above direction (first direction (x direction)).

[0039] In the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 33e of the first back surface electrode 33 is closer to the center 10c of the insulating substrate 10 than the end 52e of the land pattern 52. That is, in the above direction, the distance d1 between the end 33e of the first back surface electrode 33 and the end 52e of the land pattern 52 is greater than 0 mm. In the above direction, the distance d1 may be 0.2 mm or more, 0.4 mm or more, or 0.6 mm or more.

[0040] In the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 43e of the second back surface electrode 43 is closer to the center 10c of the insulating substrate 10 than the end 53e of the land pattern 53. That is, in the above direction, the distance d2 between the end 43e of the second back surface electrode 43 and the end 53e of the land pattern 53 is greater than 0 mm. In the above direction, the distance d2 may be 0.2 mm or more, 0.4 mm or more, or 0.6 mm or more.

[0041] As shown in FIG. 5, in the electronic circuit device 2 of the modified example of the present embodiment, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 33e of the first back electrode 33 may be at the same position as the end 52e of the land pattern 52. That is, in the above direction, the distance d1 between the end 33e of the first back electrode 33 and the end 52e of the land pattern 52 may be 0 mm. In the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 43e of the second back electrode 43 may be at the same position as the end 53e of the land pattern 53. That is, in the above direction, the distance d2 between the end 43e of the second back electrode 43 and the end 53e of the land pattern 53 may be 0 mm.

[0042] An example of a method for manufacturing the chip resistor 1 of the present embodiment will be described with reference to FIGS. 2 and 6 to 15.

[0043] 6, a sheet substrate 10s is prepared. The sheet substrate 10s is made of an insulating material such as alumina. The sheet substrate 10s includes a front surface 11 and a back surface 12 opposite to the front surface 11. A dividing groove 10g is formed in the front surface 11 and the back surface 12 of the sheet substrate 10s.

[0044] 7, a front surface conductive layer 21 and an intermediate electrode 20 are formed on the front surface 11 of the sheet substrate 10s. The front surface conductive layer 21 is formed on the front surface 11 of the sheet substrate 10s so as to straddle the dividing groove 10g of the sheet substrate 10s. The intermediate electrode 20 is formed between a pair of front surface conductive layers 21 adjacent to each other in the first direction (x direction). The front surface conductive layer 21 and the intermediate electrode 20 are formed, for example, by printing a paste containing metal particles (e.g., silver particles) and glass frit on the front surface 11 and firing it.

[0045] 8, a resin paste is printed on the rear surface 12 of the insulating substrate 10 and cured to form a first insulating resin layer 34 and a second insulating resin layer 44 on the rear surface 12 of the sheet substrate 10s. Then, a paste (e.g., silver paste) containing a binder resin (e.g., epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin is printed on the first insulating resin layer 34, the second insulating resin layer 44, and the rear surface 12 of the insulating substrate 10 and cured to form a rear surface conductive layer 22.

[0046] 9, a paste containing glass frit in an electrical resistance material such as ruthenium oxide (RuO2) or a silver-palladium alloy is printed on the front surface 11 of the sheet substrate 10s and fired to form a resistor layer 15. The resistor layer 15 includes a first resistor layer portion 16 and a second resistor layer portion 17. The first resistor layer portion 16 is connected to the front surface conductive layer 21 and the intermediate electrode 20. The second resistor layer portion 17 is connected to the front surface conductive layer 21 and the intermediate electrode 20.

[0047] With reference to FIG. 10, for example, a paste containing glass is printed on the resistor layer 15, the intermediate electrode 20 and the front surface conductive layer 21, and then fired to form the first insulating protective layer 25.

[0048] Referring to FIG. 11, trimming grooves 18 and 19 are formed in the resistor layer 15. The trimming grooves 18 and 19 are also formed in the first insulating protective layer 25. The trimming grooves 18 and 19 are formed, for example, by irradiating the resistor layer 15 and the first insulating protective layer 25 with laser light. When the resistance value of the resistor layer 15 reaches the target resistance value of the chip resistor 1, the formation of the trimming grooves 18 and 19 is completed. The first insulating protective layer 25 reduces the thermal shock acting on the resistor layer 15 when the trimming grooves 18 and 19 are formed, and prevents fine particles generated when the trimming grooves 18 and 19 are formed from adhering to the resistor layer 15, causing the resistance value of the resistor layer 15 to fluctuate.

[0049] 12, for example, a paste containing an epoxy resin is printed on the first insulating protective layer 25 and the front surface conductive layer 21, and then cured to form the second insulating protective layer 26. The second insulating protective layer 26 may be filled in the trimming grooves 18 and 19.

[0050] 13, the auxiliary electrode layer 23 is formed on the front surface conductive layer 21. The auxiliary electrode layer 23 may also be formed on the second insulating protective layer 26. For example, the auxiliary electrode layer 23 is formed by applying a paste (e.g., silver paste) containing a binder resin (e.g., epoxy resin) and metal particles (e.g., silver particles) dispersed in the binder resin onto the front surface conductive layer 21 and the second insulating protective layer 26 and curing the paste.

[0051] Referring to FIG. 14, the sheet substrate 10s is cut along the multiple division grooves 10g. The sheet substrate 10s is divided into multiple insulating substrates 10. By cutting the sheet substrate 10s, a first end surface 13 and a second end surface 14 are formed. By cutting the sheet substrate 10s, the front surface conductive layer 21 is divided into a first front surface electrode 31 and a second front surface electrode 41. By cutting the sheet substrate 10s, the auxiliary electrode layer 23 is divided into a first auxiliary electrode 32 and a second auxiliary electrode 42, and the first auxiliary electrode 32 and the second auxiliary electrode 42 are formed. By cutting the sheet substrate 10s, the back surface conductive layer 22 is divided into a first conductive layer 35 and a second conductive layer 45, and the first back surface electrode 33 and the second back surface electrode 43 are formed.

[0052] 15, a first side electrode 36 is formed on a first end surface 13 of insulating substrate 10 by sputtering, and a second side electrode 46 is formed on a second end surface 14 of insulating substrate 10 by sputtering.

[0053] Then, a first inner plating film 37 and a second inner plating film 47 (see FIG. 2) are formed by plating. The first inner plating film 37 is formed on the first auxiliary electrode 32, the first side electrode 36, and the first back electrode 33 (first conductive layer 35), and covers the first auxiliary electrode 32, the first side electrode 36, and the first back electrode 33 (first conductive layer 35). The second inner plating film 47 is formed on the second auxiliary electrode 42, the second side electrode 46, and the second back electrode 43 (second conductive layer 45), and covers the second auxiliary electrode 42, the second side electrode 46, and the second back electrode 43 (second conductive layer 45). The first inner plating film 37 and the second inner plating film 47 are, for example, nickel plating layers.

[0054] Then, a first outer plating film 38 and a second outer plating film 48 (see FIG. 2) are formed by a plating method. The first outer plating film 38 is formed on the first inner plating film 37 and covers the first inner plating film 37. The second outer plating film 48 is formed on the second inner plating film 47 and covers the second inner plating film 47. The first outer plating film 38 and the second outer plating film 48 are, for example, tin plating layers. In this way, the chip resistor 1 shown in FIGS. 1 to 3 is obtained.

[0055] The operation of the chip resistor 1 of the present embodiment will be described in comparison with the chip resistor 1 of Examples 1 to 4, which are specific examples of the present embodiment, and the chip resistor 1b of the comparative example. In the chip resistors 1 of Examples 1 to 4 and the chip resistor 1b of the comparative example, the length L1 of the insulating substrate 10 in the longitudinal direction (first direction (x direction)) of the insulating substrate 10 is 6.4 mm. Referring to FIG. 16, the chip resistor 1b of the comparative example has a similar configuration to the chip resistor 1 of the present embodiment, but the first length L1 of the first back surface electrode 33 is 6.4 mm. 21 and the second length L of the second back electrode 43 22 8mm and the area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is less than 31%.

[0056] Specifically, as shown in Table 1, in the chip resistor 1b of the comparative example, the first length L 21 and the second length L of the second back electrode 43 22 The area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is 19%. 21 and the second length L of the second back electrode 43 22 The area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is 31%. 21 and the second length L of the second back electrode 43 22The area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is 38%. 21 and the second length L of the second back electrode 43 22 The area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is 44%. 21 and the second length L of the second back electrode 43 22 The area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 is 53%. [Table 1]

[0057] Table 1 shows the short-time overload (STOL) characteristics of the chip resistors 1 of Examples 1 to 4 and the chip resistor 1b of the comparative example. r The voltage V at which the resistance value of the chip resistor changes by 2% d Ratio (V d / V r ) is expressed as V d / V r It can be seen from Table 1 that the chip resistors 1 of Examples 1 to 4 have improved STOL characteristics compared to the chip resistor 1b of the comparative example.

[0058] Specifically, the first length L of the first back surface electrode 33 21 and the second length L of the second back electrode 43 22 The longer the first length L of the first back surface electrode 33, the more the STOL characteristic of the chip resistor 1 improves. 21 and the second length L of the second back electrode 43 22The longer the length, the more efficiently the heat generated in the resistor layer 15 when a current flows through the chip resistor 1 is dissipated to the outside of the chip resistor 1 through the first back electrode 33 and the second back electrode 43. Also, the more the area ratio of the back electrode to the back surface 12 of the insulating substrate 10 increases, the more the STOL characteristics of the chip resistor 1 improve. The reason why the STOL characteristics of the chip resistor 1 improve in this way is that the more the area ratio of the back electrode to the back surface 12 of the insulating substrate 10 increases, the more efficiently the heat generated in the resistor layer 15 when a current flows through the chip resistor 1 is dissipated to the outside of the chip resistor 1 through the first back electrode 33 and the second back electrode 43.

[0059] The operation of the electronic circuit device 2 of the present embodiment will be described while comparing the electronic circuit device 2 of Examples 1 to 4 with the electronic circuit device 2b of the comparative example. With reference to FIG. 16, the electronic circuit device 2b of the comparative example has a configuration similar to that of the electronic circuit device 2 of the present embodiment, but differs from the electronic circuit device 2 of the embodiment in that it includes the chip resistor 1b of the comparative example described above instead of the chip resistor 1 of the present embodiment. Therefore, as shown in FIG. 16, in the electronic circuit device 2b of the comparative example, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 33e of the first back electrode 33 is farther from the center 10c of the insulating substrate 10 than the end 52e of the land pattern 52. In the above direction, the end 43e of the second back electrode 43 is farther from the center 10c of the insulating substrate 10 than the end 53e of the land pattern 53.

[0060] In contrast, the electronic circuit device 2 of Example 1 includes the chip resistor 1 of Example 1 already described. Therefore, as shown in FIG. 5, in the electronic circuit device 2 of Example 1, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 33e of the first back electrode 33 is at the same position as the end 52e of the land pattern 52. In the above direction, the end 43e of the second back electrode 43 is at the same position as the end 53e of the land pattern 53. That is, in the electronic circuit device 2 of Example 1, in the above direction, the distance d1 between the end 33e of the first back electrode 33 and the end 52e of the land pattern 52 is 0 mm, and the distance d2 between the end 43e of the second back electrode 43 and the end 53e of the land pattern 53 is 0 mm.

[0061] The electronic circuit device 2 of Example 2 includes the chip resistor 1 of Example 2 already described. The electronic circuit device 2 of Example 3 includes the chip resistor 1 of Example 3 already described. The electronic circuit device 2 of Example 4 includes the chip resistor 1 of Example 4 already described. Therefore, as shown in FIG. 4, in the electronic circuit devices 2 of Examples 2 to 4, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 33e of the first back electrode 33 is closer to the center 10c of the insulating substrate 10 than the end 52e of the land pattern 52, and the end 43e of the second back electrode 43 is closer to the center 10c of the insulating substrate 10 than the end 53e of the land pattern 53.

[0062] For example, in the electronic circuit device 2 of Example 2, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the end 33e of the first back electrode 33 is closer to the center 10c of the insulating substrate 10 by a distance d1 of 0.2 mm than the end 52e of the land pattern 52, and the end 43e of the second back electrode 43 is closer to the center 10c of the insulating substrate 10 by a distance d2 of 0.2 mm than the end 53e of the land pattern 53. In the electronic circuit device 2 of Example 3, in the above direction, the end 33e of the first back electrode 33 is closer to the center 10c of the insulating substrate 10 by a distance d1 of 0.4 mm than the end 52e of the land pattern 52, and the end 43e of the second back electrode 43 is closer to the center 10c of the insulating substrate 10 by a distance d2 of 0.4 mm than the end 53e of the land pattern 53. In the electronic circuit device 2 of Example 4, in the above-mentioned direction, the end 33e of the first back electrode 33 is closer to the center 10c of the insulating substrate 10 by a distance d1 of 0.6 mm than the end 52e of the land pattern 52, and the end 43e of the second back electrode 43 is closer to the center 10c of the insulating substrate 10 by a distance d2 of 0.6 mm than the end 53e of the land pattern 53.

[0063] Table 2 shows the temperature cycle characteristics of the electronic circuit device 2 of Examples 1 to 4 and the temperature cycle characteristics of the electronic circuit device 2b of the comparative example. The temperature cycle test is performed as follows. Thirty samples are prepared for each of the electronic circuit devices 2 of Examples 1 to 4 and the electronic circuit device 2b of the comparative example. A temperature cycle is applied to the 30 samples, in which the ambient temperature of the samples is repeatedly changed between a low temperature of -55°C and a high temperature of +150°C. The number of repeated temperature cycles (number of temperature cycles) and the number of samples in which the rate of change in resistance value between the land pattern 52 and the land pattern 53 via the chip resistor 1 exceeds 2% after the number of temperature cycles are recorded. In this way, the temperature cycle characteristics of the electronic circuit device 2 of Examples 1 to 4 and the temperature cycle characteristics of the electronic circuit device 2b of the comparative example are obtained. The fewer the number of samples in which the rate of change in resistance value between the land pattern 52 and the land pattern 53 via the chip resistor 1 exceeds 2%, the better the temperature cycle characteristics of the electronic circuit device. It can be seen from Table 2 that the electronic circuit devices 2 of Examples 1 to 4 have improved temperature cycle characteristics compared to the electronic circuit device 2b of the comparative example. [Table 2]

[0064] Specifically, the first length L of the first back surface electrode 33 21 When the second length L of the second back electrode 43 is longer and the end 33e of the first back electrode 33 is at the same position as the end 52e of the land pattern 52 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (the first direction (x direction)), or is closer to the center 10c of the insulating substrate 10 than the end 52e, the temperature cycle characteristic of the electronic circuit device 2 is improved. 22is longer and the end 43e of the second back surface electrode 43 is at the same position as the end 53e of the land pattern 53 in the above direction (first direction (x direction)) or is closer to the center 10c of the insulating substrate 10 than the end 53e, the temperature cycle characteristics of the electronic circuit device 2 are improved. The greater the area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10, the more improved the temperature cycle characteristics of the electronic circuit device 2. The reason why the temperature cycle characteristics of the electronic circuit device 2 are improved in this manner is as follows.

[0065] First, the first length L of the first rear electrode 33 21 The second length L of the second back surface electrode 43 becomes longer. 22 As the length of the bonding pad 54 increases or the area ratio of the back surface electrode to the back surface 12 of the insulating substrate 10 increases, at least one of the contact area between the chip resistor 1 and the bonding member 54 or the contact area between the chip resistor 1 and the bonding member 55 increases. As shown in FIG. 17, the bonding strength between the land patterns 52, 53 and the back surface electrodes (first back surface electrode 33 and second back surface electrode 43) increases. Therefore, even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the bonding members 54, 55 can be suppressed. The temperature cycle characteristics of the electronic circuit device 2 are improved.

[0066] Secondly, when a current flows through the chip resistor 1 and the temperature of the chip resistor 1 rises, the temperature of the insulating circuit board 51 also rises. In general, the thermal expansion coefficient of the insulating circuit board 51 is greater than that of the insulating substrate 10. Due to the difference between the thermal expansion coefficient of the insulating circuit board 51 and the thermal expansion coefficient of the insulating substrate 10, thermal stress is applied to the bonding members 54 and 55. Then, the thermal stress is concentrated in a portion of the bonding member 54 near the end 33e of the first back electrode 33. The thermal stress is concentrated in a portion of the bonding member 55 near the end 43e of the second back electrode 43. As the insulating substrate 10 approaches the center 10c, the pulling force of the insulating substrate 10 by the insulating circuit board 51 decreases. Therefore, as the end 33e of the first back electrode 33 approaches the center 10c of the insulating substrate 10, the thermal stress applied to the portion of the bonding member 54 near the end 33e of the first back electrode 33 decreases. As the end 43e of the second back surface electrode 43 approaches the center 10c of the insulating substrate 10, the thermal stress applied to the portion of the bonding member 55 near the end 43e of the second back surface electrode 43 decreases. As a result, even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the bonding members 54, 55 can be suppressed. The temperature cycle characteristics of the electronic circuit device 2 are improved.

[0067] A CAE (Computer Aided Engineering) analysis of thermal stress was performed on the electronic circuit device 2 of Example 3 and the electronic circuit device 2b of the comparative example. In the electronic circuit device 2b of the comparative example, the thermal stress applied to the portion of the bonding member 54 near the end 33e of the first back electrode 33 is 463.8 MPa. In contrast, in the electronic circuit device 2 of Example 3, the thermal stress applied to the portion of the bonding member 54 near the end 33e of the first back electrode 33 is reduced to 118.5 MPa. The present inventor found that a chip resistor in which the side electrodes (the first side electrode 36 and the second side electrode 46) are formed by a sputtering method is more likely to cause cracks in the bonding members 54 and 55 than a chip resistor in which the side electrodes are formed by a dip coating method. In this embodiment, the occurrence of such cracks can be prevented.

[0068] In a modification of this embodiment, the resistor layer 15 does not have to be divided into the first resistor layer portion 16 and the second resistor layer portion 17, and may be a single resistor layer.

[0069] The effects of the chip resistor 1 and the electronic circuit device 2 of this embodiment will be described.

[0070] The chip resistor 1 of this embodiment includes an insulating substrate 10, a resistor layer 15, a first electrode 30, and a second electrode 40. The insulating substrate 10 has a front surface 11, a back surface 12 opposite to the front surface 11, a first end surface 13 connected to the front surface 11 and the back surface 12, and a second end surface 14 opposite to the first end surface 13. The resistor layer 15 is disposed on the front surface 11 of the insulating substrate 10. The first electrode 30 is connected to the resistor layer 15. The second electrode 40 is connected to the resistor layer 15. The first end surface 13 and the second end surface 14 are spaced apart from each other in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other. The first electrode 30 includes a first back surface electrode 33 disposed on the back surface 12 of the insulating substrate 10 and electrically connected to the resistor layer 15. The second electrode 40 includes a second back surface electrode 43 disposed on the back surface 12 of the insulating substrate 10 and electrically connected to the resistor layer 15. The ratio of the sum of the first area of ​​the first back surface electrode 33 and the second area of ​​the second back surface electrode 43 to the area of ​​the back surface 12 of the insulating substrate 10 is 31% or more. The first length L of the first back surface electrode 33 in the above direction 21 and the second length L of the second back surface electrode 43 in the above direction. 22 are each 0.8 mm or more.

[0071] Therefore, heat generated in the resistor layer 15 when a current flows through the chip resistor 1 is more efficiently dissipated to the outside of the chip resistor 1 through the first back surface electrode 33 and the second back surface electrode 43. The STOL characteristics of the chip resistor 1 are improved.

[0072] Furthermore, the chip resistor 1 increases the bonding strength between the chip resistor 1 and the circuit board 50 via the bonding members 54, 55, and reduces the thermal stress applied to the bonding members 54, 55 due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50. Therefore, it is possible to suppress the occurrence of cracks in the bonding members 54, 55 interposed between the back electrodes (first back electrode 33 and second back electrode 43) of the chip resistor 1 and the circuit board 50.

[0073] In the chip resistor 1 of the present embodiment, the above ratio is 38% or more.

[0074] Therefore, heat generated in the resistor layer 15 when a current flows through the chip resistor 1 is more efficiently dissipated to the outside of the chip resistor 1 through the first back surface electrode 33 and the second back surface electrode 43. The STOL characteristics of the chip resistor 1 are improved. In addition, the chip resistor 1 can suppress the occurrence of cracks in the bonding members 54, 55 interposed between the back surface electrodes (first back surface electrode 33 and second back surface electrode 43) of the chip resistor 1 and the circuit board 50.

[0075] In the chip resistor 1 of the present embodiment, the first length L 21 and the second length L 22 are each 1.0 mm or more.

[0076] Therefore, heat generated in the resistor layer 15 when a current flows through the chip resistor 1 is more efficiently dissipated to the outside of the chip resistor 1 through the first back surface electrode 33 and the second back surface electrode 43. The STOL characteristics of the chip resistor 1 are improved. In addition, the chip resistor 1 can suppress the occurrence of cracks in the bonding members 54, 55 interposed between the back surface electrodes (first back surface electrode 33 and second back surface electrode 43) of the chip resistor 1 and the circuit board 50.

[0077] In the chip resistor 1 of the present embodiment, a trimming groove 18 is formed in the resistor layer 15. In a plan view of the front surface 11 of the insulating substrate 10, the first back surface electrode 33 overlaps the trimming groove 18.

[0078] When a current flows through the chip resistor 1, the temperature particularly rises in the portion of the resistor layer 15 near the trimming groove 18. Because the first back surface electrode 33 overlaps the trimming groove 18 in a plan view of the front surface 11 of the insulating substrate 10, heat generated in the portion of the resistor layer 15 near the trimming groove 18 is dissipated from the first back surface electrode 33 to the outside of the chip resistor 1 via the insulating substrate 10. The STOL characteristics of the chip resistor 1 are improved.

[0079] The chip resistor 1 of the present embodiment further includes an intermediate electrode 20 disposed on the front surface 11 of the insulating substrate 10. The first electrode 30 includes a first front surface electrode 31 disposed on the front surface 11 of the insulating substrate 10. The second electrode 40 includes a second front surface electrode 41 disposed on the front surface 11 of the insulating substrate 10. The intermediate electrode 20 is disposed between the first front surface electrode 31 and the second front surface electrode 41. The resistor layer 15 includes a first resistor layer portion 16 connected to the first front surface electrode 31 and the intermediate electrode 20. In a plan view of the front surface 11 of the insulating substrate 10, the first back surface electrode 33 overlaps the center 16c of the first resistor layer portion 16 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other.

[0080] When a current flows through the chip resistor 1, the temperature particularly rises at the center 16c of the first resistor layer portion 16. In a plan view of the front surface 11 of the insulating substrate 10, the first back surface electrode 33 overlaps the center 16c of the first resistor layer portion 16, so the heat generated at the center 16c of the first resistor layer portion 16 is dissipated from the first back surface electrode 33 to the outside of the chip resistor 1 via the insulating substrate 10. The STOL characteristics of the chip resistor 1 are improved.

[0081] In the chip resistor 1 of the present embodiment, the resistor layer 15 includes a second resistor layer portion 17 connected to the second front surface electrode 41 and the intermediate electrode 20. In a plan view of the front surface 11 of the insulating substrate 10, the second back surface electrode 43 overlaps with a center 17c of the second resistor layer portion 17 in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (the first direction (x direction)).

[0082] When a current flows through the chip resistor 1, the temperature particularly rises at the center 17c of the second resistor layer portion 17. In a plan view of the front surface 11 of the insulating substrate 10, the second back surface electrode 43 overlaps the center 17c of the second resistor layer portion 17, so the heat generated at the center 17c of the second resistor layer portion 17 is dissipated from the second back surface electrode 43 to the outside of the chip resistor 1 via the insulating substrate 10. The STOL characteristics of the chip resistor 1 are improved.

[0083] The electronic circuit device 2 of the present embodiment includes the chip resistor 1 of the present embodiment, a circuit board 50, a first bonding member (bonding member 54), and a second bonding member (bonding member 55). The circuit board 50 includes a first land pattern (land pattern 52) and a second land pattern (land pattern 53) spaced apart from the first land pattern. The first back surface electrode 33 is bonded to the first land pattern using the first bonding member. The second back surface electrode 43 is bonded to the second land pattern using the second bonding member. In the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the first end (end 33e) of the first back surface electrode 33 proximate to the center 10c of the insulating substrate 10 is at the same position as the second end (end 52e) of the first land pattern proximate to the center 10c of the insulating substrate 10, or is closer to the center 10c of the insulating substrate 10 than the second end.

[0084] Therefore, the contact area between the chip resistor 1 and the first bonding member (bonding member 54) is increased, and the bonding strength between the chip resistor 1 and the circuit board 50 via the first bonding member is improved. In addition, the thermal stress applied to the first bonding member due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. Even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the first bonding member can be suppressed. The temperature cycle characteristics of the electronic circuit device 2 are improved. In addition, the electronic circuit device 2 of this embodiment includes the chip resistor 1, and therefore has improved STOL characteristics and higher reliability.

[0085] In the electronic circuit device 2 of the present embodiment, the length L1 of the insulating substrate 10 from the first end face 13 to the second end face 14 is greater than 3.2 mm.

[0086] When the length L1 of the insulating substrate 10 from the first end surface 13 to the second end surface 14 increases, the thermal stress applied to the first bonding member (bonding member 54) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 increases. However, in the electronic circuit device 2 of this embodiment, the first end (end 33e) of the first back electrode 33 is at the same position as the second end (end 52e) of the first land pattern (land pattern 52), or is closer to the center 10c of the insulating substrate 10 than the second end. Therefore, the thermal stress applied to the first bonding member due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 decreases. Even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the first bonding member can be suppressed. The temperature cycle characteristic of the electronic circuit device 2 is improved.

[0087] In the electronic circuit device 2 of the present embodiment, the first back surface electrode 33 and the second back surface electrode 43 each include an insulating resin layer (first insulating resin layer 34, second insulating resin layer 44) disposed on the back surface 12 of the insulating substrate 10, and a conductive layer (first conductive layer 35, second conductive layer 45) disposed on the insulating resin layer. The conductive layer is formed of a conductive material including a binder resin and metal particles dispersed in the binder resin.

[0088] The insulating resin layer (first insulating resin layer 34, second insulating resin layer 44) improves the adhesive strength of the first back electrode 33 and the second back electrode 43 to the insulating substrate 10. The conductive layer (first conductive layer 35, second conductive layer 45) of the present embodiment has a lower Young's modulus than a conductive layer formed of a conductive material containing glass and metal particles. Therefore, the thermal stress applied to the first bonding member (bonding member 54) and the second bonding member (bonding member 55) due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 is reduced. Even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the first bonding member and the second bonding member can be suppressed. The temperature cycle characteristic of the electronic circuit device 2 is improved.

[0089] In the electronic circuit device 2 of this embodiment, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the first end (end 33e) of the first back surface electrode 33 is closer to the center 10c of the insulating substrate 10 by 0.2 mm or more than the second end (end 52e) of the first land pattern (land pattern 52).

[0090] Therefore, the contact area between the chip resistor 1 and the first bonding member (bonding member 54) increases, improving the bonding strength between the chip resistor 1 and the circuit board 50 via the first bonding member. Also, the thermal stress applied to the first bonding member due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 decreases. Even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the first bonding member can be suppressed. The temperature cycle characteristics of the electronic circuit device 2 are improved.

[0091] In the electronic circuit device 2 of this embodiment, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the third end (end 43e) of the second back surface electrode 43 proximate to the center 10c of the insulating substrate 10 is at the same position as the fourth end (end 53e) of the second land pattern (land pattern 53) proximate to the center 10c of the insulating substrate 10, or is closer to the center 10c of the insulating substrate 10 than the fourth end.

[0092] Therefore, the contact area between the chip resistor 1 and the second bonding member (bonding member 55) increases, improving the bonding strength between the chip resistor 1 and the circuit board 50 via the second bonding member. Also, the thermal stress applied to the second bonding member due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 decreases. Even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the second bonding member can be suppressed. The temperature cycle characteristics of the electronic circuit device 2 are improved.

[0093] In the electronic circuit device 2 of this embodiment, in the direction in which the first electrode 30 and the second electrode 40 are spaced apart from each other (first direction (x direction)), the third end (end 43e) of the second back surface electrode 43 is closer to the center 10c of the insulating substrate 10 by 0.2 mm or more than the fourth end (end 53e) of the second land pattern (land pattern 53).

[0094] Therefore, the contact area between the chip resistor 1 and the second bonding member (bonding member 55) increases, improving the bonding strength between the chip resistor 1 and the circuit board 50 via the second bonding member. Also, the thermal stress applied to the second bonding member due to the difference between the thermal expansion coefficient of the chip resistor 1 and the thermal expansion coefficient of the circuit board 50 decreases. Even if a temperature cycle is applied to the electronic circuit device 2, the occurrence of cracks in the second bonding member can be suppressed. The temperature cycle characteristics of the electronic circuit device 2 are improved.

[0095] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) an insulating substrate having a front surface, a back surface opposite to the front surface, a first end surface connected to the front surface and the back surface, and a second end surface opposite to the first end surface; a resistor layer disposed on the front surface; A first electrode connected to the resistor layer; a second electrode connected to the resistor layer; the first end surface and the second end surface are spaced apart from each other in a direction in which the first electrode and the second electrode are spaced apart from each other, the first electrode includes a first back surface electrode disposed on the back surface and electrically connected to the resistor layer; the second electrode includes a second back surface electrode disposed on the back surface and electrically connected to the resistor layer; a ratio of a sum of a first area of ​​the first back surface electrode and a second area of ​​the second back surface electrode to an area of ​​the back surface is 31% or more; A chip resistor, wherein a first length of the first back surface electrode in the said direction and a second length of the second back surface electrode in the said direction are each 0.8 mm or more. (Appendix 2) 2. The chip resistor according to claim 1, wherein the ratio is 38% or more. (Appendix 3) 3. The chip resistor according to claim 1, wherein the first length and the second length are each 1.0 mm or more. (Appendix 4) A trimming groove is formed in the resistor layer, 4. The chip resistor according to claim 1, wherein, in a plan view of the front surface, the first back surface electrode overlaps the trimming groove. (Appendix 5) further comprising an intermediate electrode disposed on the front surface; the first electrode includes a first front surface electrode disposed on the front surface; the second electrode includes a second front surface electrode disposed on the front surface; the intermediate electrode is disposed between the first front electrode and the second front electrode, the resistor layer includes a first resistor layer portion connected to the first front electrode and the intermediate electrode, 5. The chip resistor according to claim 1, wherein, in a planar view of the front surface, the first back electrode overlaps with a center of the first resistor layer portion in the direction. (Appendix 6) the resistor layer includes a second resistor layer portion connected to the second front surface electrode and the intermediate electrode, The chip resistor described in Appendix 5, wherein, in the planar view of the front surface, the second back surface electrode overlaps with the center of the second resistor layer portion in the direction. (Appendix 7) The chip resistor according to any one of Supplementary Note 1 to Supplementary Note 6, a circuit board including a first land pattern and a second land pattern spaced apart from the first land pattern; A first joining member; and a second joining member, the first back surface electrode is bonded to the first land pattern using the first bonding member; the second back surface electrode is joined to the second land pattern by using the second joining member, An electronic circuit device, wherein in the direction, a first end of the first back surface electrode proximate to the center of the insulating substrate is at the same position as a second end of the first land pattern proximate to the center of the insulating substrate, or is closer to the center of the insulating substrate than the second end. (Appendix 8) 8. The electronic circuit device of claim 7, wherein a length of the insulating substrate from the first end surface to the second end surface is greater than 3.2 mm. (Appendix 9) the first back surface electrode and the second back surface electrode each include an insulating resin layer disposed on the back surface and a conductive layer disposed on the insulating resin layer, 9. The electronic circuit device according to claim 7 or 8, wherein the conductive layer is formed of a conductive material containing a binder resin and metal particles dispersed in the binder resin. (Appendix 10) 10. The electronic circuit device according to claim 7, wherein, in the direction, the first end is closer to the center of the insulating substrate by 0.2 mm or more than the second end. (Appendix 11) An electronic circuit device as described in any one of Appendix 7 to Appendix 10, wherein, in the direction, a third end of the second back surface electrode proximate to the center of the insulating substrate is at the same position as a fourth end of the second land pattern proximate to the center of the insulating substrate, or is closer to the center of the insulating substrate than the fourth end. (Appendix 12) 12. The electronic circuit device of claim 11, wherein, in the direction, the third end is closer to the center of the insulating substrate by 0.2 mm or more than the fourth end.

[0096] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0097] 1,1b chip resistor, 2,2b electronic circuit device, 10 insulating substrate, 10c center, 10g division groove, 10s sheet substrate, 11 front surface, 12 back surface, 13 first end surface, 14 second end surface, 15 resistor layer, 16 first resistor layer portion, 16c center, 17 second resistor layer portion, 17c center, 18,19 trimming groove, 20 intermediate electrode, 21 front surface conductive layer, 22 back surface conductive layer, 23 auxiliary electrode layer, 25 first insulating protective layer, 26 second insulating protective layer, 30 first electrode, 31 first front surface electrode, 32 first auxiliary electrode, 33 first back surface electrode, 33e end, 34 first insulating resin layer, 35 first conductive layer, 36 first side electrode, 37 first inner plating film, 38 first outer plating film, 40 second electrode, 41 Second front surface electrode, 42 second auxiliary electrode, 43 second back surface electrode, 43e end portion, 44 second insulating resin layer, 45 second conductive layer, 46 second side electrode, 47 second inner plating film, 48 second outer plating film, 50 circuit board, 51 insulating circuit board, 52, 53 land pattern, 52e, 53e end portion, 54, 55 joining member.

Claims

1. an insulating substrate having a front surface, a back surface opposite to the front surface, a first end surface connected to the front surface and the back surface, and a second end surface opposite to the first end surface; a resistor layer disposed on the front surface; A first electrode connected to the resistor layer; a second electrode connected to the resistor layer; the first end surface and the second end surface are spaced apart from each other in a direction in which the first electrode and the second electrode are spaced apart from each other, the first electrode includes a first back surface electrode disposed on the back surface and electrically connected to the resistor layer; the second electrode includes a second back surface electrode disposed on the back surface and electrically connected to the resistor layer; a ratio of a sum of a first area of ​​the first back surface electrode and a second area of ​​the second back surface electrode to an area of ​​the back surface is 31% or more; A chip resistor, wherein a first length of the first back surface electrode in the said direction and a second length of the second back surface electrode in the said direction are each 0.8 mm or more.

2. The chip resistor according to claim 1 , wherein the ratio is 38% or more.

3. The chip resistor according to claim 1 , wherein the first length and the second length are each equal to or greater than 1.0 mm.

4. A trimming groove is formed in the resistor layer, The chip resistor according to claim 1 , wherein in a plan view of the front surface, the first back surface electrode overlaps the trimming groove.

5. further comprising an intermediate electrode disposed on the front surface; the first electrode includes a first front surface electrode disposed on the front surface; the second electrode includes a second front surface electrode disposed on the front surface; the intermediate electrode is disposed between the first front electrode and the second front electrode, the resistor layer includes a first resistor layer portion connected to the first front electrode and the intermediate electrode, The chip resistor according to claim 1 , wherein, in a plan view of the front surface, the first back surface electrode overlaps with a center of the first resistor layer portion in the direction.

6. the resistor layer includes a second resistor layer portion connected to the second front surface electrode and the intermediate electrode, The chip resistor according to claim 5 , wherein, in the plan view of the front surface, the second back surface electrode overlaps with a center of the second resistor layer portion in the direction.

7. The chip resistor according to claim 1 , a circuit board including a first land pattern and a second land pattern spaced apart from the first land pattern; A first bonding member; A second joining member, the first back surface electrode is joined to the first land pattern by using the first joining member, the second back surface electrode is joined to the second land pattern by using the second joining member, An electronic circuit device, wherein in the direction, a first end of the first back surface electrode proximate to the center of the insulating substrate is at the same position as a second end of the first land pattern proximate to the center of the insulating substrate, or is closer to the center of the insulating substrate than the second end.

8. The electronic circuit device according to claim 7 , wherein a length of the insulating substrate from the first end surface to the second end surface is greater than 3.2 mm.

9. the first back surface electrode and the second back surface electrode each include an insulating resin layer disposed on the back surface and a conductive layer disposed on the insulating resin layer, 8. The electronic circuit device according to claim 7, wherein the conductive layer is formed of a conductive material containing a binder resin and metal particles dispersed in the binder resin.

10. 8. The electronic circuit device according to claim 7, wherein in the direction, the first end is closer to the center of the insulating substrate by 0.2 mm or more than the second end.

11. 8. The electronic circuit device of claim 7, wherein in the direction, a third end of the second back surface electrode proximate to the center of the insulating substrate is at the same position as a fourth end of the second land pattern proximate to the center of the insulating substrate, or is closer to the center of the insulating substrate than the fourth end.

12. The electronic circuit device according to claim 11 , wherein in the direction, the third end is closer to the center of the insulating substrate by 0.2 mm or more than the fourth end.

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