Controller circuit for step-down converter, power supply management circuit, and electronic apparatus

Abstract

To provide a controller circuit for a step-down converter capable of suppressing overcurrent when reducing an output voltage at a constant slope.SOLUTION: A first error amplifier 230 generates a current control signal VERR1 by amplifying an error between a feedback voltage VFB corresponding to an output voltage VOUT of a step-down converter 100 and a first reference voltage VREF1. An NCP circuit 240 clamps the current control signal VERR1, so as not to exceed a clamp level corresponding to a second reference voltage VREF2. A second error amplifier 250 amplifies an error between the current control signal VERR1 and a current detection signal VCS corresponding to a coil current IL of the step-down converter. When decreasing the output voltage VOUT, a digital block 210 initiates decrease of a first reference signal DREF1 with setting a second reference signal DREF2 to a first value d1, then increases the second reference signal DREF2 up to a second value d2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a controller circuit for a step-down converter. [Background technology]

[0002] Many electronic devices use step-down (buck) converters that generate a stabilized voltage at a voltage level suitable for the load. Step-down (buck) converters have a soft-start function that increases the output voltage at a constant rate to suppress inrush current to the output capacitor. A power management circuit (PMIC: Power Management IC) equipped with a multi-channel DC / DC converter can independently raise and lower the output voltage of the DC / DC converter for each channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP2012-114987A

[0004] [overview] The present inventors have come to recognize the following problem when implementing a function for decreasing the output voltage at a constant rate in such a step-down converter.

[0005] In order to reduce the output voltage, it is necessary to discharge the charge from the output capacitor to ground via the inductor and low-side transistor, causing a current to flow in the opposite direction to normal. To suppress this reverse current overcurrent, an NCP (Negative Current Protection) circuit may be installed in the controller circuit of the step-down converter. When the output voltage drops sharply, the NCP circuit comes into action, limiting the reverse current flowing through the inductor and protecting the circuit. However, immediately after the reverse current begins to flow, there is a possibility that an overcurrent will flow through the inductor due to the response delay of the NCP circuit and the effects of parasitic impedance.

[0006] The present disclosure has been made in light of such a situation, and one exemplary purpose of an embodiment of the present disclosure is to provide a controller circuit for a step-down converter that is capable of suppressing an overcurrent that occurs when an output voltage is reduced at a constant slope.

[0007] An embodiment of the present disclosure relates to a controller circuit for a current-mode buck converter. The controller circuit includes a digital block that generates a first reference signal and a second reference signal, a first D / A converter that converts the first reference signal into an analog first reference voltage, a second D / A converter that converts the second reference signal into an analog second reference voltage, a first error amplifier that amplifies an error between a feedback voltage corresponding to an output voltage of the buck converter and the first reference voltage to generate a current control signal, a negative current protection circuit that clamps the current control signal so as not to exceed a clamp level corresponding to the second reference voltage, a second error amplifier that amplifies an error between the current control signal and a current detection signal corresponding to a coil current of the buck converter, and a pulse modulator that generates a pulse signal having a duty cycle corresponding to an output signal of the second error amplifier. When lowering the output voltage, the digital block starts lowering the first reference signal with the second reference signal at a first value, and then raises the second reference signal to a second value.

[0008] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, systems, etc., are also effective as aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a step-down converter including a controller circuit according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration example of the first error amplifier and the NCP circuit. [Diagram 3] FIG. 3 is a diagram illustrating an example of control of the output voltage VOUT. [Figure 4] FIG. 4 is a diagram illustrating another example of control of the output voltage VOUT. [Diagram 5] FIG. 5 is an operational waveform diagram of a conventional step-down converter that takes into consideration the response delay of an NCP circuit. [Figure 6] FIG. 6 is an operational waveform diagram of an NCP circuit in a conventional step-down converter, corresponding to the operation of FIG. [Figure 7] FIG. 7 is an operational waveform diagram of the controller circuit according to the embodiment. [Figure 8] FIG. 8 is an operational waveform diagram (simulation result) of a step-down converter according to an embodiment in which a response delay of an NCP circuit is taken into consideration. [Figure 9] FIG. 9 is an operational waveform diagram (simulation result) of the NCP circuit in the step-down converter according to the embodiment corresponding to the operation of FIG. [Figure 10] FIG. 10 is a waveform diagram of the second reference signal according to the first modification. [Figure 11] FIG. 11 is a waveform diagram of the second reference signal according to the second modification. [Figure 12] FIG. 12 is a waveform diagram of the second reference signal according to the third modification.

[0010] [Detailed Description] (Overview of the embodiment) A summary of some exemplary embodiments of the present disclosure will be described. This summary is intended to provide a simplified overview of some concepts of one or more embodiments for a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not intended to be an exhaustive overview of all possible embodiments, nor is it intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may be used to refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed in this specification.

[0011] A controller circuit according to one embodiment is a controller circuit for a current-mode buck converter. The controller circuit includes a digital block for generating a first reference signal and a second reference signal, a first D / A converter for converting the first reference signal into an analog first reference voltage, a second D / A converter for converting the second reference signal into an analog second reference voltage, a first error amplifier for amplifying an error between a feedback voltage corresponding to an output voltage of the buck converter and the first reference voltage to generate a current control signal, a negative current protection circuit for clamping the current control signal so as not to exceed a clamp level corresponding to the second reference voltage, a second error amplifier for amplifying an error between the current control signal and a current detection signal corresponding to a coil current of the buck converter, and a pulse modulator for generating a pulse signal having a duty cycle corresponding to an output signal of the second error amplifier. When lowering the output voltage, the digital block starts lowering the first reference signal with the second reference signal at a first value, and then raises the second reference signal to a second value.

[0012] When the first reference signal is reduced, the output voltage decreases accordingly. During this time, the negative current protection circuit clamps the coil current flowing through the inductor to a constant amount that corresponds to the second value of the second reference signal, allowing the output voltage to decrease at a constant rate.

[0013] Before the output voltage starts to drop, the current control signal, which is the output of the first error amplifier, is lower than the clamp level, so the negative current protection circuit does not function. After the output voltage starts to drop, when a reverse coil current flows through the inductor, the current control signal rises, and when it reaches the clamp level, the negative current protection circuit begins to function. If the second reference signal was fixed at the second value, after the current control signal reached the clamp level, there is a possibility that the current control signal would exceed the clamp level due to the response delay of the negative current protection circuit, causing an overcurrent to flow.

[0014] In one embodiment, by lowering the second reference signal to a first value lower than the second value before the output voltage starts to drop, even if there is a response delay in the negative current protection circuit, the current control signal can be prevented from significantly exceeding the clamp level corresponding to the second value of the second reference signal, thereby suppressing overcurrent.

[0015] In one embodiment, the digital block may increase the second reference signal in a step-like manner, which allows the waveform of the current control signal to be adjusted based on the step width and the timing of the change, and simplifies the control in the digital block.

[0016] In one embodiment, the digital block may increase the second reference signal in two or more steps.

[0017] In one embodiment, the negative current protection circuit may include a clamping transistor connected between an output node of the first error amplifier and ground, and a third error amplifier having an output node connected to a control electrode of the clamping transistor, a first input node receiving a second reference voltage, and a second input node receiving a voltage of the output node of the first error amplifier.

[0018] The controller circuit according to one embodiment may be integrated on a single semiconductor substrate. "Integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main components of the circuit are integrated on a single substrate, and some resistors and capacitors for adjusting the circuit constants may be provided outside the semiconductor substrate. By integrating the circuit on a single chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0019] The power management circuit according to an embodiment may include any one of the controller circuits described above. An electronic device according to an embodiment may include the power management circuit.

[0020] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and duplicated descriptions will be omitted as appropriate. In addition, the embodiments are illustrative and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0021] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0022] Similarly, "a state in which component C is connected (provided) between components A and B" includes not only the case in which components A and C, or components B and C, are directly connected to each other, but also the case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the functions or effects achieved by their combination.

[0023] FIG. 1 is a circuit diagram of a step-down converter 100 including a controller circuit 200 according to an embodiment. The step-down converter 100 receives an input voltage V IN to the target level V OUT(REF) The output voltage V OUT on output line 104.

[0024] The step-down converter 100 includes a controller circuit 200 and a peripheral circuit 110. The peripheral circuit 110 includes several components externally attached to the controller circuit 200. In this embodiment, the peripheral circuit 110 includes an inductor L1, an output capacitor C1, a first resistor R11, and a second resistor R12. The inductor L1 is connected between a switching pin SW of the controller circuit 200 and an output line 104. The output capacitor C1 is connected between the output line 104 and ground. The first resistor R11 and the second resistor R12 are connected in series between the output line 104 and ground, and the output voltage V OUT The feedback voltage V is proportional to the output voltage VOUT. FB Generates a feedback voltage V FB is input to a feedback pin FB of the controller circuit 200. The first resistor R11 and the second resistor R12 may be built into the controller circuit 200.

[0025] The controller circuit 200 controls the feedback voltage V FB is the first reference voltage V REF1 The switching operation of the step-down converter 100 is controlled so that the output voltage V OUT Target level V OUT(REF) is expressed by the following formula: V OUT(REF) =V REF1 ×(R11+R12) / R12 …(1)

[0026] The controller circuit 200 performs current mode, more specifically, average current mode control. The controller circuit 200 includes a digital block 210, a first D / A converter 220, a second D / A converter 222, a first error amplifier 230, a negative current protection circuit (NCP: Negative Current Protection) 240, a second error amplifier 250, a pulse modulator 260, a driver circuit 270, a current detection circuit 280, a high-side transistor M1, and a low-side transistor M2, and is integrated on one semiconductor substrate (chip).

[0027] The high-side transistor M1 is connected between the input pin VIN and the switching pin SW. The low-side transistor M2 is connected between the switching pin SW and the ground pin GND. The high-side transistor M1 is also called the switching transistor, and the low-side transistor M2 is also called the synchronous rectification transistor.

[0028] The digital block 210 generates a digital first reference signal D REF1 and the second reference signal D REF2 The first reference signal D REF1 is the output voltage V OUT The second reference signal D REF2 is the coil current I L This is a signal that specifies the clamp level of the

[0029] The first D / A converter 220 converts the first reference signal D REF1 The first analog reference voltage V REF1 The second D / A converter 222 converts the second reference signal D REF2 to the second analog reference voltage V REF2 Convert to.

[0030] The first error amplifier 230 is a voltage error amplifier and outputs the output voltage V OUT Feedback voltage V according to FB and the first reference voltage V REF1 The error is amplified to generate a first error signal (hereinafter also referred to as a current control signal) V ERR1 Generates the current control signal V ERR1 is the coil current I flowing through the inductor L1 L The current control signal V ERR1 is the coil current I L When the target amount of is zero, the reference level V 0 Taking the coil current I L When the current flows in the forward direction, that is, toward the output line 104 (to the right in the figure, called the current source mode), the more the current increases, the lower the reference level V 0The coil current I L When the current flows in the reverse direction, that is, toward the switching pin SW (to the left in the figure, called current sink mode), the reference level V 0 It will be higher.

[0031] The current detection circuit 280 detects the coil current I L The current detection signal V CS The circuit type of the current detection circuit 280 and the position of the current detection are not particularly limited. For example, the current detection circuit 280 may include a current sense amplifier that amplifies the voltage drop of a sense resistor (not shown in FIG. 1) that is connected in series with the inductor L1. Alternatively, the current detection circuit 280 generates the current detection signal V based on any one of the voltage of the switching pin SW, the voltage across the low-side transistor M2, and the voltage across the high-side transistor M1, or a combination of these. CS The current detection circuit 280 may be built into the controller circuit 200 or may be external to the controller circuit 200.

[0032] The second error amplifier 250 is a current error amplifier and receives the current control signal V ERR1 and the current detection signal V CS The error is amplified to produce a second error signal V ERR2 Generate.

[0033] The pulse modulator 260 converts the output signal V ERR2 A pulse signal S having a duty cycle according to P The configuration of the pulse modulator 260 is not particularly limited, and can be configured using known technology. For example, the pulse modulator 260 may include an oscillator that generates a periodic signal of a triangular wave or a sawtooth wave, and a second error signal V ERR2 and a comparator for comparing

[0034] The NCP circuit 240 receives the current control signal V ERR1 , the second reference voltage V REF2 Clamp level V according to CLAMPThe second reference voltage V is clamped so that the NCP circuit 240 operates in a current sink mode. REF2 is the reference level V 0 It is set higher.

[0035] 2 is a circuit diagram showing a configuration example of the first error amplifier 230 and the NCP circuit 240. The first error amplifier 230 includes a transconductance amplifier 232, and a resistor R21 and a capacitor C21 for phase compensation.

[0036] The NCP circuit 240 includes an operational amplifier 242, a clamping transistor 244, and a capacitor C22. The transistor 244 is connected between the output of the first error amplifier 230 and ground. The operational amplifier 242 and the transistor 244 configure a buffer (voltage follower), and the output V ERR1 is the second reference voltage V REF2 Here, since the NCP circuit 240 is an open-drain type, it only has a current sink capability and does not have a current source capability. ERR1 Therefore, the NCP circuit 240 can reduce the output V of the first error amplifier 230, but cannot increase it. ERR , the second reference voltage V REF2 Clamp level V equal to CLAMP Clamp so as not to exceed V ERR1 ≦V CLAMP

[0037] The configuration of the clamp circuit, NCP circuit 240, is not limited to that shown in FIG. 2, and various known clamp circuits can be used. CLAMP and the second reference voltage V REF2 It will be appreciated that the relationship between is determined by the configuration of the clamp circuit, and they are not necessarily equal.

[0038] The digital block 210 receives a first reference signal D REF1By controlling the waveform of the output voltage V OUT Controls the waveform of the signal.

[0039] Figure 3 shows the output voltage V OUT 1 is a diagram illustrating an example of control of the first reference signal D. REF1 Set the initial value D X to the final value D Y Towards t 0 ~t 1 The transition period τ 1 By decreasing the output voltage V OUT At this time, the output voltage V OUT is the initial value D X The voltage level V X From the final value D Y The voltage level V Y ΔV=V X -V Y Then, the output voltage V OUT The slope of dV OUT / dt=ΔV / τ 1 With this slope, the output voltage V OUT To change the output, a constant coil current I L The charge must be discharged at this time. The coil current I L Amount of I L1 teeth, I L1 =C ΔV / τ 1 It is. L1 NCP When the NCP circuit 240 is not activated, the output voltage V OUT is the first reference signal D REF1 It changes according to.

[0040] Figure 4 shows the output voltage V OUT FIG. 2 is a diagram illustrating another example of the control of the first reference signal D. REF1 Set the initial value D X to the final value D Y Towards t 0 ~t​1 The transition period τ 2 (where τ 2 <τ 1 ) at a constant rate. REF1 The output voltage V OUT The coil current I required to change L teeth, I L2 =C ΔV / τ 2 The current flow is larger than that in the case of FIG. L2 >I NCP When the NCP circuit 240 is enabled, the coil current I L I NCP The coil current I L When the output voltage V OUT The rate of change of is dV OUT / dt=I NCP / C The threshold value I NCP (That is, the second reference signal D REF2 ) is determined by

[0041] The above is the output voltage V OUT and the operation of the NCP circuit 240.

[0042] Next, problems that occur in the NCP circuit 240 will be described based on the results of a simulation.

[0043] Fig. 5 is a waveform diagram (simulation result) of a conventional step-down converter that takes into account the response delay of the NCP circuit. In Fig. 4, an ideal state in which there is no delay in the NCP circuit 240 is assumed, but in reality, the NCP circuit 240 has a response delay. Fig. 5 shows the coil current I L , switching voltage V SW , output voltage V OUT is shown.

[0044] Time t in Figure 5 0 is the time t in Fig. 4. 0In an actual circuit, the negative coil current I L Time t when the flow starts 0 Immediately after this, the coil current I L is the NCP threshold I NCP Then, the threshold I NCP In other words, a temporary overcurrent state occurs.

[0045] 6 is a waveform diagram (simulation result) of the operation of the NCP circuit 240 in the conventional step-down converter corresponding to the operation of FIG. 5. In FIG. 6, the coil current I L , output voltage V OUT , the second reference voltage V REF2 , the error signal V ERR1 , current detection signal V CS is shown.

[0046] time t 0 Before the error signal V ERR is the reference level V 0 The second reference voltage V REF2 After rising, ideally, the error signal V ERR1 is the second reference voltage V REF2 Clamp level V equal to CLAMP However, in reality, due to a response delay of the NCP circuit 240, the error signal V ERR1 is the clamp level V CLAMP After exceeding the clamp level V CLAMP It converges to.

[0047] The second error amplifier 250 and the pulse modulator 260 generate the current detection voltage V CS is the error signal V ERR1 In other words, the error signal V ERR1 is the clamp level V CLAMP During the period when the current detection signal V CS is the clamp level V CLAMP The buck converter 100 operates to approach a higher voltage level. As a result, the coil current IL is the NCP threshold I NCP , resulting in a temporary overcurrent condition.

[0048] In order to suppress this overcurrent, the digital block 210 generates a first reference signal D REF1 The waveform of the output voltage V OUT When lowering the second reference signal D REF2 By dynamically changing the clamp level V CLAMP Dynamically control.

[0049] Specifically, the digital block 210 generates a second reference signal D REF2 is changed between a first value d1 and a second value d2. REF2 The second value d2 of the NCP threshold I NCP The first value d1 is set to be smaller than the second value d2.

[0050] The digital block 210 generates a second reference signal D REF2 With the first value d1 set, the first reference signal D REF1 Then, the digital block 210 starts to drop the first reference signal D REF1 During the fall of the second reference signal D REF2 to a second value d2. That is, the first reference signal D REF1 Immediately after the second reference signal D REF2 is a first value d1 which is smaller than the second value d2.

[0051] For example, digital block 210 includes an output voltage V OUT In response to the assertion of the trigger signal TRIG, the digital block 210 generates a second reference signal D REF2 is set to a first value d1. Then, for a predetermined time T 1 After the lapse of time, the first reference signal D REF1 The digital block 210 starts to drop the first reference signal D REF1During the fall of the second reference signal D REF2 is returned to the second value d2.

[0052] The above is the configuration of the controller circuit 200. Next, the operation of the controller circuit 200 will be described.

[0053] FIG. 7 is an operational waveform diagram of the controller circuit 200 according to the embodiment.

[0054] time t 0 Prior to this, the buck converter 100 is operating in light load mode, and the inductor current I L is assumed to be 0A.

[0055] The digital block 210 is 0 In response to the trigger signal TRIG, a second reference signal D REF2 The first value d 1 Then, the first time T 1 At time t after 1 , the second reference signal D REF1 begins to decrease at time t 1 From the second hour T 2 At time t after 2 , the second reference signal D REF2 changes to a second value d2.

[0056] The second reference signal D provided to the NCP circuit 240 REF2 By appropriately controlling the waveform of the coil current I L is the NCP threshold I NCP without significantly exceeding the threshold I NCP The output voltage V OUT is the NCP threshold I NCP At time t 3 , the first reference signal D REF1 D Y At time t 4 , the output voltage V OUT But, D Y Target level V corresponding to Y When the coil current drops to I L becomes zero and the transition is completed.

[0057] 8 is an operational waveform diagram (simulation result) of the step-down converter 100 according to the embodiment in which the response delay of the NCP circuit is taken into consideration. In FIG. 8, the coil current I L , switching voltage V SW , output voltage V OUT is shown.

[0058] Time t in Fig. 8 1 is the time t in Fig. 7. 1 In Figure 5, the coil current I L is the NCP threshold I NCP However, according to the step-down converter 100 according to the embodiment, the coil current I L It can be seen that the overcurrent can be suppressed.

[0059] 9 is an operational waveform diagram (simulation result) of the NCP circuit 240 in the step-down converter according to the embodiment corresponding to the operation of FIG. 8. In FIG. 9, the coil current I L , output voltage V OUT , the second reference voltage V REF2 , the error signal V ERR1 , current detection signal V CS In this example, the first time T 1 =1μs, second time T 2 = 4μs.

[0060] time t 1 , the second reference signal D REF2 is set to a first value d1, whereby the second reference voltage V REF2 rises to a voltage level corresponding to the first value d1 (1 V in this example). 1 to the reference voltage V REF1 When begins to decrease, the error signal V ERR1 rises, but the NCP circuit 240 keeps the second reference voltage V REF2 (=1V). Then, the second error amplifier 250 outputs the current detection signal V CS is the error signal V ERR2The step-down converter 100 switches so that the input voltage Vout approaches Vout.

[0061] time t 2 , the second reference signal D REF2 is set to a second value d2, whereby the second reference voltage V REF2 is the clamp level V corresponding to the second value d2. CLAMP (1.16V in this example). This causes the error signal V ERR1 Also, clamp level V CLAMP Then, the second error amplifier 250 outputs the current detection signal V CS is the error signal V ERR2 (That is, clamp level V CLAMP The step-down converter 100 switches so that the inductor current I L is the NCP threshold I NCP is stabilized to.

[0062] In this manner, in the step-down converter 100 according to the embodiment, the second reference voltage V REF2 This causes the error signal V ERR2 The error signal V ERR2 The overshoot of the error signal V ERR2 As a result, the overshoot of the coil current I L This can suppress overshoot.

[0063] (Modification) Second reference signal D REF2 The waveforms are not limited to those shown in FIGS.

[0064] FIG. 10 shows the second reference signal D REF2 In the embodiment, the second reference signal D changes from the first value d1 to the second value d2 in one step, but it may change in two or more steps. REF2 increases from the first value d1 to the second value d2 in three steps.

[0065] FIG. 11 shows a second reference signal D REF2 In this modification 2, the second reference signal D REF2 increases continuously in a straight line from the first value d1 to the second value d2.

[0066] FIG. 12 shows the second reference signal D REF2 In this modification 3, the second reference signal D REF2 rises according to a predetermined curve.

[0067] Second reference signal D REF2 The timing at which the trigger signal TRIG changes to the second value d2 does not have to be simultaneous with the transition of the trigger signal TRIG, and may be a predetermined time after the transition of the trigger signal TRIG.

[0068] Second reference signal D REF2 The waveform of the error signal V is not limited to that shown here, and may be determined according to the response speed of the NCP circuit 240. ERR2 is the second reference voltage V REF2 Clamp level V CLAMP It should be set so as not to exceed.

[0069] Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to aid in understanding and does not limit the scope of the present disclosure or the claims, and the scope of the present invention is defined by the claims. In addition, not only the embodiments, but also embodiments, examples, and modified examples not described herein are included in the scope of the present invention.

[0070] (Additional Note) One aspect of the technology disclosed in this specification can be understood as follows.

[0071] (Item 1) 1. A controller circuit for a current mode buck converter, comprising: a digital block for generating a first reference signal and a second reference signal; a first D / A converter for converting the first reference signal into an analog first reference voltage; a second D / A converter for converting the second reference signal into an analog second reference voltage; a first error amplifier that amplifies an error between a feedback voltage corresponding to an output voltage of the step-down converter and the first reference voltage and generates a current control signal; a negative current protection circuit that clamps the current control signal so that it does not exceed a clamp level corresponding to the second reference voltage; a second error amplifier that amplifies an error between the current control signal and a current detection signal corresponding to a coil current of the step-down converter; a pulse modulator that generates a pulse signal having a duty cycle corresponding to an output signal of the second error amplifier; Equipped with The controller circuit, when lowering the output voltage, causes the digital block to start lowering the first reference signal with the second reference signal at a first value, and then causes the second reference signal to rise to a second value.

[0072] (Item 2) 2. The controller circuit of claim 1, wherein the digital block sets the second reference signal to the second value in response to a trigger signal indicating that the output voltage should start to drop, and then starts to drop the first reference signal.

[0073] (Item 3) 2. The controller circuit of claim 1, wherein the digital block increases the second reference signal in a step-like manner.

[0074] (Item 4) 3. The controller circuit of item 2, wherein the digital block increases the second reference signal in two or more steps.

[0075] (Item 5) The negative current protection circuit includes: a clamping transistor connected between an output node of the first error amplifier and ground; a third error amplifier having an output node connected to a control electrode of the clamp transistor, receiving the second reference voltage at a first input node, and receiving a voltage of an output node of the first error amplifier at a second input node; 5. A controller circuit according to any one of items 1 to 4, comprising:

[0076] (Item 6) 6. A controller circuit according to any one of items 1 to 5, integrated on a single semiconductor substrate.

[0077] (Item 7) 7. A power management circuit comprising a controller circuit according to any one of items 1 to 6.

[0078] (Item 8) 8. An electronic device comprising the power management circuit according to item 7. [Explanation of symbols]

[0079] 100 Buck Converter 102 input lines 104 Output Line 110 Peripheral circuits C1 Output capacitor L1 Inductor M1 High-side transistor M2 Low-side transistor R11 1st resistor R12 Second resistor 200 Controller Circuit 210 Digital Block 220 1st D / A converter 222 2nd D / A converter 230 First error amplifier 240 NCP circuit 242 Operational Amplifier 244 Transistor 250 Second Error Amplifier 260 Pulse Modulator 270 Driver Circuit 280 Current Detection Circuit

Claims

1. 1. A controller circuit for a current mode buck converter, comprising: a digital block for generating a first reference signal and a second reference signal; a first D / A converter for converting the first reference signal into an analog first reference voltage; a second D / A converter for converting the second reference signal into an analog second reference voltage; a first error amplifier that amplifies an error between a feedback voltage corresponding to an output voltage of the step-down converter and the first reference voltage and generates a current control signal; a negative current protection circuit that clamps the current control signal so that it does not exceed a clamp level corresponding to the second reference voltage; a second error amplifier that amplifies an error between the current control signal and a current detection signal corresponding to a coil current of the step-down converter; a pulse modulator that generates a pulse signal having a duty cycle corresponding to an output signal of the second error amplifier; Equipped with A controller circuit in which, when lowering the output voltage, the digital block starts lowering the first reference signal with the second reference signal at a first value, and then raises the second reference signal to a second value.

2. 2. The controller circuit of claim 1, wherein the digital block is responsive to a trigger signal indicating that the output voltage should start to drop to set the second reference signal to the second value and then cause the first reference signal to start to drop.

3. The controller circuit of claim 1 , wherein the digital block increases the second reference signal in a stepwise manner.

4. The controller circuit of claim 2 , wherein the digital block increases the second reference signal in two or more steps.

5. The negative current protection circuit includes: a clamping transistor connected between an output node of the first error amplifier and ground; a third error amplifier having an output node connected to the control electrode of the clamp transistor, receiving the second reference voltage at a first input node, and receiving a voltage of an output node of the first error amplifier at a second input node; A controller circuit as claimed in any preceding claim, comprising:

6. 5. The controller circuit according to claim 1, which is integrated on a single semiconductor substrate.

7. A power management circuit comprising a controller circuit according to any one of claims 1 to 4.

8. An electronic device comprising the power management circuit according to claim 7.

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