Printed circuit board and method for manufacturing printed circuit board

Abstract

To provide a printed circuit board and a method for manufacturing a printed circuit board that includes a glass layer, improves flatness, prevents warpage, and improves reliability.SOLUTION: The present disclosure relates to a printed circuit board which has a first insulating layer, a first wiring layer embedded on one side of the first insulating layer, a glass layer located on the other side opposite one side of the first insulating layer, a second wiring layer placed on the glass layer, and a first via layer that connects the first insulating layer and the second wiring layer to each other and includes a first via section through the glass layer and a second via section through the first insulating layer, and has one or more of the first and second via sections in a shape that substantially narrows in width as it moves toward the first wiring layer in cross-section.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to printed circuit boards and methods for manufacturing printed circuit boards. [Background technology]

[0002] Recently, with the development of artificial intelligence (AI) technology, etc., multi-chip packages including memory chips such as HBM (High Bandwidth Memory) for data processing that has increased exponentially, and processor chips such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), etc. are being used. Therefore, there is a demand for substrates having large area structures, and efforts are being made to overcome problems related to flatness and warpage control. Summary of the Invention [Problem to be solved by the invention]

[0003] One of several objects of the present disclosure is to provide a printed circuit board that includes a glass layer and a method for making the printed circuit board.

[0004] Another of several objects of the present disclosure is to provide a printed circuit board and a method for manufacturing the printed circuit board that can improve flatness and prevent warping.

[0005] Another of several objectives of the present disclosure is to provide a printed circuit board and a method for manufacturing a printed circuit board that can improve reliability. [Means for solving the problem]

[0006] One of the various solutions proposed through the present disclosure is to provide a printed circuit board including a first insulating layer, a first wiring layer embedded in one side of the first insulating layer, a glass layer arranged on the other side opposite to the one side of the first insulating layer, a second wiring layer arranged on the glass layer, and a first via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion that penetrates the glass layer and a second via portion that penetrates the first insulating layer, wherein, in cross section, one or more of the first via portion and the second via portion have a shape that substantially narrows in width toward the first wiring layer.

[0007] Another of the various solutions proposed through the present disclosure is to provide a printed circuit board including an insulating layer, a first wiring layer disposed on one side of the insulating layer, a glass layer disposed on the other side opposite the one side of the insulating layer, a first through hole penetrating the insulating layer to expose at least a portion of the first wiring layer, a second through hole penetrating the glass layer and connected to the first through hole, a first metal layer disposed on at least the exposed portion of the first wiring layer and on each of the wall surfaces of the first and second through holes, and a via layer including a second metal layer disposed on the first metal layer and filling at least a portion of each of the first and second through holes, and a second wiring layer disposed on the glass layer and connected to the via layer.

[0008] Another of the various solutions proposed through the present disclosure is to provide a method for manufacturing a printed circuit board, including the steps of forming a first insulating layer in which a first wiring layer is embedded, forming a glass layer on the first insulating layer, forming a first through hole penetrating the glass layer, forming a second through hole penetrating the first insulating layer to expose at least a portion of the first wiring layer, forming a first via layer in the first through hole and the second through hole, and forming a second wiring layer on the first insulating layer, connected to the first via layer. Effect of the Invention

[0009] Among other advantages, the present disclosure may provide a printed circuit board including a glass layer and a method for making the printed circuit board.

[0010] Another advantage of the present disclosure, among other advantages, is that it is possible to provide a printed circuit board and a method for manufacturing a printed circuit board that can improve flatness and prevent warping.

[0011] Another advantage of the present disclosure, among other advantages, is that it is possible to provide a printed circuit board and a method for manufacturing a printed circuit board that can improve reliability. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] 1 is a cross-sectional view showing a schematic view of a portion of a printed circuit board according to a first embodiment. [Figure 4a] 1A to 1C are cross-sectional views each showing a schematic view of a part of a method for manufacturing a printed circuit board according to a first embodiment. [Figure 4b] 1A to 1C are cross-sectional views each showing a schematic view of a part of a method for manufacturing a printed circuit board according to a first embodiment. [Figure 4c] 1A to 1C are cross-sectional views each showing a schematic view of a part of a method for manufacturing a printed circuit board according to a first embodiment. [Figure 5a] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5b] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5c] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5d] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5e]10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5f] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5g] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5h] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5i] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5j] 10A to 10C are cross-sectional views each showing a schematic diagram of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first to tenth modified examples of the first embodiment. [Figure 5k] 5i and 5j are top plan views of a part of a method for manufacturing a printed circuit board according to ninth and tenth modified examples of the first embodiment. FIG. [Figure 6] FIG. 11 is a cross-sectional view showing a schematic view of a portion of a printed circuit board according to a second embodiment. [Figure 7a] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a printed circuit board according to a second embodiment. [Figure 7b] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a printed circuit board according to a second embodiment. [Figure 7c] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a printed circuit board according to a second embodiment. [Figure 8] 13A to 13C are cross-sectional views each showing a schematic view of a printed circuit board according to a first modified example of the second embodiment and a part of a method for manufacturing the printed circuit board. [Figure 9] FIG. 11 is a cross-sectional view showing a schematic view of a portion of a printed circuit board according to a third embodiment. [Figure 10a] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a printed circuit board according to a third embodiment. [Figure 10b] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a printed circuit board according to a third embodiment. [Figure 10c] 10A to 10C are cross-sectional views each showing a schematic diagram of a part of a method for manufacturing a printed circuit board according to a third embodiment. [Figure 11a] 13A to 13C are cross-sectional views each showing a schematic view of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first and second modified examples of the third embodiment. [Figure 11b] 13A to 13C are cross-sectional views each showing a schematic view of a printed circuit board and a part of a method for manufacturing the printed circuit board according to first and second modified examples of the third embodiment. [Figure 12a] 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to a first application example to a fifth application example of the first embodiment. FIG. [Figure 12b] 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to a first application example to a fifth application example of the first embodiment. FIG. [Figure 12c] 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to a first application example to a fifth application example of the first embodiment. FIG. [Figure 12d] 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to a first application example to a fifth application example of the first embodiment. FIG. [Figure 12e] 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to a first application example to a fifth application example of the first embodiment. FIG. [Figure 13a] 12b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a first application example of the first embodiment of FIG. 12a. [Figure 13b] 12b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a first application example of the first embodiment of FIG. 12a. [Figure 13c] 12b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a first application example of the first embodiment of FIG. 12a. [Figure 13d] 12b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a first application example of the first embodiment of FIG. 12a. [Figure 14a] 12b , which is a cross-sectional view showing a schematic diagram of a method for manufacturing a printed circuit board according to a second application example of the first embodiment of FIG. 12b . [Figure 14b] 12b , which is a cross-sectional view showing a schematic diagram of a method for manufacturing a printed circuit board according to a second application example of the first embodiment of FIG. 12b . [Figure 14c] 12b , which is a cross-sectional view showing a schematic diagram of a method for manufacturing a printed circuit board according to a second application example of the first embodiment of FIG. 12b . [Figure 14d] 12b , which is a cross-sectional view showing a schematic diagram of a method for manufacturing a printed circuit board according to a second application example of the first embodiment of FIG. 12b . [Figure 15a] 11A to 11C are cross-sectional views each showing a schematic configuration of a printed circuit board according to a sixth application example to a seventh application example of the first embodiment. [Figure 15b] 11A to 11C are cross-sectional views each showing a schematic configuration of a printed circuit board according to a sixth application example to a seventh application example of the first embodiment. [Figure 16a] 15b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a sixth application example of the first embodiment of FIG. 15a. FIG. [Figure 16b] 15b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a sixth application example of the first embodiment of FIG. 15a. FIG. [Figure 16c] 15b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a sixth application example of the first embodiment of FIG. 15a. FIG. [Figure 16d] 15b is a cross-sectional view illustrating a method for manufacturing a printed circuit board according to a sixth application example of the first embodiment of FIG. 15a. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for a clearer description.

[0014] [Electronic equipment] FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0015] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also coupled to other electronic components described below to form various signal lines 1090.

[0016] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). In addition, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0017] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (such as the IEEE 802.11 family), WiMAX (such as the IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, and may include any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020 together.

[0018] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may include passive elements in the form of chip components used for various other applications. In addition, the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0019] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0020] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0021] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0022] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built in. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0023] [Printed circuit board and method for manufacturing printed circuit board] Fig. 3 is a cross-sectional view that shows a schematic view of a part of the printed circuit board according to Example 1. Specifically, Fig. 3 is a cross-sectional view that shows the insulating structure between the first wiring layer 121 and the second wiring layer 122 of the part of the printed circuit board according to Example 1.

[0024] 3, the printed circuit board according to the first embodiment may include a first insulating layer 111, a first wiring layer 121 embedded in one side of the first insulating layer 111, a glass layer 110 disposed on the other side opposite to the one side of the first insulating layer 111, a second wiring layer 122 disposed on the glass layer 110, and a first via layer 130 connecting the first wiring layer 121 and the second wiring layer 122 to each other and including a first via portion 131 penetrating the glass layer 110 and a second via portion 132 penetrating the first insulating layer 111. The first via layer 130 may include a seed layer 125 and a plating layer 126.

[0025] The printed circuit board according to the first embodiment may include a first insulating layer 111 and a glass layer 110 between the first wiring layer 121 and the second wiring layer 122. That is, the insulating structure between the first wiring layer 121 and the second wiring layer 122 of the printed circuit board according to the first embodiment may include glass 110 rather than being composed of only a single layer or only an organic insulating layer. Since the insulating structure between the first wiring layer 121 and the second wiring layer 122 may include the glass layer 110, the printed circuit board may have excellent flatness and may be resistant to warpage during the manufacturing process.

[0026] The printed circuit board according to the first embodiment may include the glass layer 110 and the first insulating layer 111 as build-up layers, rather than using the glass layer 110 as a core. Therefore, FIG. 3 shows only a part of the printed circuit board according to the first embodiment, and other build-up insulating layers may be further disposed on the upper and lower sides of FIG. 3, or a core layer may be further disposed on the lower side, or a solder resist layer may be disposed on the lower side, so that the first wiring layer 121 becomes the outermost part of the printed circuit board, and a so-called coreless type printed circuit board having an embedded pattern may be formed. FIG. 3 shows only an insulating structure between the first wiring layer 121 and the second wiring layer 122 and an interlayer connection using the first via layer 130, and modifications thereto, other embodiments, and various application examples of the printed circuit board will be described later with reference to other drawings.

[0027] The first insulating layer 111 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The insulating material may also include an adhesive sheet such as BS (Bonding Sheet). Specifically, the first insulating layer 111 may preferably include ABF (Ajinomoto Build-up Film), but is not limited thereto, and may also include other organic insulating materials. In addition, in FIG. 3, the first insulating layer 111 is shown as being a single insulating layer, but this is not necessarily limited to this and may include further configurations that can be used by a person having ordinary skill in the art, such as being composed of multiple insulating layers as necessary.

[0028] The first wiring layer 121 may be embedded in one side of the first insulating layer 111. That is, the first wiring layer 121 may be disposed on one side of the first insulating layer 111, and one surface of the first wiring layer 121 may be exposed from one surface of the first insulating layer 111. In this case, the fact that one surface of the first wiring layer 121 is exposed from one surface of the first insulating layer 111 means that one surface of the first wiring layer 121 is not covered by the first insulating layer 111, and it may be understood in the same sense that one surface of the first wiring layer 121 is covered by another configuration by further including another configuration under the first insulating layer 111. That is, it means that one surface of the first wiring layer 121 is not covered by the first insulating layer 111, and the other surface facing the one surface of the first wiring layer 121 and the side surface of the first wiring layer 121 may be covered by the first insulating layer 111. At this time, unless other adhesive means or the like is further included between the first wiring layer 121 and the first insulating layer 111, the other surface and side surfaces of the first wiring layer 121 can contact the first insulating layer 111.

[0029] The first wiring layer 121 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the first wiring layer 121 may include copper (Cu), but is not limited thereto.

[0030] The first wiring layer 121 may perform various functions according to the design. For example, it may include a signal pattern, a power pattern, a ground pattern, etc. Each of these patterns may have various forms such as a line, a plane, a pad, etc. The first wiring layer 121 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Or, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Or, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). It may also include a sputtering layer instead of the electroless plating layer (or chemical copper), or it may include both as necessary.

[0031] The first wiring layer 121 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), and subtractive methods, but is not limited thereto, and any method capable of forming a circuit on a printed circuit board may be used without limitation. Also, the first wiring layer 121 may be formed by different methods depending on the application, design, and the like.

[0032] The glass layer 110 can include glass, which is an amorphous solid. Glass can be, for example, pure silicon dioxide (about 100% SiO 2 Glass layer 110 may include, but is not limited to, alternative glass materials such as fluoroglass, phosphate glass, chalcogenide glass, etc., which may be used as the material of glass layer 110. In addition, other additives may be included to form glass having specific physical properties. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of such elements and other elements. Glass layer 110 is a layer that is distinct from materials including glass fibers (glass fiber, glass cloth, glass fabric), such as copper clad laminate (CCL) and prepreg (PPG), and may be understood as, for example, a glass sheet or a glass sheet.

[0033] Since the printed circuit board according to the first embodiment includes the glass layer 110, it can have excellent flatness and can be advantageous in warpage control through a low coefficient of thermal expansion (CTE). In particular, since the printed circuit board according to the first embodiment can have the glass layer 110 as a part of the build-up layer, it can be advantageous in warpage control even in a step of laminating other insulating layers thereafter. That is, even if other insulating layers are sequentially laminated on the glass layer 110, it can be advantageous in forming a high-density fine circuit having a fine pitch. In particular, unlike the case where the glass layer 110 is used as a core layer, the glass layer 110 can be included in a coreless type substrate, which can be advantageous in controlling warpage characteristics, which are a problem of the coreless type, and the reliability can be improved by controlling the warpage characteristics of the core type substrate to realize an asymmetric substrate.

[0034] In addition, the glass layer 110 can reduce the number of layers of a printed circuit board through the characteristics of glass having variable dielectric properties, for example, Dk2.5 to 11, thereby increasing the degree of freedom in design.

[0035] A second wiring layer 122 may be included on the glass layer 110. The second wiring layer 122 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal may include copper (Cu), but is not limited thereto.

[0036] The second wiring layer 122 may perform various functions depending on the design. For example, it may include a signal pattern, a power pattern, a ground pattern, etc. These patterns may have various forms such as a line, a plane, a pad, etc. The second wiring layer 122 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, it may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). It may also include a sputtering layer instead of the electroless plating layer (or chemical copper), or it may include both as necessary.

[0037] The second wiring layer 122 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), or subtractive methods, but is not limited thereto, and any method capable of forming a circuit on a printed circuit board may be used without limitation. The second wiring layer 122 may also be formed by different methods depending on the application, design, etc. Meanwhile, the second wiring layer 122 may be formed simultaneously with the first via layer 130, but is not limited thereto.

[0038] The first via layer 130 connects between the first wiring layer 121 and the second wiring layer 122, and may penetrate at least a portion of each of the first insulating layer 111 and the glass layer 110. The first via layer 130 may include a first via portion 131 penetrating the glass layer 110 and a second via portion 132 penetrating the first insulating layer 111. That is, the first via layer 130 may be formed to fill a through hole penetrating the first insulating layer 111 and a through hole penetrating the glass layer 110, respectively, and the first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating the first insulating layer 111 may be integrally formed.

[0039] The first via layer 130 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal may include copper (Cu), but is not limited thereto. The first via layer 130 may include a filled via that fills a via hole, but may also include a conformal via that is disposed along the wall surface of the via hole. The first via layer 130 may each perform various functions according to the design. For example, the first via layer 130 may include a ground via, a power via, a signal via, and the like.

[0040] The first via layer 130 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). It may also include a sputtering layer instead of the electroless plating layer (or chemical copper), or may include both if necessary. More specifically, the first via layer 130 may include a seed layer 125 and a plating layer 126 disposed on the seed layer 125.

[0041] The seed layer 125 may include, but is not limited to, an electroless plating layer (or chemical copper), and may include a sputtering layer. The seed layer 125 may include, but is not limited to, copper (Cu) as shown in FIG. 3, and may be composed of a plurality of metal layers. For example, when the seed layer 125 includes a sputtering layer, the seed layer may further include a metal layer including titanium (Ti). Since the seed layer 125 is formed to contact the glass layer 110, when the seed layer 125 includes a sputtering layer, the adhesion with the glass layer 110 can be more secure, but is not necessarily limited thereto. Meanwhile, the seed layer 125 may be made of any material that can function as a plating lead wire for electroplating, in addition to the above-mentioned metals, and may be made of, for example, an inorganic carbon-based conductive material, an organic carbon-based conductive material, or the like.

[0042] The seed layer 125 may be conformally disposed along the inner walls of the first through hole formed in the glass layer 110 and the second through hole formed in the first insulating layer 111. That is, the seed layer 125 may be in contact with the glass layer 110 and the first insulating layer 111, and may also be in contact with the first wiring layer 121. The seed layer 125 may be disposed at the boundary with the glass layer 110 and extend to the boundary with the first insulating layer 111 and the boundary with the first wiring layer 121. The seed layer 125 may also extend to the upper side of the glass layer 110 and function as a seed layer for the second wiring layer 122.

[0043] The plating layer 126 may include an electrolytic plating layer (or electrolytic copper), and may be formed by performing electrolytic plating using the seed layer 125 as a plating lead wire. The plating layer 126 may include, but is not limited to, copper (Cu), and may include the metal of the first via layer 130. The plating layer 126 may be disposed on the seed layer 125, and may fill a first through hole penetrating the glass layer 110 and a second through hole penetrating the first insulating layer 111.

[0044] Meanwhile, the step of forming the seed layer 125 and the step of forming the plating layer 126 may each be performed once, so that the first via portion 131 and the second via portion 132 of the first via layer 130 may be integrally formed. This means that the seed layer 125 formed in the first via portion 131 may extend to the second via portion 132 and the plating layer 126 formed in the first via portion 131 may extend to the second via portion 132, since the boundary between the first via portion 131 and the second via portion 132 of the first via layer 130 may not be recognized, and a boundary may be recognized between the plating layer 126 and the seed layer 125. In other words, the fact that the first via portion 131 and the second via portion 132 of the first via layer 130 are integrally formed is in contrast to the fact that the first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating the first insulating layer 111 are formed and then bonded, and means that the first via layer 130 may be integrally formed in a series of processes. At this time, the first via layer 130 and the second wiring layer 122 may be integral with each other. This may be the result of the second wiring layer 122 being formed during the step of forming the first via layer 130.

[0045] The first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating the first insulating layer 111 may have different widths. Also, the first via portion 131 and the second via portion 132 may each have a so-called tapered shape in which the width narrows toward the first wiring layer 121. The width and shape of the first via portion 131 and the second via portion 132 of the first via layer 130 may be measured and confirmed by photographing a cross section of the first via layer 130 cut in the stacking direction of the printed circuit board so as to pass through the central axis of the first via layer 130 using a scanning microscope or the like.

[0046] At the interface between the first insulating layer 111 and the glass layer 110, the width of the second via portion 132 may be narrower than the width of the first via portion 131. The interface between the first insulating layer 111 and the glass layer 110 may be identified as the boundary between the first insulating layer 111 and the glass layer 110 on a cross section, and the width of the second via portion 132 located on an extension line of this boundary line may be compared with the width of the first via portion 131. That is, referring to FIG. 3, the width at the top of the second via portion 132 may be narrower than the width at the bottom of the first via portion 131. This may be a result of forming a second through hole penetrating the first insulating layer 111 after forming a first through hole penetrating the glass layer 110 in a method for manufacturing a printed circuit board. After forming the first through hole penetrating the glass layer 110, the second through hole penetrating the first insulating layer 111 may be formed to have a width smaller than the first through hole. However, this is not necessarily limited thereto, and the width of the second via portion 132 may be substantially the same as the width of the first via portion 131 at the interface between the first insulating layer 111 and the glass layer 110. This means that when a second through hole penetrating the first insulating layer 111 is formed after the first through hole penetrating the glass layer 110 is formed, the glass layer 110 can function as a mask for the second through hole.

[0047] At the interface between the glass layer 110 and the second wiring layer 122, the width of the first via portion 131 may be narrower than the width of the second wiring layer 122. This is because, while the first via layer 130 and the second wiring layer 122 are formed, the second wiring layer 122 functions as a land of the first via layer 130 and may be formed to be wider than the width of the first via layer 130. Meanwhile, the width of the first via portion 131 of the first via layer 130 is not narrower than the width of all the wirings of the second wiring layer 122, but the width of the second wiring layer 122 directly connected to the first via layer 130 may be wider than the width of the first via portion 131 of the first via layer 130.

[0048] In the cross section, the first via portion 131 may have a shape in which the width narrows toward the first wiring layer 121, and the second via portion 132 may have a shape in which the width narrows toward the first wiring layer 121. The first via portion 131 and the second via portion 132 may have a shape in which the width narrows in substantially the same direction. This is a result of forming a glass layer 110 on the first insulating layer 111, forming a first through hole penetrating the glass layer 110, and then forming a second through hole penetrating the first insulating layer 111 in the same direction. Since the through hole is formed from the top to the bottom with reference to FIG. 3, the first via portion 131 and the second via portion 132 may each have a shape in which the width at the bottom is narrower than the width at the top. Meanwhile, in Fig. 3, the first via portion 131 and the second via portion 132 are shown as having a shape in which a taper is formed to have a substantially straight line on the cross section, but this is not necessarily limited thereto, and the side surface of the first via portion 131 and the side surface of the second via portion 132 may each have a curved surface. In addition, in Fig. 3, the first via portion 131 and the second via portion 132 are shown as having a taper formed to have substantially the same inclination, but this is not necessarily limited thereto, and the degree of taper of the first via portion 131 and the second via portion 132 may be different. In other words, the inclination of the side surface of the first via portion 131 and the second via portion 132 on the cross section may be different from each other. The step of forming a first through hole penetrating the glass layer 110 and the step of forming a second through hole penetrating the first insulating layer 111 may be performed in different processes, and since the glass layer 110 and the first insulating layer 111 comprise different materials, the degree to which the glass layer 110 is processed and the degree to which the first insulating layer 111 is processed may differ from each other.

[0049] The surface roughness of the glass layer 110 at the interface between the first insulating layer 111 and the glass layer 110 may be smaller than the surface roughness of the glass layer 110 at the interface between the first via layer 130 and the glass layer 110, and may be smaller than the surface roughness of the glass layer 110 at the interface between the second wiring layer 122 and the glass layer 110. That is, referring to FIG. 3, the surface roughness of the lower surface of the glass layer 110 may be smaller than the surface roughness of the upper surface of the glass layer 110, and the surface roughness of the lower surface of the glass layer 110 may be smaller than the surface roughness of the inner surface of the glass layer 110 in the direction of the first via layer 130. This may be a result of an etching process being performed on the glass layer 110 in the step of forming a first through hole penetrating the glass layer 110. That is, in the step of forming the first through hole for forming the first via portion 131 of the first via layer 130, the upper surface and the inner surface of the glass layer 110 may be processed by etching, so that surface roughness may occur on the upper surface and the inner surface of the glass layer 110, and the lower surface of the glass layer 110 in contact with the first insulating layer 111 is not etched, so that the lower surface of the glass layer 110 may have a smaller surface roughness than the upper surface and the inner surface of the glass layer 110. When the glass layer 110 is processed to form surface roughness on the upper surface and the inner surface of the glass layer 110, the adhesion between the first via layer 130 and the second wiring layer 122 and the glass layer 110 can be improved.

[0050] The surface roughness of the glass layer 110 can be measured by photographing a cut cross section in the lamination direction of the printed circuit board using a scanning microscope or the like. The roughness can be measured by a known method of measuring the roughness on the cut surface of the glass layer 110 using a center line average calculation method (Ra) or a known method of measuring the roughness using a ten-point average calculation method (Rz), but is not limited thereto, and any method that can measure the roughness can be used without limitation. For example, as a non-limiting example, the average position of the lower surface of the first wiring layer 121 can be displayed as a virtual line, and then the average of the absolute value of the height difference based on the average line can be measured, or the average of the height difference between the five points having the highest height and the five points having the lowest height based on the average line can be obtained. Meanwhile, the roughness measurement method is not limited thereto, but the comparison of the size can be made clearer only when the surfaces of the glass layer 110 to be compared are measured by the same method. In one non-limiting example, the bottom surface of the glass layer 110 may have a roughness Ra value of about 0.1 nm to 0.2 nm, and the top surface and / or inner surface of the glass layer 110 may have a roughness Ra value of about 0.4 nm to 0.6 nm. Alternatively, the bottom surface of the glass layer 110 may have a roughness Rz value of about 1 nm to 3 nm, and the top surface and / or inner surface of the glass layer 110 may have a roughness Rz value of about 4 nm to 7 nm.

[0051] The depth of the first via portion 131 of the first via layer 130 may be deeper than the depth of the second via portion 132. That is, the depth of the first via portion 131 penetrating the glass layer 110 may be deeper than the depth of the second via portion 132 penetrating the first insulating layer 111. This may mean that the insulation distance of the glass layer 110 is longer than the insulation distance of the first insulating layer 111, and referring to FIG. 3, it may mean that the distance between the upper surface and the lower surface of the glass layer 110 is longer than the distance between the upper surface of the first wiring layer 121 and the upper surface of the first insulating layer 111. The thickness of the glass layer 110 may be thicker than the thickness of the first insulating layer 111, but is not necessarily limited thereto. Since the glass layer 110 cannot be formed directly on the first wiring layer 121, the first insulating layer 111 is formed on the first wiring layer 121, and then the glass layer 110 is formed on the first insulating layer 111. In this case, since the glass layer 110 is formed after the first insulating layer 111 is formed thin, the depth of the first via portion 131 penetrating the glass layer 110 can be deeper than the depth of the second via portion 132 penetrating the first insulating layer 111.

[0052] The depths of the first via portion 131 and the second via portion 132 can be measured by photographing a cross section cut in the lamination direction of the printed circuit board with a scanning microscope or the like. The depths of the first via portion 131 and the second via portion 132 of the first via layer 130 can mean the vertical distance between the upper and lower surfaces on the cross section. However, since the first via portion 131 and the second via portion 132 are integrally formed and the boundary between them may not be clear, the depth of the first via portion 131 can be understood as the vertical distance between the upper and lower surfaces of the glass layer 110, and the depth of the second via portion 132 can be understood as the vertical distance from the upper surface of the first wiring layer 121 to the upper surface of the first insulating layer 111. That is, among the insulation distances between the first wiring layer 121 and the second wiring layer 122, the insulation distance corresponding to the region of the glass layer 110 can be understood as the depth of the first via portion 131, and the insulation distance corresponding to the region of the first insulating layer 111 can be understood as the depth of the second via portion 132.

[0053] 4a to 4c are cross-sectional views that roughly show a part of the method for manufacturing the printed circuit board according to the first embodiment.

[0054] A method for manufacturing a printed circuit board includes the steps of forming a first insulating layer 111 so as to embed a first wiring layer 121, forming a glass layer 110 on the first insulating layer 111, forming a first through hole H1 penetrating at least a portion of the glass layer 110, forming a second through hole H2 penetrating at least a portion of the first insulating layer 111, forming a first via layer 130 in the first through hole H1 and the second through hole H2, and forming a second wiring layer 122 on the first insulating layer 111.

[0055] Referring to FIG. 4 a , a method for manufacturing a printed circuit board may include forming a first insulating layer 111 and a glass layer 110 .

[0056] At this time, the first wiring layer 121 may be disposed on the insulating material 100. The insulating material 100 may correspond to any configuration, and may be a carrier substrate, a core layer, a build-up insulating layer, or even another glass layer 110. When the insulating material 100 is a carrier substrate, the first wiring layer 121 may be positioned as the outermost part of a coreless structure, when the insulating material 100 is a core layer, the first wiring layer 121 may be positioned on a core-type substrate, when the insulating material 100 is a build-up insulating layer, the first wiring layer 121 may be positioned between the build-up of the substrate to have an interlayer structure, and when the insulating material 100 is a glass layer 110, the same interlayer structure may be repeatedly laminated. That is, the printed circuit board according to the first embodiment is an insulating material 100 expressed in an arbitrary configuration in order to show only a part where an interlayer structure is formed between the first wiring layer 121 and the second wiring layer 122, and this means that the interlayer structure can be variously applied to the printed circuit board according to the first to fifth application examples described later. Meanwhile, the insulating material 100 is not necessarily composed of only one insulating material, and can have various structures as described above.

[0057] Thereafter, the method for manufacturing the printed circuit board may include forming a first insulating layer 111 to embed the first wiring layer 121 therein.

[0058] The first insulating layer 111 may be disposed on the insulating material 100 to bury the first wiring layer 121 disposed on the insulating material 100. A known insulating layer lamination method may be used as a method for forming the first insulating layer 111, and various methods may be used depending on the insulating material of the first insulating layer 111. At this time, the first insulating layer 111 may further include a temporary layer such as a protective layer, and if the first insulating layer 111 further includes the temporary layer, the temporary layer may be removed before the step of forming the glass layer 110, so that the first insulating layer 111 may be formed as shown in FIG. 4a.

[0059] Thereafter, the method for manufacturing the printed circuit board may include forming a glass layer 110 on the first insulating layer 111 .

[0060] The glass layer 110 may be formed on the first insulating layer 111 by a method of forming the glass layer 110 on the first insulating layer 111 before the first insulating layer 111 is cured or in a semi-cured state, and then curing the first insulating layer 111. If the first insulating layer 111 is formed including a temporary layer, and the temporary layer is removed immediately before forming the glass layer 110, the glass layer 110 may be attached by utilizing the adhesive force of the first insulating layer 111. However, the present invention is not necessarily limited thereto, and the glass layer 110 may be formed after forming an adhesive means on the first insulating layer 111.

[0061] Referring to FIG. 4b, the method for manufacturing a printed circuit board may include forming a first through hole H1 penetrating the glass layer 110 and forming a second through hole H2 penetrating the first insulating layer 111.

[0062] The step of forming the first through hole H1 penetrating the glass layer 110 may include a step of removing a part of the glass layer 110 and the first insulating layer 111 to form the first hole h1. The step of forming the first hole h1 may use a mechanical processing method. As a non-limiting example, the first hole h1 may be formed by irradiating a UV laser. At this time, the UV laser may be used for single laser processing or multiple laser processing.

[0063] The first hole h1 may be formed to penetrate the glass layer 110, and a part of the first insulating layer 111 may be processed at the same time when the glass layer 110 is penetrated. That is, the step of forming the first hole h1 is performed at the step of penetrating the glass layer 110, and at this time, a part of the first insulating layer 111 may be removed together, so that the first hole h1 may have a shape penetrating at least a part of the first insulating layer 111. In FIG. 4b, the first hole h1 is shown penetrating only a part of the first insulating layer 111, but is not limited thereto, and the first hole h1 may penetrate the first insulating layer 111 to expose a part of the upper surface of the first wiring layer 121. Meanwhile, is not limited thereto, and the first hole h1 may be formed to penetrate only the glass layer 110, and the first insulating layer 111 may not be removed. In this case, the first hole h1 may not penetrate a part of the first insulating layer 111.

[0064] Thereafter, at least a portion of the glass layer 110 may be removed to form a first through hole H1. The step of removing at least a portion of the glass layer 110 to form the first through hole H1 may be performed by an etching process, and wet etching may be used as a non-limiting example. The step of removing at least a portion of the glass layer 110 may be performed by a method of expanding the first hole h1 formed in the glass layer 110 to form the first through hole H1. That is, the first through hole H1 may be formed by removing a portion of the glass layer 110 adjacent to the first hole h1. However, since the first insulating layer 111 may not be removed in the step of removing the glass layer 110, a region of the first hole h1 formed in the first insulating layer 111 may not be expanded. In the step of forming the first through hole H1, a portion of the top surface of the first insulating layer 111 may be exposed.

[0065] At this time, when the process is performed by wet etching, a part of the upper side of the glass layer 110 may be removed together, so that the thickness of the glass layer 110 may be reduced. As a non-limiting example, when a part of the upper side of the glass layer 110 is removed, the reduced thickness of the glass layer 110 may correspond to half the diameter of the first through hole H1. That is, the difference between the thickness of the glass layer 110 before the first through hole H1 is formed and the thickness of the glass layer 110 after the first through hole is formed may correspond to half the width of the upper side of the first through hole H1. In the step of removing at least a part of the glass layer 110, the upper surface of the glass layer 110 and the inner surface of the glass layer 110 constituting the wall surface of the first through hole H1 may have surface roughness.

[0066] 4b, the first through hole H1 is shown to form an angle with the upper surface of the glass layer 110, but this is not necessarily limited thereto, and the first through hole H1 may be formed to have a curved surface on the upper side. Also, the first hole h1 is shown to form an angle with the first insulating layer 111, but this is not necessarily limited thereto, and the first hole h1 may also be formed to have a curved surface, or the first hole h1 may have a cone shape without a bottom surface.

[0067] Meanwhile, in FIG. 4b, the formation of the first through hole H1 penetrating the glass layer 110 is shown to proceed in two stages, but this is not necessarily limited thereto, and any via hole processing method for forming a so-called TGV (Through Glass Via), which is a via penetrating the glass layer 110, can be used without limitation. If necessary, the glass layer 110 with the first through hole H1 formed therein can also be attached to the first insulating layer 111 so that the glass layer 110 and the first through hole H1 are formed on the first insulating layer 111. For example, any method can be used at the stage where the first through hole H1 is formed in the glass layer 110.

[0068] Thereafter, a second through hole H2 penetrating at least a part of the first insulating layer 111 can be formed. The method of forming the second through hole H2 can be a known method of penetrating the first insulating layer 111, and as a non-limiting example, processing can be performed using a UV laser, a CO2 laser, or a YAG laser. By forming the second through hole H2, at least a part of the first wiring layer 121 can be exposed. Since the width of the second through hole H2 can be formed larger than the width of the first hole h1, the first hole h1 can be included in the second through hole H2. Meanwhile, after the step of forming the second through hole H2, a surface treatment can be performed on the inner side surface of the first insulating layer 111 forming the inner wall of the second through hole H2 and a part of the upper surface of the first insulating layer 111 forming the bottom surface of the first through hole H1. The surface treatment can be performed as a desmear process for removing residues generated in the first insulating layer 111, and other pretreatments for forming the first via layer 130 can be performed.

[0069] Referring to FIG. 4c, the method for manufacturing a printed circuit board may include forming a first via layer 130 and forming a second wiring layer 122.

[0070] The steps of forming the first via layer 130 and forming the second wiring layer 122 may include a step of forming a seed layer 125. The seed layer 125 may be formed along the inner walls and bottom surfaces of the first through hole H1 and the second through hole H2, and may extend onto the glass layer 110. That is, the seed layer 125 may be conformally formed along the glass layer, the first through hole H1, and the second through hole H2. The method of forming the seed layer 125 may use a deposition method such as sputtering, but is not limited thereto. Since the seed layer 125 extends onto the glass layer 110, when the sputtering method is used, the adhesion between the seed layer 125 and the glass layer 110 may be more secure, which may be more advantageous in the subsequent plating step. However, the method of forming the seed layer 125 is not limited thereto, and may be performed by an electroless plating (or chemical copper) process, and various other methods may be used depending on the material of the seed layer 125, and the seed layer 125 may be formed using a known method.

[0071] Thereafter, a plating layer 126 may be formed on the seed layer 125 to form the first via layer 130 and the second wiring layer 122. The plating layer 126 may be formed by electrolytic plating using the seed layer 125 as a plating lead-in. The plating layer 126 may be formed to fill the first through hole H1 and the second through hole H2, and may form the first via portion 131 and the second via portion 132 of the first via layer 130 together with the seed layer 125 located in the first through hole H1 and the second through hole H2, respectively. At this time, the plating layer 126 may be formed by performing plating once to simultaneously fill the second through hole H2 and the first through hole H1, so that the first via portion 131 and the second via portion 132 may be formed in the same step. This is different from a structure in which a via is formed in the glass layer 110, a via is formed in the first insulating layer 111, and then the glass layer 110 and the first insulating layer 111 are adhesively bonded, and is different in that the boundary between the first via portion 131 penetrating the glass layer 110 and the second via portion 132 penetrating the first insulating layer 111 is not unclear but is formed integrally. Since the first via portion 131 and the second via portion 132 are formed integrally, problems such as separation of the first via portion 131 and the second via portion 132 or problems of misalignment may not occur.

[0072] On the other hand, after forming a plating resist on the seed layer 125 and performing plating, the plating resist is removed, and then a part of the seed layer 125 is removed to form the second wiring layer 122. However, this is not necessarily limited to this, and a known method can be used, such as forming a plating layer 126 on the seed layer 125, and then patterning the second wiring layer 122 by a method of removing a part of the plating layer 126 and a part of the seed layer 125.

[0073] 4a to 4c only show the insulating structure of the first insulating layer 111 and the glass layer 110 between the first wiring layer 121 and the second wiring layer 122 and the interlayer connection of the first via layer 130 in the method for manufacturing a printed circuit board according to the first embodiment, and as described above, the interlayer structure of the first wiring layer 121 and the second wiring layer 122 can be provided at various positions on the printed circuit board. Details regarding this will be described later in the description of the first to fifth application examples.

[0074] 5a to 5j are cross-sectional views each showing a schematic diagram of a printed circuit board according to a first modified example to a tenth modified example of the first embodiment, and a part of a method for manufacturing the printed circuit board.

[0075] 5a to 5j show steps after the step of forming the glass layer 110 in the method for manufacturing a printed circuit board according to the first embodiment, and will focus on various shapes of the first via layer 130 and manufacturing methods thereof. The final steps in Figs. 5a to 5j may correspond to printed circuit boards according to the first to tenth modified examples of the first embodiment.

[0076] 5a, in the method for manufacturing a printed circuit board according to a first modified example of the first embodiment, in the step of forming a first through hole H1 by removing at least a portion of the glass layer 110, the inner wall of the first through hole H1 may have a curved surface. In the case of the printed circuit board according to the first modified example, the inner wall of the first through hole H1 may also have a shape in which the width at the upper part is wider than the width at the lower part, and the width becomes substantially narrower toward the lower part. That is, the width may become substantially narrower toward the first wiring layer 121.

[0077] The inner wall of the first through hole H1 may have a curved surface and a substantially narrow width because the step of removing a part of the glass layer 110 in the step of forming the first through hole H1 may be performed by etching. That is, the curved surface may be generated in a lower area where the etching solution is concentrated in the step of forming the first through hole H1. However, the present invention is not limited to this. If the etching solution is concentrated more on the lower side in the step of forming the first through hole H1, the glass layer 110 may be removed so that the width becomes wider at the center side of the first through hole H1 rather than at the top and bottom sides. However, even in this case, the first insulating layer 111 may not react to the etching solution that removes the glass layer 110, so the first hole h1 formed in the first insulating layer 111 may be maintained in the step of forming the first through hole H1.

[0078] Thereafter, in the method for manufacturing a printed circuit board according to the first modified example of the first embodiment, the width of the second through hole H2 at the upper side may be substantially the same as the width of the first through hole H1 at the lower side. This is because the glass layer 110 can function as a mask for the second through hole H2 in the step of forming the second through hole H2 by removing at least a part of the first insulating layer 111. That is, the second through hole H2 can be formed by removing the first insulating layer 111 forming the bottom surface of the first through hole H1, so that the width of the upper side of the second through hole H2 can be substantially the same as the width of the lower side of the first through hole H1. In this case, the step of forming the second through hole H2 can use a UV laser, a CO2 laser, a YAG laser, or the like, so that the second through hole H2 can have a shape in which a taper is formed to have a substantially constant amount of change.

[0079] In the printed circuit board according to the first modification of the first embodiment, the side of the first via portion 131 may have a substantially curved surface. This may be a result of the shape of the first through hole H1 as described above. Also, at the interface between the glass layer 110 and the first insulating layer 111, the width of the first via portion 131 may be substantially the same as the width of the second via portion 132. This may be a result of the shape of the second through hole H2. In the printed circuit board according to the first modification of the first embodiment, the first via portion 131 of the first via layer 130 may have a substantially curved surface, so that the contact area between the glass layer 110 and the first via portion 131 may be wider, which may be more advantageous in improving adhesion. Meanwhile, the shapes of the first via portion 131 and the second via portion 132 are not limited to those shown in FIG. 5a, and the first via portion 131 may have different curvature radii, etc. of the curved surface, such as being not symmetrical, and may have an uneven curved surface.

[0080] Referring to FIG. 5b, in the method for manufacturing a printed circuit board according to the second modified example of the first embodiment, in the step of forming the second through hole H2 by removing at least a part of the first insulating layer 111, the width of the upper side of the second through hole H2 may be substantially the same as the width of the lower side of the first through hole H1. This is because the glass layer 110 can function as a mask for the second through hole H2 in the step of forming the second through hole H2 by removing at least a part of the first insulating layer 111. However, this is not necessarily limited thereto, and a different mask for forming the second through hole H2 may be used to correspond to the width of the bottom surface of the first through hole H1. That is, since the second through hole H2 can be formed by removing the first insulating layer 111 forming the bottom surface of the first through hole H1, the width of the upper side of the second through hole H2 may be substantially the same as the width of the lower side of the first through hole H1. In this case, the step of forming the second through hole H2 may use a UV laser, a CO2 laser, a YAG laser, or the like, so that the second through hole H2 may have a tapered shape with a substantially constant change amount. Meanwhile, the first through hole H1 and the second through hole H2 may have a tapered shape with a substantially constant change amount, but are not necessarily limited thereto.

[0081] In the printed circuit board according to the second modified example of the first embodiment, the width of the first via portion 131 and the width of the second via portion 132 may be substantially the same at the boundary between the glass layer 110 and the first insulating layer 111. This may be a result of the formation of the second through hole H2 as described above. In this case, as shown in FIG. 5b, when the first via portion 131 and the second via portion 132 are formed to have substantially the same inclination, no inflection occurs between the first via portion 131 and the second via portion 132 at the boundary between the glass layer 110 and the first insulating layer 111, and the printed circuit board may have a shape in which a taper is formed with a certain inclination, but is not necessarily limited thereto.

[0082] 5c, in the method for manufacturing a printed circuit board according to the third modified example of the first embodiment, in the step of forming a second through hole H2 by removing at least a portion of the first insulating layer 111, the degree of taper of the second through hole H2 may be different from the degree of taper of the first through hole H1. As a non-limiting example, the inclination angle formed between the inner wall of the second through hole H2 and the first wiring layer 121 may be larger than the inclination angle formed between the inner wall of the first through hole H1 and the first insulating layer 111. That is, the inner wall of the second through hole H2 may be formed to be closer to vertical than the inner wall of the first through hole H1. This may result in different degrees of removal of the glass layer 110 and the first insulating layer 111 in each of the steps of removing at least a portion of the glass layer 110 to form the first through hole H1 and removing at least a portion of the first insulating layer 111 to form the second through hole H2, and may result in different thicknesses of the glass layer 110 and the first insulating layer 111. The step of removing a portion of the glass layer 110 may be performed by etching, which may involve a chemical process, whereas the step of removing the first insulating layer 111 may involve a physical process, so that the degree and speed of removal of the first insulating layer 111 may be greater than the degree and speed of removal of the glass layer 110. In addition, since the thickness of the first insulating layer 111 may be formed to be substantially thinner than the thickness of the glass layer 110, the second through hole H2 formed in the first insulating layer 111 may have a smaller degree of taper than the first through hole H1 formed in the glass layer 110.

[0083] In the printed circuit board according to the third modified example of the first embodiment, the width of the first via portion 131 and the width of the second via portion 132 may be substantially the same at the boundary between the glass layer 110 and the first insulating layer 111, and the inclination angle formed between the side surface of the first via portion 131 and the first insulating layer 111 may be substantially different from the inclination angle formed between the side surface of the second via portion 132 and the first wiring layer 121. More preferably, the inclination angle formed between the side surface of the first via portion 131 and the upper surface of the first insulating layer 111 and the inclination angle formed between the side surface of the second via portion 132 and the upper surface of the first wiring layer 121 may each be an acute angle, and the inclination angle formed between the side surface of the second via portion 132 and the upper surface of the first wiring layer 121 may be smaller than the inclination angle formed between the side surface of the first via portion 131 and the upper surface of the first insulating layer 111. This may be a result according to the shape of the first through hole H1 formed in the glass layer 110 and the second through hole H2 formed in the first insulating layer 111. In this case, the inclination angle formed by the meeting of both sides can be measured by photographing a cut surface in the stacking direction of the printed circuit board with a scanning microscope, and can be measured using an angle formed by the substantial inclination plane of each via part measured in any five regions and the first insulating layer 111 or the first wiring layer 121. Meanwhile, any known method for measuring the inclination angle formed by the meeting of a substantial plane and a plane, rather than an uneven inclination plane measured only at one point, can be used without limitation. Meanwhile, such a comparison of the inclination angles is not necessarily limited to what is measured, and can be understood to mean that the second via part 132 penetrating the first insulating layer 111 has a shape that is substantially closer to a vertical than the first via part 131 penetrating the glass layer 110.

[0084] Referring to FIG. 5d, the method for manufacturing a printed circuit board according to the fourth modified example of the first embodiment may include a step of forming a plurality of first holes h1 in the step of forming the first holes h1 by removing a portion of the glass layer 110 and the first insulating layer 111. That is, a plurality of first holes h1 for forming the first through holes H1 may be formed. When a plurality of first holes h1 are formed, the etching solution is easily permeated in the step of forming the first through holes H1, and the first through holes H1 having a wider width may be formed. At this time, the region of the first hole h1 formed in a portion of the first insulating layer 111 may not react in the step of forming the first through holes H1, and may not be included in the second through holes H2 even in the step of forming the second through holes H2 by penetrating a portion of the first insulating layer 111. That is, since at least a portion of the first hole h1 may be maintained in the step of forming the first through holes H1 and the step of forming the second through holes H2, the portion formed in at least a portion of the first insulating layer 111 remains in the step of forming the first via layer 130 thereafter.

[0085] The printed circuit board according to the fourth modified example of the first embodiment may include a groove portion in which the first via layer 130 is disposed under the first via portion 131 and is embedded in at least a portion of the first insulating layer 111. The groove portion may be a result of the first via layer 130 being formed in a remaining region of the plurality of first holes h1 that is not included in the first through hole H1 and the second through hole H2. In this case, the seed layer 125 may be conformally disposed along the boundary of the first hole h1, and may be formed on the seed layer 125 by filling the first hole h1 with the plating layer 126. Since the first hole h1 may penetrate only a portion of the first insulating layer 111 without completely penetrating the first insulating layer 111, the groove portion may not contact the first wiring layer 121, and may be disposed so as to be separated from the second via portion 132 of the first via layer 130 and may be disposed along the periphery of the second via portion 132. Since the first via layer 130 includes a groove portion, the contact area between the first via layer 130 and the first insulating layer 111 can be made larger, which can be advantageous in ensuring adhesion.

[0086] Referring to FIG. 5e, in the method for manufacturing a printed circuit board according to the fifth modified example of the first embodiment, the first through hole H1 penetrating the glass layer 110 may be substantially perpendicular to the upper surface of the first insulating layer 111. This may be a result of forming the first through hole H1 more quickly by adjusting the degree of etching in the step of forming the first through hole H1 by removing at least a part of the glass layer 110. However, the present invention is not limited to this, and the step of forming the first through hole H1 may be performed by mechanical processing such as laser processing instead of etching. Meanwhile, in FIG. 5e, the inner wall of the first through hole H1 is shown to be substantially perpendicular in the portion adjacent to the upper and lower surfaces of the glass layer 110, but the present invention is not limited to this, and the upper and lower sides of the first through hole H1 may have curved surfaces, and the inner wall of the first through hole H1 may be substantially perpendicular to the upper and lower surfaces of the glass layer 110. In other words, this means that, in cross section, the inner wall portion of the first through hole H1 can be substantially perpendicular to the upper surface of the first insulating layer 111 and the upper and lower surfaces of the glass layer 110, respectively, and does not have a tapered shape with an inclination.

[0087] In the printed circuit board according to the fifth modification of the first embodiment, the first via portion 131 of the first via layer 130 may be substantially perpendicular to the upper surface of the first insulating layer 111, and may be substantially perpendicular to the upper and lower surfaces of the glass layer 110. The first via portion 131 of the first via layer 130 may also be substantially perpendicular to the second wiring layer 122. This may be a result of forming the first via layer 130 after forming the first through hole H1 so that the first through hole H1 is substantially perpendicular to the upper surface of the first insulating layer 111 and the upper and lower surfaces of the glass layer 110, respectively. In this case, the upper and lower sides of the first via layer 130 may not necessarily form angles with the side surfaces of the glass layer 110, and may have curved surfaces, as described above.

[0088] Referring to FIG. 5f, in the method for manufacturing a printed circuit board according to the sixth modified example of the first embodiment, the width of the first hole h1 may be wider than the width of the second through hole H2. This may be a result of overlapping lasers to process a wide area in the step of forming the first hole h1. Since the width of the first hole h1 may be wider than the width of the second through hole H2 penetrating the first insulating layer 111, the first insulating layer 111 may have a stepped shape in the region where the first hole h1 and the second through hole H2 are adjacent to each other. Thereafter, in the step of forming the seed layer 125, the seed layer 125 may be conformally disposed along the boundary between the first hole h1 and the second through hole H2, and the first via layer 130 may be formed by forming a plating layer 126 on the seed layer 125.

[0089] In the printed circuit board according to the sixth modified example of the first embodiment, the first via layer 130 may have a recessed portion. The recessed portion may be disposed below the first via portion 131 and may have a step with the upper surface of the first insulating layer 111. The recessed portion may be a region corresponding to the first hole h1. Since the first via layer 130 may have the recessed portion, the contact area between the first via layer 130 and the first insulating layer 111 may be wider, which may be advantageous in ensuring adhesion.

[0090] 5g, in the method for manufacturing a printed circuit board according to the seventh modified example of the first embodiment, the first hole h1 is formed to penetrate the first insulating layer 111, and the upper part of the first wiring layer 121 may be exposed in the step of forming the first hole h1. This may be a result of forming the first hole h1 to have a larger area by overlapping the laser in the step of forming the first hole h1, and may be a result of processing the first hole h1 to be longer. Since the upper part of the first wiring layer 121 is exposed through the first hole h1, the step of forming a second through hole penetrating the first insulating layer 111 may be omitted, and one process step may be reduced. At this time, the first hole h1 may be substantially perpendicular to the upper surface of the first insulating layer 111 and may be substantially perpendicular to the upper surface of the first wiring layer 121.

[0091] In the printed circuit board according to the seventh modified example of the first embodiment, the second via portion 132 of the first via layer 130 can be substantially perpendicular to the upper surface of the first insulating layer 111, and can be substantially perpendicular to the first wiring layer 121. This is a result according to the shape of the first hole h1 in the step of forming the first hole h1, and can be a result of omitting the step of forming the second through hole H2.

[0092] Referring to FIG. 5h, in the method for manufacturing a printed circuit board according to the eighth modified example of the first embodiment, the width of the second through hole H2 may be wider than the width of the first through hole H1. At the interface between the first insulating layer 111 and the glass layer 110, the width of the second through hole H2 may be wider than the width of the first through hole H1. This may be a result of processing using a laser such as a UV laser in the step of forming the second through hole H2 penetrating the first insulating layer 111, and in this case, a laser that can process only the first insulating layer 111 while transmitting the UV laser through the glass layer 110 can be used. In this case, too, the seed layer 125 may be conformally formed along the boundary between the first through hole H1 and the second through hole H2. Meanwhile, in FIG. 5h, the second through hole H2 is shown as being tapered with a substantially constant inclination on the cross section, but is not necessarily limited thereto, and the side of the second through hole H2 may have a curved surface.

[0093] In the printed circuit board according to the eighth modified example of the first embodiment, the width of the second via portion 132 may be wider than the width of the first via portion 131 at the interface between the first insulating layer 111 and the glass layer 110. This is due to the shapes of the first through hole H1 and the second through hole H2. Since the second via portion 132 penetrating the first insulating layer 111 may be wider than the width of the first via portion 131, an anchoring effect may occur in the first via layer 130, and the adhesion of the first via layer 130 may be superior.

[0094] Referring to FIG. 5i, the method for manufacturing a printed circuit board according to the ninth modified example of the first embodiment may include forming a plurality of first through holes H1. The first hole h1 may be composed of a plurality of holes, and a plurality of first through holes H1 may be formed to correspond to each of the plurality of first holes h1. At this time, the plurality of first holes h1 and the plurality of first through holes H1 do not mean that a plurality of first holes h1 and a plurality of first through holes H1 are formed in the same layer, but mean that a plurality of first holes h1 and a plurality of first through holes H1 are connected to one wiring pattern in the first wiring layer 121. A plurality of first through holes H1 are formed in the glass layer 110, and a second through hole H2 is formed by penetrating the first insulating layer 111 so as to be connected to one second through hole H2 to be connected to one first wiring layer 121. At this time, in the step of forming the second through holes H2, if the first holes h1 formed in the glass layer 110 and a part of the first insulating layer 111 are not included in the second through holes H2, a part of the first holes h1 may remain in the first insulating layer 111. Thereafter, in the step of forming the first via layer 130, the seed layer 125 may be conformally disposed along the inner walls of each of the plurality of first through holes H1, and if the first holes h1 remain, the seed layer 125 may also be conformally disposed along the boundaries of the first holes h1. The plating layer 126 may fill each of the plurality of first through holes H1 and the plurality of first holes h1.

[0095] In the printed circuit board according to the ninth modification of the first embodiment, at least one via of the first via layer 130 includes one second via portion 132, and includes a plurality of first via portions 131, and each of the plurality of first via portions 131 may be connected to one second via portion 132. That is, the number of first via portions 131 penetrating the glass layer 110 may be multiple, but the number of second via portions 132 penetrating the first insulating layer 111 may be one and may be connected to the first wiring layer 121. The first via layer 130 may have a groove portion. The groove portion may be shaped by the first hole h1, may be disposed below the first via portion 131, and may refer to a portion embedded in the first insulating layer 111. The groove portion may be a region separated from the second via portion. The plurality of first via portions 131 may each have a shape in which the width narrows toward the first wiring layer 121, which may be the result of processing from the top to the bottom with reference to Fig. 5i, even if a plurality of first through holes H1 may be formed. Since a plurality of first via portions 131 may be formed, the contact area between the first via layer 130 and the glass layer 110 may increase, and therefore, an excellent structure may be obtained by ensuring the adhesion of the first via layer 130.

[0096] 5j, in the method for manufacturing a printed circuit board according to the tenth modified example of the first embodiment, the width of the second through hole H2 may be adjusted so that each of the first holes h1 is included in the second through hole H2. That is, in the step of forming the second through hole H2 penetrating the first insulating layer 111, the width of the second through hole may be sufficiently secured so as to be connected to the first through hole H1.

[0097] In the printed circuit board according to the tenth modified example of the first embodiment, one second via portion 132 of the first via layer 130 is connected to each of the multiple first via portions 131, and the first via layer 130 may not have a groove portion. This may be a shape according to the relationship between the first hole h1, the first through hole H1, and the second through hole H2. Since the width of the second via portion 132 can be sufficiently secured, sufficient adhesion and connection reliability can be secured between the first via portion 131 and the second via portion 132.

[0098] Fig. 5k is a top view plan view of a part of the method for manufacturing a printed circuit board according to the ninth and tenth modified examples of the first embodiment of Fig. 5i and Fig. 5j. In particular, Fig. 5k relates to the ninth and tenth modified examples in which a plurality of first holes h1 and first through holes H1 are formed, and may correspond to a top view plan view of the glass layer 110 as seen from above.

[0099] A plurality of first holes h1 spaced apart from each other may be formed in the glass layer 110, and a plurality of first through holes H1 may be formed based on the plurality of first holes h1. Then, the plurality of first through holes H1 may be filled by forming the first via layer 130. At this time, the upper part of the glass layer 110 does not change in the step of forming the second through holes H2 after the step of forming the first through holes H1, so the description of this is omitted, and the description of the second wiring layer 122 being formed on the first via layer 130 is also omitted, and only the top view plan view of the glass layer 110 seen from above is shown. Meanwhile, the shapes and the number of the first holes h1 and the first through holes H1 are merely examples, and the shapes and the number of the first holes h1 and the first through holes H1 may be variously modified.

[0100] Meanwhile, Figures 5a to 5j relate to various modified examples of the printed circuit board and the manufacturing method of the printed circuit board according to the first embodiment, and only show the insulating structure of the first insulating layer 111 and the glass layer 110 between the first wiring layer 121 and the second wiring layer 122 and the interlayer connection of the first via layer 130, and as described above, the interlayer structure of the first wiring layer 121 and the second wiring layer 122 can be formed at various positions on the printed circuit board.

[0101] FIG. 6 is a cross-sectional view that illustrates a part of a printed circuit board according to the second embodiment.

[0102] 6, the printed circuit board according to the second embodiment may further include an adhesive layer 140 interposed between the first insulating layer 111 and the glass layer 110. The adhesive layer 140 may improve adhesion between the first insulating layer 111 and the glass layer 110. Since the surface of glass is smooth and has low surface roughness, it is difficult for the glass layer 110 to ensure adhesion with other components. Therefore, by further including the adhesive layer 140 between the first insulating layer 111 and the glass layer 110, it is possible to improve adhesion between the glass layer 110 and the first insulating layer 111. The adhesive layer 140 may include an inorganic oxide film or an organic film.

[0103] When the adhesive layer 140 includes an inorganic oxide film, the adhesive layer 140 can be a thin oxide film including a metal oxide. The metal oxide can be Al. 2 O 3 , SiO 2 , TiO 2 , ZnO, ZrO 2 , HfO 2 , La 2 O 3 The metal oxide may include at least one of the above materials, but may also include a metal oxide doped with a different metal element. The metal oxide is preferably alumina (Al 2 O 3 ). When the adhesive layer 140 includes an inorganic oxide film, it may be formed using a thin film deposition method, for example, an atomic layer deposition (ALD) method, a molecular vapor deposition (MVD) method, or the like. Since the adhesive layer 140 is formed by a thin film deposition method, the adhesive layer 140 may include an oxide film that is thinner than the first insulating layer 111 and the glass layer 110. As a non-limiting example, the adhesive layer 140 may include a thin oxide film having a thickness of less than 0.1 μm, preferably about 0.001 μm to 0.05 μm.

[0104] When the adhesive layer 140 includes an organic film, the adhesive layer 140 may be a thin organic coating including an organic material. The organic material may be a primer resin for adhesion or a promoter for adhesion such as an adhesion promoter (AP). When the adhesive layer 140 includes an organic material, it may be formed using a coating method. As a non-limiting example, the adhesive layer 140 may be coated on the first insulating layer 111 by a method of spraying the material of the adhesive layer 140 on the first insulating layer 111 or a dipping method, but the present invention is not limited thereto, and any method capable of forming a thin organic film on the first insulating layer 111 may be used without limitation.

[0105] The material of the adhesive layer 140 is not limited to this, and any other material that can be placed between the first insulating layer 111 and the glass layer 110 and used as a means to ensure adhesion between the first insulating layer 111 and the glass layer 110 can be used without restrictions.

[0106] The first via layer 130 may be disposed so as to penetrate the adhesive layer 140. More specifically, the first via portion 131 of the first via layer 130 may be disposed so as to penetrate the adhesive layer 140. That is, the opening of the adhesive layer 140 may have the same width as the first through hole of the glass layer 110. However, this is not necessarily limited thereto, and the opening of the adhesive layer 140 may have the same width as the second through hole of the first insulating layer 111. In this case, the second via portion 132 of the first via layer 130 may have a shape that penetrates the adhesive layer 140, and at least a portion of the first via portion 131 of the first via layer 130 may be disposed on the adhesive layer 140. This will be described in more detail later in the manufacturing method.

[0107] 7a to 7c are cross-sectional views that roughly show a part of a method for manufacturing a printed circuit board according to a second embodiment.

[0108] 7a, the method for manufacturing a printed circuit board may further include forming an adhesive layer 140 after the step of forming the first insulating layer 111. Then, a glass layer 110 may be formed on the adhesive layer. The method for forming the adhesive layer 140 may use various methods depending on the type of the adhesive layer 140, and it goes without saying that a known method may also be used.

[0109] 7b, when the adhesive layer 140 includes an inorganic oxide film, the first holes h1 may not penetrate the adhesive layer 140 in the step of forming the first holes h1. That is, unlike the case where the first holes h1 may penetrate a portion of the first insulating layer 111 in the step of forming the first holes h1, when the adhesive layer 140 includes an inorganic oxide film, the adhesive layer 140 may function as a barrier for the first insulating layer 111.

[0110] Thereafter, even in the step of removing a portion of the glass layer 110 to form the first through hole H1, the adhesive layer 140 may not react.

[0111] Thereafter, the method may include a step of forming an opening in the adhesive layer 140 so as to correspond to the width of the first through hole H1. The second through hole H2 may be formed by removing a part of the adhesive layer 140 exposed through the lower surface of the first through hole H1 to form an opening in the adhesive layer 140 and exposing the first insulating layer 111. A method for removing a part of the adhesive layer 140 may be etching, and may be dry etching or wet etching, but is not necessarily limited thereto, and may be any method capable of selectively removing the adhesive layer 140. In the step of removing a part of the adhesive layer 140 to form an opening, the glass layer 110 may not react, and the first insulating layer 111 may not react. That is, a step of selectively removing only the adhesive layer 140 may be performed.

[0112] Thereafter, a second through hole H2 is formed penetrating the first insulating layer 111, thereby exposing an upper portion of the first wiring layer 121. At this time, a portion of the adhesive layer 140 may be removed to correspond to the first through hole H1, so that a portion of the upper surface of the first insulating layer 111 may be exposed by the first through hole H1 and the opening of the adhesive layer 140.

[0113] 7c, the method for manufacturing a printed circuit board may include forming a first via layer 130 to fill the first through hole H1 and the second through hole H2. In this case, the seed layer 125 is conformally disposed along the boundary between the portions exposed by the first through hole H1 and the second through hole H2, so that the seed layer 125 may extend to the inner wall of the first through hole H1 and the upper surface of the first insulating layer 111 exposed by the opening of the adhesive layer 140. Therefore, the first via portion 131 of the first via layer 130 may have a shape penetrating the adhesive layer 140.

[0114] FIG. 8 is a cross-sectional view illustrating a printed circuit board according to a first modified example of the second embodiment and a part of a method for manufacturing the printed circuit board.

[0115] FIG. 8 illustrates a step after the step of forming the glass layer 110 in the method for manufacturing a printed circuit board according to the second embodiment, and is a schematic diagram illustrating a step corresponding to FIGS. 7b and 7c.

[0116] Referring to FIG. 8, if the adhesive layer 140 includes an organic film, in the step of forming the first hole h1, the adhesive layer 140 may be penetrated and at least a portion of the first insulating layer 111 may be removed.

[0117] Thereafter, in the step of forming the second through-hole through the first insulating layer 111, the adhesive layer 140 may be processed simultaneously with the first insulating layer 111. That is, since the first insulating layer 111 and the adhesive layer 140 each contain an organic material, the opening of the adhesive layer 140 may be formed simultaneously in the step of forming the second through-hole H2 in one processing. By forming the second through-hole H2 and the opening of the adhesive layer 140 simultaneously, the opening of the adhesive layer 140 may correspond to the second through-hole H2, and the width of the opening may be substantially the same as the width of the second through-hole H2. At this time, the bottom surface exposed by the first through-hole H1 may be the adhesive layer 140.

[0118] Thereafter, when the step of forming the first via layer 130 is performed, the first via portion 131 of the first via layer 130 may be formed on the adhesive layer. That is, the second via portion 132 penetrating the first insulating layer 111 may have a shape penetrating the adhesive layer 140.

[0119] Meanwhile, among the configurations other than the adhesive layer 140, the configurations similar to those of the printed circuit board and the method for manufacturing a printed circuit board according to the first embodiment and its modified examples can also be applied to the printed circuit board and the method for manufacturing a printed circuit board according to the second embodiment, and therefore, duplicated explanations regarding this will be omitted.

[0120] FIG. 9 is a cross-sectional view that illustrates a part of a printed circuit board according to a third embodiment.

[0121] Referring to FIG. 9, the printed circuit board of the third embodiment may further include a second insulating layer 112 on the glass layer 110, the second wiring layer 122 is disposed on the second insulating layer 112, and the first via layer 130 may further have a third via portion 133 penetrating the second insulating layer 112.

[0122] The second insulating layer 112 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The insulating material may also include an adhesive sheet such as BS (Bonding Sheet). The second insulating layer 112 may include substantially the same insulating material as the first insulating layer 111. Specifically, the second insulating layer 112 may include ABF (Ajinomoto Build-up Film), but is not limited thereto, and may include the first insulating layer 111 and other organic insulating materials. On the other hand, while FIG. 9 illustrates the second insulating layer 112 as being a single insulating layer, this is not necessarily limited to this and may include further configurations that can be used by a person having ordinary skill in the art, such as being composed of multiple insulating layers as necessary.

[0123] Since the second insulating layer 112 may be further included on the glass layer 110, the second wiring layer 122 may be disposed on the second insulating layer 112. That is, the second wiring layer 122 may be disposed so as to be in contact with the second insulating layer 112. This can solve the problem of relatively low adhesion between the glass layer 110 and the second wiring layer 122, and in this case, even if the seed layer 125 includes an electroless plating layer (or chemical copper), adhesion on the second insulating layer 112 can be ensured.

[0124] The first via layer 130 may further include a third via portion 133 penetrating the second insulating layer 112. The third via portion 133 may be located on the first via portion 131, and the first via portion 131, the second via portion 132, and the third via portion 133 may all be formed to be integral with each other. In addition, the third via portion 133 may also be formed to be integral with the second wiring layer 122.

[0125] In the cross section, the first via portion 131, the second via portion 132, and the third via portion 133 can each have a shape that narrows toward the first wiring layer 121. This can be a result of laminating the first insulating layer 111, the glass layer 110, and the second insulating layer 112, forming a third through hole penetrating the second insulating layer 112, a first through hole penetrating the glass layer 110, and a second through hole penetrating the first insulating layer 111, and then forming the first via layer 130. That is, the through holes, which are the regions in which the first via portion 131, the second via portion 132, and the third via portion 133 of the first via layer 130 are formed, are processed in the same direction, so that the first via portion 131, the second via portion 132, and the third via portion 133 can each have a shape that narrows toward the first wiring layer 121. In FIG. 9, the first via portion 131, the second via portion 132, and the third via portion 133 are shown as having a shape in which a taper is formed so as to have a substantially straight line on the cross section, but this is not necessarily limited thereto, and the side surface of the first via portion 131, the side surface of the second via portion 132, and the side surface of the third via portion 133 may each have a curved surface. In addition, in FIG. 9, the first via portion 131, the second via portion 132, and the third via portion 133 are shown as having a taper formed with substantially the same inclination, but this is not necessarily limited thereto, and the degree of taper of the first via portion 131, the second via portion 132, and the third via portion 133 may be different. That is, the inclination of the side surface of the first via portion 131, the second via portion 132, and the third via portion 133 on the cross section may be different from each other. The step of forming a first through hole penetrating the glass layer 110 and the step of forming a second through hole penetrating the first insulating layer 111 may be performed in different processes, and since the glass layer 110 and the first insulating layer 111 comprise different materials, the degree to which the glass layer 110 is processed and the degree to which the first insulating layer 111 is processed may differ from each other.

[0126] At the interface between the glass layer 110 and the second insulating layer 112, the width of the first via portion 131 can be narrower than the width of the third via portion 133. This can be a result of forming the first through hole penetrating the glass layer 110 after forming the third through hole H3 penetrating the second insulating layer 112.

[0127] The thickness of the second insulating layer 112 may be thinner than the thickness of the glass layer 110, but is not necessarily limited thereto. When the insulation distance between the first wiring layer 121 and the second wiring layer 122 is long, the overall thickness of the printed circuit board may increase, so it is sufficient that the second insulating layer 112 is formed thin to improve the adhesion of the glass layer 110. Therefore, it is preferable that the second insulating layer 112 is formed thin, but it is sufficient that the adhesion between the glass layer 110 and the second insulating layer 112 is secured to such an extent that the second insulating layer 112 does not separate from the glass layer 110. Meanwhile, since the thickness of the second insulating layer 112 is thinner than the thickness of the glass layer 110, the depth of the first via portion 131 of the first via layer 130 may be deeper than the depth of the third via portion 133.

[0128] 10a to 10c are cross-sectional views that roughly show a part of a method for manufacturing a printed circuit board according to a third embodiment.

[0129] 10a, the method for manufacturing a printed circuit board according to the third embodiment may further include, after the step of forming a glass layer 110, a step of forming a second insulating layer 112 on the glass layer 110. The step of forming the second insulating layer 112 on the glass layer 110 may be performed using a known insulating layer lamination method.

[0130] 10b, a step of forming a third through hole H3 penetrating the second insulating layer 112 may be included before the step of forming the first through hole H1 penetrating the glass layer 110. The step of forming the third through hole H3 may use a known method of processing an insulating layer to form a via hole, and may be the same process as the method of forming the second through hole H2 penetrating the first insulating layer 111. In this case, the glass layer 110 may not be damaged even when the third through hole H3 penetrating the second insulating layer 112 is formed.

[0131] Thereafter, a first through hole H1 penetrating the glass layer 110 may be formed. The step of forming the first through hole H1 may be performed by a step of forming the first hole h1 and a step of forming the first through hole H1. Meanwhile, in the method for manufacturing a printed circuit board according to the third embodiment, since the first through hole H1 penetrating the glass layer 110 is formed after the second insulating layer 112 is formed on the glass layer 110, it is preferable to set an etching condition in the step of forming the first through hole H1 so that the thickness of the glass layer 110 is not reduced. Thus, the thickness of the glass layer 110 may not be reduced in the step of forming the first through hole H1.

[0132] Meanwhile, in FIG. 10b, the first through hole H1 is shown as having a tapered shape with a substantially constant inclination, but this is not necessarily limited thereto, and the inner wall of the first through hole H1 may be uneven, and in some cases, a step portion where the etching solution is concentrated may also be formed.

[0133] Thereafter, a step of forming a second through hole H2 penetrating the first insulating layer 111 may be performed.

[0134] 10c, the method may include forming a first via layer 130. The first via layer 130 may include a third via portion 133 filling the third through hole H3, the seed layer 125 may be disposed along an inner wall of the third through hole H3, and the first via portion 131, the second via portion 132, and the third via portion 133 may be formed simultaneously.

[0135] 11a and 11b are cross-sectional views that roughly show a part of a printed circuit board and a method for manufacturing the printed circuit board according to a first and second modified examples of the third embodiment.

[0136] 11a-11b show steps after the step of forming the second insulating layer 112 in the method for manufacturing a printed circuit board according to the third embodiment, and will focus on various shapes of the first via layer 130 and the manufacturing method thereof. The final steps in Figs. 11a-11b may correspond to printed circuit boards according to first and second modified examples of the third embodiment.

[0137] 11a, in the method for manufacturing a printed circuit board according to the first modified example of the third embodiment, in the step of forming a first through hole H1 penetrating the glass layer 110, the width of the upper part of the first through hole H1 may be wider than the width of the lower part of the third through hole H3. This may be a result of an etching solution entering the lower part of the second insulating layer 112 when wet etching is used in the step of forming the first through hole H1. Since the etching solution for removing a part of the glass layer 110 does not react with the second insulating layer 112, only the glass layer 110 disposed under the second insulating layer 112 may be removed. In this case, the width of the upper part of the first through hole H1 may be wider than the width of the lower part of the third through hole H3. Then, a second through hole H2 penetrating the first insulating layer 111 may be formed. Then, a step of forming a first via layer 130 may be performed. In this case, the seed layer 125 may be conformally disposed along the inner wall of each through hole.

[0138] In the printed circuit board according to the first modified example of the third embodiment, the width of the first via portion 131 of the first via layer 130 may be wider than the width of the third via portion 133 at the interface between the glass layer 110 and the second insulating layer 112. This may be due to the shape of the through hole generated in the step of forming the first through hole H1 penetrating the glass layer 110. As the width of the first via portion 131 of the first via layer 130 becomes wider, the contact area with the second insulating layer 112 may become wider, which may be advantageous in ensuring adhesion.

[0139] Referring to FIG. 11b, in the method for manufacturing a printed circuit board according to the second modified example of the third embodiment, the first through hole H1 may be formed to have a step in the step of forming the first through hole H1 penetrating the glass layer 110. That is, the first through hole H1 may have a step in the glass layer 110. This may occur in a portion where the etching solution is concentrated in the step of forming the first through hole H1, and the region where the etching solution is concentrated may have a flat surface as more of the glass layer 110 is removed. Meanwhile, in FIG. 11b, the first through hole H1 is shown to have a flat surface as a step, but is not necessarily limited thereto, and it may be understood that the first through hole H1 does not have a substantially constant change, but may have an inflection point where the degree of change changes. In this case, the inner wall of the first through hole H1 may have a curved surface. Then, the second through hole H2 penetrating the first insulating layer 111 may be formed. Then, the step of forming the first via layer 130 may be performed. Again, the seed layer 125 can be conformally disposed along the inner walls of each through-hole.

[0140] In the printed circuit board according to the second modified example of the third embodiment, the first via portion 131 of the first via layer 130 may have a step between the upper and lower surfaces of the glass layer 110. Without being limited thereto, the first via portion 131 of the first via layer 130 may have an inflection portion in the glass layer 110 or may have a curved surface. This may be due to the shape of the first through hole H1 penetrating the glass layer 110 in the above-mentioned method for manufacturing a printed circuit board. As the width of the first via portion 131 of the first via layer 130 becomes wider and a point where the width changes occurs, the contact area with the second insulating layer 112 and the glass layer 110 may become wider, which may be advantageous in ensuring adhesion.

[0141] Meanwhile, among the configurations other than the shapes of the second insulating layer 112 and the first via layer 130, the same configurations as those of the printed circuit board and the manufacturing method of a printed circuit board according to the first embodiment and its modified examples, and the printed circuit board and the manufacturing method of a printed circuit board according to the second embodiment and its modified examples can also be applied to the printed circuit board and the manufacturing method of a printed circuit board according to the third embodiment, and therefore duplicated explanations regarding this will be omitted.

[0142] As described above, the printed circuit boards and the methods for manufacturing the printed circuit boards according to the first to third embodiments are described mainly with respect to the insulating structure between the first wiring layer 121 and the second wiring layer 122, and therefore, hereinafter, printed circuit boards to which such insulating structures are applied will be roughly described with reference to the drawings. For convenience, various application examples to which the interlayer structure of the first embodiment is applied are shown, but the present invention is not limited thereto, and the interlayer structures of the second and third embodiments may be applied, and modified examples of each of them may be applied, and various combinations thereof may be applied.

[0143] 12a to 12e are cross-sectional views that show schematic diagrams of printed circuit boards according to the first to fifth application examples of the first embodiment. Referring to FIG. 12a to 12e, the first to fifth application examples may have a coreless type printed circuit board. Meanwhile, in the first to fifth application examples, the first wiring layer 121 is disposed to be located above the second wiring layer 122, so that the up-down relationship may differ from the direction described in the first to third embodiments. However, this is merely described relatively for convenience, and will be clearer when understood with reference to the drawings.

[0144] 12a, the printed circuit board according to the first application example of the first embodiment may further include a build-up insulating layer 151 disposed on the glass layer 110 and covering at least a portion of the second wiring layer 122, a build-up wiring layer 152 disposed on the build-up insulating layer 151, and a build-up via layer 153 penetrating at least a portion of the build-up insulating layer 151 to connect the build-up wiring layer 152 and the second wiring layer 122. That is, other build-up layers may be further included in the structure of the printed circuit board according to the first embodiment.

[0145] The build-up insulating layer 151 may include an organic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the insulating material may be a non-photosensitive insulating material such as ABF (Ajinomoto Build-up Film) or PPG (Prepreg), but is not limited thereto, and other polymer materials may be used. The insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric). The insulating material may also include an adhesive sheet such as BS (Bonding Sheet). Specifically, the build-up insulating layer 151 preferably includes ABF (Ajinomoto Build-up Film), but is not limited thereto, and may include other organic insulating materials. On the other hand, in FIG. 12a, the build-up insulation layer 151 is shown as being an insulation layer composed of a single layer, but this is not necessarily limited to this and may include further configurations that can be used by a person having ordinary skill in the art, such as being composed of multiple insulation layers if necessary.

[0146] The build-up wiring layer 152 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the build-up wiring layer 152 may include copper (Cu), but is not limited thereto. The build-up wiring layer 152 may perform various functions according to the design. For example, the build-up wiring layer 152 may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. The build-up wiring layer 152 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, the build-up wiring layer 152 may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, the build-up wiring layer 152 may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). Instead of the electroless plating layer (or chemical copper), a sputtering layer may be included, and both may be included as necessary. The build-up wiring layer 152 may be formed by any one of SAP (Semi Additive Process), MSAP (Modified Semi Additive Process), TT (Tenting), and subtractive methods, but is not limited thereto, and may be formed by any method capable of forming a circuit on a printed circuit board. Also, the build-up wiring layer 152 may be formed by different methods depending on the application, design, and the like.

[0147] The build-up via layer 153 may include microvias. The microvias may be filled vias that fill a via hole, or conformal vias that are arranged along the wall surface of a via hole. The microvias may be arranged in a stacked type and / or staggered type. The build-up via layer 153 may include a metal, which may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may preferably include, but is not limited to, copper (Cu). The build-up via layer 153 may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The build-up via layer 153 may perform various functions depending on the design of the corresponding layer. For example, they may include ground vias, power vias, signal vias, and the like.

[0148] Meanwhile, in the printed circuit board according to the first application example of the first embodiment, the first wiring layer 121 and the first insulating layer 111 can be positioned on the outermost side of the printed circuit board. That is, the first wiring layer 121 can function as a connection pad of the printed circuit board, and can perform a function of connecting with electronic components mounted on the printed circuit board.

[0149] The printed circuit board according to the first application example of the first embodiment may include a solder resist layer 160 disposed on the first insulating layer 111 and covering at least a portion of the first wiring layer 121. The solder resist layer 160 may be disposed on the outermost side of the printed circuit board to protect the printed circuit board. The solder resist layer 160 may be disposed on the first insulating layer 111, which is the uppermost side, with reference to FIG. 12a, and may also be disposed on the build-up insulating layer 151, which is the lowermost side. The solder resist layer 160 may include an insulating material and may include, but is not limited to, a liquid or film type solder resist, and other types of insulating materials may be used. The solder resist layer 160 may have an opening that exposes at least a portion of the first wiring layer 121, and may have an opening that exposes at least a portion of the build-up wiring layer 152.

[0150] 12b, in a printed circuit board according to a second application example of the first embodiment, a first wiring layer 121 can be disposed on a build-up insulating layer 151, and a first insulating layer 111 can be disposed on the build-up insulating layer 151. That is, a printed circuit board can be configured by disposing the structure of the printed circuit board according to the first embodiment on another build-up layer.

[0151] The printed circuit board according to the second application example of the first embodiment may further include a build-up insulating layer 151 arranged on one side of the first insulating layer 111, a build-up wiring layer 152 embedded on one side of the build-up insulating layer 151, and a build-up via layer 153 penetrating at least a portion of the build-up insulating layer 151 to connect the build-up wiring layer 152 and the first wiring layer 121 to each other.

[0152] 12c, the printed circuit board according to the third application example of the first embodiment may have a structure in which a first insulating layer 111 is repeatedly disposed on a glass layer 110. That is, the interlayer structure of the printed circuit board according to the first embodiment may be repeated to form a printed circuit board. In this case, the second wiring layer 122 may be disposed as a first wiring layer 121 having the following structure. At this time, the first insulating layer 111 may be disposed on the glass layer 110.

[0153] In addition, the second wiring layer 122 may be disposed on the outermost side of the printed circuit board. That is, the solder resist layer 160 may be disposed on the glass layer 110.

[0154] 12d, the printed circuit board according to the fourth application example of the first embodiment may have a structure in which an interlayer structure and a build-up structure are mixed. That is, the interlayer structure according to the first embodiment is a form of a build-up structure, and the insulating structure consisting of only an insulating layer may be replaced with an insulating structure including a first insulating layer 111 and a glass layer 110. However, even in this case, in consideration of the lamination direction of the coreless type printed circuit board, it is preferable to apply the interlayer structure according to the first embodiment to the uppermost side based on FIG. 12d in order to control the flatness and warpage characteristics of the printed circuit board.

[0155] Referring to FIG. 12e, a printed circuit board according to a fifth application example of the first embodiment may have a structure in which a coreless type printed circuit board is formed only by the interlayer structure of the first embodiment.

[0156] Meanwhile, Fig. 12a to Fig. 12e are merely examples showing how the interlayer structure of the first embodiment is applied to other interlayer structures, and the number of insulating layers and the number of wiring layers can be freely changed, and the wiring patterns of the wiring layers can also be changed in various ways. Note that the first to fifth application examples of the printed circuit board are not limited to the configurations shown in Fig. 12a to Fig. 12e, and other configurations may be further included, or may be omitted in some cases. In other words, they may further include configurations that can be used by a person having ordinary skill in the art.

[0157] As a non-limiting example, the printed circuit board according to the first to fifth application examples may further include a surface treatment layer disposed on the wiring layer exposed by the opening of the solder resist layer 160. The surface treatment layer may include any one of nickel (Ni), palladium (Pd), and gold (Au), and may be realized by a plurality of these metal layers. For example, the surface treatment layer may be at least a part of an ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) structure, or at least a part of an ENIG (Electroless Nickel Immersion Gold) structure. The surface treatment layer is not limited thereto, and may include an OSP (Organic Solder Passivation) structure including an organic substance. The surface treatment layer may improve the adhesion and signal transmission between the wiring layer and a connecting means such as a solder.

[0158] 13a to 13d are cross-sectional views illustrating a method for manufacturing a printed circuit board according to a first application example of the first embodiment of FIG. 12a.

[0159] Referring to FIG. 13a, before the step of forming the first insulating layer 111, a step of forming a first wiring layer 121 on a carrier substrate C may be further included.

[0160] The carrier substrate C is for supporting the insulating layer and the wiring layer when they are formed, and may be made of an insulating material or a metal material. In FIG. 13a, the carrier substrate C is shown to include a core C0 and a seed C1 formed on both sides of the core C0, but is not limited thereto, and may be a carrier substrate C formed of a single layer, or may have a double seed C1. That is, the carrier substrate C is an example of one case, and the carrier substrate C can be used by anyone having ordinary skill in the art, and can be used without any particular limitation in the present disclosure as long as it is used as a support substrate and can be detached or removed later. As a non-limiting example, a stopper layer including a different metal layer may be further included on the carrier substrate C.

[0161] The first wiring layer 121 may be formed on a carrier substrate C, and the first insulating layer 111 may also be disposed on the carrier substrate C to embed the first wiring layer 121. That is, in the method for manufacturing a printed circuit board according to the first embodiment described with reference to FIGS. 4a to 4c, the insulating material 100 may be understood to correspond to the carrier substrate C.

[0162] 13b and 13c may be substantially the same as the method for forming an interlayer structure of the printed circuit board according to the first embodiment, and therefore detailed description thereof will be omitted. Meanwhile, the step of forming through holes penetrating the glass layer 110 and the first insulating layer 111 is simply depicted, and the detailed content thereof may be substituted for the printed circuit board and the method for manufacturing the printed circuit board according to the first embodiment.

[0163] Referring to FIG. 13d, the method may include forming a build-up insulating layer 151, a build-up wiring layer 152, and a build-up via layer 153 on the glass layer 110, removing the carrier substrate C, and forming a solder resist layer 160.

[0164] The step of forming the build-up insulating layer 151 on the glass layer 110 may be performed using a known build-up layer lamination method, and the steps of forming the build-up wiring layer 152 and the build-up via layer 153 may be performed using any build-up method for insulating layers and wiring layers that can be used by a person having ordinary knowledge in the relevant technical field, without any restrictions.

[0165] The step of removing the carrier substrate C may be performed in various ways depending on the shape of the carrier substrate C. For example, the step of removing the carrier substrate C may involve removing the core included in the carrier substrate and then sequentially removing the seed, or the step of removing the carrier substrate as a whole, i.e., removing the core and the copper foil at the same time. The step of removing the carrier substrate C may be performed using any known process used for carrier detachment without any limitations.

[0166] Meanwhile, although not shown in Fig. 13d, a part of the first wiring layer 121 may be removed during the step of removing the carrier substrate C, so that a so-called recess may be formed in which a step occurs between the first wiring layer 121 and the first insulating layer 111. This may be the result of a part of the first wiring layer 121 being removed by an etchant when the seed C1 of the carrier substrate C is removed.

[0167] After removing the carrier substrate C, the method may include forming a solder resist layer 160 on each of the first insulating layer 111 and the build-up insulating layer 151. The method for forming the solder resist layer 160 may be any method for building up an insulating layer and a wiring layer that can be used by a person having ordinary skill in the art, without any limitations.

[0168] 14a to 14d are cross-sectional views illustrating a method for manufacturing a printed circuit board according to a second application example of the first embodiment of FIG. 12b.

[0169] 14a, the method for manufacturing a printed circuit board according to the second application example of the first embodiment may include a step of forming a build-up insulating layer 151, a build-up wiring layer 152, and a build-up via layer 153 on a carrier substrate C. Thereafter, a step of forming a first insulating layer 111 on the build-up insulating layer 151 may be included, and at this time, the build-up insulating layer 151 may have an interlayer structure as the first wiring layer 121. That is, in the method for manufacturing a printed circuit board according to the first embodiment described with reference to FIGS. 4a to 4c, the insulating material 100 may be understood to correspond to the build-up insulating layer 151.

[0170] 14a to 14c may be substantially the same as the method for forming an interlayer structure of a printed circuit board according to the first embodiment, and therefore detailed description thereof will be omitted. Meanwhile, the step of forming through holes penetrating the glass layer 110 and the first insulating layer 111 is simply described, and the detailed content thereof can be substituted for the printed circuit board and the method for manufacturing the printed circuit board according to the first embodiment, as described above.

[0171] Referring to FIG. 14d, the method may further include removing the carrier substrate C and forming a solder resist layer 160, and the content relating to this may be performed in substantially the same manner as in the first application example, so duplicate content will be omitted.

[0172] 15a and 15b are cross-sectional views that roughly show printed circuit boards according to sixth to seventh application examples of the first embodiment.

[0173] 15a and 15b, the sixth to seventh application examples may have a cored-type printed circuit board. Meanwhile, the sixth to seventh application examples are stacked on the upper and lower sides with the core layer 157 at the center, so the up-down relationship may differ in part from the direction described in the first to third embodiments. However, this is merely described relatively for convenience, and will be clearer when understood with reference to the drawings.

[0174] Referring to FIG. 15a, the printed circuit board according to the sixth application example of the first embodiment may include a core layer 157 disposed on one side of the first insulating layer 111 and a through via 158 penetrating the core layer 157.

[0175] The core layer 157 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, and / or glass fabric) together with such a resin, and may be a photosensitive material and / or a non-photosensitive material. The insulating material may include, but is not limited to, SR (Solder Resist), ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), RCC (Resin Coated Copper) insulating material, CCL (Copper Clad Laminate) insulating material, and the like, and may include other polymer materials. Meanwhile, it is also possible to use a resin including an inorganic filler such as silica and a reinforcing material such as glass fiber. For example, a prepreg may be used, but is not limited to this. Meanwhile, as a non-limiting example, the core layer 157 may include a glass substrate, and the material constituting the core layer 157 may not be limited.

[0176] The through via 158 may include a metal layer formed on the wall surface of a through hole penetrating the core layer 157, and a plug filling the metal layer. The metal layer may include, but is not limited to, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof, and may preferably include, but is not limited to, copper (Cu). The plug may include an ink of an insulating material. The metal layer may include, but is not limited to, an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be formed instead of the electroless plating layer, or both may be included. The through via 158 may perform various functions depending on the design. For example, it may include a ground via, a power via, a signal via, etc.

[0177] In the printed circuit board according to the sixth application example of the first embodiment, a wiring layer in contact with the core layer 157 may be positioned as the first wiring layer 121, and the interlayer structure according to the first embodiment may be applied on the core layer 157. Meanwhile, in Fig. 15a, the interlayer structure according to the first embodiment is shown as being disposed on the outermost side of the printed circuit board, but is not limited thereto, and another build-up insulating layer and a build-up wiring layer may be further included on the glass layer 110.

[0178] 15b, the printed circuit board according to the seventh application example of the first embodiment may have an asymmetrical board structure that is not symmetrical with respect to the core layer 157, and a build-up layer including a build-up insulating layer 151, a build-up wiring layer 152, and a build-up via layer 153 may be laminated on the upper part of the core layer 157, and the interlayer structure of the printed circuit board according to the first embodiment may be applied to the lower part of the core layer. That is, the interlayer structure according to the first embodiment may be included on one side of the core layer 157, and a build-up layer may be disposed on the other side of the core layer 157, and may be connected to each other by a through via. Since the printed circuit board according to the first embodiment includes the glass layer 110 in the interlayer structure, flatness and warpage characteristics may be improved, and therefore warpage may be suppressed even when an asymmetric board is realized.

[0179] Meanwhile, Figs. 15a and 15b are merely examples showing how the interlayer structure of the first embodiment is applied to other interlayer structures, and the number of insulating layers and the number of wiring layers can be freely changed, and the wiring pattern of the wiring layer can also be changed in various ways. The sixth to seventh application examples of the printed circuit board are not limited to the configurations shown in Figs. 15a and 15b, and other configurations can be further included, or may be omitted in some cases. That is, the sixth to seventh application examples can further include configurations that can be used by a person having ordinary skill in the art. The printed circuit boards according to the sixth to seventh application examples can also further include a surface treatment layer on the wiring layer exposed by the opening of the solder resist layer 160.

[0180] 16a to 16d are cross-sectional views illustrating a method for manufacturing a printed circuit board according to a sixth application example of the first embodiment of FIG. 15a.

[0181] The method for manufacturing a printed circuit board according to the sixth application example of the first embodiment may further include a step of forming a first wiring layer 121 on a core layer 157, and a step of forming a first insulating layer 111 on the core layer 157 so as to cover at least a portion of the first wiring layer 121. That is, it can be understood that the insulating material 100 corresponds to the core layer 157 in the method for manufacturing a printed circuit board according to the first embodiment described with reference to Figs. 4a to 4c.

[0182] 16a to 16d may be substantially the same as the method for forming an interlayer structure of a printed circuit board according to the first embodiment, and therefore detailed description thereof will be omitted. Meanwhile, the step of forming through holes penetrating the glass layer 110 and the first insulating layer 111 is simply described, and the detailed content thereof can be substituted for the printed circuit board and the method for manufacturing the printed circuit board according to the first embodiment, as described above.

[0183] In addition, the printed circuit boards and the methods for manufacturing the printed circuit boards according to the first to seventh application examples are not limited to the configurations shown in the drawings, and may further include other configurations, or may be omitted in some cases. In other words, they are not limited to the configurations shown in the drawings, and may further include configurations that can be used by a person having ordinary skill in the art.

[0184] In the present disclosure, the expressions "cover" and "enclose" may include not only the case of covering entirely but also the case of covering at least a part, and may include not only the case of covering directly but also the case of covering indirectly. Furthermore, the expression "fill" may include not only the case of filling completely but also the case of filling roughly, for example, the case where some gaps or voids are present.

[0185] In the present disclosure, the term "substantially" can be determined by including step errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, "substantially perpendicular" can include not only a case where the two are completely perpendicular, but also a case where the two are approximately perpendicular. Furthermore, "substantially coplanar" can include not only a case where the two are completely in the same plane, but also a case where the two are approximately in the same plane.

[0186] In the present disclosure, the same insulating material can mean not only the completely same insulating material, but also the same type of insulating material. Thus, the compositions of the insulating materials are substantially the same, but the specific composition ratios thereof can differ slightly.

[0187] In the present disclosure, the meaning of a cross section can mean the cross-sectional shape of an object cut vertically, or the cross-sectional shape of an object cut vertically, or the cross-sectional shape of an object when viewed from a side, and the meaning of a plane can mean the planar shape of an object cut horizontally, or the planar shape of an object when viewed from a top view or a bottom view.

[0188] In this disclosure, for convenience, the terms lower, bottom, and lower surface are used to mean the downward direction based on the cross section of the drawing, and the terms upper, top, and upper surface are used to mean the opposite direction. However, this is merely a definition of the direction for convenience of explanation, and the scope of the claims is not particularly limited by the description of the direction, and the concepts of up / down can be changed at any time.

[0189] In the present disclosure, the term "connected" refers not only to a direct connection but also to an indirect connection via an adhesive layer or the like. The term "electrically connected" refers to a physical connection and a non-connection. Furthermore, the terms "first" and "second" are used to distinguish one component from another, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly the second component may be named the first component, without departing from the scope of the right.

[0190] The expression "one example" used in the present disclosure does not mean the same embodiment as the other, but is provided to emphasize and describe the unique features that are different from each other. However, the above-mentioned one example does not exclude being realized in combination with the features of another example. For example, even if the matter described in a particular example is not described in another example, it can be understood as being related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0191] The terms used in the present disclosure are merely used to describe an example and are not intended to limit the present disclosure. In this case, the singular expression includes the plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0192] 100 Insulation 110 Glass layer 111 First insulating layer 112 Second insulating layer 121 1st wiring layer 122 2nd wiring layer 125 seed layer 126 Plating layer 130 First via layer 131 First Via Section 132 2nd Via Section 133 Third Beer Section 140 Adhesive layer 151 Build-up insulation layer 157 Core Layer 152 Build-up wiring layer 153 Build-up via layer 158 Through Via 160 Solder resist layer C Carrier Board h1 1st hole H1 1st through hole H2 2nd through hole H3 3rd through hole 1000 electronic equipment 1010 Mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 Camera 1060 Antenna 1070 display 1080 Battery 1090 Signal Line 1100 Smartphone 1110 Motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 Speaker

Claims

1. A first insulating layer; a first wiring layer embedded in one side of the first insulating layer; a glass layer disposed on the other side of the first insulating layer; a second wiring layer disposed on the glass layer; a first via layer connecting the first wiring layer and the second wiring layer to each other and including a first via portion penetrating the glass layer and a second via portion penetrating the first insulating layer; A printed circuit board, wherein, in a cross section, at least one of the first via portion and the second via portion has a shape that substantially narrows in width toward the first wiring layer.

2. The printed circuit board according to claim 1 , wherein the first via portion and the second via portion are integrally formed.

3. The printed circuit board according to claim 1 , wherein the width of the second via portion is narrower than the width of the first via portion at the interface between the first insulating layer and the glass layer.

4. The printed circuit board according to claim 1 , wherein at an interface between the glass layer and the second wiring layer, a width of the first via portion is narrower than a width of the second wiring layer.

5. The printed circuit board according to claim 1 , wherein a width of the first via portion and a width of the second via portion are substantially the same at an interface between the glass layer and the first insulating layer.

6. The printed circuit board according to claim 5 , wherein an inclination angle formed between a side surface of the first via portion and another surface facing one surface of the first insulating layer is larger than an inclination angle formed between a side surface of the second via portion and one surface of the first wiring layer.

7. The printed circuit board of claim 1 , wherein the first via layer includes a groove portion disposed on one side of the first via portion and embedded within at least a portion of the first insulating layer.

8. The printed circuit board according to claim 7 , wherein the groove portion is spaced apart from the second via portion and is disposed along a periphery of the second via portion.

9. The printed circuit board of claim 1 , wherein the first via layer includes a recess portion disposed on one side of the first via portion and having a step with another surface facing the one surface of the first insulating layer.

10. The printed circuit board of claim 1 , wherein in a cross section, the first via portion is substantially perpendicular to the first insulating layer.

11. The printed circuit board according to claim 1 , wherein the second via portion is substantially perpendicular to the first wiring layer in a cross section.

12. The printed circuit board according to claim 1 , wherein the width of the second via portion is wider than the width of the first via portion at the interface between the first insulating layer and the glass layer.

13. The printed circuit board according to claim 1 , wherein at least one first via of the first via layer includes a second via portion and a plurality of first via portions each in contact with the second via portion.

14. The printed circuit board of claim 13 , wherein the first via is disposed on one side of at least one of the plurality of first via portions and includes a groove portion embedded within at least a portion of the first insulating layer.

15. The printed circuit board according to claim 13 , wherein each of the plurality of first via portions has a shape whose width narrows toward the first wiring layer in a cross section.

16. The printed circuit board of claim 1 , further comprising an adhesive layer interposed between the glass layer and the first insulating layer.

17. The printed circuit board of claim 16 , wherein the first via portion penetrates at least a portion of the adhesive layer.

18. The printed circuit board of claim 16 , wherein the second via portion penetrates at least a portion of the adhesive layer.

19. The printed circuit board of claim 16 , wherein the adhesion layer comprises an inorganic oxide film or an organic film.

20. a second insulating layer disposed on the glass layer; the second wiring layer is disposed on the second insulating layer; The printed circuit board according to claim 1 , wherein the first via layer includes a third via portion penetrating the second insulating layer.

21. The printed circuit board according to claim 20 , wherein in a cross section, the first via portion, the second via portion, and the third via portion each have a shape whose width narrows toward the first wiring layer.

22. At an interface between the glass layer and the second insulating layer, a width of the first via portion is narrower than a width of the third via portion; 21. The printed circuit board of claim 20, wherein the width of the second via portion is narrower than the width of the first via portion at the interface between the glass layer and the first insulating layer.

23. 21. The printed circuit board of claim 20, wherein the width of the first via portion is greater than the width of the third via portion at the interface between the glass layer and the second insulating layer.

24. The printed circuit board according to claim 20 , wherein the first via portion has a step between one surface of the glass layer and another surface opposite to the one surface.

25. The printed circuit board of claim 1 , wherein a surface roughness of the glass layer at an interface between the first insulating layer and the glass layer is less than a surface roughness of the glass layer at an interface between the first via layer and the glass layer.

26. 26. The printed circuit board of claim 25, wherein a surface roughness of the glass layer at an interface between the first insulating layer and the glass layer is less than a surface roughness of the glass layer at an interface between the second wiring layer and the glass layer.

27. The printed circuit board according to claim 1 , wherein a depth of the first via portion is greater than a depth of the second via portion.

28. a build-up insulating layer disposed on the glass layer and covering at least a portion of the second wiring layer; a build-up wiring layer disposed on the build-up insulating layer; The printed circuit board according to claim 1 , further comprising: a build-up via layer penetrating at least a portion of the build-up insulating layer so as to connect the build-up wiring layer and the second wiring layer to each other.

29. a build-up insulating layer disposed on one side of the first insulating layer; a build-up wiring layer embedded in one side of the build-up insulating layer; The printed circuit board according to claim 1 , further comprising: a build-up via layer penetrating at least a portion of the build-up insulating layer so as to connect the build-up wiring layer and the first wiring layer to each other.

30. The printed circuit board of claim 1 , further comprising a solder resist layer disposed on one side of the first insulating layer and covering at least a portion of the first wiring layer.

31. The printed circuit board according to claim 30 , further comprising a surface treatment layer disposed on at least a portion of the first wiring layer exposed by the solder resist layer.

32. The printed circuit board according to claim 1 , further comprising a solder resist layer disposed on the glass layer and covering at least a portion of the second wiring layer.

33. a core layer having one side disposed on one side of the first insulating layer; The printed circuit board of claim 1 , further comprising a through via extending through at least a portion of the core layer.

34. the first insulating layer, the first wiring layer, the glass layer, the second wiring layer, and the first via layer are further disposed on the other side of the core layer, the other side being opposed to the one side of the core layer; The printed circuit board of claim 33 , wherein the through vias connect the first wiring layers together.

35. a build-up insulating layer disposed on the other side of the core layer; a build-up wiring layer disposed on the other side of the core layer and on the build-up insulating layer; The printed circuit board of claim 33, further comprising: a build-up via layer penetrating at least a portion of the build-up insulating layer to connect the build-up wiring layers to each other.

36. An insulating layer; a first wiring layer disposed on one side of the insulating layer; a glass layer disposed on the other side of the insulating layer; a via layer including a first through hole penetrating the insulating layer and exposing at least a portion of the first wiring layer, a second through hole penetrating the glass layer and connected to the first through hole, at least a portion of the first wiring layer exposed, a first metal layer disposed on each wall surface of the first through hole and the second through hole, and a second metal layer disposed on the first metal layer and filling at least a portion of each of the first through hole and the second through hole; a second wiring layer disposed on the glass layer and coupled to the via layer.

37. 37. The printed circuit board according to claim 36, wherein the first metal layer is integrally formed on at least an exposed portion of the first wiring layer and on wall surfaces of the first through hole and the second through hole.

38. a portion of each of the first metal layer and the second metal layer extends onto the glass layer; 37. The printed circuit board of claim 36, wherein the second wiring layer includes a portion of each of the first metal layer and the second metal layer that extends onto the glass layer.

39. forming a first insulating layer in which the first wiring layer is embedded; forming a glass layer on the first insulating layer; forming a first through hole through the glass layer; forming a second through hole penetrating the first insulating layer and exposing at least a portion of the first wiring layer; forming a first via layer in the first through hole and the second through hole; forming a second wiring layer on the first insulating layer, the second wiring layer being connected to the first via layer.

40. 40. The method of claim 39, wherein in forming the first via layer, filling the first through holes and filling the second through holes are performed simultaneously.

41. 40. The method of claim 39, wherein forming the first via layer comprises forming a seed layer along inner walls of the first through hole and the second through hole, and forming a plating layer on the seed layer.

42. The step of forming the first through hole includes:

40. The method of claim 39, further comprising the steps of forming a first hole through the glass layer to remove a portion of the first insulating layer, and removing a portion of the glass layer adjacent to the first hole to form a first through hole.

43. the step of forming the first hole is performed by processing the glass layer and the first insulating layer by irradiating a laser; The method of claim 42, wherein the forming of the first through hole is performed by etching.

44. 43. The method of claim 42, wherein forming the first through hole includes expanding at least a portion of the first hole and removing at least a portion of an upper portion of the glass layer.

45. The method further includes forming an adhesive layer on the first insulating layer before the step of forming the glass layer, The method of claim 39 , wherein the forming of the glass layer is performed by forming the glass layer on the adhesive layer.

46. 46. ​​The method of claim 45, further comprising removing at least a portion of the adhesive layer to form an opening after the step of forming the first through hole.

47. Before the step of forming the first through hole, forming a second insulating layer on the glass layer; 46. ​​The method of claim 45, further comprising forming a third through hole penetrating at least a portion of the second insulating layer.

48. forming the first wiring layer on a carrier substrate before forming the first insulating layer; 40. The method for manufacturing a printed circuit board according to claim 39, further comprising the step of: removing the carrier substrate after the step of forming the second wiring layer.

49. The method further includes forming the first wiring layer on a build-up layer before forming the first insulating layer, 40. The method for manufacturing a printed circuit board according to claim 39, wherein the build-up layer includes a build-up insulating layer, a build-up wiring layer disposed on or within the build-up insulating layer, and a build-up via layer penetrating at least a portion of the build-up insulating layer to connect the build-up wiring layers to each other.

50. The method for manufacturing a printed circuit board according to claim 39, further comprising forming the first wiring layer on a core layer before forming the first insulating layer.

51. The method further includes forming a build-up layer on the glass layer after the step of forming the second wiring layer, 40. The method for manufacturing a printed circuit board according to claim 39, wherein the build-up layer includes a build-up insulating layer, a build-up wiring layer disposed on the build-up insulating layer, and a build-up via layer penetrating at least a portion of the build-up insulating layer to connect the build-up wiring layers to each other.

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