Drive circuit, control apparatus and driving method

Abstract

To provide a drive circuit, a control apparatus, and a driving method capable of simplifying the circuit configuration for suppressing fluctuations in the threshold voltage of semiconductor switching elements.SOLUTION: A drive circuit 11 comprises a first voltage application section 111 that alternately applies a plus bias voltage VP and a zero bias voltage VM to the gate terminal G of SiCMOSFET 31 with respect to the reference potential when the SiCMOSFET 31 is operated for switching, and a second voltage application section 112 that applies a minus bias voltage VN to the gate terminal G of SiCMOSFET 31 only once with respect to the reference potential during the period when SiCMOSFET 31 is not operated for switching.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a drive circuit, a control device, and a drive method for a semiconductor switching element. [Background technology]

[0002] Patent Document 1 discloses the following technology: "A switching circuit comprising a switching element having a silicon carbide substrate, and a reset voltage application circuit which applies a reset voltage to the gate of the switching element, the reset voltage alternating between positive and negative voltages and gradually attenuating in amplitude. When a reset voltage is applied to the gate of the switching element having a silicon carbide substrate, the gate threshold fluctuates up and down before converging to a normal value. Therefore, the gate threshold that has changed due to BTI can be restored to the normal value." [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-68434 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, the reset voltage for restoring the gate threshold of the switching element to a normal value has a complex voltage waveform, and the configuration of the circuit for generating the reset voltage is complicated. Therefore, in the conventional technology, there is a problem that the circuit configuration for restoring the gate threshold of the switching element to a normal value is complicated.

[0005] An object of the present invention is to provide a drive circuit, a control device, and a drive method that can simplify the circuit configuration for suppressing fluctuations in the threshold voltage of a semiconductor switching element. [Means for solving the problem]

[0006] In order to achieve the above object, a drive circuit according to one embodiment of the present invention includes a first voltage application unit that, when performing switching operation on a field effect transistor having a silicon carbide substrate, alternately applies a positive bias voltage and a zero bias voltage with respect to a reference potential to a gate terminal of the field effect transistor, and a second voltage application unit that applies a negative bias voltage with respect to the reference potential to the gate terminal only once during a period when the field effect transistor is not performing switching operation.

[0007] In order to achieve the above-mentioned object, a control device according to one aspect of the present invention comprises a drive circuit according to the above-mentioned aspect of the present invention, and a control circuit that controls the timing at which the drive circuit applies the positive bias voltage, the zero bias voltage, and the negative bias voltage to the gate terminal.

[0008] In order to achieve the above object, a driving method according to one embodiment of the present invention, when performing switching operation on a field effect transistor having a silicon carbide substrate, alternately applies a positive bias voltage and a zero bias voltage with respect to a reference potential to a gate terminal of the field effect transistor, and applies a negative bias voltage with respect to the reference potential to the gate terminal only once during a period in which the field effect transistor is not performing switching operation. Effect of the Invention

[0009] According to one aspect of the present invention, it is possible to simplify the circuit configuration for suppressing fluctuations in the threshold voltage of a semiconductor switching element. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a drive circuit and a control device according to an embodiment of the present invention. [Diagram 2] 4 is a timing chart showing an example of a driving method according to an embodiment of the present invention. [Diagram 3] 1 is a diagram for explaining the operation and effect of a drive circuit, a control device, and a drive method according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The embodiments of the present invention are examples of devices and methods for embodying the technical idea of ​​the present invention, and the technical idea of ​​the present invention does not specify the materials, shapes, structures, arrangements, etc. of the components as described below. The technical idea of ​​the present invention can be modified in various ways within the technical scope defined by the claims.

[0012] [Configuration of the drive circuit and control device] A drive circuit and a control device according to an embodiment of the present invention will be described with reference to FIG. 1. FIG. 1 is a diagram showing a schematic configuration of a drive circuit 11 and a control device 1 according to this embodiment. In this embodiment, the drive circuit 11 drives a circuit having a configuration including a silicon carbide metal oxide semiconductor field effect transistor 31 and a resistance element 33 connected in series to a DC power source 32. However, the drive circuit 11 is not limited to this configuration, and may be, for example, an inverter circuit or a converter circuit as long as it has a semiconductor switching element. In addition, the load provided in the circuit to be driven is not limited to the resistance element 33, and may be an inductive load or a capacitive load. Hereinafter, the "silicon carbide metal oxide semiconductor field effect transistor" (SiC Metal-Oxide-Semiconductor Field Effect Transistor) is abbreviated as "SiCMOSFET".

[0013] 1, the drive circuit 11 according to the present embodiment includes a first voltage application unit 111 that alternately applies a positive bias voltage VP and a zero bias voltage VM with respect to a reference potential to a gate terminal G of a SiCMOSFET (an example of a field effect transistor having a silicon carbide substrate) 31 when the SiCMOSFET 31 is subjected to a switching operation. The SiCMOSFET 31 is, for example, an N-type transistor.

[0014] In this embodiment, the reference potential is, for example, a ground potential. A source terminal S of the SiCMOSFET 31 is connected to a reference terminal 2 fixed to a reference potential. A drain terminal D of the SiCMOSFET 31 is connected to a resistance element 33 provided in a circuit to be driven. A positive bias voltage VP and a zero bias voltage VM applied to the SiCMOSFET 31 by the first voltage application unit 111 are applied to the SiCMOSFET 31 as a gate-source voltage VGS. The positive bias voltage VP has, for example, a voltage value capable of turning the SiCMOSFET 31 on, and is a voltage equal to or higher than the threshold voltage (gate threshold voltage) of the SiCMOSFET 31. The zero bias voltage VM has, for example, a voltage value capable of turning the SiCMOSFET 31 off, and is a voltage in a range from the reference potential to a voltage lower than the threshold voltage of the SiCMOSFET 31.

[0015] The drive circuit 11 includes a second voltage application unit 112 that applies a negative bias voltage VN with respect to a reference potential to the gate terminal G of the SiCMOSFET 31 only once during a period in which the SiCMOSFET 31 is not subjected to a switching operation. The negative bias voltage VN is, for example, a voltage that is a lower potential than the potential of the zero bias voltage VM. For example, when the potential of the zero bias voltage VM is 0 V, the negative bias voltage VN is a negative voltage.

[0016] The drive circuit 11 includes connection terminals 113, 114 connected to a circuit to be driven including the SiCMOSFET 31, and a gate resistor 115. The gate resistor 115 is provided to reduce unnecessary oscillations in the drain-source voltage of the SiCMOSFET 31. The connection terminal 113 is connected to a gate terminal G of the SiCMOSFET 31. The connection terminal 114 is connected to a source terminal S of the SiCMOSFET 31 and a reference terminal 2.

[0017] The first voltage application unit 111 has a positive voltage generation unit 111a that generates a positive bias voltage, a first switch 111b that connects the positive voltage generation unit 111a to the gate terminal G of the SiCMOSFET 31, and a second switch 111c that connects the gate terminal G of the SiCMOSFET 31 to a reference terminal 2 fixed to a reference potential. The second voltage application unit 112 has a negative voltage generation unit 112a that generates a negative bias voltage VN, and a third switch 112b that connects the negative voltage generation unit 112a to the gate terminal G of the SiCMOSFET 31.

[0018] The positive voltage generating unit 111a and the negative voltage generating unit 112a are each formed of, for example, a DC power supply. The first switch 111b, the second switch 111c, and the third switch 112b are each formed of, for example, a semiconductor switching element such as a bipolar transistor or a field effect transistor.

[0019] The positive electrode side of the positive voltage generating unit 111a is connected to one terminal of the first switch 111b, and the negative electrode side of the positive voltage generating unit 111a is connected to the positive electrode side of the negative voltage generating unit 112a and the connection terminal 114. As a result, the negative electrode side of the positive voltage generating unit 111a and the positive electrode side of the negative voltage generating unit 112a are connected to the source terminal S of the SiCMOSFET 31 and the reference terminal 2 via the connection terminal 114. The connection part between the negative electrode side of the positive voltage generating unit 111a and the positive electrode side of the negative voltage generating unit 112a is connected to the reference terminal 2. Therefore, the connection part between the negative electrode side of the positive voltage generating unit 111a and the positive electrode side of the negative voltage generating unit 112a is fixed to a reference potential (for example, 0V), and the positive voltage generating unit 111a can generate a positive voltage with respect to the reference potential, and the negative voltage generating unit 112a can generate a negative voltage with respect to the reference potential. In the drive circuit 11, the positive bias voltage VP is generated by the positive voltage generated by the positive voltage generating unit 111a, and the negative bias voltage VN is generated by the negative voltage generated by the negative voltage generating unit 112a. In the drive circuit 11, the zero bias voltage VM is generated by connecting the connection between the negative side of the positive voltage generating unit 111a and the positive side of the negative voltage generating unit 112a to the reference terminal 2 via the connection terminal 114.

[0020] The other terminal of the first switch 111b is connected to one terminal of the second switch 111c, one terminal of the third switch 112b, and one terminal of the gate resistor 115. The other terminal of the second switch 111c is connected to the negative side of the positive voltage generating unit 111a, the positive side of the negative voltage generating unit 112a, and the connection terminal 114. As a result, the other terminal of the second switch 111c is connected to the source terminal S and the reference terminal 2 of the SiCMOSFET 31 via the connection terminal 114. The negative side of the negative voltage generating unit 112a is connected to the other terminal of the third switch 112b. The other terminal of the gate resistor 115 is connected to the connection terminal 113. As a result, the other terminal of the gate resistor 115 is connected to the gate terminal G of the SiCMOSFET 31 via the connection terminal 113.

[0021] Since the first voltage application unit 111 is configured with a single power supply, the power supply configuration is simplified. In addition, the first voltage application unit 111 can set the gate terminal G of the SiCMOSFET 31 to a zero-bias state by shorting the gate terminal G to the source terminal S connected to the reference terminal 2 by the second switch 111c. This allows the drive circuit 11 to have a reduced circuit scale. Therefore, the drive circuit 11 is suitable for an on-board conversion device that requires a small size and weight. The drive circuit 11 and the control device 1 described later are not limited to on-board equipment, and are suitable for devices using SiCMOSFETs in industry, electric railways, and the like.

[0022] 1, the control device 1 according to the present embodiment includes a drive circuit 11 according to the present embodiment, and a control circuit 12 that controls the timing at which the drive circuit 11 applies a positive bias voltage VP, a zero bias voltage VM, and a negative bias voltage VN to a gate terminal G of a SiCMOSFET 31. The control circuit 12 outputs control signals Psw, Msw, and Nsw that control the switching operations of the first switch 111b, the second switch 111c, and the third switch 112b, respectively, to the drive circuit 11. The control signal Psw is a signal for controlling the switching operation of the first switch 111b, the control signal Msw is a signal for controlling the switching operation of the second switch 111c, and the control signal Nsw is a signal for controlling the switching operation of the third switch 112b.

[0023] A drive signal Ds is input to the control circuit 12 from an external device (not shown) that controls the operation of the control device 1. The control circuit 12 determines, according to the signal level of the drive signal Ds, a drive period during which the SiCMOSFET 31 is caused to perform a switching operation and a non-drive period during which the SiCMOSFET 31 is not caused to perform a switching operation.

[0024] The control circuit 12 determines that the period is a driving period when the signal level of the drive signal Ds input from the external device is, for example, a high level, and determines that the period is a non-driving period when the signal level of the drive signal Ds is, for example, a low level. When the control circuit 12 determines that the period is a driving period, the control circuit 12 alternately controls the first switch 111b to an on state and the second switch 111c to an off state or the first switch 111b to an off state and the second switch 111c to an on state at a predetermined timing, and generates control signals Psw, Msw, and Nsw for controlling the third switch 112b to an off state, and outputs the generated control signals Psw, Msw, and Nsw to the drive circuit 11.

[0025] On the other hand, when the control circuit 12 determines that it is a non-driving period, it generates control signals Psw, Msw, and Nsw for controlling the third switch 112b to an ON state only once, and outputs the generated control signals Psw, Msw, and Nsw to the drive circuit 11. When turning the third switch 112b to an ON state, the control circuit 12 controls the first switch 111b and the second switch 111c to an OFF state. During the non-driving period, except for the period in which the third switch 112b is turned to an ON state, the control circuit 12 controls the second switch 111c to an ON state and the first switch 111b and the third switch 112b to an OFF state.

[0026] In addition, the control circuit 12 does not necessarily control the third switch 112b to the on state once when it is determined that the non-driving period is occurring, but may control the third switch 112b to the on state as necessary. For example, the control circuit 12 may control the third switch 112b to the on state only once during the non-driving period after the cumulative driving period has elapsed a predetermined period. Therefore, when the control circuit 12 determines that it is not necessary to turn the third switch 112b to the on state even during the non-driving period, it may control the second switch 111c to the on state and the first switch 111b and the third switch 112b to the off state throughout the non-driving period. Note that the control circuit 12 may control the third switch 112b to the on state once every time the non-driving period occurs.

[0027] The drive circuit 11 operates the first switch 111b, the second switch 111c, and the third switch 112b based on control signals Psw, Msw, and Nsw input from the control circuit 12, and applies any one of a positive bias voltage VP, a zero bias voltage VM, and a negative bias voltage VN to the gate terminal G of the SiCMOSFET 31. The SiCMOSFET 31 is in an ON state when a positive bias voltage VP is applied to the gate terminal G, in an OFF state when a zero bias voltage VM is applied to the gate terminal G, and in a reset state of the threshold voltage when a negative bias voltage VN is applied to the gate terminal G.

[0028] [Driving method] The driving method according to the present embodiment will be described with reference to FIG. 1 and FIG. 2. FIG. 2 is a timing chart showing an example of the operation of the driving circuit 11 and the control device 1. In FIG. 2, the first row shows the voltage waveform of the driving signal Ds input to the control circuit 12. In FIG. 2, the second row shows the voltage waveform of the control signal Psw input from the control circuit 12 to the driving circuit 11, the third row shows the voltage waveform of the control signal Msw input from the control circuit 12 to the driving circuit 11, and the fourth row shows the voltage waveform of the control signal Nsw input from the control circuit 12 to the driving circuit 11. In FIG. 2, the fifth row shows the voltage waveform of the gate-source voltage VGS of the SiCMOSFET 31. In FIG. 2, the passage of time is represented from left to right.

[0029] 2, when the voltage level of the drive signal Ds changes from low to high at time t1, the control circuit 12 (see FIG. 1) determines that the drive period DP for switching the SiCMOSFET 31 (see FIG. 1) has begun. As a result, the control circuit 12 outputs to the drive circuit 11 (see FIG. 1) a control signal Psw, which is a pulse signal whose voltage level alternates between high and low at a predetermined cycle, a control signal Nsw whose phase is inverted by 180° with respect to the control signal Psw, and a control signal Msw whose voltage level is constant at a low level.

[0030] When the voltage level of the control signal Psw is high and the voltage levels of the control signals Msw and Nsw are low, the first switch 111b (see FIG. 1) is turned on, and the second switch 111c and the third switch 112b (see FIG. 1) are turned off. As a result, the positive electrode side of the positive voltage generating unit 111a (see FIG. 1) is connected to the gate terminal G of the SiCMOSFET 31 via the gate resistor 115 (see FIG. 1). Therefore, a positive bias voltage VP is applied to the gate terminal G of the SiCMOSFET 31, and the gate terminal G of the SiCMOSFET 31 is in a positive bias state.

[0031] A source terminal S of the SiCMOSFET 31 is connected to a reference terminal 2 (see FIG. 1), and a reference potential is applied to the source terminal S of the SiCMOSFET 31. In addition, the source terminal S of the SiCMOSFET 31 and the negative electrode side of the positive voltage generating unit 111a are connected to each other via a connection terminal 114 and are at the same potential.

[0032] As a result, as shown in FIG. 2, when the voltage level of the control signal Psw is high and the voltage levels of the control signals Msw and Nsw are low, the gate-source voltage VGS of the SiCMOSFET 31 becomes equal to the positive bias voltage VP.

[0033] When the voltage level of the control signal Msw is high and the voltage levels of the control signals Psw and Nsw are low, the second switch 111c is turned on, and the first switch 111b and the third switch 112b are turned off. As a result, the gate terminal G of the SiCMOSFET 31 is connected to the source terminal S of the SiCMOSFET 31 and the reference terminal 2 via the connection terminal 114 and the gate resistor 115. Therefore, a zero bias voltage VM is applied to the gate terminal G of the SiCMOSFET 31, and the potential of the gate terminal G of the SiCMOSFET 31 becomes the reference potential. In addition, the gate terminal G of the SiCMOSFET 31 and the source terminal S of the SiCMOSFET 31 are connected to each other and have the same potential, so that the gate terminal G of the SiCMOSFET 31 is in a zero bias state in which no bias voltage is applied.

[0034] As a result, as shown in FIG. 2, when the voltage level of the control signal Nsw is high and the voltage levels of the control signals Psw and Msw are low, the gate-source voltage VGS of the SiCMOSFET 31 becomes the same as the zero bias voltage VM, for example, 0 V.

[0035] In this manner, in the driving method according to the present embodiment, when the SiCMOSFET 31 is subjected to a switching operation, a positive bias voltage VP and a zero bias voltage VM are alternately applied to the gate terminal G of the SiCMOSFET 31 with respect to a reference potential. As a result, when a positive bias voltage VP is applied to the gate terminal G of the SiCMOSFET 31, the gate-source voltage VGS of the SiCMOSFET 31 becomes equal to the positive bias voltage VP, and the SiCMOSFET 31 is in an ON state. On the other hand, when a zero bias voltage VM is applied to the gate terminal G of the SiCMOSFET 31, the gate-source voltage VGS of the SiCMOSFET 31 becomes equal to the zero bias voltage VM (e.g., 0 V), and the SiCMOSFET 31 is in an OFF state. In this manner, the driving circuit 11 can drive the SiCMOSFET 31 provided in the circuit to be driven by a switching operation that repeats an ON state and an OFF state at a predetermined cycle during the driving period DP.

[0036] 2, when the voltage level of the drive signal Ds changes from high to low at time t2, the control circuit 12 determines that the non-drive period NDP has begun during which no switching operation is performed on the SiCMOSFET 31. As a result, the control circuit 12 outputs to the drive circuit 11 the control signals Psw, Msw whose voltage level is constant at a low level, and the control signal Nsw whose voltage level is constant at a high level.

[0037] When the voltage levels of the control signals Psw and Msw are low and the voltage level of the control signal Nsw is high, the first switch 111b and the second switch 111c are turned off and the third switch 112b is turned on. As a result, the negative side of the negative voltage generating unit 112a is connected to the gate terminal G of the SiCMOSFET 31 via the gate resistor 115. Therefore, a negative bias voltage VN is applied to the gate terminal G of the SiCMOSFET 31, and the gate terminal G of the SiCMOSFET 31 is in a negative bias state.

[0038] As a result, as shown in Fig. 2, when the voltage levels of the control signals Psw and Msw are low and the voltage level of the control signal Msw is high, the gate-source voltage VGS of the SiCMOSFET 31 becomes equal to the negative bias voltage VN. In this manner, the second voltage application unit 112 (see Fig. 1) applies the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 after the switching operation of the SiCMOSFET 31 is completed. That is, in the driving method according to the present embodiment, the negative bias voltage VN is applied to the gate terminal G of the SiCMOSFET 31 after the switching operation of the SiCMOSFET 31 is completed. Although the details will be described later, by applying the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31, it is possible to suppress fluctuations in the threshold voltage of the SiCMOSFET 31.

[0039] As shown in FIG. 2, at time t3, which is a predetermined time after time t2, the control circuit 12 outputs to the drive circuit 11 control signals Psw and Nsw whose voltage level is constant at a low level, and a control signal Msw whose voltage level is constant at a high level.

[0040] When the voltage levels of the control signals Psw and Nsw are low and the voltage level of the control signal Msw is high, the first switch 111b and the third switch 112b are turned off and the second switch 111c is turned on. As a result, the reference terminal 2 and the source terminal S of the SiCMOSFET 31 are connected to the gate terminal G of the SiCMOSFET 31 via the connection terminal 114 and the gate resistor 115. Therefore, a zero bias voltage VM is applied to the gate terminal G of the SiCMOSFET 31, and the gate terminal G of the SiCMOSFET 31 is in a zero bias state.

[0041] As a result, as shown in FIG. 2, when the voltage levels of the control signals Psw and Nsw are low and the voltage level of the control signal Nsw is high, the gate-source voltage VGS of the SiCMOSFET 31 becomes equal to the zero bias voltage VM, and the SiCMOSFET 31 is turned off.

[0042] By switching the voltage applied to the gate terminal G of the SiCMOSFET 31 from the negative bias voltage VN to the zero bias voltage VM, the fluctuation of the threshold voltage of the SiCMOSFET 31 is suppressed, and the reset period in which the threshold voltage is reset to its initial value ends. That is, the period from time t2 to time t3 corresponds to the reset period, and the reset period is set to, for example, several seconds to several minutes.

[0043] 2, from time t3 until time t4 when a predetermined time has elapsed and the voltage level of the drive signal Ds switches to a high level, the drive circuit 11 continues to apply the zero bias voltage VM to the gate terminal G of the SiCMOSFET 31. When the voltage level of the drive signal Ds switches to a high level at time t4, the drive circuit 11 operates in the same manner as in the period from time t1 to time t2, causing the SiCMOSFET 31 to perform a switching operation.

[0044] In this manner, the first voltage application unit 111 (see FIG. 1) continues to apply the zero bias voltage VM to the gate terminal G of the SiCMOSFET 31 until the switching operation of the SiCMOSFET 31 starts after the negative bias voltage VN is applied to the gate terminal G of the SiCMOSFET 31. In other words, the driving method according to the present embodiment continues to apply the zero bias voltage VM to the gate terminal G of the SiCMOSFET 31 until the switching operation of the SiCMOSFET 31 starts after the negative bias voltage VN is applied to the gate terminal G of the SiCMOSFET 31.

[0045] Therefore, as shown in FIG. 2, in the driving method according to the present embodiment, a negative bias voltage VN with respect to the reference potential is applied to the gate terminal G of the SiCMOSFET 31 only once during a period in which the SiCMOSFET 31 is not subjected to a switching operation.

[0046] The drive circuit 11 does not necessarily apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 once every time the non-driving period NDP occurs, but may apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 as necessary. For example, the drive circuit 11 may apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 only once during the non-driving period NDP after the cumulative driving period DP has elapsed a predetermined period. Therefore, when it is determined that it is not necessary to apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 even during the non-driving period NDP, the drive circuit 11 may not apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 throughout the non-driving period NDP. The drive circuit 11 may apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 once every time the non-driving period NDP occurs.

[0047] In this embodiment, the drive circuit 11 applies the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 immediately after the drive period DP ends (i.e., immediately after switching from the drive period DP to the non-drive period NDP), but this is not limited to the above. For example, the drive circuit 11 may apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 within the non-drive period NDP and after a predetermined time has elapsed since the drive period DP ends. Also, for example, the drive circuit 11 may apply the negative bias voltage VN to the gate terminal G of the SiCMOSFET 31 immediately before the drive period DP starts (i.e., immediately before switching from the non-drive period NDP to the drive period DP). Regardless of which of these timings the negative bias voltage VN is applied to the gate terminal G of the SiCMOSFET 31, the threshold voltage of the SiCMOSFET 31 is reset to its initial value. As a result, throughout the period in which the control device 1 controls the switching operation of the SiCMOSFET 31, in other words, the period in which the drive circuit 11 drives the SiCMOSFET 31 by switching operation, fluctuations in the threshold voltage of the SiCMOSFET 31 are suppressed.

[0048] [Functions and Effects of the Drive Circuit, Control Device, and Drive Method] The operation and effect of the drive circuit, control device, and drive method according to this embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram for explaining the effects of the drive circuit 11, control device 1, and drive method according to this embodiment, and is a graph showing the amount of variation in threshold voltage with respect to the accumulated drive time of the SiCMOSFET. The graph shown in Fig. 3 is a double logarithmic graph, with the horizontal axis showing the actual measured value of the accumulated drive time and the vertical axis showing the actual measured value of the amount of variation with respect to the initial value of the threshold voltage of the SiCMOSFET.

[0049] The operation pattern PTN1 shown in FIG. 3 is a measurement result when the SiCMOSFET is driven in the same manner as the driving method according to the present embodiment. Specifically, the operation pattern PTN1 is a pattern in which a positive bias voltage and a zero bias voltage are alternately and repeatedly applied to the gate terminal of the SiCMOSFET at a predetermined period, and a negative bias voltage is applied only once immediately before measuring the threshold voltage. The operation pattern PTN2 is a pattern in which a positive bias voltage and a zero bias voltage are alternately and repeatedly applied to the gate terminal of the SiCMOSFET at a predetermined period. That is, the operation pattern PTN2 is a pattern similar to the operation pattern PTN1, except that a negative bias voltage is not applied to the gate terminal of the SiCMOSFET. The operation pattern PTN3 is a pattern in which a positive bias voltage and a negative bias voltage are alternately and repeatedly applied to the gate terminal of the SiCMOSFET at a predetermined period. That is, the operation pattern PTN3 is a pattern similar to the operation pattern PTN2, except that a negative bias voltage, not a zero bias voltage, is applied to the gate terminal of the SiCMOSFET.

[0050] Incidentally, it is known that threshold voltage fluctuations are an issue in the reliability of SiCMOSFETs. One of the characteristic fluctuations in SiCMOSFETs is known to be the BTI (bias temperature instability) phenomenon. The BTI phenomenon is thought to occur due to charge being trapped at the gate oxide film interface of SiCMOSFETs when they are subjected to switching operations at high temperatures.

[0051] In the graph shown in FIG. 3, the cumulative drive time T1 with the shortest cumulative drive time and the fluctuation amount ΔV1 with the smallest fluctuation amount of the threshold voltage of the SiCMOSFET are used as the reference. As shown in FIG. 3, in the operation pattern PTN2, the fluctuation amount of the threshold voltage of the SiCMOSFET is actually measured at the cumulative drive times T2b, T3b, T3d, and T4a. The cumulative drive time T2b corresponds to about 65 times the cumulative drive time T1. The cumulative drive time T3b corresponds to about 270 times the cumulative drive time T1. The cumulative drive time T3d corresponds to about 650 times the cumulative drive time T1. The cumulative drive time T4a corresponds to about 1200 times the cumulative drive time T1. The amount of change in the threshold voltage of the SiCMOSFET in the operation pattern PTN2 is approximately 4.8 times the amount of change ΔV1 at cumulative drive time T2b, approximately 55 times at cumulative drive time T3b, approximately 60 times at cumulative drive time T3d, and approximately 50 times at cumulative drive time T4a.

[0052] In the operation pattern PTN3, the variation of the threshold voltage of the SiCMOSFET is actually measured at the cumulative drive times T2a, T3a, T3c, and T3e. The cumulative drive time T2a corresponds to about 45 times the cumulative drive time T1. The cumulative drive time T3a corresponds to about 180 times the cumulative drive time T1. The cumulative drive time T3c corresponds to about 450 times the cumulative drive time T1. The cumulative drive time T3e corresponds to about 750 times the cumulative drive time T1. The variation of the threshold voltage of the SiCMOSFET in the operation pattern PTN3 is about 20 times the variation ΔV1 at the cumulative drive time T2a, about 40 times at the cumulative drive time T3a, about 50 times at the cumulative drive time T3c, and about 65 times at the cumulative drive time T3e.

[0053] Unlike the driving method according to the present embodiment, when a positive bias voltage and a zero bias voltage or a negative bias voltage are repeatedly applied to the gate terminal of the SiCMOSFET and then a negative bias voltage is not applied only once, as in the operation patterns PTN2 and PTN3, the variation in the threshold voltage of the SiCMOSFET tends to continue to increase or to saturate after increasing to a predetermined cumulative drive time. In both of the operation patterns PTN2 and PTN3, the variation in the threshold voltage of the SiCMOSFET becomes 50 times or more larger than the reference variation ΔV1 as the cumulative drive time increases.

[0054] 3, in operation pattern PTN1 corresponding to the driving method according to the present embodiment, the amount of variation in the threshold voltage of the SiCMOSFET is actually measured over the same accumulated driving time as in operation pattern PTN2. The amount of variation in the threshold voltage of the SiCMOSFET in operation pattern PTN2 is approximately 1.2 times the amount of variation ΔV1 at accumulated driving time T2b, approximately 8.5 times at accumulated driving time T3b, approximately 1 time at accumulated driving time T3d, and approximately 1.1 times at accumulated driving time T3d.

[0055] The difference between the fluctuation amount ΔV1 and the fluctuation amount ΔV2 is such that it can be considered as a measurement error. Therefore, unlike the operation patterns PTN2 and PTN3, the operation pattern PTN1 corresponding to the driving method according to the present embodiment shows a tendency to suppress the fluctuation of the threshold voltage of the SiCMOSFET even if the cumulative driving time increases. The inventors have found that the fluctuation of the threshold voltage of the SiCMOSFET can be suppressed by repeatedly applying a positive bias voltage and a zero bias voltage to the gate terminal of the SiCMOSFET and then applying a negative bias voltage only once, as in the operation pattern PTN1. In other words, it is considered that the charge trapped at the gate oxide film interface, which is considered to be the cause of the fluctuation of the threshold voltage of the SiCMOSFET, can be released from the gate oxide film interface by applying a negative bias voltage only once to the gate terminal of the SiCMOSFET, even if the charge does not have a complex voltage waveform such as a voltage whose amplitude gradually attenuates while alternating between positive and negative voltages.

[0056] Therefore, in the drive circuit 11, the control device 1, and the drive method according to the present embodiment, a negative bias voltage with respect to a reference potential is applied to the gate terminal of the SiCMOSFET only once during a period in which the SiCMOSFET is not subjected to switching operation. As a result, the drive circuit 11, the control device 1, and the drive method according to the present embodiment can release the charge trapped at the gate oxide film interface of the SiCMOSFET during the period in which the SiCMOSFET is operated. As a result, the drive circuit 11, the control device 1, and the drive method according to the present embodiment can suppress fluctuations in the threshold voltage of the SiCMOSFET.

[0057] In the drive circuit 11, the first voltage application unit 111 that generates a positive bias voltage and a zero bias voltage for switching the SiCMOSFET is configured with a single power supply. Furthermore, in the drive circuit 11, the second voltage application unit 112 that generates a zero bias voltage for resetting the threshold voltage of the SiCMOSFET is also configured with a single power supply. Therefore, the drive circuit 11, the control device 1, and the drive method according to the present embodiment can simplify the circuit configuration for suppressing fluctuations in the threshold voltage of the SiCMOSFET.

[0058] As described above, the drive circuit 11 according to the present embodiment includes a first voltage application unit 111 that alternately applies a positive bias voltage VP and a zero bias voltage VM with respect to a reference potential to the gate terminal G of the SiCMOSFET 31 when the SiCMOSFET 31 is subjected to switching operation, and a second voltage application unit 112 that applies a negative bias voltage VN with respect to the reference potential only once to the gate terminal of the SiCMOSFET 31 during a period when the SiCMOSFET 31 is not subjected to switching operation.

[0059] The control device 1 according to this embodiment also includes a drive circuit 11 according to this embodiment, and a control circuit 12 that controls the timing at which the drive circuit 11 applies a positive bias voltage VP, a zero bias voltage VM, and a negative bias voltage VN to the gate terminal G of the SiCMOSFET 31.

[0060] Furthermore, in the driving method of the present embodiment, when performing switching operation on the SiCMOSFET 31, a positive bias voltage VP and a zero bias voltage VM with respect to a reference potential are alternately applied to the gate terminal G of the SiCMOSFET 31, and a negative bias voltage VN with respect to the reference potential is applied only once to the gate terminal G of the SiCMOSFET 31 during a period in which the SiCMOSFET 31 is not performing switching operation.

[0061] According to the drive circuit 11, control device 1, and drive method of this embodiment having such a configuration, it is possible to simplify the circuit configuration for suppressing fluctuations in the threshold voltage of the semiconductor switching element.

[0062] The present invention is not limited to the above-described embodiment, and various modifications are possible. In the above embodiment, the first voltage application unit 111 has a positive voltage generation unit 111a configured with a DC power supply, and the second voltage application unit 112 has a negative voltage generation unit 112a configured with a DC power supply, but the present invention is not limited to this. For example, each of the positive voltage generation unit and the negative voltage generation unit may be configured with an operational amplifier or a transistor. In this case, the operational amplifier and the transistor only need to be configured to be able to output a DC voltage of a predetermined voltage level, so compared with the positive voltage generation unit 111a and the negative voltage generation unit 112a in the above embodiment, the circuit configuration is hardly complicated and the circuit scale is hardly increased. Therefore, even if a drive circuit is provided with a positive voltage generation unit and a negative voltage generation unit having an operational amplifier or a transistor, the same effect as the above embodiment can be obtained.

[0063] In the above embodiment, the potential of the zero bias voltage is set to the reference potential, but the present invention is not limited to this. For example, when applying a zero bias voltage to the gate terminal of a SiCMOSFET, as long as the gate-source voltage of the SiCMOSFET has the same potential, the potential of the zero bias voltage may be a potential other than the reference potential. In this case, the same effect as in the above embodiment can be obtained.

[0064] In the above embodiment, the negative bias voltage has a rectangular voltage waveform, but the present invention is not limited to this. For example, the negative bias voltage may have a voltage waveform such as a sawtooth wave or a triangular wave, and the same effect as the above embodiment can be obtained.

[0065] The scope of the present invention is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the object of the present invention. Furthermore, the scope of the present invention is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective features disclosed. [Explanation of symbols]

[0066] 1 Control device 2 Reference terminal 11 Drive circuit 12 Control circuit 31 SiC MOSFET 32 DC power supply 33 Resistance element 111 First voltage application unit 111a Positive voltage generator 111b First Switch 111c Second Switch 112 Second voltage application unit 112a Negative voltage generating unit 112b Third Switch 113,114 Connection terminal 115 Gate resistor D Drain terminal Ds drive signal G Gate terminal Msw, Nsw, Psw control signals S Source terminal SiCMOS reference terminal SiCMOS gate terminal

Claims

1. a first voltage application unit that alternately applies a positive bias voltage and a zero bias voltage with respect to a reference potential to a gate terminal of a field effect transistor having a silicon carbide substrate when the field effect transistor is subjected to a switching operation; a second voltage application unit that applies a negative bias voltage with respect to the reference potential to the gate terminal only once during a period in which the field effect transistor is not switched; A drive circuit comprising:

2. The second voltage application unit applies the negative bias voltage to the gate terminal after the switching operation of the field effect transistor is completed.

2. The drive circuit according to claim 1.

3. The first voltage application unit continues to apply the zero bias voltage to the gate terminal until a switching operation of the field effect transistor starts after the negative bias voltage is applied to the gate terminal.

3. The drive circuit according to claim 2.

4. The first voltage application unit is a positive voltage generating unit that generates the positive bias voltage; a first switch that connects the positive voltage generating unit to the gate terminal; a second switch connecting the gate terminal to a reference terminal fixed to the reference potential; having The second voltage application unit is a negative voltage generating unit that generates the negative bias voltage; a third switch that connects the negative voltage generating unit to the gate terminal; have 2. The drive circuit according to claim 1.

5. A drive circuit according to any one of claims 1 to 3; a control circuit that controls a timing at which the drive circuit applies the positive bias voltage, the zero bias voltage, and the negative bias voltage to the gate terminal; A control device comprising:

6. The first voltage application unit is a positive voltage generating unit that generates the positive bias voltage; a first switch that connects the positive voltage generating unit to the gate terminal; a second switch connecting a reference terminal fixed to the reference potential to the gate terminal; having The second voltage application unit is a negative voltage generating unit that generates the negative bias voltage; a third switch that connects the negative voltage generating unit to the gate terminal; having The control circuit outputs a control signal to the drive circuit to control a switching operation of each of the first switch, the second switch, and the third switch. The control device according to claim 5.

7. When a field effect transistor having a silicon carbide substrate is subjected to a switching operation, a positive bias voltage and a zero bias voltage are alternately applied to a gate terminal of the field effect transistor with respect to a reference potential; A negative bias voltage with respect to the reference potential is applied to the gate terminal only once during a period in which the field effect transistor is not switched. Drive method.

8. After the switching operation of the field effect transistor is completed, the negative bias voltage is applied to the gate terminal. The driving method according to claim 7.

9. The zero bias voltage is continued to be applied to the gate terminal until the field effect transistor starts to perform a switching operation after the negative bias voltage is applied to the gate terminal. The driving method according to claim 7 or 8.

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