Test circuit and clock circuit

Abstract

To easily make a determination relating to an oscillatory frequency of a clock signal output from an oscillation circuit.SOLUTION: A test circuit includes: a counter circuit that counts a clock of a clock signal having a preset oscillatory frequency output from an oscillation circuit; a plurality of comparison circuits that receive a plurality of different clock standard values to compare the clock count values counted by the counter circuit with the plurality of clock standard values, respectively; and a determination unit that makes a determination relating to the oscillatory frequency on the basis of comparison results of the plurality of comparison circuits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed technology relates to a test circuit and a clock circuit. [Background technology]

[0002] Patent Document 1 describes a method for testing an integrated circuit in which a loop filter and a voltage-controlled oscillator are connected to an integrated circuit incorporating a phase comparator, a charge pump, and a prescaler to test the PLL circuit, the method comprising: a first process for setting a division ratio in the prescaler and generating a clock signal at the same time as the PLL circuit starts a lock-up operation; and a second process for measuring the output frequency of the voltage-controlled oscillator at each rising or falling edge of the clock signal. a second process of counting the number of clocks from the generation of the clock signal; a third process of storing the measured value of the output frequency of the voltage controlled oscillator and the count value of the number of clocks at the time of the measurement; and a fourth process of sequentially determining the difference between the measured frequency when the count value of the number of clocks is m (m is an integer equal to or greater than 1) and the measured frequency when the count value of the number of clocks is m+n (n is an integer equal to or greater than 1) while updating the value of m until it falls within a standard range, and a method for testing an integrated circuit is disclosed, characterized in that the value of m when the difference determined in the fourth process falls within the standard range is determined to be the count value of the number of clocks at the time when the PLL circuit is locked.

[0003] Patent Document 2 discloses a test circuit for a clock generation circuit that measures the center frequency of a clock signal output from a clock generation circuit having a frequency modulation function that generates a clock signal by adding a predetermined analog modulated wave signal to a control voltage to a voltage controlled oscillator, the test circuit comprising: an A / D conversion circuit that converts the analog modulated wave signal into a digital signal and outputs it; a counter that counts the period of the clock signal output from the clock generation circuit in response to the digital signal from the A / D conversion circuit; a counter memory that stores the count value of the counter; a standard value memory that stores a predetermined standard value of the center frequency of the clock signal output from the clock generation circuit; and a comparison circuit that compares the value stored in the counter memory with the standard value stored in the standard value memory and outputs the comparison result.

[0004] Patent Document 3 discloses a clock loss detection circuit that detects a loss of an input clock signal input to a clock receiving circuit including a phase-locked oscillator, comprising: an input counter circuit that counts 1 / n (n is a positive integer greater than 1) of the number of clocks of the input clock signal and outputs it as an input phase comparison signal; a phase-locked oscillator circuit that receives an output phase comparison signal formed based on its own output and the input phase comparison signal, performs phase comparison and generates a clock signal that ensures phase synchronization and frequency synchronization with the input clock signal; an output counter circuit that counts 1 / n of the clock signal output by the phase-locked oscillator circuit and outputs it as the output phase comparison signal; and an alarm circuit that determines a loss of the input clock signal based on the count number of the input clock signal, the count of which is set by the input clock signal and reset by the output phase comparison signal, and outputs an alarm signal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2004-015366 A [Patent Document 2] JP 2006-333119 A [Patent Document 3] Japanese Patent Application Publication No. 4-104615 Summary of the Invention [Problem to be solved by the invention]

[0006] One method for testing whether the oscillation frequency of a clock signal output from an oscillator circuit is normal is to test the oscillation period by measuring the rising and falling timing of a divided signal obtained by dividing the clock signal by N (e.g., 8) while changing the strobe signal using a tester. Another method is to measure the number of clocks in a clock signal, output a pulse signal when the number of clocks reaches 1000, and determine that the signal is normal if a pulse signal is detected between the lower and upper limits using a tester.

[0007] However, when testing the oscillation period using the above method, it is necessary to repeatedly perform measurements while gradually changing the strobe signal, which poses the problem that the test is time-consuming and cumbersome.

[0008] In addition, when correcting the oscillation frequency, the correction setting value needs to be calculated outside the oscillation circuit based on the measured value of the oscillation period, which requires the use of a high-performance tester, making testing complicated.

[0009] The disclosed technology has been made to solve the above-mentioned problems, and aims to provide a test circuit and a clock circuit that can easily determine the oscillation frequency of a clock signal output from an oscillator circuit. [Means for solving the problem]

[0010] The test circuit according to the first aspect includes a counter circuit which counts the clocks of a clock signal having a preset oscillation frequency output from an oscillation circuit, a plurality of comparison circuits to which different clock standard values ​​are respectively input and which compare the clock count value of the clock counted by the counter circuit with each of the plurality of clock standard values, and a judgment unit which makes a judgment regarding the oscillation frequency based on the comparison results of the plurality of comparison circuits.

[0011] A clock circuit according to a second aspect includes an oscillator circuit that outputs a clock signal, and the test circuit according to the first aspect. Effect of the Invention

[0012] The disclosed technique has the effect of easily determining and correcting the oscillation frequency of a clock signal output from an oscillation circuit. [Brief description of the drawings]

[0013] [Figure 1] FIG. 2 is a configuration diagram of a clock circuit. [Diagram 2] FIG. 13 is a diagram showing a table relating to correction setting values. [Diagram 3] FIG. 11 is a diagram illustrating an example of a clock standard value. [Figure 4] 13 is a diagram showing the correspondence relationship between the output pattern of a comparison circuit and a correction setting value. FIG. [Diagram 5] 13 is a diagram showing the correspondence relationship between the measured clock count value, the output of the comparison circuit, and the correction setting value. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an example of an embodiment of the disclosed technology will be described with reference to the drawings.

[0015] First Embodiment

[0016] As shown in FIG. 1, a clock circuit 10 includes an oscillator circuit 12 and a test circuit 14.

[0017] The oscillator circuit 12 outputs a clock signal having a set oscillation frequency to an external circuit (not shown), and also outputs the clock signal to a test circuit 14 that performs a determination regarding the oscillation frequency of the clock signal.

[0018] The test circuit 14 includes a counter circuit 16, n comparison circuits 18-1 to 18-n (n≧2), and a determination unit 20.

[0019] The counter circuit 16 counts the clocks of the clock signal having a preset oscillation frequency output from the oscillation circuit 12. The counter circuit 16 outputs the clock count values ​​of the counted clocks to the plurality of comparison circuits 18-1 to 18-n. Specifically, the counter circuit 16 receives a count execution signal from an external device (not shown), starts counting the clocks when the count execution signal switches from a low level to a high level, for example, and ends counting the clocks when the count execution signal switches from a high level to a low level.

[0020] A plurality of different clock standard values ​​are input to the plurality of comparison circuits 18-1 to 18-n, respectively, and the comparison circuits 18-1 to 18-n compare the count value of the clock counted by the counter circuit 16 with each of the plurality of clock standard values.

[0021] 1, a predetermined clock standard value 1 is input to the comparison circuit 18-1. The comparison circuit 18-1 compares the clock count value output from the counter circuit 16 with the clock standard value 1, and outputs the comparison result to the judgment unit 20. Specifically, the comparison circuit 18-1 outputs a high level (H) signal to the judgment unit 20 when the clock count value is equal to or greater than the clock standard value 1, and outputs a low level (L) signal to the judgment unit 20 when the clock count value is less than the clock standard value 1. The comparison circuits 18-2 to 18-n each receive predetermined clock standard values ​​2 to n, and perform a comparison process similar to that of the comparison circuit 18-1.

[0022] The judgment unit 20 makes a judgment regarding the oscillation frequency based on the comparison results of the multiple comparison circuits 18-1 to 18-n.

[0023] In this embodiment, a case will be described in which the test circuit 14 includes two comparison circuits 18-1 and 18-2, and the determination unit 20 determines whether or not the oscillation frequency is within the allowable range.

[0024] The comparator circuit 18-1 compares the clock count value with a clock standard value 1 as a first clock standard value indicating a predetermined lower limit value smaller than a reference clock count value corresponding to a preset oscillation frequency. If the clock count value is equal to or greater than the clock standard value 1, i.e., equal to or greater than the lower limit value, the comparator circuit 18-1 outputs a high-level signal to the judgment unit 20, and if the clock count value is less than the lower limit value, the comparator circuit 18-1 outputs a low-level signal to the judgment unit 20.

[0025] The comparator circuit 18-2 compares the clock count value with a clock standard value 2, which is a second clock standard value indicating a predetermined upper limit value that is greater than a reference clock count value corresponding to a preset oscillation frequency. If the clock count value is equal to or greater than the clock standard value 2, i.e., equal to or greater than the upper limit value, the comparator circuit 18-2 outputs a high-level signal to the decision unit 20, and if the clock count value is less than the upper limit value, the comparator circuit 18-2 outputs a low-level signal to the decision unit 20.

[0026] The determination unit 20 determines that the oscillation frequency is within the allowable range when the signal input from the comparison circuit 18-1 is a high-level signal and the signal input from the comparison circuit 18-2 is a low-level signal. That is, the oscillation circuit 12 determines that the oscillation frequency is within the allowable range when the clock count value is equal to or greater than the lower limit and less than the upper limit.

[0027] For example, assume that the preset oscillation frequency is 10 MHz, and the period during which the count execution signal becomes high level, i.e., the count period for counting the number of clocks, is set to 100 μs. In this case, the reference clock count value corresponding to the oscillation frequency to be counted during the count period is 1000. If the allowable range is, for example, ±1% of the preset oscillation frequency, the clock standard value 1, which is the lower limit, is set to 990, and the clock standard value 2, which is the upper limit, is set to 1010. Therefore, when the clock count value is 990 or more and less than 1010, the determination unit 20 determines that the clock signal is normal because the oscillation frequency is within the allowable range, and when the clock count value is less than 990 or greater than 1010, the determination unit 20 determines that the clock signal is abnormal because the oscillation frequency is outside the allowable range.

[0028] If you want to know the value of the oscillation period, you can calculate it by dividing the time of the count period during which the count execution signal is at high level by the clock count value. For example, if the count period is 100 μs and the clock count value is 1000, the oscillation period is 100 ns.

[0029] In this manner, in this embodiment, whether or not the clock signal is normal is determined based on the comparison result of the comparator circuit 18-1, which compares the clock count value with the clock standard value 1 indicating a lower limit value smaller than the reference clock count value corresponding to the oscillation frequency, and the comparison result of the comparator circuit 18-2, which compares the clock count value with the clock standard value 2 indicating an upper limit value larger than the reference clock count value. Therefore, when testing the clock signal, it is not necessary to repeatedly perform measurements while gradually changing the strobe signal, and the time required for testing can be shortened.

[0030] <Second embodiment>

[0031] Next, a second embodiment will be described. Note that the clock circuit 10 according to the second embodiment is the same as that of the first embodiment, and therefore the description thereof will be omitted.

[0032] The oscillation frequency of the clock signal output from the oscillation circuit 12 may vary due to various reasons such as variations in characteristics during manufacturing, temperature changes, and fluctuations in power supply voltage, and may require correction (trimming) of the oscillation frequency. Therefore, in this embodiment, a case will be described in which the degree of fluctuation of the oscillation frequency is determined and the oscillation frequency is corrected according to the determined degree of fluctuation.

[0033] In this embodiment, the oscillator circuit 12 is capable of setting n correction setting values ​​for performing n-stage correction of the oscillation frequency.

[0034] Furthermore, the determination unit 20 sets in the oscillation circuit 12 a correction setting value that corresponds to the degree of fluctuation in the oscillation frequency.

[0035] In this embodiment, the multiple comparison circuits 18-1 to 18-n each compare the clock count value with n (n is an integer equal to or greater than 2) clock standard values ​​that are predetermined within a predetermined range including a reference clock count value corresponding to the oscillation frequency.

[0036] As an example, in this embodiment, a case where the correction setting value set in the oscillation circuit 12 can be set in eight stages from 0 to 7, that is, a case where n=7, will be described.

[0037] The comparator circuits 18-1 to 18-7 are respectively input with the clock standard values ​​1 to 7. In the following, the comparator circuits 18-1 to 18-7 are referred to as comparator circuits 1 to 7.

[0038] Here, a method for setting the clock standard values ​​1 to 7 will be described. For the sake of simplicity, a case will be described in which the oscillation frequency is 10 MHz, the clock count period is 100 μs, and the reference clock count value is 1000. It is also assumed that the oscillation frequency may fluctuate within a range of about ±20%, and the correction setting value is set as shown in FIG. 2. In the example of FIG. 2, if the correction setting value is "0", no correction is performed. In the example of FIG. 2, if the correction range is within a correction range of about 5% centered on the reference clock count value, no correction is performed. Therefore, as shown in FIG. 2, the center value of the range in which the correction setting value "0" is selected is set to 1000, the lower limit is set to 976, and the upper limit is set to 1026. Therefore, if the measured clock count value is 976 or more and less than 1026, the correction setting value "0" is selected, and no correction of the oscillation frequency is performed.

[0039] When the correction setting value is "1", the oscillation frequency is corrected so that the clock count value becomes 1050. In other words, when "1" is set as the correction setting value, the oscillation frequency becomes 1.05 times.

[0040] Therefore, when the oscillation frequency fluctuates and the oscillation period becomes 1.05 times, the oscillation frequency is corrected to 9.5 MHz by setting the correction setting value to "1". This causes the clock count value to be close to the reference clock count value of 1000. For this reason, as shown in FIG. 2, the count value "952", which is the value closest to the reference clock count value of 1000 when the measured clock count value is multiplied by 1.05, is set as the center value of the range in which the correction setting value "1" is applied. Then, the lower limit and upper limit are set to a range of about 5% from the center value of the range in which the correction setting value "1" is applied. In the example of FIG. 2, the lower limit is set to 931 and the upper limit is set to 976. Therefore, when the measured clock count value is 931 or more and less than 976, the correction setting value "1" is selected and the oscillation frequency is corrected to be 1.05 times. Similarly, for each of the correction setting values ​​"2" to "7," the center value, lower limit value, and upper limit value of the range in which the correction setting value is applied are set.

[0041] As described above, the center value, lower limit value, and upper limit value of the range in which the correction setting value is applied are set for each of the correction setting values ​​"0" to "7." Note that, as shown in Fig. 2, the lower limit value of the range in which the correction setting value "0" is applied and the upper limit value of the range in which the correction setting value "4" is applied are not set.

[0042] Then, as shown in FIG. 3, the upper limit values ​​"889", "931", "976", "1026", "1082", "1144", and "1213" of the range to which the correction setting values ​​"0" to "7" are applied are set as clock standard values ​​1 to 7.

[0043] 2 is an example assuming that ideal correction is performed, and there are cases where ideal correction cannot be performed. Therefore, each of all correction set values ​​may be set in the oscillation circuit 12 and oscillated at an oscillation frequency, and at least one of the clock count value, oscillation period, and oscillation frequency may be measured, and the clock standard value may be set based on the measurement result. More specifically, the correction magnification may be calculated based on the measurement result of measuring at least one of the clock count value, oscillation period, and oscillation frequency, and the center value, lower limit value, and upper limit value (clock standard value) of the range to which each of the correction set values ​​"0" to "7" is applied may be set based on the calculated magnification.

[0044] 2 and 3, the correspondence between the outputs (H / L) of the comparator circuits 1 to 7 and the correction set values ​​is as shown in FIG.

[0045] The judgment unit 20 sets a correction setting value corresponding to the degree of fluctuation in the oscillation frequency using table data showing the correspondence between the comparison results of the comparison circuits 1 to 7 and the correction setting value as shown in Fig. 4. Then, the judgment unit 20 changes the setting of the oscillation circuit 12 based on the set value. This makes it possible to maintain the clock count value at a value close to 1000, and suppress fluctuations in the oscillation frequency, even in a situation where the oscillation frequency may fluctuate due to temperature changes, fluctuations in the power supply voltage, etc.

[0046] 5 shows a specific example of the correction setting value set for the measured clock count value. As shown in FIG. 5, when the measured clock count value is 850, all the outputs of the comparison circuits 1 to 7 are at a low level. Therefore, the judgment unit 20 selects "3" as the correction setting value and sets it in the oscillation circuit 12. As a result, the oscillation frequency is corrected so that the clock count value becomes larger, that is, so that the oscillation frequency becomes higher.

[0047] Furthermore, when the measured clock count value is 950, the outputs of the comparator circuits 1 and 2 are at high level, and the outputs of the comparator circuits 3 to 7 are at low level. Therefore, the judgment unit 20 selects "1" as the correction setting value and sets it in the oscillator circuit 12. As a result, the oscillation frequency is corrected so that the clock count value becomes larger, that is, the oscillation frequency becomes higher.

[0048] Furthermore, when the measured clock count value is 1099, the outputs of the comparator circuits 1 to 5 are at high level, and the outputs of the comparator circuits 6 and 7 are at low level. Therefore, the judgment unit 20 selects "6" as the correction setting value and sets it in the oscillation circuit 12. As a result, the oscillation frequency is corrected so that the clock count value becomes smaller, that is, the oscillation frequency becomes lower.

[0049] Furthermore, when the measured clock count value is 1215, the outputs of the comparison circuits 1 to 7 all become high level. Therefore, the judgment unit 20 selects "4" as the correction setting value and sets it in the oscillation circuit 12. As a result, the oscillation frequency is corrected so that the clock count value becomes smaller, that is, the oscillation frequency becomes lower.

[0050] In this manner, in this embodiment, the comparator circuits 1 to 7 compare the clock count value with different clock standard values, and the judgment unit 20 sets a setting value for correcting the oscillation frequency based on the comparison results of the comparator circuits 1 to 7. This eliminates the need to set a correction setting value outside the clock circuit 10, and allows the oscillation frequency to be easily corrected.

[0051] Regarding the above embodiment, the following supplementary notes are further disclosed.

[0052] (Appendix 1) a counter circuit that counts clocks of a clock signal having a preset oscillation frequency output from the oscillation circuit; a plurality of comparison circuits to which a plurality of different clock standard values ​​are input, and which compare a clock count value of the clock counted by the counter circuit with each of the plurality of clock standard values; a determination unit that performs a determination regarding the oscillation frequency based on a comparison result of the plurality of comparison circuits; A test circuit comprising: (Appendix 2) the plurality of comparison circuits are comprised of a first comparison circuit which compares the clock count value with a first clock standard value which indicates a predetermined lower limit value which is smaller than a reference clock count value corresponding to the oscillation frequency, and a second comparison circuit which compares the clock count value with a second clock standard value which indicates a predetermined upper limit value which is larger than the reference clock count value; the determination unit determines that the clock signal is normal when the comparison result of the first comparison circuit indicates that the clock count value is equal to or greater than the first clock standard value and when the comparison result of the second comparison circuit indicates that the clock count value is less than the second clock standard value. Test circuit described in Appendix 1. (Appendix 3) the plurality of comparison circuits are composed of n comparison circuits each comparing the clock count value with n predetermined clock standard values ​​(n is an integer of 2 or more) within a predetermined range including a reference clock count value corresponding to the oscillation frequency, The determination unit determines a degree of fluctuation in the oscillation frequency based on the comparison results of the n comparison circuits. Test circuit described in Appendix 1. (Appendix 4) the oscillation circuit is capable of setting n correction setting values ​​for performing n-stage correction of the oscillation frequency; The determination unit sets a correction setting value corresponding to the degree of the fluctuation in the oscillation circuit. Test circuit described in Appendix 3. (Appendix 5) The determination unit sets a correction setting value corresponding to the degree of the fluctuation using table data indicating a correspondence relationship between the comparison results of the n comparator circuits and the correction setting value. Test circuit described in Appendix 4. (Appendix 6) The n clock standard values ​​are values ​​that are set based on the measured oscillation frequency that is measured when the n correction setting values ​​are sequentially set in the oscillation circuit and the circuit oscillates at the oscillation frequency. 5. A test circuit as described in appendix 3 or appendix 4. (Appendix 7) an oscillator circuit that outputs a clock signal; A test circuit according to any one of claims 1 to 6; A clock circuit comprising: [Explanation of symbols]

[0053] 10 Clock Circuit 12 Oscillator Circuit 14 Test Circuit 16 Counter Circuit 18-1~18-n Comparison circuit 20 Judgment section

Claims

1. a counter circuit that counts clocks of a clock signal having a preset oscillation frequency output from the oscillation circuit; a plurality of comparison circuits to which a plurality of different clock standard values ​​are input, and which compare a clock count value of the clock counted by the counter circuit with each of the plurality of clock standard values; a determination unit that performs a determination regarding the oscillation frequency based on a comparison result of the plurality of comparison circuits; A test circuit comprising:

2. the plurality of comparison circuits are comprised of a first comparison circuit which compares the clock count value with a first clock standard value which indicates a predetermined lower limit value which is smaller than a reference clock count value corresponding to the oscillation frequency, and a second comparison circuit which compares the clock count value with a second clock standard value which indicates a predetermined upper limit value which is larger than the reference clock count value, the determination unit determines that the clock signal is normal when the comparison result of the first comparison circuit indicates that the clock count value is equal to or greater than the first clock standard value and when the comparison result of the second comparison circuit indicates that the clock count value is less than the second clock standard value.

2. The test circuit of claim 1.

3. the plurality of comparison circuits are composed of n comparison circuits each comparing the clock count value with n predetermined clock standard values ​​(n is an integer of 2 or more) within a predetermined range including a reference clock count value corresponding to the oscillation frequency, The determination unit determines a degree of fluctuation in the oscillation frequency based on the comparison results of the n comparison circuits.

2. The test circuit of claim 1.

4. the oscillation circuit is capable of setting n correction setting values ​​for performing n-stage correction of the oscillation frequency, The determination unit sets a correction setting value corresponding to the degree of the fluctuation in the oscillation circuit.

4. The test circuit according to claim 3.

5. The determination unit sets a correction setting value corresponding to the degree of the fluctuation using table data indicating a correspondence relationship between the comparison results of the n comparator circuits and the correction setting value.

5. The test circuit according to claim 4.

6. The n clock standard values ​​are values ​​that are set based on a measurement result when each of the n correction setting values ​​is set in the oscillation circuit, the oscillation circuit oscillates at the oscillation frequency, and at least one of a clock count value, an oscillation period, and an oscillation frequency is measured.

4. The test circuit according to claim 3.

7. an oscillator circuit that outputs a clock signal; A test circuit according to any one of claims 1 to 6; A clock circuit comprising:

Images