Image sensor

Abstract

To provide an image sensor in which the conversion gain (CG) is improved, the arrangement efficiency and size of pixel transistors are increased, and a metal wiring layer is reduced.SOLUTION: An image sensor of the present invention includes a pixel including two photodiodes (PDs) disposed on both sides in a first direction, a deep trench isolation (DTI) structure including an internal DTI structure that separates the two PDs in the pixel from each other and extends in a second direction that is orthogonal to the first direction and an external DTI structure that separates the pixels from each other and extends in the first direction or the second direction, a floating diffusion (FD) region that is disposed between a central part of the external DTI structure extending in the first direction and an edge of the internal DTI structure, and a transmission gate (TG) disposed adjacent to the FD region and disposed at least one by one in the PD. The two PDs in the pixel share the FD region.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an image sensor, and more particularly to an image sensor including a two-photodiode (PD) pixel structure. [Background technology]

[0002] An image sensor is configured by arranging a plurality of unit pixels in a two-dimensional array. In general, a unit pixel is configured with one photodiode and a plurality of pixel transistors. Here, the pixel transistor includes, for example, a transfer transistor, a reset transistor, a source follower transistor, and a selection transistor. Recently, as pixel sizes are becoming smaller, a so-called shared pixel structure in which a pixel transistor is shared by a plurality of pixels in order to increase the area of ​​a photodiode is adopted in image sensors. In such a shared pixel structure, each pixel is isolated from each other by a deep trench isolation (DTI) structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,609,250 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor which increases the layout efficiency and size of pixel transistors. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to one embodiment of the present invention includes a pixel having two photodiodes (PD) arranged on both sides in a first direction, an internal deep trench isolation (DTI) structure separating the two PDs in the pixel from each other and extending in a second direction perpendicular to the first direction, and an external DTI structure separating the pixels from each other and extending in the first direction or the second direction, a floating diffusion (FD) region arranged between a central portion of the external DTI structure extending in the first direction and an edge of the internal DTI structure, and transfer gates (TG) arranged adjacent to the FD region and at least one for each of the PDs, and the two PDs in the pixel share the FD region.

[0006] In order to achieve the above object, an image sensor according to another aspect of the present invention includes a shared pixel including four pixels, each including two photodiodes (PD) arranged on both sides in a first direction; an internal deep trench isolation (DTI) structure separating the two PDs in the pixel from each other and extending in a second direction perpendicular to the first direction, and an external DTI structure separating the pixels from each other and extending in the first direction or the second direction; a floating diffusion (FD) region disposed between a central portion of the external DTI structure extending in the first direction and an edge of the internal DTI structure; transmission gates (TG) disposed adjacent to the FD region and at least one on each of the PDs; a reset gate (RG) disposed in any one of the pixels of the shared pixel and arranged in an outer portion of the shared pixel; and a source follower gate (SF) disposed in at least another of the pixels of the shared pixel and arranged adjacent to the RG in the outer portion of the shared pixel, wherein the two PDs in the pixel share the FD region.

[0007] In order to achieve the above-mentioned object, an image sensor according to yet another aspect of the present invention includes a shared pixel composed of four pixels, each having two photodiodes (PD) arranged on both sides in a first direction, an internal deep trench isolation (DTI) structure separating the two PDs in the pixel from each other and extending in a second direction perpendicular to the first direction, and an external DTI structure separating the pixels from each other and extending in the first direction or the second direction, a floating diffusion (FD) region arranged between a central portion of the external DTI structure extending in the first direction and an edge of the internal DTI structure, and a transmission gate (TG) arranged adjacent to the FD region and at least one on each of the PDs, wherein two of the pixels adjacent to each other in the second direction constitute a sub-shared pixel, and the shared pixel includes two of the sub-shared pixels adjacent to each other in the first direction, the FD region is arranged between two of the sub-shared pixels, and the four PDs of the sub-shared pixel share the FD region. Effect of the Invention

[0008] The image sensor of the present invention can improve the conversion gain (CG), increase the layout efficiency and size of pixel transistors, and reduce the number of metal wiring layers. [Brief description of the drawings]

[0009] [Figure 1] 2 is an equivalent circuit diagram corresponding to a shared pixel of an image sensor according to an embodiment of the present invention; [Diagram 2] 2 is a plan view illustrating a first example of a shared pixel of the image sensor of FIG. 1; [Figure 3A] FIG. 11 is a plan view showing a wiring routine for an FD region in an image sensor of a comparative example. [Figure 3B] 2 is a plan view showing a wiring routine of an FD area in the image sensor of FIG. 1. [Figure 4A]FIG. 4 is a plan view illustrating a second example of a shared pixel of an image sensor according to an embodiment of the present invention. [Figure 4B] FIG. 11 is a plan view illustrating a third example of a shared pixel of an image sensor according to an embodiment of the present invention. [Figure 5A] FIG. 11 is a plan view illustrating a fourth example of a shared pixel of an image sensor according to an embodiment of the present invention. [Figure 5B] 2 is a cross-sectional view of an example of a transmission gate portion according to an embodiment of the present invention. [Figure 5C] 11 is a cross-sectional view showing another example of a transmission gate portion according to an embodiment of the present invention. [Figure 6A] FIG. 11 is a plan view illustrating a fifth example of a shared pixel of an image sensor according to an embodiment of the present invention. [Figure 6B] FIG. 1 is a plan view showing a wiring routine for an FD area according to one embodiment of the present invention. [Figure 7] FIG. 13 is a plan view illustrating a sixth example of a shared pixel of an image sensor according to an embodiment of the present invention. [Figure 8A] FIG. 2 is a plan view showing an example of a microlens arrangement of a shared pixel of an image sensor according to an embodiment of the present invention. [Figure 8B] 11 is a plan view showing another example of a microlens arrangement of a shared pixel of an image sensor according to an embodiment of the present invention. FIG. [Figure 9] FIG. 2 is a plan view illustrating the separation distance of the DTI structures of the shared pixels of the image sensor according to one embodiment of the present invention. [Figure 10] FIG. 2 is a plan view showing the width of a DTI structure of a shared pixel of an image sensor according to one embodiment of the present invention. [Figure 11] FIG. 13 is a plan view illustrating a modified example of the third example of the shared pixel of the image sensor according to an embodiment of the present invention. [Figure 12] 3 is a plan view showing a structure in which shared pixels of the image sensor in FIG. 2 are arranged in a two-dimensional array. [Figure 13] 1 is a block diagram showing an overall structure of an image sensor according to an embodiment of the present invention; [Figure 14]1 is a block diagram illustrating an electronic device including an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are designated by the same reference numerals, and duplicated descriptions thereof will be omitted.

[0011] FIG. 1 is an equivalent circuit diagram corresponding to a shared pixel of an image sensor according to an embodiment of the present invention, and FIG. 2 is a plan view showing a first example of the shared pixel of the image sensor of FIG.

[0012] 1 and 2, the image sensor 100 of this embodiment includes a number of shared pixels SPX arranged in a two-dimensional array on a substrate. The shared pixel SPX includes four unit pixels PXs arranged in a 2×2 structure. For example, the four unit pixels PXs include first to fourth unit pixels (PX1 to PX4). Hereinafter, the "unit pixel" will be simply referred to as "pixel".

[0013] Each of the first to fourth pixels (PX1 to PX4) includes two photodiodes (PD) 110. Specifically, the first pixel PX1 includes first and second PDs (PD1-1, PD1-2), the second pixel PX2 includes third and fourth PDs (PD2-1, PD2-2), the third pixel PX3 includes fifth and sixth PDs (PD3-1, PD3-2), and the fourth pixel PX4 includes seventh and eighth PDs (PD4-1, PD4-2).

[0014] Each of the four pixels PXs includes at least one of two PDs 110, a part of a floating diffusion (FD) region 140, and a pixel transistor. In the vertical structure, the pixel transistor is disposed on a surface portion of a substrate (see 101 in FIG. 5C), and the PD 110 is disposed inside the substrate 101. For example, the PD 110 is disposed under an active region 160 constituting a pixel transistor. Therefore, in FIG. 2, the exposed portion between the DTI (deep trench isolation) structure 120 and the active region 160 corresponds to the device isolation film 115, and the PD 110 is not exposed to the outside. Here, the pixel transistor includes, for example, a transfer transistor TX, a reset transistor RX, a source follower transistor SFX, and a selection transistor SX. The substrate 101 and the PD 110 will be described in more detail in the description of FIGS. 5A to 5C.

[0015] For reference, the isolation film 115 is disposed on the front surface (see FS in FIG. 5B) of the substrate 101 to define an active region 160. Meanwhile, the active region 160 includes a region in which the transmission gate 130 and the FD region 140 are disposed, a region in which the gate 150 is disposed, a region in which the ground contact 170 is disposed, etc. The bottom surface of the isolation film 115 is separated from the PD 110. The depth of the isolation film is shallower than the depth of the DTI structure 120. The isolation film 115 is, for example, a Shallow Trench Isolation (STI) film. The DTI structure 120 overlaps a portion of the isolation film 115. For example, the DTI structure 120 extends through the isolation film 115.

[0016] The pixel PX includes two PDs 110, and two transmission gates 130 are disposed in each of the PDs 110. For example, the first and second PDs (PD1-1, PD1-2) of the first pixel PX1 include a first transmission gate 130-1 and a second transmission gate 130-2, respectively. The first transmission gate 130-1 and the second transmission gate 130-2 transmit charges generated in the corresponding PDs 110 to the adjacent FD regions 140. By disposing two transmission gates 130 in one PD 110, charge leakage is minimized. For reference, one PD 110, two transmission gates 130, and the FD region 140 constitute one transmission transistor TX. Also, each of the two transmission gates 130 has a single vertical gate structure similar to FIG. 5C. However, the structure of the transmission gate 130 is not limited to the single vertical gate structure.

[0017] The four pixels PXs are isolated from one another via a DTI (Deep Trench Isolation) structure 120. The two PDs 110 inside each of the four pixels PXs are also isolated from one another via the DTI structure 120. For example, the DTI structure 120 includes an external DTI structure 120out that isolates the pixels PXs from one another, and an internal DTI structure 120in that isolates the two PDs 110 in the pixel PX from one another.

[0018] The external DTI structure 120out includes a portion extending in the x-direction and a portion extending in the y-direction. The portion extending in the y-direction of the external DTI structure 120out completely separates two pixels PXs adjacent in the x-direction. The portion extending in the x-direction of the external DTI structure 120out partially separates two pixels PXs adjacent in the y-direction. Specifically, the portion extending in the x-direction of the external DTI structure 120out is divided into two portions by the FD region 140.

[0019] The internal DTI structure 120in is disposed inside the pixel PX and extends in the y direction, separating the two PDs 110 from each other. Thus, within the pixel PX, the two PDs 110 are disposed on both sides in the x direction, sandwiching the internal DTI structure 120in therebetween. Also, two transmission gates 130 are disposed on both sides in the x direction, sandwiching the internal DTI structure 120in therebetween. The FD region 140 is disposed adjacent to the edge of the internal DTI structure 120in in the y direction.

[0020] For reference, the x direction and the y direction are relative concepts, and when the shared pixel SPX is rotated by 90°, the x direction becomes the y direction and the y direction becomes the x direction. Therefore, the extension directions and structures of the external DTI structure 120out and the internal DTI structure 120in described above are not fixed to the directions and structures described above.

[0021] Meanwhile, the DTI structure 120 prevents charges generated when light is incident on the PD 110 of a particular pixel PX from entering an adjacent pixel PX or PD 110. That is, the DTI structure 120 prevents optical crosstalk between adjacent pixels PXs. The DTI structure 120 extends from the front surface FS to the back surface BS of the substrate 101 and penetrates the substrate 101.

[0022] More specifically, the DTI structure 120 includes a central conductive layer and an outer insulating layer. The central conductive layer is disposed in the central portion of the DTI structure 120 and includes, for example, polysilicon doped with impurities. A ground or negative voltage is applied to the central conductive layer. By applying a ground or negative voltage to the central conductive layer, positive charges generated in the pixel PX are induced to the voltage of the central conductive layer and removed through the ground contact. As a result, the DTI structure 120 improves the dark current characteristics of the image sensor 100 through the central conductive layer. The outer insulating layer is disposed in the outer portion of the DTI structure 120 in a form surrounding the central conductive layer. The outer insulating layer insulates the central conductive layer from the substrate 101. The outer insulating layer includes, for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like.

[0023] In some embodiments, a buried layer is disposed within the central conductive layer. The buried layer is disposed to prevent void formation within the DTI structure 120 and to counteract tensile stress applied to the substrate 101 during high temperature processing to prevent bending of the substrate 101. Thus, the buried layer includes a material having a thermal expansion coefficient different from that of the central conductive layer. For example, the buried layer includes a metal oxide, a metal nitride, a metal, or a combination thereof. Alternatively, the buried layer may include a silicon compound such as SiCN, SiON, or SiOC.

[0024] The DTI structure 120 is formed by forming a deep trench in the substrate 101 and filling the trench with an insulating material and a conductive material. The DTI structure 120 is classified as a front-side DTI (FDTI) structure or a back-side DTI (BDTI) structure depending on whether the trench is formed on the front side FS or the back side BS of the substrate 101. The DTI structure 120 may have various forms depending on the form of the trench. For example, in some embodiments, the DTI structure 120 does not completely penetrate the substrate 101. In the image sensor 100 of this embodiment, the DTI structure 120 has an FDTI structure. However, the DTI structure 120 is not limited thereto.

[0025] The FD region 140 is disposed between two pixels PXs adjacent in the y direction. Specifically, the FD region 140 is formed in the active region 160 between two pixels PXs adjacent in the y direction through high-concentration impurity doping. For example, the FD region 140 is disposed between the first and second pixels (PX1, PX2), and the FD region 140 is disposed between the third and fourth pixels (PX3, PX4). Thus, the first and second pixels (PX1, PX2) share the FD region 140 to form a first sub-shared pixel SPXs1. Also, the third and fourth pixels (PX3, PX4) share the FD region 140 to form a second sub-shared pixel SPXs2. As a result, the four PDs 110 of the first and second pixels (PX1, PX2) share one FD region 140, and the four PDs 110 of the third and fourth pixels (PX3, PX4) share one FD region 140.

[0026] Meanwhile, since two pixels PXs constitute a sub-shared pixel, the shared pixel SPX includes two sub-shared pixels (SPXs1, SPXs2) adjacent to each other in the x-direction. In addition, since two pixels PXs share one FD region 140 with each other, the wiring connection relationship of the shared pixel SPX is simplified. The wiring connection relationship of the shared pixel SPX will be described in more detail in the description of Figures 3A and 3B.

[0027] The shared pixel SPX has a substantially rectangular shape in plan view. However, the shared pixel SPX is not limited to a rectangular shape in plan view. Meanwhile, the microlenses are arranged in a structure in which they are arranged in each of the pixels PXs, in a structure in which they are arranged in each of the sub-shared pixels (SPXs1, SPXs2), or in a structure in which they are arranged over the entire shared pixel SPX. The arrangement structure of the shared pixel SPX and the microlenses will be described in further detail in the description of Figures 8A and 8B.

[0028] 2, only one shared pixel SPX is illustrated, but the image sensor 100 of this embodiment includes a large number of shared pixels SPX arranged in a two-dimensional array. That is, in the image sensor 100 of this embodiment, a plurality of shared pixels SPX are arranged along each of the x direction and the y direction. The two-dimensional array of shared pixels SPX will be described in further detail in the description of FIG. 12.

[0029] Based on the equivalent circuit diagram of FIG. 1, looking at the connection relationship between the PD 110, the FD region 140, and the pixel transistors, the four PDs (PD1-1, PD1-2, PD2-1, PD2-2) of the first sub-shared pixel SPXs1 are respectively connected to the source regions of the four corresponding transfer transistors (TX1-1, TX1-2, TX2-1, TX2-2), and the four PDs (PD3-1, PD3-2, PD4-1, PD4-2) of the second sub-shared pixel SPXs2 are respectively connected to the source regions of the four corresponding transfer transistors (TX3-1, TX3-2, TX4-1, TX4-2).

[0030] The drain regions of the transfer transistors (TX1-1, TX1-2, TX2-1, TX2-2) of the first sub-shared pixel SPXs1 and the transfer transistors (TX3-1, TX3-2, TX4-1, TX4-2) of the second sub-shared pixel SPXs12 are connected to the source region of the reset transistor RX. That is, the common drain region of the transfer transistors (TX1-1, TX1-2, TX2-1, TX2-2) of the first sub-shared pixel SPXs1 corresponds to the first FD region FD1, and the common drain region of the transfer transistors (TX3-1, TX3-2, TX4-1, TX4-2) of the second sub-shared pixel SPXs2 corresponds to the second FD region FD2. In addition, the source region of the reset transistor RX corresponds to two FD regions 140 connected by wiring, that is, the first FD region FD1 of the first sub-shared pixel SPXs1 and the second FD region FD2 of the second sub-shared pixel SPXs2. The first FD region FD1 and the second FD region FD2 are connected to the source follower gate of the source follower transistor SFX (see SF in FIG. 3B) via wiring. As shown in FIG. 1, the drain region of the reset transistor RX and the drain region of the source follower transistor SFX are connected to a power supply voltage Vpix. Also, the source region of the source follower transistor SFX and the drain region of the selection transistor SX are connected to each other. Meanwhile, an output line is connected to the source region of the selection transistor SX, and the voltage of the source region of the selection transistor SX is output as an output voltage Vout.

[0031] In addition, pixel transistors, such as the source follower transistor SFX, the reset transistor RX, and the selection transistor SX, are realized through a gate 150 and an active region 160 disposed in the pixel PXs constituting the shared pixel SPX. The specific arrangement structure of the source follower transistor SFX, the reset transistor RX, and the selection transistor SX will be described in further detail in the description of FIG. 3B.

[0032] Meanwhile, the size of the pixel transistor is determined by the size of the gate 150. The size of the gate 150 in the x direction is the width of the gate 150, and the size of the gate 150 in the y direction is the length of the gate 150. As can be seen from FIG. 2, the width of the gate 150 is determined to some extent by the DTI structure 120. In the image sensor 100 of this embodiment, the gate 150 has a first gate length Lg1. Also, the size of the pixel transistor is changed by changing the first gate length Lg1 of the gate 150. In the image sensor 100 of this embodiment, the size of the pixel transistor is appropriately changed to improve charge transfer efficiency and CG (conversion gain).

[0033] The ground contact 170 is disposed in each active region 160 of the first and second sub-shared pixels (SPXs1, SPXs2). Specifically, the ground contact 170 of the first sub-shared pixel SPXs1 is disposed at the right outer edge in the x direction and at the center in the y direction of the entire shared pixel SPX. In FIG. 2, the ground contact 170 of the first sub-shared pixel SPXs1 is disposed in the first pixel PX1, but it may be disposed in the second pixel PX2. Similarly, the ground contact 170 of the second sub-shared pixel SPXs2 is disposed at the left outer edge in the x direction and at the center in the y direction of the entire shared pixel SPX. Also, the ground contact 170 of the second sub-shared pixel SPXs2 is disposed in the fourth pixel PX4.

[0034] Meanwhile, the ground contact is not limited to the position at which it is disposed in the shared pixel SPX of the image sensor 100 of Fig. 2, but may be disposed in various positions of the shared pixel depending on the structure of the shared pixel. Various arrangement structures of the ground contact will be described in more detail in the description of Figs. 4A, 4B, 6A, 7, etc.

[0035] 3A and 3B are plan views showing the wiring routine of the FD region in the image sensor of the comparative example and the image sensor of Fig. 1. The description will be given with reference to Fig. 1, and the contents already described in the description of Fig. 1 and Fig. 2 will be briefly described or omitted.

[0036] 3A and 3B, in the image sensor Com. of the comparative example, the shared pixel includes four pixels. Also, each pixel includes two PDs, and one FD region FD is disposed in one PD. A ground contact GND is disposed in the center of each pixel. Therefore, in the image sensor Com. of the comparative example, eight FD regions FD are disposed in the shared pixel, and the eight FD regions FD are connected to the source region of the reset transistor and the source follower gate SF of the source follower transistor through wiring. As a result, in the image sensor Com. of the comparative example, the wiring route between the FD region FD and the pixel transistor becomes very complicated. The wiring is generally formed by a metal such as copper (Cu), and the complicated wiring route increases the resistance and decreases the conversion gain (CG). Here, CG means the ratio at which the charge generated in the PD moves to the FD region and is accumulated, and the charge is converted into a voltage through the source follower transistor. Also, in the image sensor Com. of the comparative example, the complicated wiring route hinders the layout efficiency and increase in size of the pixel transistor, and increases the wiring layer.

[0037] Meanwhile, in the image sensor 100 of the present embodiment, the shared pixel SPX includes four pixels PXs, and two pixels PXs form one sub-shared pixel and share one FD region 140. Therefore, only two FD regions FD are arranged in the shared pixel SPX, and the two FD regions FD are connected to the source region of the reset transistor RX and the source follower gate SF of the source follower transistor SFX through wiring. As a result, as shown in FIG. 3B, in the image sensor 100 of the present embodiment, the wiring route between the FD region 140 and the pixel transistor is simplified. Such a simplified wiring route reduces resistance and improves CG. In addition, in the image sensor 100 of the present embodiment, the simplified wiring route enables an increase in layout efficiency and size of the pixel transistor, and contributes to a reduction in the number of wiring layers. The layout efficiency and increase in size of the pixel transistor will be described in more detail in the description of FIG. 4B or FIG. 11.

[0038] In the image sensor 100 of this embodiment, the gates 150 are disposed at the outer periphery of the shared pixel SPX, one for each PD 110. Thus, eight gates 150 are disposed in the shared pixel SPX. At least three of the eight gates 150 are used as pixel transistors of the shared pixel SPX. For example, the gate 150 on the left side of the first pixel PX1 is used as a reset gate RG of the reset transistor RX. Also, the gate 150 on the right side of the third pixel PX3 is used as a source follower gate SF of the source follower transistor SFX, and the gate 150 on the left side is used as a selection gate SG of the selection transistor SX. Of course, the positions of the gates used as pixel transistors are not limited to the above. For example, the reset gate RG may be disposed in the third pixel PX3, and the source follower gate SF and the selection gate SG may be disposed in the first pixel PX1. Also, the gates 150 of the second pixel PX2 and the fourth pixel PX4 may be used as gates of pixel transistors.

[0039] Meanwhile, the gate 150 that does not constitute a pixel transistor corresponds to a dummy gate. The dummy gate is used to realize other operation characteristics in the image sensor 100. For example, the dummy gate is used to realize a dual CG or triple CG of a shared pixel. Also, the dummy gate is used as an additional source follower gate SF when a plurality of source follower gates SF are configured.

[0040] 4A and 4B are plan views illustrating various examples of shared pixels of an image sensor according to an embodiment of the present invention, which will be described with reference to FIG. 1, and the contents already described in the description of FIGS. 1 to 3B will be briefly described or omitted.

[0041] Referring to FIG. 4A, the image sensor 100a of the present embodiment differs from the image sensor 100 of FIG. 2 in the position of the ground contact 170a. Specifically, in the image sensor 100a of the present embodiment, the ground contact 170a is disposed adjacent to the central portion of the shared pixel SPX in the x-direction and the y-direction. For example, the ground contact 170a is disposed adjacent to the central portion of the shared pixel SPX in which the external DTI structure 120out is disposed in a + shape. In FIG. 4A, the ground contact 170a is disposed at the first pixel PX1 and the third pixel PX3 in the central portion of the shared pixel SPX, but the position of the ground contact 170a is not limited thereto. For example, the ground contact 170a may be disposed at the second pixel PX2 and the fourth pixel PX4, the first pixel PX1 and the fourth pixel PX4, or the second pixel PX2 and the third pixel PX3 in the central portion of the shared pixel SPX.

[0042] In addition, in the image sensor 100a of this embodiment, the wiring connection structure between the FD region 140 and the pixel transistor is substantially the same as the wiring connection structure shown in Fig. 3B. Hereinafter, when the shared pixel has a structure including two sub-shared pixels (SPXs1, SPXs2) and two FD regions 140, the wiring connection structure between the FD region 140 and the pixel transistor is substantially the same as the wiring connection structure shown in Fig. 3B.

[0043] Referring to FIG. 4B, the image sensor 100b of the present embodiment differs from the image sensor 100 of FIG. 2 in the position of the ground contact 170b and the arrangement of the gate 150. Specifically, in the image sensor 100b of the present embodiment, the ground contact 170b is disposed adjacent to the outer edge of the shared pixel SPX in the x and y directions. For example, when four pixels PXs form a quadrant, the ground contact 170b is disposed on the outer edge of the second and fourth quadrants. It goes without saying that the position of the ground contact 170b is not limited thereto. For example, the ground contact 170b may be disposed on the outer edge of the first and third quadrants, the outer edge of the first and second quadrants, or the outer edge of the third and fourth quadrants.

[0044] In addition, in the image sensor 100b of the present embodiment, the ground contact 170b is disposed at the outer edge of the shared pixel SPX, so that the gate on the upper part of the corresponding active region 160 is omitted. Meanwhile, although not shown, in the image sensor 100b of the present embodiment, the right gate 150 of the third pixel PX3 becomes the reset gate RG of the reset transistor RX, the right gate 150 of the first pixel PX1 becomes the selection gate SG of the selection transistor SX, and the left gate 150 becomes the source follower gate SF of the source follower transistor SFX. Of course, the gates of the pixel transistors are disposed in the second pixel PX2 and the fourth pixel PX4. In the image sensor 100b of the present embodiment, the arrangement position of the ground contact 170b is diversified, so that the arrangement efficiency of the pixel transistors is increased.

[0045] 5A to 5C are plan views showing a fourth example of a shared pixel of an image sensor according to an embodiment of the present invention, and cross-sectional views showing various examples of a transmission gate portion, and Fig. 5B and Fig. 5C are cross-sectional views of the transmission gate portion cut along the x direction. The description will be given with reference to Fig. 1, and the contents already described in the description of Figs. 1 to 4B will be briefly described or omitted.

[0046] 5A and 5B, the image sensor 100c of the present embodiment differs from the image sensor 100 of FIG. 2 in that one transmission gate 130a is disposed for each PD 110. Specifically, the image sensor 100c of the present embodiment includes a substrate 101, a PD 110, a DTI structure 120, a transmission gate 130a, an FD region 140, and a gate 150.

[0047] The substrate 101 includes a front side (FS) and a back side (BS) facing the front side. A wiring layer is disposed on the front side FS of the substrate 101, and a light-transmitting layer is disposed on the back side BS. The light-transmitting layer includes, for example, a color filter and a microlens. Light passes through the light-transmitting layer on the back side BS of the substrate 101 and enters the photodiode 110.

[0048] The substrate 101 is a substrate in which an epitaxial layer of a first conductivity type (e.g., p-type) is grown on a bulk silicon substrate of a first conductivity type. In some embodiments, the substrate 101 includes only an epitaxial layer, with all of the bulk silicon substrate removed. Meanwhile, the substrate 101 is a bulk silicon substrate including a well of a first conductivity type. The substrate 101 may also include various types of substrates, such as a substrate including an epitaxial layer of a second conductivity type (e.g., n-type) and an SOI (Silicon On Insulator) substrate.

[0049] The PD 110 generates and accumulates charges in proportion to the intensity of light incident through the back surface BS of the substrate 101, i.e., the amount of incident light. The PD 110 includes, for example, a first impurity region doped with impurities of a first conductivity type (e.g., p-type) and a second impurity region doped with impurities of a second conductivity type (e.g., n-type). The first impurity region and the second impurity region form a pn junction. In some embodiments, the substrate 101 serves as the first impurity region. In such a case, the first impurity region is not necessary, and the substrate 101 and the second impurity region form the PD 110. The PD 110 is disposed inside the substrate 101 in a central portion of each pixel PXx. For example, as shown in FIG. 5B, the PD 110 is disposed inside the substrate 101 below the transfer gate 130a of the transfer transistor TX.

[0050] In the image sensor 100c of this embodiment, one transmission transistor TX is arranged for each PD 110, and the transmission transistor TX includes a transmission gate 130a. Considering the functional aspect of the transistor, the transmission gate 130a, the PD 110, and the FD region 140 constitute the transmission transistor TX. That is, the PD 110 / FD region 140 constitute the source / drain of the transmission transistor TX.

[0051] The transmission gate 130a is made of polysilicon. However, the material of the transmission gate 130a is not limited to polysilicon. For example, the transmission gate 130a is made of a multi-layer structure including a barrier film and at least one metal layer. The transmission gate 130a has, for example, a dual vertical gate structure. Accordingly, the transmission gate 130a includes two vertical extension portions 132 and a connection portion 134. Each of the two vertical extension portions 132 is vertically extended into the substrate 101 and is spaced apart from each other in the x direction. Here, "vertical" refers to the z direction perpendicular to the upper surface of the substrate 101. The connection portion 134 connects the two vertical extension portions 132 to each other from the upper surface of the substrate 101. For reference, the vertical extension portion 132 and the connection portion 134 are merely a formal distinction for the purpose of explanation, and the vertical extension portion 132 and the connection portion 134 are made of the same material and have a form of being integrally combined. For example, the vertical extension portion 132 and the connecting portion 134 are integrally formed from polysilicon.

[0052] 5A, the horizontal cross section of the transmission gate 130a has a rectangular shape. This rectangle corresponds to the horizontal cross section of the transmission gate 130a at a level equal to or higher than the z-direction connecting portion 134. If the horizontal cross section of the transmission gate 130a is at a level lower than the z-direction connecting portion 134, the horizontal cross section has a shape in which two small rectangles of the vertical extension portion 132 are spaced apart from each other in the x-direction.

[0053] The bottom and side surfaces of the vertical extension portion 132 and the connecting portion 134 are surrounded by a bottom gate insulating layer 135. For example, the gate insulating layer 135 is disposed between the vertical extension portion 132 and the substrate 101, between the connecting portion 134 and the substrate 101, and on the top surface of the substrate 101 outside the transmission gate 130a in the x-direction.

[0054] In the image sensor 100c of the present embodiment, the transfer gate 130a is arranged in a dual vertical gate structure, so that charge leakage is minimized, similar to a structure in which two transfer gates 130 are arranged in a vertical gate structure. In addition, the transfer gate 130a includes a wide connection portion 134 on the upper portion, so that the problem of an increase in the area of ​​the gate contact 180 and misalignment can be solved. More specifically, if only two transfer gates are arranged without a connection portion, a problem of an increase in the contact area occurs because a gate contact must be arranged on each of the transfer gates. In addition, a problem of misalignment with the gate contact occurs because the width of the upper surface of each of the transfer gates is narrow. Meanwhile, in the case of the image sensor 100c of the present embodiment, the transfer gate 130a includes the connection portion 134, so that only one gate contact 180 is arranged, reducing the area of ​​the gate contact 180, and the problem of misalignment with the gate contact 180 is also solved because the upper surface area of ​​the connection portion 134 is relatively wide.

[0055] Meanwhile, in some embodiments, a spacer of a certain thickness is disposed between the connection portion 134 of the transmission gate 130a and the substrate 101 to eliminate a potential hump of the transmission gate 130a. Here, the potential hump refers to a phenomenon in which a field is concentrated at an edge of an active region corresponding to a bent portion of the gate. When the spacer is disposed, the length of the vertical extension portion 132 of the transmission gate 130a increases by the thickness of the spacer. Therefore, the thickness of the spacer is appropriately determined in consideration of the distance of the vertical extension portion 132 of the transmission gate 130a and the effect of eliminating the potential hump.

[0056] 5A and 5C, the image sensor 100c' of the present embodiment is similar to the image sensor 100c of FIG. 5B in that one transmission gate 130a' is arranged for each PD 110. However, the image sensor 100c' of the present embodiment is different from the image sensor 100c of FIG. 5B in that the transmission gate 130a' has a single vertical gate structure. Specifically, the image sensor 100c' of the present embodiment includes a substrate 101, a PD 110, a DTI structure 120, a transmission gate 130a', an FD region 140, and a gate 150. The substrate 101, the PD 110, the DTI structure 120, the FD region 140, and the gate 150 are the same as those described in the description of the image sensors (100, 100c) of FIG. 2 and FIG. 5B.

[0057] 5C, the transmission gate 130a' has a single vertical gate structure. Accordingly, the transmission gate 130a' includes a vertical extension portion 132 and a horizontal extension portion 136. The vertical extension portion 132 extends vertically into the substrate 101. The horizontal extension portion 136 extends horizontally from the vertical extension portion 132 on the upper surface of the substrate 101. In the structure of the transmission gate 130a', the vertical extension portion 132 and the horizontal extension portion 136 are only distinguished formally for the purpose of explanation, and the vertical extension portion 132 and the horizontal extension portion 136 are made of the same material and have a form of being integrally combined.

[0058] In the image sensor 100c' of this embodiment, the vertical extension portion 132 of the transmission gate 130a' is vertically extended into the substrate 101, and the horizontal extension portion 136 is horizontally extended on the substrate 101. Therefore, even if the vertical extension portion 132 is small, the area of ​​the gate contact 180 can be sufficiently secured through the horizontal extension portion 316. As a result, the problem of an increase in the area of ​​the gate contact 180 and misalignment can be solved. Meanwhile, in some embodiments, a spacer having a certain thickness is disposed between the horizontal extension portion 136 of the transmission gate 130a and the substrate 101 to eliminate a potential hump of the transmission gate 130a'.

[0059] 6A and 6B are plan views showing various examples of shared pixels of an image sensor according to an embodiment of the present invention, and plan views showing wiring routines in an FD region. The description will be given with reference to FIG. 1, and the contents already described in the description of FIGS. 1 to 5C will be briefly described or omitted.

[0060] 6A and 6B, the image sensor 100d of the present embodiment differs from the image sensor 100 of FIG. 2 in that two unit pixels PXs do not share the FD region 140a. Specifically, in the image sensor 100d of the present embodiment, the shared pixel SPXa includes four pixels (PX1a to PX4a), but there is no concept of a sub-shared pixel configuration of two pixels PXs. In addition, the four pixels (PX1a to PX4a) are completely isolated from each other by the DTI structure 120a, for example, the external DTI structure 120out.

[0061] Each of the pixels PX1s includes an FD region 140a. Therefore, the two PDs 110 of each of the pixels PX1s share the FD region 140a. Due to such an arrangement of the FD regions 140a, in the shared pixel SPXa, as shown in FIG. 6B, the four FD regions 140a are connected to the source region of the reset transistor RX and the source follower gate SF of the source follower transistor SFX via wiring.

[0062] Meanwhile, the ground contact 170c is disposed in each of the pixels PX1s. For example, the ground contact 170c is disposed in each of the pixels PX1s adjacent to the outer portion in the x direction and the central portion in the y direction in the shared pixel SPXa. However, the arrangement position of the ground contact 170c is not limited thereto. For example, the ground contact 170c may be disposed in each of the pixels PX1s adjacent to the central portions in the x direction and the y direction in the shared pixel SPXa.

[0063] The wiring connection structure between the FD region 140a and the pixel transistors of the image sensor 100d of this embodiment is simpler than the wiring connection structure of the FD region FD of the image sensor Com. of the comparative example of Fig. 3A. Therefore, the image sensor 100d of this embodiment also contributes to improving CG, increasing the layout efficiency and size of the pixel transistors, and reducing the wiring layers.

[0064] 7 to 11 are plan views illustrating various examples of shared pixels of an image sensor according to an embodiment of the present invention, which will be described with reference to FIG. 1, and the contents already described in the description of FIGS. 1 to 6B will be briefly described or omitted.

[0065] 7, the image sensor 100e of the present embodiment differs from the image sensor 100 of FIG. 2 in the structure of the shared pixel SPXb. Specifically, in the image sensor 100e of the present embodiment, the shared pixel SPXb includes four pixels (PX1b to PX4b), but there is no concept of a sub-shared pixel configuration of two pixels PXs. As a result, each of the pixels PXs includes an FD region 140a. Therefore, the two PDs 110 of each pixel PXs share the FD region 140a.

[0066] The layout and wiring structure of the FD region 140a are substantially the same as those of the FD region 140a shown in Fig. 6B. Hereinafter, when each of the pixels SXs in a shared pixel has a structure including the FD region 140a, the wiring structure between the FD region 140a and the pixel transistors is substantially the same as the wiring structure shown in Fig. 6B.

[0067] Meanwhile, in the image sensor 100e of this embodiment, the four pixels (PX1b to PX4b) in the shared pixel SPXb are incompletely isolated by the DTI structure 120b, for example, the external DTI structure 120out. Specifically, a ground contact 170d commonly applied to the entire shared pixel SPXb is disposed at the center of the shared pixel SPXb in the x and y directions. By the ground contact 170d disposed at the center of the shared pixel SPXb, the external DTI structure 120out extending in the x direction is isolated in both directions in the x direction, and the external DTI structure 120out extending in the y direction is isolated in both directions in the y direction.

[0068] 8A, in the image sensor 100 of the present embodiment, four microlenses 190 are arranged corresponding to the four pixels PXs of the shared pixel SPX. As described above, the microlenses 190 are arranged on the lower surface of the substrate 101. Thus, dotted lines corresponding to the microlenses 190 are shown in FIG. 8A. Meanwhile, although the planar shape of the microlenses 190 is shown as a square corresponding to the planar shape of the pixel PX, the planar shape of the microlenses 190 is not limited to a square, and may be a circle or an ellipse.

[0069] Meanwhile, since each pixel PXs includes two PDs 110 and a transmission transistor TX is disposed corresponding to each PD 110, at least one pixel PX among the pixels PXs may be used for implementing AF (Auto Focus). For reference, AF may be performed in various ways. For example, AF may be performed in a contrast AF, a phase difference AF, an image plane phase difference AF, a dual pixel AF, etc. Here, the dual pixel AF method is a method in which two or more PDs 110 are collected and used as one AF pixel, and each PD in the AF pixel is individually controlled to operate as a phase difference sensor using the respective photodetection signals of the PDs when AF information is used, and the photodetection signals of the PDs are combined to output one image signal when image information is used. The image sensor 100 of the present embodiment may perform AF in a dual pixel AF method using two PDs 110 in the pixel PX.

[0070] 8B, in the image sensor 100f of this embodiment, two microlenses 190a are arranged corresponding to two sub-shared pixels (SPXs1, SPXs2) of the shared pixel SPX. The microlenses 190a are arranged on the lower surface of the substrate 101, and in FIG. 8B, dotted lines corresponding to the microlenses 190a are shown. Meanwhile, the planar shape of the microlenses 190a has a rectangular shape that is longer in the y direction corresponding to the planar shapes of the sub-shared pixels (SPXs1, SPXs2). However, the planar shape of the microlenses 190 is not limited thereto, and may have an elliptical shape that is longer in the y direction.

[0071] Meanwhile, in the image sensor 100f of the present embodiment, each of the sub-shared pixels (SPXs1, SPXs2) includes two pixels PXs. Therefore, the upper and lower pixels PXs of each of the sub-shared pixels (SPXs1, SPXs2) can be used to implement AF. That is, in the image sensor 100f of the present embodiment, at least one of the sub-shared pixels (SPXs1, SPXs2) can perform AF in a dual pixel AF manner using two pixels PXs.

[0072] 9, in the image sensor 100g of this embodiment, the structure of the shared pixel SPX is substantially the same as the structure of the shared pixel SPX of the image sensor 100 of Fig. 2. For example, the shared pixel SPX includes two sub-shared pixels (SPXs1, SPXs2) arranged adjacent to each other in the X direction, and each of the sub-shared pixels (SPXs1, SPXs2) includes two pixels PXs adjacent to each other in the y direction.

[0073] In the image sensor 100g of this embodiment, the FD region 140 is disposed in the center of each of the sub-shared pixels (SPXs1, SPXs2) and is shared by two pixels PXs. The FD region 140 is also formed in the active region 160 disposed in the center of each of the sub-shared pixels (SPXs1, SPXs2).

[0074] Since the FD region 140 is disposed in the central portion of each of the sub-shared pixels (SPXs1, SPXs2), the external DTI structure 120out extending in the x-direction in each of the sub-shared pixels (SPXs1, SPXs2) is separated into two parts on both sides in the x-direction by the active region 160 including the FD region 140. The separation distance in the x-direction between the two parts of the separated external DTI structure 120out has, for example, a first separation distance Sx.

[0075] Furthermore, by disposing the FD region 140 in the central portion of each of the sub-shared pixels (SPXs1, SPXs2), the internal DTI structures 120in in two pixels PXs adjacent in the y direction are separated from each other by the active region 160 including the FD region 140. The separation distance in the y direction between the internal DTI structures 120in of two pixels PXs adjacent in the y direction has, for example, a second separation distance Sy.

[0076] In the image sensor 100g of the present embodiment, at least one of the first separation distance Sx and the second separation distance Sy is adjusted to adjust a potential barrier between adjacent pixels and / or prevent optical crosstalk. For example, by narrowing the first separation distance Sx, the potential barrier between adjacent pixels PXs in the y direction in each of the sub-shared pixels (SPXs1, SPXs2) can be increased to strengthen the electrical isolation and reduce the optical crosstalk. In addition, by narrowing the second separation distance Sy, the electrical isolation between adjacent PDs 110 in the x direction in each of the pixels PXs can be strengthened to reduce the optical crosstalk. For reference, the adjustment of the first separation distance Sx corresponds to an inter-pixel adjustment, and the adjustment of the second separation distance Sy corresponds to an in-pixel adjustment.

[0077] 10, in the image sensor 100h of this embodiment, the structure of the shared pixel SPX is substantially the same as the structure of the shared pixel SPX of the image sensor 100 of Fig. 2. For example, the shared pixel SPX includes two sub-shared pixels (SPXs1, SPXs2) arranged adjacent to each other in the X direction, and each of the sub-shared pixels (SPXs1, SPXs2) includes two pixels PXs adjacent to each other in the y direction.

[0078] In the image sensor 100g of this embodiment, the internal DTI structure 120in of the DTI structure 120 has a first width Wx in the X direction. Also, the external DTI structure 120out of the DTI structure 120 has a predetermined width in the X direction or the y direction. In particular, of the external DTI structures 120out, the external DTI structures 120out extending in the y direction are disposed at the center of the sub-shared pixels (SPXs1, SPXs2), and the external DTI structures 120out extending in the x direction have a second width Wy in the y direction.

[0079] In the image sensor 100h of this embodiment, at least one of the first width Wx and the second width Wy is adjusted to adjust the potential barrier between adjacent pixels and / or prevent optical crosstalk. For example, by widening the first width Wx, the electrical isolation between the PDs 110 in the x direction can be strengthened to reduce optical crosstalk. In addition, by widening the second width Wy, the electrical isolation between the pixels PXs adjacent to each other in the y direction in each of the sub-shared pixels (SPXs1, SPX2) can be strengthened to reduce optical crosstalk. For reference, the adjustment of the first width Wx corresponds to an adjustment within a pixel, and the adjustment of the second width Wy corresponds to an adjustment between pixels.

[0080] 11, in the image sensor 100i of the present embodiment, the structure of the shared pixel SPX is similar to that of the image sensor 100b of FIG. 4B. For example, in the shared pixel SPX, the ground contact 170b is disposed on the outer periphery in the X and y directions. Also, no gate is disposed on the active region 160 where the ground contact 170b is disposed.

[0081] Meanwhile, in the image sensor 100i of the present embodiment, the size of the gate 150a of the shared pixel SPX is larger than the size of the gate 150 of the shared pixel SPX of the image sensor 100b of FIG. 4B. Specifically, in the image sensor 100i of the present embodiment, the gate 150a has a second gate length Lg2 in the y direction. The second gate length Lg2 is longer than the first gate length Lg1. Therefore, the size of the pixel transistors, such as the reset transistor RX, the source follower transistor SFX, and the selection transistor SX, can be increased by increasing the size of the gate 150a.

[0082] In the image sensor 100i of the present embodiment, the gate 150a has a second gate length Lg2. In addition, the size of the pixel transistor is changed by changing the second gate length Lg2 of the gate 150a. For example, in the image sensor 100 of the present embodiment, the charge transfer efficiency, CG, etc. can be improved by increasing the size of the gate 150a and thereby increasing the size of the pixel transistor.

[0083] Fig. 12 is a plan view showing a structure in which shared pixels of the image sensor of Fig. 2 are arranged in a two-dimensional array. The description will be given with reference to both Fig. 1 and Fig. 2, and the contents already described in the description of Figs. 1 to 11 will be briefly described or omitted.

[0084] 12, the image sensor 100 of this embodiment has a two-dimensional array structure in which the shared pixels SPX shown in FIG. 2 are arranged along the x and y directions. The shared pixels SPX adjacent to each other in the x and y directions are separated from each other by a DTI structure 120, for example, an external DTI structure 120out. Meanwhile, FIG. 12 shows an image sensor 100 in which the shared pixels SPX of FIG. 2 are arranged in a two-dimensional array. However, in each of the image sensors 100a to 100i in FIGS. 3B to 5A and 6A to 11, the shared pixels (SPX, SPXa, SPXb) are also arranged in a two-dimensional array.

[0085] Fig. 13 is a block diagram showing the overall structure of an image sensor according to an embodiment of the present invention. The description will be given with reference to Fig. 1 and Fig. 2, and the contents already described in the description of Fig. 1 to Fig. 12 will be briefly described or omitted.

[0086] 13, the image sensor 1000 of the present embodiment includes a pixel array 1100, a timing controller (T / C) 1010, a row decoder 1020, and an output circuit 1030. The image sensor 1000 of the present embodiment is, for example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor.

[0087] Meanwhile, the image sensor 1000 of the present embodiment is any one of the image sensors (100, 100a to 100i) of FIG. 2, FIG. 3B to FIG. 5A, and FIG. 6A to FIG. 11. Thus, the pixel array 1100 includes a plurality of shared pixels (SPX, SPXa, SPXb) arranged in a two-dimensional array along a plurality of rows and a plurality of columns. The row decoder 1020 selects any one of a plurality of rows of the pixel array 1100 in response to a row address signal output from the timing controller 1010. The output circuit 1030 outputs an image signal in units of columns from a plurality of pixels and / or shared pixels SPX arranged along the selected row. The output circuit 1030 includes an A / D (analog-to-digital) converter ADC. For example, the output circuit 1030 includes a plurality of A / D converters ADC respectively arranged for each column between the column decoder and the pixel array 1100, or includes one A / D converter ADC arranged at the output end of the column decoder. Depending on the embodiment, the timing controller 1010, the row decoder 1020, and the output circuit 1030 may be implemented as a single chip or may be implemented as separate chips.

[0088] In the image sensor 1000 of this embodiment, the shared pixel SPX includes two sub-shared pixels (SPXs1, SPXs2), and each of the sub-shared pixels (SPXs1, SPXs2) includes two pixels PX2 and one FD region 140. This simplifies the wiring connection relationship between the FD region 140 and the pixel transistor, contributing to improved CG, increased layout efficiency and size of the pixel transistor, and reduced wiring layers.

[0089] Fig. 14 is a block diagram showing an electronic device including an image sensor according to an embodiment of the present invention. The description will be made with reference to Figs. 1, 2 and 13, and the contents already described in the description of Figs. 1 to 12 will be briefly described or omitted.

[0090] Referring to FIG. 14, an electronic device 2000 including an image sensor according to the present embodiment (hereinafter, simply referred to as "electronic device") includes an imaging unit 2100, an image sensor 1000, and a processor (PRC.) 2200. The electronic device 2000 is, for example, a camera. The imaging unit 2100 focuses light reflected from an object OBJ to form an optical image. The imaging unit 2100 includes an objective lens 2010, a lens driver (L-DR.) 2120, an aperture (IRIS) 2130, and an aperture driver (I-DR.) 2140. Although only one lens is illustrated in FIG. 14 for convenience, the objective lens 2010 may actually include a plurality of lenses having different sizes and shapes. In some embodiments, the electronic device 2000 is a mobile camera, and the aperture 2130 and the aperture driver 2140 may be omitted in the mobile camera.

[0091] The lens driver 2120 communicates information related to focus detection with the processor 2200 and adjusts the position of the objective lens 2010 according to a control signal provided by the processor 2200. The lens driver 1120 moves the objective lens 2010 to adjust the distance between the objective lens 2010 and the object OBJ, or adjusts the position of each individual lens in the objective lens 2010. The lens driver 1120 drives the objective lens 2010 to adjust the focus on the object OBJ. In addition, the lens driver 1120 receives AF information and adjusts the position of each individual lens in the objective lens 2010 to achieve focus.

[0092] The aperture driver 2140 communicates information regarding the amount of light with the processor 2200 and adjusts the aperture 2130 according to a control signal provided by the processor 2200. For example, the aperture driver 2140 increases or decreases the aperture of the aperture 2130 according to the amount of light incident on the inside of the electronic device 2000 through the objective lens 2010. In addition, the aperture driver 2140 adjusts the opening time of the aperture 2130.

[0093] The image sensor 1000 generates an electrical image signal based on the intensity of incident light. The image sensor 1000 is, for example, any one of the image sensors (100, 100a to 100i) of FIG. 2, FIG. 3B to FIG. 5A, and FIG. 6A to FIG. 11. The image sensor 1000 is the image sensor 1000 of FIG. 13. Thus, the image sensor 1000 includes a pixel array 1100, a timing controller 1010, and an output circuit 1030. Although not shown in FIG. 14, the image sensor 1000 further includes a row decoder 1020.

[0094] The processor 2200 controls the overall operation of the electronic device 2000 and performs an image processing function. For example, the processor 2200 provides control signals for the operation of each component, such as the lens driver 2120, the aperture driver 2140, and the timing controller 1010.

[0095] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical spirit of the present invention. [Explanation of symbols]

[0096] 100, 100a~100i, 1000 image sensor 101 Substrate 110 Photodiode (PD) 115 Element Isolation Film 120, 120a, 120b Deep Trench Isolation (DTI) Structure 120in internal DTI structure 120out external DTI structure 130, 130a Transmission gate 130-1 First Transmission Gate 130-2 Second Transmission Gate 132 Vertical Extension 134 Connecting part 135 Gate insulating film 136 Horizontal extension 140, 140a Floating Diffusion (FD) Area Gate 150, 150a 160 Active Area 170, 170a~170d Ground Contact 180 Gate Contact 190, 190a Micro Lenses 1010 Timing Controller (T / C) 1020 Row Decoder 1030 Output circuit (OC) 1100 Pixel Array (PA) 2000 Electronic equipment 2010 Objective Lens 2120 Lens drive unit (L-DR.) 2100 Imaging unit 2130 Aperture (IRIS) 2140 Aperture drive unit (I-DR.) 2200 Processor (PRC.) BS back FD1 1st FD area FD2 2nd FD area FS front GND Ground Contact Lg1, Lg2 First and second gate lengths OBJ Subject PD1-1, PD1-2 1st and 2nd PD PD2-1, PD2-2 3rd and 4th PD PD3-1, PD3-2 5th and 6th PD PD4-1, PD4-2 7th and 8th PD PX unit pixel PX1, PX1a, PX1b First unit pixel PX2, PX2a, PX2b Second unit pixel PX3, PX3a, PX3b 3rd unit pixel PX4, PX4a, PX4b 4th unit pixel RG Reset Gate RX Reset Transistor SF Source Follower Gate SG Select Gate SFX Source Follower Transistor SPX, SPXa, SPXb Shared Pixel SPXs1, SPXs2 1st and 2nd sub-shared pixels SX selection transistor Sx, Sy 1st, 2nd separation distance TG (Transfer Gate) TX Transmission Transistor TX1-1, TX1-2, TX2-1, TX2-2: Transfer transistors of the first sub-shared pixel TX3-1, TX3-2, TX4-1, TX4-2: Transfer transistors of the second sub-shared pixel Vout Output voltage Vpix power supply voltage Wx, Wy 1st, 2nd

Claims

1. 1. An image sensor comprising: A pixel including two photodiodes (PD) arranged on both sides in a first direction; a deep trench isolation (DTI) structure including an inner DTI structure that separates two PDs in the pixel from each other and extends in a second direction perpendicular to the first direction, and an outer DTI structure that separates the pixels from each other and extends in the first direction or the second direction; a floating diffusion (FD) region disposed between a central portion of the outer DTI structure and an edge of the inner DTI structure extending in the first direction; and a transfer gate (TG) arranged adjacent to the FD region and at least one transfer gate is arranged in each of the PDs; The image sensor is characterized in that the two PDs in the pixel share the FD region.

2. Two of the pixels adjacent to each other in the second direction constitute a sub-shared pixel, Two of the sub-shared pixels adjacent to each other in the first direction constitute a shared pixel, The image sensor of claim 1 , wherein the shared pixels are arranged in a two-dimensional array along the first and second directions.

3. The FD region is disposed between two of the pixels of the sub-shared pixel; The image sensor of claim 2 , wherein the four PDs of the sub-shared pixel share the FD region.

4. the sub-shared pixel includes a ground contact region; The ground contact area is a first arrangement structure arranged adjacent to an outer portion of the shared pixel in the first direction and a center portion of the shared pixel in the second direction; a second arrangement structure arranged adjacent to a central portion of the shared pixel in the first direction and the second direction; and a third arrangement structure disposed adjacent to an outer portion of the shared pixel in the first direction and a third arrangement structure disposed adjacent to an outer portion of the shared pixel in the second direction.

5. an active area and a gate corresponding to the PD are disposed on an outer edge of the pixel in the second direction; In the third arrangement structure, the ground contact region is arranged in an active region corresponding to the PD instead of the gate; 5. The image sensor according to claim 4, wherein the length of the gate in the first direction in the third arrangement structure is longer than the length of the gate in the first direction in the first arrangement structure or the second arrangement structure.

6. the FD region is disposed in a central portion of the sub-shared pixel; the two internal DTI structures of the sub-shared pixel are spaced apart from each other in the second direction by the FD region; 4. The image sensor of claim 3, wherein the outer DTI structure extending in the first direction is separated into two portions at the central portion by the FD region.

7. 7. The image sensor of claim 6, wherein a separation distance between two of the inner DTI structures in the second direction and a separation distance between two portions of the outer DTI structure in the first direction are changed.

8. The image sensor of claim 2 , wherein a width of the internal DTI structure in the first direction and a width of the external DTI structure in the first direction or a width of the external DTI structure in the second direction are changed.

9. A reset gate (RG) is disposed in one of the pixels of the shared pixel and is disposed on an outer periphery of the shared pixel; and a source follower gate (SF) disposed in at least another one of the pixels of the shared pixel and adjacent to the RG in an outer portion of the shared pixel, In the sub-shared pixel, two of the FD regions are arranged corresponding to two of the pixels, or one of the FD regions shared by two of the pixels is arranged; The image sensor of claim 2 , wherein the FD regions of the two or four shared pixels are connected to the SF via wiring.

10. In the sub-shared pixel, two of the FD regions are arranged corresponding to two of the pixels; The image sensor of claim 2 , wherein the ground contact region of the shared pixel is disposed adjacent to an outer portion of the shared pixel in the first direction and a central portion of the shared pixel in the second direction.

11. In the sub-shared pixel, two of the FD regions are arranged corresponding to two of the pixels; A ground contact region of the shared pixel is disposed at a central portion of the shared pixel in the first direction and the second direction; 3. The image sensor of claim 2, wherein in the shared pixel, the external DTI structure extending in the first direction and the external DTI structure extending in the second direction are separated by the ground contact region.

12. Further comprising a microlens covering the sub-shared pixel; The image sensor of claim 2, wherein the image sensor performs an auto focus.

13. The image sensor according to claim 1 , wherein two TGs are arranged for one PD.

14. A shared pixel including four pixels, each including two photodiodes (PD) arranged on both sides in a first direction; a deep trench isolation (DTI) structure including an inner DTI structure separating two of the PDs in the pixel from each other and extending in a second direction perpendicular to the first direction, and an outer DTI structure separating the pixels from each other and extending in the first direction or the second direction; a floating diffusion (FD) region disposed between a central portion of the outer DTI structure and an edge of the inner DTI structure extending in the first direction; A transmission gate (TG) is disposed adjacent to the FD region and at least one TG is disposed in each of the PDs; A reset gate (RG) is disposed in one of the pixels of the shared pixel and is disposed on an outer periphery of the shared pixel; a source follower gate (SF) disposed in at least another one of the pixels of the shared pixel and adjacent to the RG in an outer portion of the shared pixel; The image sensor is characterized in that the two PDs in the pixel share the FD region.

15. Two of the pixels adjacent to each other in the second direction constitute a sub-shared pixel, The shared pixel includes two of the sub-shared pixels adjacent to each other in the first direction, The FD region is disposed between two of the pixels of the sub-shared pixel; The image sensor of claim 14 , wherein the four PDs of the sub-shared pixel share the FD area.

16. the sub-shared pixel includes a ground contact region; The ground contact area is a first arrangement structure arranged adjacent to an outer portion of the shared pixel in the first direction and a center portion of the shared pixel in the second direction; a second arrangement structure arranged adjacent to a central portion of the shared pixel in the first direction and the second direction; and a third arrangement structure disposed adjacent to an outer portion of the shared pixel in the first direction and a third arrangement structure disposed adjacent to an outer portion of the shared pixel in the second direction.

17. In the sub-shared pixel, two of the FD regions are arranged corresponding to two of the pixels; A ground contact region of the shared pixel is disposed at a central portion of the shared pixel in the first direction and the second direction; 16. The image sensor of claim 15, wherein in the shared pixel, the external DTI structure extending in the first direction and the external DTI structure extending in the second direction are separated by the ground contact region.

18. The image sensor of claim 14 , wherein two or four of the FD regions of the shared pixel are connected to the SF via wiring.

19. A shared pixel including four pixels, each including two photodiodes (PD) arranged on both sides in a first direction; a deep trench isolation (DTI) structure including an inner DTI structure separating two of the PDs in the pixel from each other and extending in a second direction perpendicular to the first direction, and an outer DTI structure separating the pixels from each other and extending in the first direction or the second direction; a floating diffusion (FD) region disposed between a central portion of the outer DTI structure and an edge of the inner DTI structure extending in the first direction; and a transmission gate (TG) arranged adjacent to the FD region and at least one TG is arranged in each of the PDs; Two of the pixels adjacent to each other in the second direction constitute a sub-shared pixel, The shared pixel includes two of the sub-shared pixels adjacent to each other in the first direction, The FD region is disposed between two of the pixels of the sub-shared pixel; The image sensor is characterized in that the four PDs of the sub-shared pixel share the FD region.

20. the sub-shared pixel includes a ground contact region; The ground contact area is a first arrangement structure arranged adjacent to an outer portion of the shared pixel in the first direction and a center portion of the shared pixel in the second direction; a second arrangement structure arranged adjacent to a central portion of the shared pixel in the first direction and the second direction; a third arrangement structure disposed adjacent to an outer portion of the shared pixel in the first direction and an outer portion of the shared pixel in the second direction; The image sensor of claim 19, wherein the two FD regions of the shared pixel are connected to a source follower gate (SF) through a wiring.

Images