Level shifter

Abstract

To obtain an output signal that is suitable even when a level of a power source voltage supplied to an input-stage circuit decreases.SOLUTION: A level shifter includes: an input-stage circuit to which an input signal with a relatively low level is input; and an output-stage circuit that converts the input signal into a signal with a relatively high level and outputs the resulting signal. The output-stage circuit includes: a first transistor and a second transistor to which complementary signals generated in accordance with the input signal are input; a first switch circuit whose main path is connected to the first transistor, that is turned on when the second transistor is turned on, and that is turned off when the second transistor is turned off; and a second switch circuit whose main path is connected to the second transistor, that is turned on when the first transistor is turned on, and that is turned off when the first transistor is turned off. The on-state resistance of the first switch circuit is higher than the on-state resistance of the first transistor, and the on-state resistance of the second switch circuit is higher than the on-state resistance of the second transistor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The disclosed technology relates to a level shifter. [Background technology]

[0002] The following techniques are known as techniques related to level shifters. Patent Document 1 describes a level shifter circuit including a first voltage conversion circuit that generates a drive voltage that is lower than a first power supply voltage supplied from a first power supply line and corresponds to the first power supply voltage, generates a complementary signal corresponding to an input signal using the drive voltage, and outputs the complementary signal, a second voltage conversion circuit that uses a second power supply voltage supplied from a second power supply line to generate a signal corresponding to the voltage of the complementary signal output by the first voltage conversion circuit, and outputs the signal, and an output latch circuit that holds the signal output by the second voltage conversion circuit according to its voltage.

[0003] Patent Document 2 describes a voltage level shifter comprising first to fourth transistors of a first conductivity type. The first and second transistors are connected in series between a first and a second power supply input. A control electrode of the second transistor is connected to a first input for receiving a direct input signal. The third and fourth transistors are connected in series between the first and the second power supply input. A control electrode of the fourth transistor is connected to a second input for receiving a complementary input signal. A control electrode of the first transistor is connected to an output electrode of the third transistor and a common electrode of the fourth transistor. A control electrode of the third transistor is connected to an output electrode of the first transistor and a common electrode of the second transistor.

[0004] Patent Document 3 describes a level shift circuit including a level shifter that converts a low-voltage signal into a high-voltage signal. The level shifter includes an input transistor to which a low-voltage signal is input, and generates an output signal of the level shifter according to the on / off state of the input transistor. The level shift circuit includes a means for determining an input signal to the input transistor of the level shifter when the high-voltage power supply is turned on before the low-voltage power supply. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2008-131457 A [Patent Document 2] JP 2001-24502 ​​A [Patent Document 3] JP 2003-17996 A Summary of the Invention [Problem to be solved by the invention]

[0006] In a level shifter that includes an input stage circuit to which a relatively low level input signal is input, and an output stage circuit that converts the input signal into a relatively high level signal and outputs it, if the level of the power supply voltage supplied to the input stage circuit drops to approximately the level of the threshold voltage of a transistor that constitutes the output stage circuit, an appropriate output signal may not be obtained.

[0007] The disclosed technology aims to obtain an appropriate output signal in a level shifter including an input stage circuit to which a relatively low level input signal is input, and an output stage circuit that converts the input signal into a relatively high level signal and outputs it, even when the level of the power supply voltage supplied to the input stage circuit drops. [Means for solving the problem]

[0008] A level shifter according to the disclosed technology includes an input stage circuit to which a relatively low-level input signal is input, and an output stage circuit to convert the input signal into a relatively high-level signal and output the converted signal, the output stage circuit including a first transistor and a second transistor to which complementary signals generated according to the input signal are input, a first switch circuit having a main path connected to the first transistor and turned on when the second transistor is turned on and turned off when the second transistor is turned off, and a second switch circuit having a main path connected to the second transistor and turned on when the first transistor is turned on and turned off when the first transistor is turned off, the on-resistance of the first switch circuit being larger than the on-resistance of the first transistor, and the on-resistance of the second switch circuit being larger than the on-resistance of the second transistor. Effect of the Invention

[0009] According to the disclosed technology, in a level shifter including an input stage circuit to which a relatively low level input signal is input, and an output stage circuit that converts the input signal into a relatively high level signal and outputs it, it is possible to obtain an appropriate output signal even when the level of the power supply voltage supplied to the input stage circuit drops. [Brief description of the drawings]

[0010] [Figure 1] 1 is a circuit diagram illustrating an example of a configuration of a level shifter according to an embodiment of the disclosed technique. [Diagram 2] FIG. 1 is a circuit diagram showing an example of a configuration of a level shifter according to a comparative example. [Diagram 3] FIG. 11 is a circuit diagram showing an example of a configuration of a level shifter according to another embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an example of an embodiment of the disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals, and duplicated description will be omitted.

[0012] [First embodiment] 1 is a circuit diagram showing an example of a configuration of a level shifter 10 according to a first embodiment of the disclosed technique. The level shifter 10 includes an input stage circuit 30 and an output stage circuit 40. The input stage circuit 30 receives a relatively low-level input signal S in The output stage circuit 40 receives the input signal S in is converted to a relatively high level signal and this is output as the output signal S out The output is as follows:

[0013] The input stage circuit 30 includes a P-channel transistor 15, N-channel transistors 16, 17, and 18, and inverters 19 and 20. The source of the transistor 15 is connected to a relatively low-level power supply voltage V L The drain is connected to the power supply line 31 to which a reset signal S is applied, the drain is connected to the power supply terminals of the inverters 19 and 20, and the gate is connected to the power supply line 31 to which a reset signal S is applied. rst is connected to a reset input line 32 to which a reset signal is input.

[0014] The inverter 19 has an input terminal connected to the input signal S in The inverter 20 has an output terminal connected to the gate of the transistor 12 of the output stage circuit 40. The inverters 19 and 20 are connected to a signal input line 33 to which a signal is input, and an output terminal connected to the input terminal of the inverter 20. The output terminal of the inverter 20 is connected to the gate of the transistor 12 of the output stage circuit 40. L Powered by.

[0015] The transistor 16 has a drain connected to the input terminal of the inverter 20, a source connected to the ground line 34, and a gate connected to the reset input line 32. The transistor 17 has a drain connected to the drain (node ​​n1) of the transistor 11 of the output stage circuit 40, a source connected to the ground line 34, and a gate connected to the reset input line 32. The transistor 18 has a drain connected to the gate of the transistor 12 of the output stage circuit 40, a source connected to the ground line 34, and a gate connected to the reset input line 32.

[0016] The output stage circuit 40 includes P-channel transistors 13, 14, 23, and 24, N-channel transistors 11 and 12, and an inverter 21. The source of the transistor 13 is connected to a relatively high-level power supply voltage V H The transistor 23 is connected to a power supply line 41 to which a voltage is applied, its drain is connected to the source of the transistor 23, and its gate is connected to the drain (node ​​n2) of the transistor 12. The transistor 23 has its drain connected to the drain (node ​​n1) of the transistor 11, and its gate connected to the drain (node ​​n2) of the transistor 12. The cascade-connected transistors 13 and 23 form a first switch circuit 42. The transistor 13 is an example of a "third transistor" in the disclosed technology. The transistor 23 is an example of a "fourth transistor" in the disclosed technology. The first switch circuit 42 is an example of a "first switch circuit" in the disclosed technology.

[0017] The transistor 14 has a source connected to the power supply line 41, a drain connected to the source of the transistor 24, and a gate connected to the drain (node ​​n1) of the transistor 11. The transistor 24 has a drain connected to the drain (node ​​n2) of the transistor 12, and a gate connected to the drain (node ​​n1) of the transistor 11. The cascade-connected transistors 14 and 24 form a second switch circuit 43. The transistor 14 is an example of a "fifth transistor" in the disclosed technology. The transistor 24 is an example of a "sixth transistor" in the disclosed technology. The second switch circuit 43 is an example of a "second switch circuit" in the disclosed technology.

[0018] The transistor 11 has a source connected to the ground line 34 and a gate connected to the output terminal of the inverter 19. The transistor 12 has a source connected to the ground line 34 and a gate connected to the output terminal of the inverter 20.

[0019] The inverter 21 has a power supply terminal connected to the power supply line 41, and an input terminal connected to the drain (node ​​n2) of the transistor 12. The inverter 21 is connected to a relatively high-level power supply voltage V H The logic level of the signal input to the input terminal is inverted and the output signal S out The output is as follows:

[0020] The input stage circuit 30 converts the input signal S input to the signal input line 33 into in That is, the inverter 19 generates a complementary signal based on the input signal S in The inverter 20 outputs a signal that inverts the logic level of the input signal S in The RC21 outputs a signal of the same logic level as

[0021] In the output stage circuit 40, an output signal of an inverter 19 is input to the gate of the transistor 11, and an output signal of an inverter 20 is input to the gate of the transistor 12. The transistors 11 and 12 operate complementarily in response to complementary signals input thereto. The transistor 11 is an example of a "first transistor" in the disclosed technology. The transistor 12 is an example of a "second transistor" in the disclosed technology.

[0022] A first switch circuit 42 constituted by cascaded transistors 13 and 23 has a main path connected to the transistor 11 and a control end connected to a node n2. The first switch circuit 42 is turned on when the transistor 12 is turned on, and is turned off when the transistor 12 is turned off.

[0023] The second switch circuit 43, which is composed of cascaded transistors 14 and 24, has a main path connected to the transistor 12 and a control end connected to a node n1. The second switch circuit 43 is turned on when the transistor 11 is turned on, and is turned off when the transistor 11 is turned off.

[0024] The first switch circuit 42 and the second switch circuit 43 operate complementarily in response to the on / off of the transistors 11 and 12, which operate complementarily. The first switch circuit 42 is configured by cascaded transistors 13 and 23, so that the on-resistance (output resistance) of the first switch circuit 42 is larger than the on-resistance of the transistor 11. Similarly, the second switch circuit 43 is configured by cascaded transistors 14 and 24, so that the on-resistance of the second switch circuit 43 is larger than the on-resistance of the transistor 12. Here, the on-resistance of the transistors 11 and 12 refers to the on-resistance when they are half on.

[0025] The operation of the level shifter 10 will be described below. First, the reset operation will be described. When the level shifter 10 is caused to perform the reset operation, a high-level reset signal S rst As a result, each of the transistors 16, 17, and 18 is turned on, and the input signal S in Regardless of the logic level of the node n1, the transistors 11 and 12 are turned off. When the transistor 17 is turned on, the potential of the node n1 becomes low level, and the transistors 14 and 24 are turned on. As a result, the potential of the node n2 becomes high level, and the output signal S output from the output terminal of the inverter 21 becomes high level. out As described above, when the level shifter 10 is reset, the reset signal S ret When the input signal S in Regardless of the logic level of out will be output.

[0026] Next, in the level shift operation, the low-level input signal S in When the level shifter 10 is to perform a level shift operation, a low-level reset signal S is input to the reset input line 32. rst As a result, each of the transistors 16, 17, and 18 is turned off. In this state, a low-level input signal S is applied to the signal input line 33. in When the input signal S is input, a high-level signal is output from the inverter 19, which turns the transistor 11 on. Also, a low-level signal is output from the inverter 20, which turns the transistor 12 off. With the transistor 11 in the on state and the transistor 12 in the off state, the potential of the node n1 converges to a low level and the potential of the node n2 converges to a high level. As a result, the output signal S output from the output terminal of the inverter 21 out As described above, during the level shift operation of the level shifter 10, the low-level input signal S in When the input is low, the output signal Sout will be output.

[0027] Next, in the level shift operation, the high-level input signal S in When the level shifter 10 is to perform a level shift operation, a low-level reset signal S is input to the reset input line 32. rst is input, and a high-level input signal S in is input. As a result, a low level signal is output from the inverter 19, which turns the transistor 11 into an off state. Also, a high level signal is output from the inverter 20, which turns the transistor 12 into an on state. With the transistor 11 in an off state and the transistor 12 in an on state, the potential of the node n1 converges to a high level and the potential of the node n2 converges to a low level. As a result, the output signal S out As described above, when the level shifter 10 performs a level shift operation, the high-level input signal S in When the input is high, the output signal S out The relatively high level of the power supply voltage V H The output signal S output from the inverter 21 driven by out The level of the supply voltage V L An input signal S is input to an inverter 19 driven by in higher than the level of

[0028] 2 is a circuit diagram showing a configuration of a level shifter 10X according to a comparative example. The level shifter 10X according to the comparative example differs from the level shifter 10 (see FIG. 1) according to the embodiment of the disclosed technique in that, in an output stage circuit 40X, a first switch circuit 42X is composed only of a transistor 13, and a second switch circuit 43X is composed only of a transistor 14. The basic operation of the level shifter 10X according to the comparative example is the same as that of the level shifter 10 according to the embodiment of the disclosed technique.

[0029] In the level shifter 10X according to the comparative example, the power supply voltage V L Consider the case where the level of the input signal S drops to about the level of the threshold voltage of the transistors 11 and 12. In this case, in In response to this, the transistor 11 or 12 is in an incomplete half-on state. This causes the potential of the node n1 or the node n2 to become an intermediate potential, and an appropriate output signal S out may not be output.

[0030] On the other hand, in the level shifter 10 according to the embodiment of the disclosed technique, the first switch circuit 42 is composed of cascaded transistors 13 and 23, and the second switch circuit 43 is composed of cascaded transistors 14 and 24. This allows the on-resistance of the first switch circuit 42 to be greater than the on-resistance of the transistor 11 when half-on, and the on-resistance of the second switch circuit 43 to be greater than the on-resistance of the transistor 12 when half-on.

[0031] In the level shifter 10 according to the embodiment of the disclosed technique, the power supply voltage V L When the level of the input signal S drops to about the level of the threshold voltage of the transistors 11 and 12, as in the comparative example, in In response, the transistor 11 or 12 is in a half-on state.

[0032] For example, a low-level input signal S inWhen a voltage is input and the transistor 11 is in a half-on state, the on-resistance of the first switch circuit 42 is made larger than the on-resistance of the transistor 11 when it is half-on, so that the potential of the node n1 can be lowered to a level where the second switch circuit 43 is in a half-on state. With the second switch circuit 43 in a half-on state, the potential of the node n2 can be raised to a level where the first switch circuit 42 is in a half-off state. As a result, the potential of the node n1 can be converged to a low level, and the potential of the node n2 can be converged to a high level, so that a low-level output signal S out will be output.

[0033] Also, a high-level input signal S in When a voltage is input and the transistor 12 is in a half-on state, the on-resistance of the second switch circuit 43 is made larger than the on-resistance of the transistor 12 when it is half-on, so that the potential of the node n2 can be lowered to a level where the first switch circuit 42 is in a half-on state. With the first switch circuit 42 in a half-on state, the potential of the node n1 can be raised to a level where the second switch circuit 43 is in a half-off state. As a result, the potential of the node n1 can be converged to a high level, and the potential of the node n2 can be converged to a low level, so that a high-level output signal S out will be output.

[0034] As described above, according to the level shifter 10 according to the embodiment of the disclosed technique, the power supply voltage V L Even if the level of the input signal S in The appropriate output signal S out can be obtained.

[0035] In addition, by using multiple cascaded transistors as a means for increasing the on-resistance of the first switch circuit 42 and the second switch circuit 43, it is possible to obtain the substrate bias effect of the transistors 23 and 24. This can enhance the effect of increasing the on-resistance compared to the case where a single transistor is used as a means for increasing the on-resistance of the first switch circuit 42 and the second switch circuit 43. As a result, it is possible to reduce the size of the transistors, and to reduce the area and dead space of the first switch circuit 42 and the second switch circuit 43.

[0036] [Second embodiment] 3 is a circuit diagram showing an example of the configuration of a level shifter 10A according to a second embodiment of the disclosed technique. In the level shifter 10A according to the second embodiment, an output stage circuit 40A has a first switch circuit 42A composed of cascaded transistors 13 and 23, and a second switch circuit 43A composed of cascaded transistors 14 and 24, similar to the level shifter 10 according to the first embodiment (see FIG. 1). In the first switch circuit 42A, the gate of the transistor 23 is connected to the drain (node ​​n1) of the transistor 11, and the gate of the transistor 24 is connected to the drain (node ​​n2) of the transistor 12. That is, the transistors 23 and 24 are each diode-connected.

[0037] The first switch circuit 42A is configured with cascaded transistors 13 and 23, so that the on-resistance of the first switch circuit 42A is larger than the on-resistance of the transistor 11 when it is half on. Similarly, the second switch circuit 43 is configured with cascaded transistors 14 and 24, so that the on-resistance of the second switch circuit 43 is larger than the on-resistance of the transistor 12 when it is half on.

[0038] According to the level shifter 10A of the second embodiment, similarly to the level shifter 10 of the first embodiment, for example, when the input signal S in When a voltage is input and the transistor 11 is in a half-on state, the on-resistance of the first switch circuit 42A is made larger than the on-resistance of the transistor 11 when it is half-on, so that the potential of the node n1 can be lowered to a level where the second switch circuit 43A is in a half-on state. With the second switch circuit 43A in a half-on state, the potential of the node n2 can be raised to a level where the first switch circuit 42A is in a half-off state. As a result, the potential of the node n1 can be converged to a low level, and the potential of the node n2 can be converged to a high level, so that a low-level output signal S out If the potential of node n1 can be made to be a potential lower than the drain potential of transistor 13 by the threshold voltage of transistor 23 by transistor 11 in the half-on state, the potential of node n1 can be made to converge to a low level and the potential of node n2 can be made to converge to a high level.

[0039] Also, a high-level input signal S in When a voltage is input and the transistor 12 is in a half-on state, the on-resistance of the second switch circuit 43A is made larger than the on-resistance of the transistor 12 when it is half-on, so that the potential of the node n2 can be lowered to a level where the first switch circuit 42A is in a half-on state. With the first switch circuit 42A in a half-on state, the potential of the node n1 can be raised to a level where the second switch circuit 43A is in a half-off state. As a result, the potential of the node n1 can be converged to a high level, and the potential of the node n2 can be converged to a low level, so that a high-level output signal S out If the potential of node n2 can be made to be a potential lower than the drain potential of transistor 14 by the threshold voltage of transistor 24 by transistor 12 in the half-on state, the potential of node n1 can be made to converge to a high level, and the potential of node n2 can be made to converge to a low level.

[0040] As described above, according to the level shifter 10A according to the second embodiment of the disclosed technique, the power supply voltage V L Even if the level of the input signal S in The appropriate output signal S out can be obtained.

[0041] Moreover, according to the level shifter 10A of the second embodiment, if the transistor 11 in the half-on state can set the potential of the node n1 to a potential lower than the drain potential of the transistor 13 by the threshold voltage of the transistor 23, the potential of the node n1 can be converged to a low level and the potential of the node n2 can be converged to a high level, and if the transistor 12 in the half-on state can set the potential of the node n2 to a potential lower than the drain potential of the transistor 14 by the threshold voltage of the transistor 24, the potential of the node n1 can be converged to a high level and the potential of the node n2 can be converged to a low level. This makes it possible to further reduce the size of the transistors constituting the first switch circuit 42A and the second switch circuit 43A, and further reduce the area and dead space of the first switch circuit 42 and the second switch circuit 43.

[0042] Moreover, according to the level shifter 10A of the second embodiment, the output signal S out Since the state of the input signal can be fixed, it can also be used as a state fixing circuit.

[0043] The following supplementary notes are further disclosed regarding the above first and second embodiments. (Appendix 1) 1. A level shifter including an input stage circuit to which a relatively low-level input signal is input, and an output stage circuit to convert the input signal into a relatively high-level signal and output the converted signal, the output stage circuit includes a first transistor and a second transistor to which complementary signals generated in response to the input signal are respectively input; a first switch circuit, the main path of which is connected to the first transistor, the first switch circuit being turned on when the second transistor is turned on, and being turned off when the second transistor is turned off; a second switch circuit, the main path of which is connected to the second transistor, the second switch circuit being turned on when the first transistor is turned on, and being turned off when the first transistor is turned off; Including, The on-resistance of the first switch circuit is larger than the on-resistance of the first transistor, and the on-resistance of the second switch circuit is larger than the on-resistance of the second transistor. Level shifter.

[0044] (Appendix 2) the first switch circuit includes a third transistor and a fourth transistor connected in cascade; The second switch circuit includes a fifth transistor and a sixth transistor that are cascaded together. 2. A level shifter as defined in claim 1.

[0045] (Appendix 3) the gates of the third transistor and the fourth transistor are connected to the drain of the second transistor; The gates of the fifth transistor and the sixth transistor are connected to the drain of the first transistor. 2. A level shifter as defined in claim 2.

[0046] (Appendix 4) a gate of the third transistor is connected to a drain of the second transistor; a gate of the fourth transistor is connected to a drain of the first transistor; a gate of the fifth transistor is connected to a drain of the first transistor; The gate of the sixth transistor is connected to the drain of the second transistor. 2. A level shifter as defined in claim 2.

[0047] (Appendix 5) the input stage circuit includes a first inverter and a second inverter connected in cascade and driven by a relatively low-level power supply voltage; the input signal is input to the first inverter; an output signal of the first inverter is input to the second inverter and the first transistor; an output signal of the second inverter is input to the second transistor; the output stage circuit includes a third inverter driven by a relatively high level power supply voltage; A signal generated at a connection point between the second transistor and the second switch circuit is input to the third inverter. 5. A level shifter according to any one of claims 1 to 4. [Explanation of symbols]

[0048] 10, 10A, 10X Level Shifter 11, 12, 13, 14, 15, 16, 17, 18, 23, 24 Transistors 19, 20, 21 Inverter 30 Input stage circuit 40, 40A, 40X output stage circuit 42, 42A, 42X First switch circuit 43, 43A, 43X Second switch circuit

Claims

1. 1. A level shifter including an input stage circuit to which a relatively low-level input signal is input, and an output stage circuit to convert the input signal into a relatively high-level signal and output the converted signal, the output stage circuit includes a first transistor and a second transistor to which complementary signals generated in response to the input signal are respectively input; a first switch circuit, the main path of which is connected to the first transistor, the first switch circuit being turned on when the second transistor is turned on, and being turned off when the second transistor is turned off; a second switch circuit, the main path of which is connected to the second transistor, the second switch circuit being turned on when the first transistor is turned on, and being turned off when the first transistor is turned off; Including, The on-resistance of the first switch circuit is larger than the on-resistance of the first transistor, and the on-resistance of the second switch circuit is larger than the on-resistance of the second transistor. Level shifter.

2. the first switch circuit includes a third transistor and a fourth transistor connected in cascade; The second switch circuit includes a fifth transistor and a sixth transistor that are cascaded together.

2. The level shifter according to claim 1.

3. the gates of the third transistor and the fourth transistor are connected to the drain of the second transistor; The gates of the fifth transistor and the sixth transistor are connected to the drain of the first transistor.

3. The level shifter according to claim 2.

4. a gate of the third transistor is connected to a drain of the second transistor; a gate of the fourth transistor is connected to a drain of the first transistor; a gate of the fifth transistor is connected to a drain of the first transistor; The gate of the sixth transistor is connected to the drain of the second transistor.

3. The level shifter according to claim 2.

5. the input stage circuit includes a first inverter and a second inverter connected in cascade and driven by a relatively low-level power supply voltage; the input signal is input to the first inverter; an output signal of the first inverter is input to the second inverter and the first transistor; an output signal of the second inverter is input to the second transistor; the output stage circuit includes a third inverter driven by a relatively high level power supply voltage; A signal generated at a connection point between the second transistor and the second switch circuit is input to the third inverter.

2. The level shifter according to claim 1.

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