Digital output mechanism for analog neural memory in deep learning artificial neural network

Abstract

To provide an output block that reads or verifies a value stored in selected non-volatile memory cells within a vector matrix multiplication (VMM) array in an artificial neural network.SOLUTION: An output block 4500 includes a current-to-voltage converter 4501 and an analog-to-digital converter 4502. The output block 4500 receives an output current from a VMM array, shown here as Ineu. Here, the output current represents an output value from the VMM array for a read or verification operation being performed. The current-to-voltage converter 4501 converts the output current Ineu into a voltage signal, shown here as VOUT, such that the voltage VOUT represents the output current Ineu from the VMM. The analog-to-digital converter 4502 converts the voltage VOUT to a digital form and provides a digital output, shown here as DOUT.SELECTED DRAWING: Figure 45

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 133,270, entitled "Input and Digital Output Mechanisms for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on January 1, 2021, and U.S. Patent Application No. 17 / 219,352, entitled "Digital Output Mechanisms for Analog Neural Memory in a Deep Learning Artificial Neural Network," filed on March 31, 2021.

[0002] FIELD OF THEINVENTION Numerous embodiments of an output mechanism for reading or verifying non-volatile memory cells within a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages between each other.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the output of the neural network. At each level, the neurons make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Serial No. 15 / 594,439, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each of which includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate insulated and disposed above a first portion of the channel region, and a non-floating gate insulated and disposed above a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons in the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0007] Each non-volatile memory cell used in an analog neuromorphic memory system must hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate in response to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] Since the output of one VMM often needs to be applied to another VMM, it is desirable in a VMM system to be able to convert the output of a VMM into bits and apply the input bits to another VMM. The question then arises as to how best to implement the bit encoding mechanism of the VMM system.

[0009] What is needed is an improved input and output block for the VMM to perform programming, verifying, and reading. Summary of the Invention

[0010] Numerous embodiments are disclosed for reading or verifying values ​​stored in selected memory cells in a vector matrix multiplication (VMM) array in an artificial neural network. The embodiments include various designs of input and output blocks for use with the VMM array.

[0011] In one embodiment, an output block for generating an output from an array of non-volatile memory cells comprises a current-to-voltage converter for receiving a series of currents from one or more selected non-volatile memory cells in the generated array in response to a series of inputs to the array, and for generating a voltage or series of voltages in response to the series of currents, and an analog-to-digital converter for converting the voltage or series of voltages into a plurality of output bits, the plurality of output bits reflecting a weighting function performed on one or more of the series of currents or voltages or series of voltages.

[0012] In another embodiment, an output block for generating an output from an array of non-volatile memory cells comprises a current-to-voltage converter for receiving a current from one or more selected non-volatile memory cells in the array in response to an input applied to the array and converting the current to a voltage, the current-to-voltage converter comprising a sample-and-hold circuit for holding the voltage.

[0013] In another embodiment, an output block for generating an output from a series of currents received from the array of non-volatile memory cells in response to a series of inputs received by the array of non-volatile memory cells comprises an analog-to-digital converter for receiving the series of currents and converting the series of currents into an output comprising a plurality of output bits.

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[0071] [Brief description of the drawings]

[0072] [Figure 1] FIG. 1 illustrates an artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more vector matrix multiplication systems. [Figure 9] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 10] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 11] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 1 shows a prior art long-term and short-term memory system. [Figure 15]An exemplary cell for use in a long- and short-term memory system is shown. [Figure 16] 16 illustrates an embodiment of the exemplary cell of FIG. 15. [Figure 17] 16 illustrates an alternative embodiment of the exemplary cell of FIG. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an embodiment of the exemplary cell of FIG. 19. [Figure 21] 20 illustrates an alternative embodiment of the exemplary cell of FIG. 19. [Figure 22A] 1 illustrates one embodiment of a method for programming a non-volatile memory cell. [Figure 22B] 1 illustrates another embodiment of a method for programming a non-volatile memory cell. [Diagram 23] 1 illustrates one embodiment of a coarse programming method. [Figure 24] 3 illustrates exemplary pulses used in programming non-volatile memory cells. [Diagram 25] 3 illustrates exemplary pulses used in programming non-volatile memory cells. [Figure 26A] 1 illustrates a calibration algorithm for programming non-volatile memory cells that adjusts programming parameters based on the tilt characteristics of the cell. [Figure 26B] 1 illustrates a calibration algorithm for programming non-volatile memory cells that adjusts programming parameters based on the tilt characteristics of the cell. [Figure 27] 27 shows the circuit used in the calibration algorithm of FIG. 26. [Figure 28] 1 illustrates a calibration algorithm for programming non-volatile memory cells. [Figure 29] 29 shows the circuit used in the calibration algorithm of FIG. 28. [Diagram 30]4 illustrates an exemplary progression of voltages applied to the control gates of non-volatile memory cells during a programming operation. [Diagram 31] 4 illustrates an exemplary progression of voltages applied to the control gates of non-volatile memory cells during a programming operation. [Diagram 32] 1 illustrates a system for applying programming voltages during programming of non-volatile memory cells in a vector multiplication matrix system. [Diagram 33] 1 shows a charge summer circuit. [Diagram 34] 1 shows a current totalizer circuit. [Diagram 35] 1 shows a digital totalizer circuit. [Figure 36A] 1 illustrates one embodiment of an integrated analog-to-digital converter for neuron outputs. [Figure 36B] 36B shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter of FIG. 36A. [Figure 36C] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 36D] 36D shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter of FIG. 36C. [Figure 36E] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 36F] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 37A] 1 shows a successive approximation analog-to-digital converter for neuron outputs. [Figure 37B] 1 shows a successive approximation analog-to-digital converter for neuron outputs. [Figure 38] 1 illustrates an embodiment of a sigma-delta analog-to-digital converter. [Figure 39] The output block is shown. [Diagram 40] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 41] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 42] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 43] 1 shows a block diagram of a vector matrix multiplication system. [Diagram 44] A digital totalizer is shown. [Diagram 45] The output block is shown. [Diagram 46] 1 illustrates an embodiment of a current-to-voltage converter. [Figure 47] 3 illustrates another embodiment of a current-to-voltage converter. [Figure 48] 3 illustrates another embodiment of a current-to-voltage converter. [Figure 49A] 3 illustrates another embodiment of a current-to-voltage converter. [Figure 49B] 1 illustrates an embodiment of a lossless variable resistor. [Figure 50] 3 illustrates another embodiment of a current-to-voltage converter. [Figure 51] 3 illustrates another embodiment of a current-to-voltage converter. [Figure 52A] 1 illustrates an embodiment of a hybrid serializer. [Figure 52B] 1 illustrates an embodiment of a hybrid serializer. [Figure 52C] 1 illustrates an embodiment of a hybrid serializer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0073] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. Non-volatile Memory Cell

[0074] Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18) and a second portion extending upwardly above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0075] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0076] The memory cell 210 is programmed by hot electron source side injection (SSI) (electrons are injected into the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electron current flows from the drain region 16 towards the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0077] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0078] Table 1 shows typical voltage and current ranges that can be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. [Table 1]

[0079] Other split-gate memory cell configurations are also known for other types of flash memory cells. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0080] Table 2 shows typical voltage / current ranges that can be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the Flash Memory Cell 310 of FIG. [Table 2]

[0081] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (where erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line during a program operation to compensate for the lack of control gate bias.

[0082] Table 3 shows typical voltage / current ranges that can be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 410 of FIG. [Table 3]

[0083] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. The memory cell 510 is similar to the memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and the control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is done by FN tunneling of electrons from the FG to the substrate, and programming is done by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 towards the drain region 16, and by a read operation that is similar to the read operation of the memory cell 210 with a higher control gate voltage.

[0084] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 510 of FIG. [Table 4]

[0085] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive random access memory), PCM (phase change memory), MRAM (magnetoresistive memory), FeRAM (ferroelectric memory), CT (charge trap) memory, CN (carbon tube) memory, OTP (bi-level or multi-level one-time programmable) and CeRAM (strongly correlated electron memory).

[0086] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0087] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), which allows every cell in the memory array to be very precisely and individually tunable, making the memory array ideal for storage and fine tuning adjustments to the synaptic weights of neural networks. Neural network using non-volatile memory cell arrays

[0088] 6 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiment. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0089] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, each pixel with 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplication, determines a single output value, which is given by the first synapse of CB1 to generate one pixel of the feature map of layer C1. The 3x3 filter is then shifted by one pixel to the right in the input layer S0 (i.e., adding a column of 3 pixels to the right and dropping a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of layer C1, until all feature maps of layer C1 have been calculated.

[0090] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, and a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0091] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function P1 is to average nearby positions (or a max function can be used), e.g., to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). The synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At the synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. The synapse CB4 going from layer C3 to the output layer S3 fully connects C3 to S3, i.e. every neuron in layer C3 connects to every neuron in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identity or classification (class) of the content of the original image.

[0092] Each layer of the synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0093] 7 is a block diagram of an array that can be used for that purpose. A vector matrix multiplication (VMM) array 32 contains non-volatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in FIG. 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the non-volatile memory cell array 33.

[0094] The non-volatile memory cell array 33 serves two purposes. First, the memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and adds them for each output line (source line or bit line) to generate an output that becomes the input to the next layer or the input to the last layer. With the non-volatile memory cell array 33 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and in-memory computation is also more power efficient.

[0095] The outputs of the non-volatile memory cell array 33 are provided to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0096] The summed output values ​​of the differential summers 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function circuit 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a number of synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing op-amps 38 and the activation function circuit 39 constitute a number of neurons.

[0097] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0098] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be done by an analog to analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0099] The output generated by the input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as input to the input VMM array (hidden level 2) 32c, and so on. The various layers of the VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM arrays 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or the multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or the multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. The example shown in FIG. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that the system may instead include more than two hidden layers and more than two fully connected layers. Vector Matrix Multiplication (VMM) Array

[0100] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0101] In the VMM array 900, control gate lines such as control gate line 903 run vertically (so that the row-wise reference array 902 is orthogonal to control gate line 903) and erase gate lines such as erase gate line 904 run horizontally. Here, inputs to the VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 900 appear on the source lines (SL0, SL1). In one embodiment, only the even rows are used, and in another embodiment, only the odd rows are used. The current in each source line (SL0, SL1 respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0102] As described herein for neural networks, the non-volatile memory cells of VMM array 900, namely memory cells 310 of VMM array 900, are preferably configured to operate in the sub-threshold region.

[0103] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids=Io*e(Vg-Vth) / nVt=w*Io*e(Vg) / nVt Wherein w=e(-Vth) / nVt; where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k * T / q, k is the Boltzmann constant, T is the temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is proportional to (Wt / L) * u * Cox * (n-1) * Vt2, where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0104] When using an IV-log converter that uses memory cells (such as reference or peripheral memory cells) or transistors to convert the input current to an input voltage: Vg=n*Vt*log[Ids / wp*Io] where wp is the w of the reference or periphery memory cell.

[0105] For a memory array used as a vector matrix multiplier VMM array with current inputs, the output current is: Iout=wa*Io*e(Vg) / nVt, i.e. Iout=(wa / wp)*Iin=W*Iin W=e(Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is designated Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth=Vth0+gamma(SQRT|Vsb-2*ΦF)-SQRT|2*ΦF|) where Vth0 is the threshold voltage with zero substrate bias, ΦF is the surface potential, and gamma is the body effect parameter.

[0106] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0107] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta*(Vgs-Vth)*Vds; beta=u*Cox*Wt / L W = α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth)

[0108] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0109] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert the input and output currents to input and output voltages.

[0110] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2*beta*(Vgs-Vth)2; beta=u*Cox*Wt / L W α (Vgs-Vth)2, i.e., the weight W is proportional to (Vgs-Vth)2

[0111] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0112] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation) for each layer or layers of a neural network.

[0113] Other embodiments for the VMM array 32 of Figure 7 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0114] FIG. 10 shows a neuron VMM array 1000, which is particularly suitable for the memory cells 210 shown in FIG. 2 and is used as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of a first non-volatile reference memory cell, and a reference array 1002 of a second non-volatile reference memory cell. The reference arrays 1001 and 1002 arranged in the columns of the array function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (only a portion of which is shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0115] The memory array 1003 serves two purposes. First, it stores the weights in each memory cell that are used by the VMM array 1000. Second, it effectively multiplies the weights stored in it by the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1001 and 1002 convert to input voltages and provide to the word lines WL0, WL1, WL2, and WL3) and then adds all the results (memory cell currents) to generate an output for each bit line (BL0-BLN), which is the input to the next layer or the input to the last layer. By performing the multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current in each of the bit lines BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0116] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the selected cell's word line, the unselected cell's word line, the selected cell's bit line, the unselected cell's bit line, the selected cell's source line, and the unselected cell's source line. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0117] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of non-volatile memory cells, a reference array 1101 of first non-volatile reference memory cells, and a reference array 1102 of second non-volatile reference memory cells. The reference arrays 1101 and 1102 run in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current of each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0118] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table show the voltages applied to the selected cell's word line, the unselected cell's word line, the selected cell's bit line, the unselected cell's bit line, the selected cell's source line, and the unselected cell's source line. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in FIG. 11 [Table 6]

[0119] 12 shows a neuron VMM array 1200, which is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexer 1212 includes a corresponding multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0120] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, it effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to the control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to produce an output that appears on BL0-BLN and is the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient, where the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current in each bit line is a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0121] The VMM array 1200 implements one-way tuning of the non-volatile memory cells in the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (such as an incorrect value being stored in the cell), the cell is erased and the series of partial programming operations starts over again. As shown, two rows that share the same erase gate (such as EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0122] Table 7 shows the operating voltages and currents of VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the control gate of the selected cell, the control gate of the unselected cells in the same sector as the selected cell, the control gate of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gate of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in FIG. 12 [Table 7]

[0123] FIG. 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of non-volatile memory cells, a reference array 1301 or a first non-volatile reference memory cell, and a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 run vertically, and the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 run horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2 and BLR3 into control gate voltages CG0, CG1, CG2 and CG3 (through the action of diode-connected reference cells via multiplexer 1314) which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums all the currents from the non-volatile memory cells connected to that particular bit line.

[0124] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the control gate of the selected cell, the control gate of the unselected cells in the same sector as the selected cell, the control gate of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gate of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in FIG. 13 [Table 8] Improved VMM systems through page or word based tuning.

[0125] FIG. 40 illustrates a VMM array 4000. The VMM array 4000 implements one-way or two-way tuning of pages of non-volatile memory cells. Here, an exemplary page 4001 includes two words, each in a different row. A word includes multiple memory cells, e.g., 8-64. A particular word may include only one cell or a few cells. Pairs of adjacent rows share a source line, such as SL0 or SL1. All cells in a page 4001 share a common erase gate line controlled by an erase gate enable transistor 4002, which controls the provision of a voltage to the erase gate terminal EGW of all cells in an exemplary page set 4001. Here, all cells in a page 4001 may be erased simultaneously. Thereafter, the cells in the page 4001 may be tuned unidirectionally or bidirectionally through program (cell-by-cell, meaning that each cell in a word may be tuned at once; word-by-word, meaning that all cells in a word may be tuned simultaneously) and erase (word-by-word, meaning that all cells in a word may be tuned simultaneously) operations, and some cells in the page 4001 may be tuned unidirectionally through a program operation. The program operation may include precision programming techniques described below with reference to Figures 24-26. If too much electronic charge is placed on the floating gate (causing an incorrect current value, i.e., a current value lower than the intended current value, to be stored in the cell), the cell must be erased and the partial programming operation sequence must be repeated.

[0126] FIG. 41 illustrates a VMM array 4100. The VMM array 4100 implements unidirectional or bidirectional tuning of a word of non-volatile memory cells, where an exemplary word 4101 includes multiple cells in a row. All cells in the word 4101 share a common erase gate line controlled by an erase gate enable transistor 4102, which controls the provision of a voltage to the erase gate terminals of all cells in the word 4101. Here, all cells in the word 4101 can be erased simultaneously. The cells in the word 4101 can then be tuned unidirectionally or bidirectionally through program (cell-by-cell means that each cell in the word can be tuned at once, word-by-word means that all cells in the word can be tuned at the same time) and erase (word-by-word means that all cells in the word can be tuned at the same time) operations. The program operation can include precision programming techniques described below. If too much electronic charge is placed on the floating gate (resulting in an incorrect current value, i.e., a current value lower than intended, being stored in the cell), the cell must be erased and the partial programming sequence must be repeated.

[0127] FIG. 42 illustrates a VMM array 4200. The VMM array 4200 implements unidirectional or bidirectional tuning of words of non-volatile memory cells. Here, an exemplary word 4201 includes two half-words of cells. Each half-word belongs to a row that shares an erase gate. All cells in the word 4201 share a common erase gate line connected to the erase gate terminal EGW. Unlike the VMM arrays 1800 and 1700, there is no erase gate enable transistor. Here, all cells in the word 4201 can be erased simultaneously. Then, the cells in the word 4201 can be tuned unidirectionally or bidirectionally through program (cell-by-cell means that each cell in the word can be tuned at once, word-by-word means that all cells in the word can be tuned at the same time) and erase (word-by-word means that all cells in the word can be tuned at the same time) operations. The program operation can include the precision programming technique described below. If too much electronic charge is placed on the floating gate (resulting in an incorrect current value, i.e., a current value lower than intended, being stored in the cell), the cell must be erased and the partial programming sequence must be repeated. Long and short term memory

[0128] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any given period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0129] FIG. 14 illustrates an exemplary LSTM 1400. The LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, an output vector (hidden state) h0 from cell 1401, and a cell state c0 from cell 1401, and generates an output vector h1 and a cell state vector c1. Cell 1403 receives an input vector x2, an output vector (hidden state) h1 from cell 1402, and a cell state c1 from cell 1402, and generates an output vector h2 and a cell state vector c2. Cell 1404 receives an input vector x3, an output vector (hidden state) h2 from cell 1403, and a cell state c2 from cell 1403, and generates an output vector h3. Additional cells can be used, the LSTM with four cells is just an example.

[0130] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. The LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0131] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0132] 16 shows an example of an implementation of LSTM cell 1500, LSTM cell 1600. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each include multiple VMM arrays 1601 and activation circuit blocks 1602. Thus, VMM arrays prove particularly useful in LSTM cells used in certain neural network systems.

[0133] An alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502 and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adding device 1708 for adding two vectors, a tanh device 1505 (including an activation circuit block 1702), a register 1707 for storing a value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing a value f(t)*c(t-1) when that value is output from the multiplier device 1703 via a multiplexer 1710, a register 1705 for storing a value i(t)*u(t) when that value is output from the multiplier device 1703 via the multiplexer 1710, a register 1706 for storing a value o(t)*ĉ(t) when that value is output from the multiplier device 1703 via the multiplexer 1710, and a multiplexer 1709.

[0134] Whereas LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in embodiments of LSTM cell 1700. LSTM cell 1700 requires less space than LSTM cell 1600 because LSTM cell 1700 requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 1600.

[0135] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as a summer and activation circuit block and a high voltage generation block. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself. Gated Recurrent Unit

[0136] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain a smaller number of components than LSTM cells.

[0137] 18 illustrates an exemplary GRU 1800. The GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells may be used, and a GRU with four cells is merely an example.

[0138] FIG. 19 illustrates an exemplary implementation of a GRU cell 1900 that can be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. The GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number from 0 to 1 to the output vector h(t-1) and components from the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an addition device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0139] Figure 20 shows GRU cell 2000, which is an example of one implementation of GRU cell 1900. For the convenience of the reader, the same numbering scheme from GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. It can therefore be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems.

[0140] An alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902, and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. The GRU cell 2100 also comprises a multiplier device 2103 for multiplying the two vectors, an addition device 2105 for adding the two vectors, a complementation device 2109 for subtracting an input from one to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)*r(t) as it is output from the multiplier device 2103 via the multiplexer 2104, a register 2107 for holding the value h(t-1)*z(t) as it is output from the multiplier device 2103 via the multiplexer 2104, and a register 2108 for holding the value h^(t)*(1-z((t)) as it is output from the multiplier device 2103 via the multiplexer 2104.

[0141] Whereas GRU cell 2000 includes multiple sets of VMM array 2001 and activation function blocks 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function blocks 2102, which are used to represent multiple tiers in an embodiment of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because GRU cell 2100 requires ⅓ of the space for the VMM and activation function blocks compared to GRU cell 2000.

[0142] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as summer and activation circuit blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0143] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in this case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in this case an output ADC is required to convert the output analog level to a digital bit).

[0144] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, or by a differential cell, or by two blended memory cells (average of two cells). In the case of differential cells, two memory cells are required to implement weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to implement weight W as an average of two cells. VMM System Overview

[0145] 43 shows a block diagram of a VMM system 4300. The VMM system 4300 comprises a VMM array 4301, a row decoder 4302, a high voltage decoder 4303, a column decoder 4304, a bit line driver 4305, an input circuit 4306, an output circuit 4307, a control logic 4308, and a bias generator 4309. The VMM system 4300 further comprises a high voltage generation block 4310, including a charge pump 4311, a charge pump regulator 4312, and a high voltage level generator 4313. The VMM system 4300 further comprises a (program / erase, or also known as weight tuning) algorithm controller 4314, an analog circuit 4315, a control engine 4316 (which may include special functions such as arithmetic functions, start-up functions, embedded microcontroller logic, etc.), and a test control logic 4317. The systems and methods described below may be implemented in the VMM system 4300.

[0146] The input circuit 4306 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time modulated pulse converter), an AAC (analog-to-analog converter such as a current-to-voltage converter, a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 4306 may implement a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 4306 may implement a temperature compensation function for the input level. The input circuit 4306 may implement an activation function such as ReLU or sigmoid. The output circuit 4307 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog output to digital bits), an AAC (analog-to-analog converter such as a current-to-voltage converter, a logarithmic converter), an APC (analog-to-pulse converter, analog-to-time modulated pulse converter), or any other type of converter. The output circuit 4307 may implement an activation function such as ReLU or sigmoid. The output circuit 4307 may implement statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) of the neuron outputs. The output circuit 4307 may implement temperature compensation functions for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant, or to increase the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same. Embodiments for precision programming of cells in a VMM

[0147] FIG. 22A illustrates a programming method 2200. Initially, the method begins (step 2201), typically in response to a program command received. Next, a mass program operation programs all cells to a "0" state (step 2202). Then, a soft erase operation erases all cells to an intermediate level (achieved by weak erasure, i.e., not complete erasure) so that each cell draws about 3-5 μA of current during a read operation (step 2203). This is in contrast to a deeply erased level, where each cell draws about 20-30 μA of current during a read operation. Then, a hard program is performed (step 2204) that adds electrons to the floating gates of all unselected or zero weight cells (i.e., cells with weight=zero or negligible weight, i.e., weight within the negligible threshold) to a very deep programmed state and removes all positive charge, ensuring that those cells are truly "off", meaning that they draw a negligible amount of current during a read operation.

[0148] A coarse programming method is then performed on the selected cells (step 2205), followed by a fine programming method (step 2206) to program the desired fine value into each selected cell, where a selected cell is one that has been identified as a target for the programming method 2200 and selected by asserting appropriate word and bit lines or by some other mechanism.

[0149] FIG. 22B illustrates another programming method 2210 similar to programming method 2200. However, after the method starts (step 2201), instead of a program operation to program all cells to a "0" state as in step 2202 of FIG. 22A, an erase operation is used to erase all cells to a "1" state (step 2212). A soft program operation (step 2213) is then used to program all cells to an intermediate level (achieved by soft programming, i.e., not full programming), so that each cell draws about 3-5 uA of current during a read operation. This is followed by hard programming of unselected cells (step 2204) as well as coarse and fine programming methods (steps 2205-2206), as described above in connection with FIG. 22A. A variation of the embodiment of FIG. 22B removes the soft programming method (step 2213) entirely.

[0150] FIG. 23 illustrates a first embodiment of the coarse programming method 2205, which is a search and execute method 2300. First, a lookup table lookup, or a predefined function, is performed to determine a coarse target current value (ICT) for each selected cell based on the value intended to be stored in the selected cell (step 2301). The selected cell can be programmed to store one of N (e.g., without limitation, 128, 64, 32) possible values. Each of the N values ​​corresponds to a different desired current value (ID) to be drawn by the selected cell during a read operation. In one embodiment, the lookup table or function (e.g., a function derived from a curve fit to the data, or a function based on the physics of memory behavior, which operates on variables such as the final target value and existing values ​​to calculate the expected or desired target for the next operation) contains M possible current values ​​to use as the coarse target current value ICT for the selected cell during the search and execute method 2300, where M is an integer less than N. For example, if N is 8, then M could be 4, meaning that there are 8 possible values ​​that the selected cell can store, and one of the four coarse target current values ​​ICT is selected as the coarse target current value ICT for the search and execute method 2300. That is, the search and execute method 2300 is arranged to quickly program the selected cell to a coarse target current value (ICT) that is somewhat close to the desired current value ID, and then the fine programming method 2206 more precisely programs the selected cell to be very close to the desired current value ID.

[0151] Examples of cell values, desired current values, and coarse target current values ​​are shown in Tables 9 and 10 for a simple example of N=8 and M=4. Table 9: Example of N desired current values ​​for N=8 [Table 9] Table 10: Example of M target current values ​​for M=4 [Table 10] The offset values ​​ICTOFFSETx are used to prevent overshooting the desired current value during coarse programming.

[0152] Once the coarse target current value ICT is selected, the selected cell is programmed (step 2302) by applying a voltage v0 to an appropriate terminal of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510). If the selected cell is of the type of memory cell 310 of FIG. 3, then a voltage v0 is applied to control gate terminal 28, where v0 can be 5-7 V depending on the coarse target current value ICT. The value of v0 can optionally be determined from a voltage lookup table that stores v0 in correspondence with the coarse target current value ICT.

[0153] The selected cell is then programmed by applying a voltage vi=vi-1+vincrement, where i starts at 1 and increments each time this step is repeated (step 2303), with vinccrement being a small voltage that causes programming to a degree commensurate with the granularity of the change desired. Thus, a first time step 2303 is performed with i=1, and v1 is v0+vincrement. A read operation is then performed on the selected cell, and a verify operation is performed in which the current drawn through the selected cell (Icell) is measured (step 2304). If Icell is less than or equal to ICT (first threshold value), the search and execute method 2300 is complete and the fine programming method 2206 can begin. If Icell is not less than or equal to ICT, step 2303 is repeated and i is incremented.

[0154] Thus, at the point where the coarse programming method 2205 ends and the fine programming method 2206 begins, the voltage vi is the last voltage used to program the selected cell, and the selected cell stores a value associated with the coarse target current value ICT. The fine programming method 2206 programs the selected cell to a point where, during a read operation, the selected cell will draw a desired current value ID (plus or minus an acceptable amount of deviation, such as 50 pA or less), this current being the desired current value ID associated with the value intended to be stored in the selected cell.

[0155] FIG. 24 shows examples of different voltage progressions that can be applied to the control gates of selected memory cells during the fine programming method 2206.

[0156] In the first embodiment, an increasing voltage is applied progressively to the control gate to further program the selected memory cell. The starting point is vi, which is the last voltage applied during the coarse programming method 2205. An increment vp1 is applied to v1, and then a voltage v1+vp1 is used to program the selected cell (indicated by the second pulse from the left in progression 2401). vp1 is an increment smaller than v increment (the voltage increment used during the coarse programming method 2205). After each programming voltage is applied, a verify step (similar to step 2304) is performed in which a determination is made whether Icell is less than or equal to IPT1 (the first precision target current value, here the second threshold value), where IPT1=ID+IPT1OFFSET, where IPT1OFFSET is an offset value added to prevent program overshoot. If not, another increment vp1 is added to the previously applied programming voltage, and the process is repeated. This part of the programming sequence stops when Icell is less than or equal to IPT1 Optionally, if IPT1 is equal to ID or approximately equal to ID with sufficient accuracy (meaning an acceptable amount of deviation), the selected memory cell has been successfully programmed.

[0157] If IPT1 is not equal to ID or is not nearly equal to ID with sufficient accuracy, further programming of smaller granularity is performed. Now, progression 2402 is used. The starting point of progression 2402 is the last voltage used for programming under progression 2401. An increment Vp2 (less than vp1) is added to that programming voltage and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verify step (similar to step 2304) is performed in which a determination is made whether Icell is less than or equal to IPT2 (a second precision target current value, here a third threshold value), where IPT2=ID+IPT2OFFSET, where IPT2OFFSET is an offset value added to prevent program overshoot. If Icell is not less than or equal to IPT2, another increment Vp2 is added to the previously applied programming voltage and the process is repeated. At the point where Icell is less than or equal to IPT2, this part of the programming sequence stops. Here, it is assumed that the target value has been achieved with sufficient accuracy so that IPT2 is equal to ID or close enough to ID that programming can stop. Those skilled in the art can appreciate that if IPT2 is not equal to ID or close enough to ID that programming can stop, additional progressions can be applied using smaller and smaller programming increments. For example, in Figure 25, three progressions (2501, 2502, and 2503) are applied instead of just two.

[0158] A second embodiment is shown in progression 2403. Here, instead of increasing the programming voltage applied during programming of a selected memory cell, the same programming voltage is applied for increasing periods of time duration. Instead of adding an incremental voltage, such as vp1 in progression 2401 and vp2 in progression 2403, an additional time increment tp1 is added to the programming pulse such that each applied pulse is tp1 longer than the previously applied pulse. In the illustrated example, the first pulse has duration tp0 and the second pulse has duration tp0+tp1. After each programming pulse is applied, the same verify step is performed as described above for progression 2401. Optionally, additional progressions can be applied in which the additional time increment added to the programming pulse is of a shorter duration than the previous progression used. Although only one temporal progression is shown, one skilled in the art will understand that any number of different temporal progressions can be applied.

[0159] Further details are now provided for two further embodiments of the coarse programming method 2205.

[0160] FIG. 26A illustrates a second embodiment of the coarse programming method 2205 (shown in FIG. 22A and FIG. 22B), which is an adaptive calibration method 2600. The method starts (step 2601). A selected cell is programmed with a default starting programming voltage value v0 (step 2602). Unlike the search and execute method 2300, here the programming voltage value v0 is not obtained from a lookup table or from a function, but is instead a relatively small initial value. The control gate voltage (Vcg) of the cell is measured at a first current value IR1 (e.g., 100 na) and a second current value IR2 (e.g., 10 na), and a slope is determined (e.g., 360 mV / decade of current) based on those measurements and stored (step 2603).

[0161] A new programming voltage v is determined. The first time this step is performed, i=1, and v is determined based on the stored slope value and a current target value, such as a coarse target current value ICT, and an offset value, using a subthreshold equation as follows: vi=vi-1+vincrement, The vincrement is proportional to the slope of Vcg relative to log[Ids / wa*Io]. Vcg=n*Vt*log[Ids / wa*Io] where Vcg is the control gate voltage, wa is the w of the memory cell, and Ids is the current target plus an offset value.

[0162] If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Thus, determining the slope information allows a current offset value to be selected that is customized for the particular cell in question. This ultimately makes the programming process shorter. As this step is repeated, i is incremented and vi=vi-1+vincrement. The cell is then programmed using vi. The vincrement can be determined from a lookup table that stores values ​​of vincrement versus a current target value such as a coarse target current value ICT.

[0163] A verify operation is then performed and a read operation is performed on the selected cell, and the current drawn through the selected cell (Icell) is compared (step 2605) to the coarse target current value ICT. If Icell is less than or equal to the coarse target current value ICT, and ICT is set to ID+ICTOFFSET, where ICTOFFSET is an offset value added to prevent program overshoot, then the adaptive calibration method 2600 is complete and the fine programming method 2206 may begin. If Icell is not less than or equal to ICT, steps 2604-2605 are repeated and i is incremented.

[0164] 26B illustrates a second embodiment of the coarse programming method 2205, which is an adaptive calibration method 2650. The method starts (step 2651). The cell is programmed with a default starting value v0 (step 2652). v0 is obtained from a lookup table created from silicon characterization, and the table value further provides an offset value ICTOFFSET so as not to overshoot the programmed target.

[0165] In step 2653, an IV slope parameter is created for use in determining the next programming voltage. A first control gate read voltage VCGR1 is applied to the selected cell and the resulting cell current IR1 is measured. Then, a second control gate read voltage VCGR2 is applied to the selected cell and the resulting cell current IR2 is measured. A slope is determined based on those measurements and stored, for example, according to the following equation in the sub-threshold region (cells operating at sub-threshold): Slope=(VCGR1-VCGR2) / (LOG(IR1)-LOG(IR2)) (Step 2653). Example values ​​for VCGR1 and VCGR2 are 1.5V and 1.3V, respectively.

[0166] Determining the tilt value allows a customized vincrement value to be selected for each selected cell, which makes the programming process shorter.

[0167] When step 2654 is executed, i is incremented and a new programming voltage vi is determined based on the stored slope value and the coarse target current value ICT and the offset value using the following equation: vi=vi-1+vincrement, where vincrement=alpha*slope*(LOG(IR1)-LOG(ICT)), where alpha is a predetermined constant, for example 0.9, less than 1 (the programming offset value) to prevent overshoot.

[0168] The cell is then programmed (step 2655) using a programming voltage v, where v can be applied to the source line terminal, control gate terminal, or erase gate terminal of the selected cell, depending on the programming scheme used.

[0169] A verify operation is then performed and a read operation is performed on the selected cell and the current drawn through the selected cell (Icell) is compared to the coarse target current value ICT (step 2656). If Icell is less than or equal to the coarse target current value ICT and the coarse target threshold ICT is set to ID+ICTOFFSET, where ICTOFFSET is an offset value added to prevent program overshoot, the process proceeds to step 2657. Otherwise, the process returns to step 2654 and i is incremented.

[0170] In step 2657, Icell is compared to a threshold value, ICT2, which is less than the coarse target current value ICT to determine if an overshoot has occurred. That is, steps 2654-2656 ensure that Icell is less than the coarse target current value ICT, but it is possible that Icell may be much less than the coarse target current value ICT, i.e., an overshoot has occurred and Icell may represent a stored value that corresponds to an erroneous value. If Icell is not less than or equal to ICT2, then an overshoot has not occurred and the adaptive calibration method 2650 is complete, at which point the process proceeds to the fine programming method 2206 with the starting value vi and the cell programmed to or near the coarse target threshold value ICT. If Icell is less than or equal to ICT2, then an overshoot has occurred and the selected cell is erased (step 2658) and the programming process is restarted at step 2652, this time with a smaller Vincrement to again avoid an overshoot. Optionally, if step 2658 is performed more than a predetermined number of times, the selected cell may be considered a bad cell that should not be used.

[0171] The precision program method 2206 consists of multiple verify and program cycles, where the program voltage is incremented by a constant fine voltage with a fixed pulse width, or the program voltage is fixed and the program pulse width varies or is constant for the next pulse, as described above in connection with Figures 24-25.

[0172] Optionally, the step of determining (2656) whether the current through the selected non-volatile memory cell during the read or verify operation is less than or equal to the coarse target current threshold value ICT may be performed by applying a fixed bias to the terminals of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate a digital output bit, and comparing the digital output bit to a digital bit representing the first threshold current value ICT.

[0173] Optionally, the step of determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the coarse target current value ICT may be performed by applying an input to a terminal of the non-volatile memory cell, modulating a current drawn by the non-volatile memory cell with the input pulse to generate a modulated output, digitizing the modulated output to generate a digital output bit, and comparing the digital output bit to a digital bit representative of the first threshold current ICT. 27 shows an exemplary circuit implementation for performing a portion of the adaptive calibration method 2600. During step 2603, a current source 2701 is used to apply exemplary current values ​​IR1 and IR2 to a selected cell (here memory cell 2702), and then the voltage at the control gate of memory cell 2702 (CGR1 for IR1 and CGR2 for IR2) is measured. As indicated above, the slope value is (VCGR1-VCGR2) / (LOG(IR1)-LOG(IR2)).

[0174] 28 illustrates another embodiment of the coarse programming method 2205, which is an absolute calibration method 2800. The method starts (step 2801). The cell is programmed with a default starting value v0 (step 2802). The cell's control gate voltage VCGRx is measured and stored at a current value Itarget (i.e., the final desired value of the cell current) (step 2803). A programming voltage v1 is determined based on the stored control gate voltage and the current value Itarget plus an offset value, Ioffset+Itarget (step 2804). For example, a new programming voltage v1 can be calculated as follows: v1=v0+(VCGBIAS-stored VCGR), where VCGBIAS is the default read control gate voltage at the maximum target current (which is about 1.5V in one embodiment) and stored VCGR is the measured read control gate voltage of step 2803.

[0175] The cell is then programmed using a programming voltage vi. When i=1, the voltage v1 from step 2804 is used. When i≧2, the voltage vi=vi−1+Vincrement is used. The v increment can be determined from a lookup table that stores values ​​of v increment corresponding to current values ​​I target . A verify operation is then performed, where a read operation is performed on the selected cell and the current drawn through the selected cell (I cell ) is compared to the coarse target current value ICT (step 2806). If I cell is less than or equal to the coarse target current value ICT , the absolute calibration method 2800 is complete and the fine programming method 2206 can be initiated. If I cell is not less than or equal to the coarse target current value ICT , steps 2805-2806 are repeated and i is incremented.

[0176] Figure 29 shows a circuit 2900 for implementing step 2803 of the absolute calibration method 2800. A voltage source (not shown) generates a VCGR, which starts at an initial voltage and rises. Here, n + 1 different current sources 2901 (2901-0, 2901-1, 2901-2,..., 2901-n) generate different currents IO0, IO1, IO2,... IOn with increasing magnitudes. Each current source 2901 is connected to a respective inverter 2902 (2902-0, 2902-1, 2902-2,..., 2902-n) and memory cell 2903 (2903-0, 2903-1, 2903-2,... 2903-n). As the VCGR rises, each memory cell 2903 draws an increasing amount of current, and the input voltage to each inverter 2902 decreases. Since IO0 < IO1 < IO2 <... < IOn, as the VCGR increases, first the output of inverter 2902-0 switches from low to high. Next, the output of inverter 2902-1 switches from low to high, then the output of inverter 2902-2 switches in the same way, and so on until the output of inverter 2902-n switches from low to high. Each inverter 2902 controls a respective switch 2904 (2904-0, 2904-1, 2904-2,.., 2904-n) such that the switch 2904 is closed when the output of the inverter 2902 is low and the switch 2904 is open when the output of the inverter 2902 is high. When the inverter 2902 switches from low to high, the VCGR sampled when the switch 2904 is low is held by a respective capacitor 2905 (2905-0, 2905-1, 2905-2,..., 2905-n). Thus, each of the switches 2904 and capacitors 2905 forms a sample-and-hold circuit. The values of IO0, IO1, IO2,..., IOn are used as possible values of Itarget, and each sampled voltage is used as the associated value VCGRx in the absolute calibration method 2800 of Figure 28. Graph 2906 shows the rising VCGR over time and the outputs of inverters 2902-0, 2902-1, and 2902-n that switch from low to high at various times.

[0177] FIG. 30 shows an exemplary progression 3000 for programming selected cells during the adaptive calibration method 2600 or the absolute calibration method 2800. In one embodiment, a voltage vcgp is applied to the control gates of memory cells of a selected row. The number of selected memory cells in the selected row is, for example, 32 cells. Thus, up to 32 memory cells in the selected row can be programmed in parallel. Each memory cell is enabled to couple to a programming current Iprog by a bit line enable signal. When the bit line enable signal is inactive (meaning a positive voltage is applied to the selected bit line), the memory cell is inhibited (not programmed). As shown in FIG. 30, the bit line enable signal En_blx (x varies from 1 to n, n being the number of bit lines) is enabled at different times (and thus for the selected memory of said bit line) with the vcgp voltage level desired for that bit line. In another embodiment, the voltage applied to the control gates of the selected cells can be controlled using an enable signal on the bit line. Each bit line enable signal applies a desired voltage (such as vi in ​​FIG. 28) corresponding to that bit line as vcgp. The bit line enable signal can also control the programming current flowing into the bit line. In this example, each subsequent control gate voltage vcgp is higher than its previous voltage. Alternatively, each subsequent control gate voltage may be lower or higher than its previous voltage. Each subsequent increment of vcgp may be either equal or unequal to its previous increment.

[0178] FIG. 31 illustrates an exemplary progression 3100 for programming a selected cell during adaptive calibration method 2600 or absolute calibration method 2800. In one embodiment, the bit line enable signals (e.g., EN_bln, EN_bl1, EN_bl5) enable the selected bit line (i.e., the bit line coupled to the selected memory cell) to be programmed at the corresponding Vcgp voltage level. In another embodiment, the voltage applied to the incrementally increasing control gate of the selected cell can be controlled using the bit line enable signals. Each bit line enable signal applies a desired voltage (such as vi in ​​FIG. 28) corresponding to that bit line to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

[0179] FIG. 32 shows a system for implementing an input and output method for reading or verifying in a VMM array. An input function circuit 3201 receives digital bit values ​​and converts them to analog signals that are then used to apply voltages to the control gates of selected cells in the array 3204 selected by a control gate decoder 3202, a word line decoder 3203, and bit lines (not shown). In the embodiment described below, an input is applied to a selected memory cell, which generates an output current representing a multiplication operation of the received input and a weight W stored in the selected cell. An output neuron circuit block 3205 performs the output function of each column of cells (neurons) in the VMM array 3204. The output circuit block 3205 can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation (SAR) ADC, or a sigma-delta ADC.

[0180] In one embodiment, the digital value provided to the input function circuit 3201 includes 4 bits (DIN3, DIN2, DIN1, and DIN0), meaning that the input can be one of 16 different values. Each of the 16 different combinations of bit values ​​corresponds to a different number of input pulses applied to the control gate of a selected cell, which generates an output current representing the multiplication of the input value with the weight W stored in the cell. The higher the number of pulses, the higher the output value (current) of the cell. Examples of input bit values ​​DIN[3:0] and the corresponding number of pulses applied to the control gate are shown in Table 11. Table 11: Digital bit input and number of generated pulses [Table 11]

[0181] In the above example, there are up to 16 pulses for a 4-bit digital value to read the cell value. Each pulse is equal to one unit of cell value (current). For example, if Icell unit = 1nA, then for DIN[3~0]=0001, Icell = 1*1nA = 1nA, and for DIN[3~0]=1111, Icell = 15*1nA = 15nA.

[0182] In another embodiment, the digital bit input uses digital bit position summation to read the cell value, as shown in Table 12. Here, only four pulses are needed to evaluate a four-bit digital value. For example, the first pulse is used to evaluate DIN0, the second pulse is used to evaluate DIN1, the third pulse is used to evaluate DIN2, and the fourth pulse is used to evaluate DIN3. The results from the four pulses are then summed according to the bit position. The digital bit summation formula realized is: Output = 2^0*DIN0 + 2^1*DIN1 + 2^2*DIN2 + 2^3*DIN3) * Icell units.

[0183] For example, if Icell unit = 1nA, then for DIN[3~0] = 0001, Icell total = 0 + 0 + 0 + 1 * 1nA = 1nA, and for DIN[3~0] = 1111, Icell total = 8 * 1nA + 4 * 1nA + 2 * 1nA + 1 * 1nA = 15nA. Table 12: Total Digital Bits Input [Table 12]

[0184] FIG. 33 shows an example of a charge summer 3300 that can be used to sum the outputs of the VMM during a verify or read operation to obtain a single analog value representing the output, which can be optionally converted to a digital bit value. The charge summer 3300 includes a current source 3301 and an array of sample-and-hold circuits including switches 3302 and sample-and-hold (S / H) capacitors 3303. As shown in the example of a 4-bit digital value, there are four S / H circuits to hold values ​​from the four evaluation pulses, which are summed at the end of the process. The S / H capacitors 3303 are selected with a ratio associated with the 2^n*DINn bit position of that S / H capacitor, e.g., C_DIN3=x8 Cu DIN3 (where Cu is the unity capacitor), C_DIN2=x4 Cu for bit DIN2, C_DIN1=x2 Cu for bit DIN1, and DIN0=x1 Cu for bit DIN9. Current source 3301 is also scaled accordingly.

[0185] FIG. 34 shows a current summer 3400 that can be used to sum the output of a VMM during a verify or read operation. The current summer 3400 includes a current source 3401 (which is the output of the VMM array, Icell), a transistor 3402, a switch 3403, a node 3404, and a transistor 3405. In this example, the current summer 3400 serially outputs four digital values ​​DIN0, DIN1, DIN2, and DIN3 to node 3404. Four evaluation pulses are input to the VMM array in sequence. During the first pulse, during the period t_DIN0, the switch 3403 corresponding to DIN0 is closed and the other switches 3403 are opened. During the second pulse, during the period t_DIN1, the switch 3404 corresponding to DIN1 is closed and the other switches are opened. During the third pulse, the switch 3404 corresponding to DIN2 is closed during the period t_DIN2 and the other switches are opened. During the fourth pulse, the switch 3404 corresponding to DIN3 is closed for a period t_DIN3, while the other switches are open. At the end of the process, the values ​​are summed to generate a digital output, and a weighting process is applied to the DIN values ​​based on the relative bit positions of DIN. For example, DOUT can be equal to 8*I_DIN3+4*I_DIN2,+2*I_DIN1+1*I_DIN0.

[0186] Figure 39 shows an output block 3900 (which is an embodiment of output block 3205 of Figure 32). Output block 3900 receives an output current from a VMM array (such as array 3204 of Figure 32), here shown as ICELL 3901. Output block 3900 includes a D / A converter 3902, a shifter 3903, an adder 3904, and an output register 3905.

[0187] Here, the input to an input block of the VMM (such as input block 3201 in FIG. 32) is assumed to be DIN[n:0], where n is the input bit binary index number, and there are a total of i bits, where i can range from 1 to n+1. For example, if i=4, then the input would be four input bits: DIN3, DIN2, DIN1, and DIN0. Each input bit DINx is applied to input block 3201 of the VMM 3204 at a time.

[0188] Input block 3201 converts DINx (using one of the embodiments described herein or other known techniques) into an input signal that is applied to a terminal of a selected cell in array 3204, where the selected cell is selected by word line decoder 3203 and a selected bit line (not shown). In one embodiment, the input signal is a single pulse of variable duration for an exemplary 4-bit input as shown in Table 13. The pulse TPULSE input signal (row input to the VMM array) has a width proportional to the decimal value (0-15) of datain DIN[3:0]. Table 13. Example table of 4-bit inputs and pulses [Table 13]

[0189] In another embodiment, the input signal is an analog bias voltage for an exemplary 4-bit input as shown in Table 14A. The input signal may have, for example, 16 voltage levels that are linearly spaced for a cell operating in the linear region. Alternatively, the input signal may be logarithmically spaced (meaning that the voltage value is proportional to the logarithm of the cell current) for a cell operating in the sub-threshold region, for example, VCGINk=VCGIN(k-1)-(1 / n*Vt)*LN2 for a binary current value, where VCGIN is the voltage of the corresponding CG terminal. Table 14A: Example table of 4-bit inputs and analog bias levels [Table 14A]

[0190] A 4-bit input DIN[3:0] for a particular row allows one analog level out of 16 levels (e.g., VCGIN0, ..., or VCGIN15) to be selected and applied to the row of the VMM array. In one embodiment, this operates on all four input data bits simultaneously, meaning that the four input data bits are converted to one of 16 possible voltage levels and applied to the row. An alternative embodiment is that the data input bits are applied sequentially, one at a time (input bit-wise operation), and the results for each data input are then added (summed) together in the analog domain (FIGS. 33, 34) or digital domain (FIGS. 35, 39). Optionally, each data input bit may be weighted based on its bit position. For example, by using output block 3900 of FIG. 39, a "1" in the least significant bit position may cause voltage VCGIN1 to be applied as an input to the row of the VMM array, and a "1" in the most significant bit position may cause voltage VCGIN8 to be applied as an input to the row of the VMM array.

[0191] In another embodiment, the input signal to the input block of the array is the exemplary 4-bit input shown in Table 14B for an input bit-by-input operation (e.g., the operation is performed on DIN0, then DIN1, then DIN2, then DIN3 inputs) with a constant analog bias voltage for cells operating in linear or subthreshold or any region. Table 14B: Example table of single analog bias levels with 4-bit input and input bit-wise operations [Table 14B]

[0192] The binary weighted results for each input bit DIN are summed together in the analog domain, such as by using a current summer such as that shown in Figure 34, or in the digital domain, such as by using the embodiments of Figures 35 or 44. Figure 44 shows a digital summer 4400 that is the same as digital summer 3500 of Figure 35, except that a particular weight is assigned to each generated output stream in response to the input bits.

[0193] In another embodiment, the input signal to the input block of the array is an exemplary 4-bit input as shown in Table 14C for an input multi-bit per operation (e.g., DIN3 and DIN2 together and DIN1 and DIN0 together) with four analog bias level examples. In one embodiment, the four analog levels are linearly spaced for cells operating in the linear region, e.g., 0V, 0.25V, 0.5V, 1.0V, to ensure linear equal scaling for the output cell current. In another embodiment, the levels are logarithmically spaced for cells operating in the subthreshold region to ensure linear scaling of the output cell current, which means, for example, that the voltage value is proportional to the logarithm of the current for cells operating in the subthreshold region, e.g., VCGINk=VCGIN(k-1)-(1 / n*Vt)*LN2 for binary current values. Table 14C: Example table of analog bias levels with 4-bit input and input multi-bit operations [Table 14C]

[0194] The multi-bitwise binary weighted results DIN[1:0] and DIN[3:2] are summed in the analog domain (such as the current summer in FIG. 34) or in the digital domain (FIGS. 35, 39).

[0195] In another embodiment, the input signal is a hybrid signal that includes an analog bias voltage component with a pulse component (analog bias supply modulated pulse) added, as shown in Table 15 for an exemplary 4-bit input with analog bias supply and pulses. The pulses can be modulated by length (TPULSE) or by the number of pulses in a given period (PULSES). Table 15: Example table for 4-bit input and hybrid input of analog bias levels and pulses [Table 15] In the above table, a value of "4.5X" means a pulse having a width equal to 4.5 times the width of a 1X pulse, or four 1X pulses plus a pulse having half the width of a 1X pulse.

[0196] The input data is divided into a number of input data insets, and each data inset is assigned to a specific voltage bias level. For example, for an 8-bit input DIN[7:0], a first row power supply VCGIN1 is applied to the input bits in the set DIN[3:0], and a second row power supply VCGIN2, different from VCGIN1, is applied to the input bits in the set DIN[7:4]. In this exemplary embodiment of two binary input set division, the analog bias power supply VCGIN2 (for the second data inset DIN[7:4]) generates a cell current that is twice the cell current generated by the analog bias power supply VCGIN1 (for the first data inset DIN[3:0]). For example, the ratio of VCGIN2 / VCGIN1 may be twice for a cell operating in a linear region. Because a different VCGIN voltage is applied to each data inset, the same number of pulses with the same period can be applied to members of data inset DIN[7:4] and members of data inset DIN[3:0] because the difference in VCGIN distinguishes the two members.

[0197] In a variation of this embodiment, two divisions can be used for each input data in set, with each division corresponding to a different analog bias voltage, meaning that four different voltages VCGIN1, VCGIN2, VCGIN3, and VCGIN4 are used. This can further reduce the number / duration of pulses required. That is, four different data in values ​​can use the same number / duration of pulses, since the difference in VCGIN distinguishes between the four different members.

[0198] 39, output block 3900 receives an output current ICELL from the VMM in response to an input DINx. A D / A converter 3902 converts ICELL to a digital form DOUT[m:0] that represents the digital value of the output generated in response to DINn, where each DOUT_n is a set of one or more output bits.

[0199] The shifter 3903, adder 3904, and register 3905 operate to apply a different weight to each generated output DOUT[m:0]_n in response to each input bit DINn. In a simple example where n=4, the shifter 3902, adder 3904, and register 3905 perform the following functions: (1) In response to DIN0, shifter 3903 receives DOUT_0[m:0]0 and does not shift it, producing the result of (1). (2) In response to DIN1, shifter 3903 receives DOUT_1[m:0] and shifts it left one bit, and adder 3904 adds the shifted result to the result of (1) to generate the result of (2). (3) In response to DIN2, shifter 3903 receives DOUT_2[m:0] and shifts it left by 2 bits, and adder 3904 adds the shifted result to the result of (2) to generate the result of (3). (4) In response to DIN3, shifter 3903 receives DOUT_3[m:0] and shifts it to the left by 3 bits, and adder 3904 adds the shifted result to the result of (3) to generate the result of (4), i.e., the final result DOUT[m:0].

[0200] When the DIN[n:0] inputs are combined with analog voltage levels representing the binary weight of each data input, only addition is required, no shifting for such a hybrid input bit-wise operation. The output register 3905 stores and outputs the result of (4) as DOUT. Additional Input and Output Circuits

[0201] FIG. 35 shows a digital summer 3500 that receives multiple digital values ​​and sums them together to generate an output DOUT that represents the sum of the inputs. The digital summer 3500 can be used during a verify or read operation. FIG. 35 shows an example of a 4-bit digital value that includes bits DOUT0, DOUT1, DOUT2, and DOUT3. Each bit is generated from an evaluation input pulse. Each bit can be weighted based on its bit position, with a weight t_DINn of 2^n being applied to bit DINn. For example, DOUT3 can be multiplied by 2^3 (=8), DOUT2 can be multiplied by 2^2 (=4), DOUT1 can be multiplied by 2^1 (=2), and DOUT0 can be multiplied by 2^0 (=1).

[0202] FIG. 36A shows a dual slope integrating ADC 3600 applied to an output neuron to convert the array cell current to a digital output bit DOUTx. An integrator consisting of an integrating op-amp 3601 and an integrating capacitor 3602 integrates the cell current ICELL against a reference current IREF. As shown in FIG. 36B, for a fixed time t1 (integration time), the cell current is integrated upwards (VOUT rises), and then a reference current is applied such that it is integrated downwards (VOUT falls, non-integration time) for a time t2. The current Icell is =t2 / t1*IREF. For example, for t1, with a digital bit resolution of 10 bits, 1024 cycles are used, and for t2, the number of cycles varies from 0 to 1024 cycles depending on the Icell value. A digital counter 3630 enabled by a signal EC is used to generate the digital output bit DOUTx during the t2 period.

[0203] 36C shows a single slope integrating ADC 3660 applied to the output neuron to convert the array cell current into a digital output bit. An integrator consisting of an integrating opamp 3661, an integrating capacitor 3662, a switch S3, and a comparator 3664 integrates the array cell current ICELL 3666 and generates an output signal EC.

[0204] As shown in Figure 36D, graph 3670 shows that during time t1, cell current ICELL1 is integrated up (VOUT rises until it reaches VREF2, which corresponds to the change in value of EC in Figure 36C), and during time t2, another cell current ICELL2 is integrated up. Cell current ICELL = Cint * VREF2 / t, where t is the time that elapses before EC changes value. A pulse counter 3668 enabled by signal EC is used to count the number of pulses during the integration time t, which represents the digital output value DOUTx.

[0205] In the example shown, the digital output at t1 is less than the digital output at t2 because the count at t1 is less than the count at t2, which also means that the cell current ICELL1 during period t1 was greater than the cell current ICELL2 during period t2. An initial calibration is performed to calibrate the integrating capacitor 3662 value with a reference current Iref and a fixed time Tref, where Cint=Tref*Iref / VREF2.

[0206] FIG. 36E shows a dual slope integrating ADC 3680 comprising ICELL 3684, comparator 3681, switch S1, switch S2, switch S3, capacitor 3682, and reference current source 3683. Dual slope integrating ADC 3680 receives the output neuron current (ICELL 3684) and generates an output EC. Dual slope integrating ADC 3680 does not utilize an integrating opamp. The cell current or the reference current is directly integrated on capacitor 3682. A pulse counter 3687 enabled by signal EC is used to count pulses during the integration time, which ends when EC changes value. The output of the pulse counter is a digital output DOUTx, which represents ICELL. The current ICELL is =t2 / t1*IREF.

[0207] FIG. 36F shows a single-slope integrating ADC 3690 comprising ICELL 3694, comparator 3691, switch S2, switch S3, and capacitor 3692. The single-slope integrating ADC 3690 receives the output neuron current (ICELL 3694) and generates an output EC. The single-slope integrating ADC 3690 does not utilize an integrating op-amp. The cell current is directly integrated on capacitor 3692. A pulse counter 3697 enabled by signal EC is used to count digital output pulses during the integration time, which ends when EC changes value. The output of the pulse counter is a digital output DOUTx, which represents ICELL. The cell current ICELL=Cint*VREF2 / t.

[0208] FIG. 37A shows a SAR (Successive Approximation Register) ADC 3700 applied to the output neuron to convert the cell (array) current to a digital output bit. The cell current can be dropped through a resistor and converted to a VCELL. Alternatively, the cell current can be converted to a VCELL by charging up a S / H capacitor. A binary search is used to calculate the bits starting from the MSB bit (most significant bit). A DAC 3702 is used to set the appropriate analog reference voltage to the comparator 3703 based on the digital bit from the SAR 3701. The output of the comparator 3703 is fed back to the SAR 3701 to select the next analog level. As shown in FIG. 37B, for an example of a 4-bit digital output bit, there are four evaluation periods, a first pulse to evaluate DOUT3 by setting the analog level to the middle, then a second pulse to evaluate DOUT2 by setting the analog level to the middle of the upper half or the middle of the lower half, etc. DOUT3 and DOUT4 also split the range in half in a similar manner. Another embodiment can use a SAR CDAC (charge redistribution CDAC) to convert neuronal currents into digital output bits.

[0209] FIG. 38 shows a sigma-delta ADC 3800 applied to an output neuron to convert the cell current into a digital output bit. An integrator consisting of an opamp 3801 and a capacitor 3805 integrates the sum of the current from the selected cell current and a reference current provided by a 1-bit current DAC 3804. A comparator 3802 compares the integrated output voltage against a reference voltage. A clocked DFF 3803 provides a digital output stream according to the output of the comparator 3802. The digital output stream typically goes to a digital filter before being output into a digital output bit.

[0210] FIG. 45 shows an output block 4500. The output block 4500 comprises a current-to-voltage converter 4501 and an analog-to-digital converter 4502. The output block 4500 receives an output current from the VMM array, here shown as Ineu, where the output current represents an output value from the VMM array for a read or verify operation being performed. The current-to-voltage converter 4501 converts the output current Ineu to a voltage signal, here shown as VOUT, such that the voltage VOUT represents the output current Ineu from the VMM. The A / D converter 4502 converts the voltage VOUT to digital form and outputs a digital output, here shown as DOUT.

[0211] In one implementation of output block 4500, current-to-voltage converter 4501 receives a series of currents from one or more selected non-volatile memory cells in the array in response to a series of inputs and converts the series of currents to a series of voltages. An A / D converter then converts the series of voltages received from current-to-voltage converter 4501 into a plurality of output bits, which are generated based on a weighted sum of the series of voltages.

[0212] Figure 46 shows a lossless (no I*Rmux drop) current-to-voltage converter 4600, which is one embodiment of the current-to-voltage converter 4501 of Figure 45. The current-to-voltage converter 4600 comprises an operational amplifier 4601, resistors 4602, 4603, 4604, and 4605, and switches 4606, 4607, 4608, 4609, 4610, 4611, 4612, and 4613. The lossless rheostat unit consists of a resistor and two switches (mux), e.g. resistor 4602 and switches 4610 and 4606, one switch carries current (switch 4610) and one switch does not carry current (switch 4606), and the output is taken from the switch that does not carry current.

[0213] The current-to-voltage converter 4600 receives the current Ineu and outputs a voltage VOUT. In particular, VOUT can be measured without incurring a voltage drop due to multiplication (I*R drop of the switches) in the output voltage VOUT, which means that the output voltage is sampled outside the feedback loop or current loop. For example, when switches 4613 and 4609 are closed (on) and the other switches are open (off), VOUT is equal to VREF+(R4602+R4603+R4604+R4605)*(Ineu). As another example, when switches 4610 and 4606 are closed (on) and the other switches are open (off), VOUT is VREF+(R4602*Ineu). After the current Ineu is converted to the voltage VOUT, the voltage VOUT can be sampled and held by opening all the switches. In this case, the voltage VOUT is referenced to a reference level VREF.

[0214] FIG. 47 shows a current-to-voltage converter 4700, which is one embodiment of the current-to-voltage converter 4501 of FIG. 45. The current-to-voltage converter 4700 includes a comparator 4701, switches 4702, 4705, 4706, and 4707, a S / H (sample and hold) capacitor 4703, and a variable resistor 4704. The current-to-voltage converter 4700 receives a current Ineu and outputs a S / H voltage VOUT. The lossless variable resistor 4704 is similar to the resistor 4650 of FIG. During current to voltage conversion, current Ineu flows through resistor 4704 to generate an output voltage=R4704*Ineu, S1 (4702), S2 (4705) and S3 (4707) are closed (on), S4 (4706) is open (off) and S3 carries no current, so the output VOUT is=R4704*Ineu. During a hold period, S4 is closed (on), S1, S2 and S3 are open (off) and VOUT is held on capacitor 4703. In particular, VOUT is measured (enabled) external to the current carrying switches so that VOUT can be measured without experiencing a voltage drop.

[0215] FIG. 48 shows a current-to-voltage converter 4800, which is an embodiment of the current-to-voltage converter 4501 of FIG. 45. The current-to-voltage converter 4800 includes an operational amplifier 4801, switches 4802 and 4805, an S / H capacitor 4803, and a variable resistor 4804. The current-to-voltage converter 4800 receives a current Ineu and outputs a voltage VOUT. Notably, VOUT can be measured without a voltage drop due to VOUT being measured (enabled) outside the switch (mux) carrying the current. During the current-to-voltage conversion, the current Ineu flows through the resistor 4804 to generate an output voltage=R4804*Ineu, and since S1 (4802) and S2 (4805) are closed (on) and S2 does not carry current, the output VOUT is=R4804*Ineu. During a hold period, S1 and S2 are open (off) and VOUT is held in the capacitor 4803. In this case, the S / H voltage VOUT is referenced to the ground level.

[0216] Alternatively, the current-to-voltage converter 4700 and 4800 does not include a variable resistor 4704 or 4804, in which case Ineu charges the S / H capacitor 4703 or 4803 by a variable signal pulse enable switch 4702 or 4802 controlled by a predetermined adjustable timing pulse value, where the timing pulse value is selected based on the Ineu dynamic current range. In this case, the S / H capacitor can be a variable capacitor with an adjustable capacitance value.

[0217] FIG. 49A shows a current-to-voltage converter 4900, which is one embodiment of the current-to-voltage converter 4501 of FIG. 45. The current-to-voltage converter 4900 includes switches 4901 and 4902, a variable resistor 4903, and a capacitor 4904. The current-to-voltage converter 4800 receives a current Ineu and outputs a voltage VOUT. During the current-to-voltage conversion, the current Ineu flows through the variable resistor 4903 to generate an output voltage=R4804*Ineu, S1 (4901) is closed (on), and the output VOUT=R4903*Ineu. During the hold period, S1 is opened (off), VOUT is held in the capacitor 4904, and the switches (mux) inside the variable resistor 4903 (e.g., S1a / S2a / S3a / S4a in the variable resistor 4950 of FIG. 49B) are also opened (off). Notably, VOUT can be measured without incurring the voltage drop that results from VOUT being measured (enabled) outside the current carrying switch (mux).

[0218] 49B shows a variable resistor 4950 such as that used in 4903. Variable resistor 4950 includes switches S1a, S2a, S3a, S4a, S1b, S2b, S3b, and S4b.

[0219] FIG. 50 shows a current-to-voltage converter 5000, which is an embodiment of the current-to-voltage converter 4501 of FIG. 45. The current-to-voltage converter 5000 comprises an operational amplifier (op amp) 5001, a level shifter 5002 (gate of transistor 5004=drain of transistor 5004-Voffset), an NMOS transistor 5003, PMOS transistors 5004 and 5005, switches 5006 and 5007, a variable resistor 5008 (which can be implemented as described above in connection with FIG. 49B), a capacitor 5009, and a voltage source VH. The current-to-voltage converter 5000 receives a current Ineu and outputs a voltage VOUT. In particular, VOUT can be measured in the same way (as in FIG. 49) without incurring a voltage drop. The S / H voltage VOUT in this case is referenced to ground. The op amp 5001 and the transistor 5003 apply a fixed bias voltage VREF 5010 to the bit lines of the array during a read operation. PMOS transistors 5004 and 5005 act as a variable ratio current mirror to mirror the array output current (Ineu) to a variable resistor 5008 and an S / H capacitor 5009. Alternatively, the current-to-voltage converter 5000 does not include a variable resistor 5008, in which case the mirrored Ineu charges the S / H capacitor 5009 by a variable signal pulse enable switch 5006 controlled by a predetermined adjustable timing pulse value, where the timing pulse value is selected based on the Ineu dynamic current range. In this case, the S / H capacitor can be a variable capacitor with an adjustable capacitance value.

[0220] FIG. 51 shows a current-to-voltage converter 5100, which is one embodiment of the current-to-voltage converter 4501 of FIG. 45. The current-to-voltage converter 5100 comprises an operational amplifier 5101, an NMOS transistor 5102, a variable resistor 5103 (which may be implemented as described above in connection with FIG. 49B), switches 5104 and 5105, a capacitor 5106, and a voltage source VH. The current-to-voltage converter 5100 receives a current Ineu and outputs a voltage VOUT. In particular, VOUT can be measured without incurring a voltage drop as in FIG. 50. The S / H voltage VOUT in this case is referenced to a high power supply VH. The operational amplifier 5101 and the transistor 5102 serve to apply a fixed bias VREF 5110 to the bit line during a read operation. Alternatively, the current-to-voltage converter 5100 does not include a variable resistor 5103, in which case Ineu discharges the S / H capacitor 5106 through a variable signal pulse enable switch 5106 controlled by a predetermined adjustable pulse timing value, where the timing value is selected based on the Ineu dynamic current range. In this case, the S / H capacitor may be a variable capacitor with an adjustable capacitance value.

[0221] FIG. 52A shows a hybrid serial analog-to-digital converter 5200 utilizing the lossless current-to-voltage converter 4800 described above in connection with FIG. 48. It consists of a current-to-voltage converter 5220, a comparator 5209, current sources 5206 and 5207, and switches S1 and S2. The current-to-voltage converter 5220 may alternatively be implemented using any of the current-to-voltage converters described above in FIG. 46, FIG. 47, FIG. 49, FIG. 50, and FIG. 51. The current-to-voltage converter 5220 comprises an operational amplifier 5201, a switch 5205, a variable resistor 5204, and a sample-and-hold capacitor 5203.

[0222] FIG. 52B shows a timing diagram 5250 of the operation of the hybrid serial ADC converter 5200, during a period t1, the current ICELL 5206 is converted to a voltage VOUT by closing switch 5202 (S2) while keeping switch 5208 (S1) open, and then held by the capacitor 5203 by opening switch 5202 (S2). During a period t2, IREF 5207 is enabled by closing switch 5208 (S1) to begin a non-integration period, i.e., a counting period, during which, for a time shown as t2, clock pulses (not shown) are counted by the pulse counter 5210 as long as EC is high, which is converted to a digital bit DOUT, i.e., a count number. Not shown is the digital counter and clock and control logic for converting the comparator output EC to a digital bit.

[0223] FIG. 52C shows another timing diagram 5250 of the operation of the hybrid serial ADC converter 5200, where the t1 period is the same as that of FIG. 52B. During the period t2, the voltage VOUT is converted to a digital bit DOUT by raising the reference voltage VREF2 from a reference level, such as VREF1, to its maximum level. During the period t2, a digital counter (not shown) counts pulses, and the output of the digital counter is the output DOUT. The period t2 ends when VREF2 exceeds VOUT, resulting in a change in the value of EC in FIG. 52A.

[0224] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed between them) and "indirectly" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above the substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. an output block for generating an output from an array of non-volatile memory cells, a current-to-voltage converter for receiving a series of currents from one or more selected non-volatile memory cells in the array generated in response to a series of inputs to the array, and for generating a voltage or series of voltages in response to the series of currents; an analog-to-digital converter for converting the voltage or series of voltages into a plurality of output bits, the plurality of output bits reflecting a weighting function performed on one or more of the series of currents or the voltage or series of voltages.

2. 2. The output block of claim 1, wherein each input in the series of inputs comprises a pulse, the width of the pulse being proportional to a data value of the input.

3. 2. The output block of claim 1, wherein each input in the series of inputs comprises a pulse that is added to an analog bias voltage, the width of the pulse being proportional to a data value of the input.

4. 2. The output block of claim 1, wherein each input in the series of inputs comprises a series of one or more pulses, the number of pulses in the series of one or more pulses being proportional to a data value of the input.

5. 2. The output block of claim 1, wherein each input in the series of inputs comprises a series of one or more pulses that are added to an analog bias voltage, the number of pulses in the series of one or more pulses being proportional to a data value of the input.

6. 2. The output block of claim 1, wherein each input in the series of inputs comprises a pulse that is added to an analog bias voltage, the width of the pulse being proportional to a data value of the input.

7. 2. The output block of claim 1, wherein each input in the series of inputs includes an analog bias voltage, the magnitude of the analog bias voltage being proportional to a data value of the input.

8. 2. The output block of claim 1, wherein each input in the series of inputs comprises an analog bias voltage, the magnitude of the analog bias voltage being proportional to a data value of a plurality of digital bits represented by the input.

9. 2. The output block of claim 1, wherein each input in the series of inputs includes an analog bias voltage, the magnitude of the analog bias voltage varying depending on the bit position of a digital bit represented by the input.

10. The output block of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.

11. The output block of claim 1 , wherein the non-volatile memory cells are stacked gate flash memory cells.

12. The output block of claim 1 , wherein the current-to-voltage converter is lossless.

13. 2. The output block of claim 1, wherein the current-to-voltage converter comprises a sample-and-hold circuit that outputs the voltage or the series of voltages.

14. The output block of claim 1 , wherein the current-to-voltage converter comprises an operational amplifier that outputs the voltage or the series of voltages.

15. 2. The output block of claim 1, wherein the current-to-voltage converter comprises a lossless variable resistor unit that outputs the voltage or the series of voltages.

16. The output block of claim 1 , wherein the array is a vector matrix multiplier array.

17. 17. The output block of claim 16, wherein the non-volatile memory cells are split-gate flash memory cells.

18. 17. The output block of claim 16, wherein the non-volatile memory cells are stacked gate flash memory cells.

19. an output block for generating an output from an array of non-volatile memory cells, an output block comprising a current-to-voltage converter for receiving a current from one or more selected non-volatile memory cells in the array in response to an input applied to the array and converting the current to a voltage, the current-to-voltage converter comprising a sample and hold circuit for holding the voltage.

20. 20. The output block of claim 19, further comprising an analog-to-digital converter for converting the voltage to a plurality of output bits.

21. 20. The output block of claim 19, wherein the current-to-voltage converter comprises a lossless variable resistance unit that provides the voltage.

22. 21. The output block of claim 20, wherein the analog-to-digital converter is a hybrid serial analog-to-digital converter.

23. 21. The output block of claim 20, wherein the analog-to-digital converter performs counting to convert the voltage to digital bits.

24. 24. The output block of claim 23, wherein the period of the count is determined by a reference current that discharges a holding capacitor.

25. 24. The output block of claim 23, wherein the period of the count is determined by a reference voltage rising until it crosses a threshold voltage.

26. 20. The output block of claim 19, wherein the non-volatile memory cells are split-gate flash memory cells.

27. 20. The output block of claim 19, wherein the non-volatile memory cells are stacked gate flash memory cells.

28. 20. The output block of claim 19, wherein the current-to-voltage converter converts the series of currents into a series of voltages without a voltage drop from the output currents of the output block.

29. 20. The output block of claim 19, wherein the current-to-voltage converter comprises an operational amplifier that provides the voltage.

30. 30. The output block of claim 29, wherein the array is a vector matrix multiplier array.

31. 20. The output block of claim 19, wherein the current-to-voltage converter comprises a capacitor that is charged by the current from one or more selected non-volatile memory cells via a controlled switch.

32. 32. The output block of claim 31, wherein the capacitor is a variable capacitor.

33. 33. The output block of claim 32, wherein the variable capacitor is adjustable.

34. 32. The output block of claim 31, wherein the capacitor is charged for a first period of time that ends when the voltage exceeds a reference voltage.

35. 35. The output block of claim 34, wherein the current-to-voltage converter comprises an operational amplifier for comparing the voltage to the reference voltage.

36. 35. The output block of claim 34, wherein the capacitor is discharged during a second period that ends when the voltage provided by the current-to-voltage converter reaches ground.

37. 37. The output block of claim 36, wherein a counter counts clock pulses during the second period and outputs a count, the count being a digital version of the voltage.

38. an output block for generating an output from a series of currents received from an array of non-volatile memory cells in response to a series of inputs received by said array of non-volatile memory cells, An output block comprising an analog-to-digital converter for receiving the series of currents and converting the series of currents into an output comprising a plurality of output bits.

39. 39. The output block of claim 38, wherein each input in the series of inputs comprises a pulse, the width of the pulse being proportional to a data value of the input.

40. 40. The output block of claim 38, wherein each input in the series of inputs comprises a pulse that is added to an analog bias voltage, the width of the pulse being proportional to a data value of the input.

41. 39. The output block of claim 38, wherein each input in the series of inputs comprises a series of one or more pulses, the number of pulses in the series of one or more pulses being proportional to a data value of the input.

42. 40. The output block of claim 38, wherein each input in the series of inputs comprises a series of one or more pulses that are added to an analog bias voltage, the number of pulses in the series of one or more pulses being proportional to a data value of the input.

43. 40. The output block of claim 38, wherein each input in the series of inputs comprises a pulse that is added to an analog bias voltage, the width of the pulse being proportional to a data value of the input.

44. 40. The output block of claim 38, wherein each input in the series of inputs includes an analog bias voltage, the magnitude of the analog bias voltage being proportional to a data value of the input.

45. 40. The output block of claim 38, wherein each input in the series of inputs comprises an analog bias voltage, the magnitude of the analog bias voltage being proportional to a data value of a plurality of digital bits represented by the input.

46. 39. The output block of claim 38, wherein each input in the series of inputs comprises an analog bias voltage, the magnitude of the analog bias voltage varying depending on the bit position of a digital bit represented by the input.

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