Time-digital conversion device, distance measuring device, and movable body

Abstract

To provide a technique advantageous for reducing the power consumption of a latch circuit in a time-digital conversion device.SOLUTION: A time-digital conversion circuit comprises: a pulse signal generator that generates a pulse signal in response to the activation of a transition detection signal; and a latch circuit that latches a multi-phase clock signal in response to a trailing edge of the pulse signal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a time-to-digital conversion device, a distance measuring device, and a moving object. [Background technology]

[0002] In recent years, time-to-digital converters (TDCs) that convert time into digital signals have been used in various fields. The time-to-digital converter described in Patent Document 1 is applied to a sensor capable of capturing a three-dimensional (3D) distance image, and measures the time-of-flight of photons detected by a SPAD (Single Photon Avalanche Diode) pixel. The time-to-digital converter in Patent Document 1 also includes a coarse TDC and a fine TDC. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2013 / 034770 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, the TDC may start time measurement and then end the time measurement in response to a trigger signal such as a stop signal. The time measurement may be performed by latching the multi-phase clock signal by a latch circuit in response to the activation of the trigger signal. The latch circuit may be configured, for example, as a D latch. During the period when the trigger signal is in an active state (the period when the latch circuit is in a transparent state), the multi-phase clock signal, which toggles at high speed, toggles a group of logic gates that constitute the latch circuit. When the trigger signal is inactivated, the input stage (e.g., a transfer gate) of the latch circuit cuts off signal transmission to the subsequent holding circuit (e.g., an SR latch), and the state of the holding circuit is fixed. Therefore, during the period when the trigger signal is in an inactive state, the power consumption of the latch circuit is small, but during the period when the trigger signal is waiting for the transition of the trigger signal from an active state to an inactive state, the power consumption of the latch circuit may be significant. In addition, a drop in the power supply voltage caused by the power consumption may reduce the accuracy of the time measurement.

[0005] The present invention provides an advantageous technique for reducing the power consumption of a latch circuit in a time-to-digital conversion device. [Means for solving the problem]

[0006] One aspect of the present invention relates to a time-to-digital conversion circuit, the time-to-digital conversion circuit comprising: a pulse signal generator that generates a pulse signal in response to activation of a transition detection signal; and a latch circuit that latches a multi-phase clock signal in response to a trailing edge of the pulse signal. Effect of the Invention

[0007] SUMMARY OF THE PRESENTLY PREFERRED EMBODIMENTS According to the present invention, an advantageous technique is provided for reducing the power consumption of a latch circuit in a time-to-digital conversion device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a distance measuring device according to an embodiment. [Diagram 2] FIG. 1 is a diagram showing the configuration of a range image sensor according to an embodiment. [Diagram 3] FIG. 2 is a diagram showing an example of the configuration of a measurement block according to an embodiment that can be used as a first measurement block and a second measurement block. [Figure 4] FIG. 4 is a circuit diagram showing a more specific example of the configuration of the measurement block according to the embodiment. [Diagram 5] 4 is a timing chart showing an example of the operation of a measurement block according to an embodiment; [Figure 6] 4 is a timing chart showing an example of the operation of a measurement block according to an embodiment; [Figure 7] 5A to 5C are diagrams for explaining the operation of a comparative example and the operation of the embodiment. [Figure 8] FIG. 13 is a diagram showing the configuration of a measurement block of a comparative example. [Figure 9] FIG. 4 is a circuit diagram showing a configuration example of a start control circuit. [Figure 10] FIG. 4 is a circuit diagram showing a first modified example of an input circuit and a pulse signal generating circuit in a measurement block according to an embodiment of the present invention. [Figure 11] FIG. 11 is a circuit diagram showing a second modified example of an input circuit and a pulse signal generating circuit in the measurement block of the embodiment. [Figure 12] FIG. 11 is a circuit diagram showing a third modified example of an input circuit and a pulse signal generating circuit in a measurement block according to an embodiment of the present invention. [Figure 13] FIG. 4 is a circuit diagram showing an improved example 1 of the measurement block according to the embodiment. [Figure 14] FIG. 4 is a circuit diagram showing an improved example 2 of the measurement block according to the embodiment. [Figure 15] 15 is a timing chart showing the operation of a synchronization circuit and a higher-order TDC in the measurement block shown in FIG. 14. [Figure 16] FIG. 2 is a circuit diagram showing a configuration example of a pixel. [Figure 17] FIG. 11 is a circuit diagram showing another example of the configuration of a pixel. [Figure 18] FIG. 2 is a diagram showing the configuration of a range image sensor. [Figure 19] FIG. 1 is a diagram showing an example of the configuration of a moving object. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] FIG. 1 is a diagram showing the configuration of a distance measuring device RS according to an embodiment. The distance measuring device RS may be configured as, for example, a distance image generating device that generates a distance image. The distance measuring device RS measures the distance from the distance measuring device RS to an object OBJ based on the time of flight (TOF: Time Of Flight) of light. The distance measuring device RS may include, for example, a light emitting unit 110, an optical system 105, a distance image sensor 100, an image processing circuit 101, a memory 102, a monitor 103, and a control unit 104. Note that, although the distance measuring device RS is described here as including the distance image sensor 100 as one of a plurality of components, the distance image sensor 100 can also be understood as a distance measuring device. That is, the distance image sensor 100 can also be understood as the smallest component of the distance measuring device RS.

[0011] The control unit 104 controls the light emitting unit 110, the optical system 105, the range image sensor 100, the image processing circuit 101, the memory 102, and the monitor 103. The control unit 104 can be configured to send a synchronization signal LSS to the light emitting unit 110 and the range image sensor 100 (a time-to-digital conversion circuit). Sending the synchronization signal LSS is synonymous with activating the synchronization signal LSS. The synchronization signal LSS is a signal that commands the light emitting unit 110 to emit light.

[0012] The light emitting unit 110 emits pulsed light such as a laser beam in response to the synchronization signal LSS. If an object OBJ exists in an area where the pulsed light is irradiated, the pulsed light may be reflected by the object OBJ and enter the optical system 105. The optical system 105 forms an optical image of the object OBJ by the incident pulsed light on a pixel array of the distance image sensor 100. The distance image sensor 100 may include a pixel array having a plurality of pixels constituting the pixel array, and a time-to-digital conversion circuit that converts the time from the reception of the synchronization signal LSS to the reception of a stop signal output from each of the plurality of pixels of the pixel array into a digital signal. The pixels are preferably, for example, avalanche photodiodes, particularly SPADs (Single Photon Avalanche Diodes) that receive single photons, but may be other types of pixels, for example, event detection type pixels. The image processing circuit 101 may generate a distance image including distance information to the object OBJ based on the signal output from the time-to-digital conversion device and the known speed of light. The generated distance image can be output to the memory 102 and the monitor 103. The memory 102 stores the distance image, and the monitor 103 displays the distance image. The image processing circuit 101 may be incorporated in the distance image sensor 100.

[0013] 2 is a block diagram of the range image sensor 100. The range image sensor 100 includes a pixel array 70 configured with a plurality of pixels 10 arranged to form a plurality of rows and a plurality of columns. The range image sensor 100 may also include a time-to-digital conversion device TDCC that converts the time from light emission by the light-emitting unit 110 (activation of a start signal START) to light reception by the pixel 10 (activation of a stop signal STOP) into a digital signal based on signals from the plurality of pixels 10.

[0014] The digital conversion device TDCC may include a first measurement block (TDC1) 20-1 and a plurality of second measurement blocks (TDC2) 20-2. The plurality of second measurement blocks 20-2 may be arranged such that each of the second measurement blocks 20-2 corresponds to one column of the pixel array 70. Here, an example in which the digital conversion device TDCC includes a plurality of second measurement blocks 20-2 will be described, but the digital conversion device TDCC may include only one second measurement block 20-2. That is, the digital conversion device TDCC may include one or a plurality of second measurement blocks 20-2. As described below, the first measurement block 20-1 and the second measurement block 20-2 may have the same configuration, or may have different configurations from each other.

[0015] The digital conversion device TDCC may include a clock generation circuit 40 that generates a multi-phase clock signal (a plurality of clock signals φ0 to φ8 in this example). The clock generation circuit 40 may include, for example, a multi-phase PLL (Phase Locked Loop) circuit. The digital conversion device TDCC may also include a code generation circuit 50 that generates a code whose value changes with the same period as the period of the multi-phase clock signal generated by the clock generation circuit 40. In this example, the code generation circuit 50 includes a Gray code counter that generates a Gray code GC (G0 to G5). The digital conversion device TDCC may also include a start control circuit 30 that activates a start signal START and a measurement start signal SM in response to activation of the synchronization signal LSS. When the measurement start signal SM is activated, the multi-phase clock signals (φ0 to φ8) generated by the clock generation circuit 40 may be supplied to a first measurement block (TDC1) 20-1 and a plurality of second measurement blocks (TDC2) 20-2.

[0016] The range image sensor 100 may include a digital circuit 90. The digital circuit 90 may function as a control circuit in the range image sensor 100. The digital circuit 90 may also control, for example, activation and deactivation of a reset signal RESET. The range image sensor 100 may include a vertical scanning circuit 60 that selects at least one row from a plurality of rows of the pixel array 70 in a predetermined order. The range image sensor 100 may also include a horizontal scanning circuit 80 that selects output data of the first measurement block 20-1 and the plurality of second measurement blocks 20-2 in a predetermined order and provides the selected output data to the digital circuit 90. The digital circuit 90 processes the output data provided from the horizontal scanning circuit 80.

[0017] 3 is a diagram showing a configuration example of a measurement block 20 that can be used as the first measurement block 20-1 and the second measurement block 20-2. A start signal SART generated by the start control circuit 30 can be provided to a trigger input terminal TRIG of the measurement block 20 configured as the first measurement block 20-1. On the other hand, a stop signal STOP output from the pixel array 70 can be provided to a trigger input terminal TRIG of the measurement block 20 configured as the second measurement block 20-2. Note that the first measurement block 20-1 and the second measurement block 20-2 may have different configurations.

[0018] The measurement block 20 may include a pulse signal generator 22, a lower TDC 23, and an upper TDC 25. In this configuration example, the measurement block 20 includes the lower TDC 23 and the upper TDC 25, but the upper TDC 25 may be omitted. In a configuration in which the measurement block 20 includes the upper TDC 25, the measurement block 20 preferably includes a synchronization circuit 24.

[0019] The measurement block 20 may include an input circuit 21 that generates a transition detection signal DS. The input circuit 21 may activate the transition detection signal DS in response to activation of a trigger signal TRIG (a start signal START or a stop signal STOP). The pulse signal generator 22 generates a pulse signal PS in response to activation of the transition detection signal DS. The pulse signal PS transitions from an inactive state to an active state at a leading edge (first edge), and then transitions from an active state to an inactive state at a trailing edge (second edge). The pulse signal generator 22 may be understood as a differentiation circuit that differentiates an input signal to the pulse signal generator 22 (here, the transition detection signal DS). The pulse signal generator 22 may be configured to generate the pulse signal PS by, for example, a logical operation between a delayed signal obtained by delaying the transition detection signal DS and the transition detection signal DS.

[0020] The pulse signal generator 22 may generate a transition detection signal DSA by slightly delaying the transition detection signal DS so that the transition occurs at the same timing as the activation of the pulse signal PS. If the delay in the activation timing of the pulse signal PS relative to the activation timing of the transition detection signal DS is negligible, the transition detection signal DA may be used as the transition detection signal DSA.

[0021] The lower TDC 23 may be configured by a latch circuit that latches the multiphase clock signals φ0 to φ7 in response to the trailing edge of the pulse signal PS. Here, the latch circuit transitions from an enabled state to a disabled state at the edge at which the pulse signal PS transitions from an active state to an inactive state, and latches the multiple clock signals φ0 to φ7 that constitute the multiphase clock signal. The lower TDC 23 generates and outputs a lower bit string of the digital data (time-digital conversion result) output by the measurement block 20 as a lower result. The upper TDC 25 may be configured by a latch circuit that latches the Gray code GC generated by the code generation circuit 50 as a code whose value changes in the same period as the period of the multiphase clock signals φ0 to φ7 in response to activation of the timing signal TMG output by the synchronization circuit 24. The upper TDC 25 generates and outputs a higher bit string of the digital data (time-digital conversion result) output by the measurement block 20 as a higher result.

[0022] The synchronization circuit 24 receives at least one of the multiple clock signals φ0 to φ7 constituting the multi-phase clock signal φ, here φ2 and φ6 among φ0 to φ7, as a synchronous clock signal SCLK. The synchronization circuit 24 can supply a signal synchronized by receiving the transition detection signal DSA at a timing defined by the synchronous clock signal SCLK (synchronized transition detection signal) to the upper TDC 25 as a timing signal TMG. The synchronization circuit 24 can supply a signal synchronized by receiving the transition detection signal DSA at a timing determined according to signals (e.g., H0 to H3 described later) generated by the lower TDC 23 as a timing signal TMG to the upper TDC 25.

[0023] FIG. 4 is a circuit diagram showing a more specific example of the configuration of the measurement block 20 shown in FIG. 3. FIG. 5 and FIG. 6 are timing charts showing an example of the operation of the measurement block 20. "START@TDC1" is a start signal input to the first measurement block (TDC1) 20-1. "DSA@TDC1" is a transition detection signal DSA in the first measurement block (TDC1) 20-1. "PS@TDC1" is a pulse signal PS in the first measurement block (TDC1) 20-1. "Fine[7:0] of TDC1" is a lower-level result output by the lower TDC 23 of the first measurement block (TDC1) 20-1. "Coarse[5:0] of TDC1" is a lower-level result output by the upper TDC 25 of the first measurement block (TDC1) 20-1. "STOP from SPAD" is a stop signal input from the pixel array 70 to the second measurement block (TDC2) 20-2. “DSA@TDC2” is the transition detection signal DSA in the second measurement block (TDC2) 20-2. “PS@TDC2” is the pulse signal PS in the second measurement block (TDC2) 20-2. “Fine[7:0] of TDC2” is the lower result output by the lower TDC 23 of the second measurement block (TDC2) 20-2. “Coarse[5:0] of TDC2” is the lower result output by the upper TDC 25 of the second measurement block (TDC2) 20-2. “FF output A” is the output A of DFF241. “FF output B” is the output B of DFF242. “MUX selection output” is the selection signal input to the multiplexer 244.

[0024] The input circuit 21 may be configured, for example, as an SR latch, and a trigger signal TRIG may be supplied to a set terminal of the SR latch, and a reset signal RESET may be supplied to a reset terminal of the SR latch. The pulse signal generator 22 may be configured to generate a pulse signal PS by performing a logical operation (e.g., a logical AND operation) on the transition detection signal DS and a delayed signal obtained by delaying the transition detection signal DS using a delay device (e.g., a buffer circuit, etc.).

[0025] The lower TDC 23 may include a plurality of D latches 231 that latch a plurality of clock signals φ0 to φ7 that constitute a multi-phase clock signal in accordance with the trailing edge of the pulse signal PS. In the illustrated example, the pulse signal PS is a low-active pulse, and each D latch 231 has an enable terminal E of negative logic. When the input signal (pulse signal PS) to the enable terminal E is at a low level (active state), the D latch 231 is in a transparent state that transmits the input (multi-phase clock signal) to the D terminal. The D latch 231 is in a latch state that latches (determines) the input signal to the D terminal at the timing (trailing edge) when the input signal (pulse signal PS) to the enable terminal E transitions from a low level (active state) to a high level (inactive state). Then, while the input signal to the enable terminal E is at a high level, the D latch 231 maintains the latch state in which it continues to output the latched signal.

[0026] The D latch 231 includes an input stage (e.g., a transfer gate) and a subsequent holding circuit (e.g., an SR latch). When the input to the enable terminal E is in an active state (the D latch 231 is in a transparent state), the input stage transmits the input signal (multi-phase clock signal) to the D terminal to the holding circuit, and the holding circuit outputs a signal of the same level as the input signal. A multi-phase clock signal that toggles at high speed is input to the D terminal of the D latch 231. Therefore, when the D latch 231 is in a transparent state, the holding circuit of the D latch 231 repeats toggling at high speed, so power consumption may not be negligible. On the other hand, when the D latch 231 is in a latching state, the input stage blocks the input (multi-phase clock signal) to the D terminal, and the input signal to the holding circuit does not change. Therefore, when the D latch 231 is in a latching state, power consumption in the D latch 231 is negligible.

[0027] In this embodiment, the pulse signal PS output by the pulse signal generating circuit PS is supplied to the lower TDC 23 and input to the enable terminal E of the D latch 231, thereby reducing power consumption in the D latch 231. This suppresses a drop in the power supply voltage caused by power consumption in the D latch 231, and improves the time measurement accuracy.

[0028] The lower TDC 23 may be configured with a plurality of D flip-flops (DFFs) that latch the plurality of clock signals φ0 to φ7 that make up the multi-phase clock signal in accordance with the pulse signal PS, and in this case, the same effect as above can be obtained. In this case, the clock input terminal of the DFF can be set to positive logic.

[0029] A plurality of D latches 231 constituting a latch circuit output latched data (latch data) Rφ0 to Rφ7. The lower TDC 23 may include a one-shot code generation circuit 232 and an encoder 233. The one-shot code generation circuit 232 performs a logical operation on each pair (e.g., Rφ0 and Rφ1) of adjacent latch data Rφ0 to Rφ7 to generate one-shot codes H0 to H7 in which each bit is exclusively activated. The encoder 233 generates lower results by converting the one-shot codes H0 to H7 generated by the one-shot code generation circuit 232 into binary values. Some of the one-shot codes H0 to H7, in this example, H0 to H3, are also provided to the synchronization circuit 24.

[0030] The synchronization circuit 24 can capture the transition detection signal DSA in accordance with a clock signal (φ2, φ6) selected from the multi-phase clock signals (φ0 to φ7) based on H0 to H3 that are part of the one-shot codes H0 to H7 that are signals generated by the lower TDC 23. More specifically, the synchronization circuit 24 can select a clock signal having a transition timing that does not overlap with the activation timing of the transition detection signal DSA from the multi-phase clock signals (φ0 to φ7) based on H0 to H3 that are signals generated by the lower TDC 23.

[0031] As a specific example, the synchronization circuit 24 may include DFFs 241, 242, and 243, a multiplexer 244, and an OR circuit 245. DFF241 latches the clock signal φ6 out of the plurality of φ0 to φ7 signals constituting the multi-phase clock signal in accordance with the transition detection signal DS to generate the latch output A. DFF242 latches the clock signal φ2 out of the plurality of φ0 to φ7 signals constituting the multi-phase clock signal in accordance with the transition detection signal DS to generate the latch output B. Here, φ2 and φ6 may be clock signals having a phase difference of 180 degrees between them, that is, clock signals of opposite phases.

[0032] The multiplexer 244 calculates a logical sum of H0 to H3 which are parts of the one-shot codes H0 to H7, and causes the multiplexer 244 to select either the latch output A or B according to the logical sum. The selected latch output is a signal latched by a clock signal (a clock signal more preferable for avoiding metastability) having a transition timing that does not overlap with the activation timing of the transition detection signal DSA. DFF243 generates the timing signal TMG by latching, that is, synchronizing, the output of the multiplexer 244 in accordance with φ6. The synchronization circuit 24 can capture the transition detection signal DSA in accordance with a clock signal (φ2 or φ6) selected from the multi-phase clock signals (φ0 to φ7) based on H0 to H3 which are parts of the one-shot codes H0 to H7 which are signals generated by the lower TDC 23.

[0033] The upper TDC 25 latches the Gray code GC (G0 to G5) generated by the code generating circuit 50 in accordance with the timing signal TMG provided by the synchronization circuit 24.

[0034] Fig. 7(a) is a diagram illustrating the operation of the comparative example, and Fig. 7(b) is a diagram illustrating the operation of this embodiment. As shown in Fig. 8, the comparative example has a configuration in which the pulse signal generator 22 is removed from the configuration shown in Fig. 4, and a transition detection signal DS is provided to the lower TDC 23 and the upper TDC 25. In the comparative example, a start signal START is input to a first measurement block (TDC1), and a transition detection signal DS is provided to the lower TDC 23 and the upper TDC 25. Also, in the comparative example, a stop signal STOP is input to a second measurement block (TDC2), and a transition detection signal DS is provided to the lower TDC 23 and the upper TDC 25.

[0035] 7(a), in the comparative example, in the second measurement block (TDC2), the transition detection signal DS is maintained in an active state for a long period of time from when the synchronization signal LSS is activated until when it is deactivated in response to the stop signal STOP. Therefore, in the comparative example, the latch circuits constituting the lower TDC 23 and the upper TDC 25 toggle at high speed in the transparent state for a long period of time, resulting in high power consumption.

[0036] 7(b), in this embodiment, in both the first measurement block (TDC1) and the second measurement circuit (TDC2), a pulse signal PS having a short active period is supplied to the latch circuits constituting the lower TDC 23 and the upper TDC 25. Therefore, in this embodiment, power consumption by the latch circuits constituting the lower TDC 23 and the upper TDC 25 in the transparent state is reduced.

[0037] Here, an example of estimating the effect of power consumption will be described. For example, when the time resolution is 50 ps, ​​a toggle operation occurs at 20 GHz (= 1 / 50 ps) in the latch circuit of each measurement block. In a comparative example, each measurement block may consume about 0.5 mW of power. In this embodiment, this power consumption can be suppressed to 0.1 mW or less.

[0038] In addition, in the comparative example, if the impedance of the power supply line and the ground line is 1 Ω, and the current flowing from the power supply line to the ground line through each measurement block is 0.5 A, the voltage drop of the power supply line is 0.5 V. If the nominal value of the power supply voltage is 1 V, a voltage drop of 0.5 V may cause a malfunction. If the inductance of the bonding wire causes a voltage drop due to an instantaneous current, this may also cause a malfunction. According to the present embodiment, resistance to such a malfunction is also provided.

[0039] 9 is a circuit diagram showing a configuration example of the start control circuit 30. The start control circuit 30 may include, for example, an SR latch 301 that activates a measurement start signal SM in response to activation of a synchronization signal LSS, and a delay circuit 302 that delays the synchronization signal LSS to generate the start signal START. The delay circuit 302 may have the same delay time as the delay from the activation of the synchronization signal LSS to the activation of the measurement start signal SM in the SR latch 301.

[0040] FIG. 10 is a diagram showing a first modification of the input circuit 21 and the pulse signal generator 22 of each measurement block 20. In the first modification, the pulse signal generator 22 may include a delay device 221 that delays the transition detection signal DS, and a logic circuit 222 that generates a pulse signal PS by a logical operation (e.g., a logical AND operation) between the output signal of the delay device 221 and the transition detection signal DS. The delay device 221 may include an RC circuit. The pulse signal generator 22 may include a logic circuit 223 that generates a transition detection signal DSA that is a slightly delayed version of the transition detection signal DS so that the transition occurs at the same timing as the activation of the pulse signal PS. Note that, if the delay in the activation timing of the pulse signal PS relative to the activation timing of the transition detection signal DS is negligible, the logic circuit 223 is not necessary, and the transition detection signal DA may be used as the transition detection signal DSA. In the first modification, the input circuit 21 may be configured, for example, with an SR latch.

[0041] 11 is a diagram showing a second modification of the input circuit 21 and the pulse signal generator 22 of each measurement block 20. In the second modification, the delay device 225 generates a pulse signal PS by delaying a pulse signal as the trigger signal TRIG, and the SR latch 224 generates a transition detection signal DSA in response to the trigger signal TRIG. In the second modification, the trigger signal TRIG can be understood as being provided to the measurement block 20 as a transition detection signal.

[0042] 12 is a diagram showing a third modification of the input circuit 21 and the pulse signal generator 22 of each measurement block 20. In the third modification, the delay unit 226 generates a pulse signal PS by delaying a pulse signal as the trigger signal TRIG, and the SR latch 224 generates a transition detection signal DSA in response to the trigger signal TRIG. The delay unit 226 may include, for example, a current source arranged between a power supply line and an inverter circuit, a current source arranged between the inverter circuit and a ground line, and a buffer circuit. Even in the third modification, the trigger signal TRIG can be understood as being provided to the measurement block 20 as a transition detection signal.

[0043] 13 is a circuit diagram showing a first improvement of the measurement block 20. In the first improvement, the measurement block 20 has a pulse signal generator 22 having a different configuration from the pulse signal generator 22 shown in FIG. 4. In the first improvement, the pulse signal generator 22 includes a delay device DL, and the transition detection signal DS is delayed by the delay device DL and provided to the synchronization circuit 24 as the transition detection signal DSA. The delay time by the delay device DL can be adjusted so that the pulse signal PS supplied to the lower TDC 23 and the transition detection signal DSA supplied to the synchronization circuit 24 are accurately synchronized.

[0044] FIG. 14 is a circuit diagram showing a second improvement of the measurement block 20. The measurement block 20 shown in FIG. 14 differs from the synchronization circuit 24 shown in FIG. 4 in the configuration of the synchronization circuit 24. In the second improvement, the pulse signal generator 22 generates a pulse signal as the synchronized timing signal TMG. In the second improvement, DFF246 and a logic gate 247 are added to the synchronization circuit 24 shown in FIG. 4. DFF246 latches the output of DFF243 in accordance with φ6, and the logic gate 247 generates a pulsed timing signal TMG by a logical operation on the outputs of DFF243 and DFF246.

[0045] Fig. 15 is a timing chart showing the operation of the synchronization circuit 24 and the upper TDC 25 in the measurement block 20 shown in Fig. 14. The timing signal TMG is generated as a pulse signal, so that the time during which the upper TDC 25 is in a transparent state is limited to the pulse width of the pulse signal. This reduces the power consumption in the upper TDC 25.

[0046] 16 is a circuit diagram showing an example of a configuration of a pixel 10. The pixel 10 includes, for example, a SPAD 11, a quenching element 12, and a waveform shaping unit 13, and functions as a light receiving unit of pulsed light. The SPAD 11 generates a pair of charges according to incident light by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the SPAD 11, and a voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the SPAD 11. A reverse bias voltage is applied between the anode and the cathode, and the SPAD 11 is in a state where avalanche multiplication is possible. When a photon is incident on the SPAD 11 in a state where the reverse bias voltage is supplied, the charge generated by the photon causes avalanche multiplication, and an avalanche current is generated.

[0047] The quench element 12 is provided between a power supply line that supplies the voltage VH and the cathode of the SPAD 11. The quench element 12 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has the function of suppressing the voltage supplied to the SPAD 11 and suppressing the avalanche multiplication (quench operation). The quench element 12 also has the function of returning the voltage supplied to the SPAD 11 to the voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0048] The waveform shaping unit 13 can function as a signal generating unit that generates a detection pulse as a stop signal STOP in response to an output change occurring at the cathode of the SPAD 11 due to the incidence of a photon. That is, the waveform shaping unit 13 can shape the potential change at the cathode of the SPAD 11 obtained when a photon is detected, and output a square-wave STOP signal (detection pulse). The waveform shaping unit 13 can be configured, for example, by an inverter circuit. Although FIG. 16 illustrates an example of the waveform shaping unit 13 configured by one inverter circuit, the waveform shaping unit 13 may be configured by connecting a plurality of inverter circuits in series, or may be configured by another circuit having a waveform shaping effect.

[0049] FIG. 17 shows another example of the configuration of the pixel 10. In the example of the configuration of FIG. 17, the pixel 10 is an event detection type pixel. The pixel 10 may include a logarithmic response unit 410, a buffer 420, a differentiation circuit 430, and a comparator 440. The logarithmic response unit 410 may include a photoelectric conversion element 411 and a current-voltage conversion unit 416. The photoelectric conversion element 411 may be a photodiode that does not cause avalanche multiplication. When pulsed light is incident on the photoelectric conversion element 411, the photoelectric conversion element 411 generates a photocurrent by photoelectric conversion. The current-voltage conversion unit 416 logarithmically converts the photocurrent into a pixel voltage Vp. The current-voltage conversion unit 416 may include N-type transistors 412 and 415, a capacitance 413, and a P-type transistor 414.

[0050] The source of N-type transistor 412 is connected to the cathode of photoelectric conversion element 411, and the drain is connected to a power supply terminal. P-type transistor 414 and N-type transistor 415 are connected in series between a power supply line and a ground line. The connection point of P-type transistor 414 and N-type transistor 415 is connected to the gate of N-type transistor 412 and the input terminal of buffer 420. The connection point of N-type transistor 412 and photoelectric conversion element 411 is connected to the gate of N-type transistor 415. A bias voltage Vb1 is applied to the gate of P-type transistor 414. Capacitor 413 is disposed between the gate of N-type transistor 412 and the gate of N-type transistor 415.

[0051] Buffer 420 may include P-type transistors 421 and 422. P-type transistors 421 and 422 are connected in series between a power supply line and a ground line. The gate of P-type transistor 422 is connected to logarithmic response unit 410, and the connection point of P-type transistors 421 and 422 is connected to differentiation circuit 430. A bias voltage Vb2 is applied to the gate of P-type transistor 421.

[0052] The differentiation circuit 430 includes a capacitance 431, P-type transistors 432 and 433, and an N-type transistor 435. The differentiation circuit 430 may further include a capacitance 434. The P-type transistor 433 and the N-type transistor 435 are connected in series between a power supply line and a ground line. A bias voltage Vdiff is applied to the gate of the N-type transistor 435. The capacitance 431 is inserted between the buffer 420 and the input terminal 491. The capacitance 431 supplies a current corresponding to the time differential of the pixel voltage Vp from the buffer 420 to the input terminal 491. The capacitance 434 may be disposed between the gate and drain of the P-type transistor 433, but the capacitance 434 may be omitted.

[0053] In response to the initialization signal Trs, the P-type transistor 432 shorts the gate and drain of the P-type transistor 433, and sets the differentiated signal Vout to its initial value.

[0054] The comparator 440 may include a P-type transistor 441 and an N-type transistor 442. The P-type transistor 441 and the N-type transistor 442 are connected in series between a power supply line and a ground line. The gate of the P-type transistor 441 is connected to the differentiation circuit 430. A threshold voltage Vth is applied to the gate of the N-type transistor 442. A stop signal STOP is output from the connection point of the P-type transistor 441 and the N-type transistor 442.

[0055] FIG. 18 shows a configuration example of the range image sensor 100. In this configuration example, the range image sensor 100 has a stacked structure of multiple substrates. The range image sensor 100 includes a sensor substrate (first substrate) 1 and a circuit substrate (second substrate) 2 stacked on top of each other, and the sensor substrate 1 and the circuit substrate 2 are electrically connected to each other. The range image sensor 100 is a back-illuminated type, in which light is incident from a first surface of the sensor substrate 1, and the circuit substrate 2 is disposed on a second surface of the sensor substrate 1. The sensor substrate 1 has a first semiconductor layer and a first wiring structure. The circuit substrate 2 has a second semiconductor layer and a second wiring structure. The second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer are stacked in this order to form the range image sensor 100.

[0056] The sensor substrate 1 and the circuit substrate 2 may be diced chips, but are not limited to chips. For example, each substrate may be a wafer. Also, each substrate may be stacked in a wafer state and then diced, or may be chipped and then stacked and bonded. The sensor substrate 1 is provided with a pixel region 1a including an array of SPADs 11 of each of the multiple pixels 10, and the circuit substrate 2 is provided with a circuit region 2a for processing signals detected by the pixel region 1a. Circuits of the pixels 10 other than the SPADs 11, a time-to-digital conversion device TDCC, and the like may be arranged in the circuit region 2a.

[0057] An application example of the range image sensor 100 will be described below. Fig. 19(a) shows a configuration example of a device mounted on a vehicle as an on-board camera. The device 300 has a distance measurement unit 303 and a collision determination unit 304. The distance measurement unit 303 is configured by the above-mentioned range image sensor 100, and measures the distance to an object. The distance information is information related to the distance to the object, etc. The collision determination unit 304 determines whether or not there is a possibility of a collision based on the distance measured by the distance measurement unit 303.

[0058] The device 300 is connected to a vehicle information acquisition device 310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. In addition, the device 300 is connected to a control ECU 320, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 304. In addition, the device 300 is also connected to an alarm device 330 that issues an alarm to the driver based on the judgment result of the collision judgment unit 304. For example, when the judgment result of the collision judgment unit 304 indicates that there is a high possibility of a collision, the control ECU 320 instructs the vehicle to apply the brakes, stop the accelerator, suppress the engine output, etc., to avoid the collision and reduce damage. The alarm device 330 warns the user through alarm output such as sound, display of alarm information on the screen of a car navigation system, etc., and vibration of the seat belt and steering wheel. These devices of the device 300 function as a mobile object control unit that controls the operation of controlling the vehicle as described above.

[0059] In this embodiment, the device 300 measures distances around the vehicle, for example, in front or behind. Fig. 19(b) shows the device when measuring distances in front of the vehicle (distance measurement range 350). A vehicle information acquisition device 310 as a distance measurement control means sends an instruction to the device 300 or the distance measurement unit 303 to perform a distance measurement operation. With this configuration, the accuracy of distance measurement can be further improved.

[0060] Although the above describes the control of avoiding collision with other vehicles, the present embodiment can also be applied to control of automatic driving by following other vehicles, control of automatic driving so as not to deviate from lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present embodiment can be applied to devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, in addition to moving bodies.

[0061] The disclosure of the present specification includes the following configurations. (Item 1) a pulse signal generator for generating a pulse signal in response to activation of the transition detection signal; a latch circuit for latching the multi-phase clock signals in response to a trailing edge of the pulse signal; A time-to-digital conversion circuit comprising: (Item 2) 2. The time-to-digital conversion circuit according to item 1, further comprising an input circuit that activates the transition detection signal in response to activation of a trigger signal. (Item 3) the input circuit includes an SR latch; 3. The time-to-digital conversion circuit according to item 2. (Item 4) the latch circuit includes a plurality of D latches that latch a plurality of clock signals that constitute the multi-phase clock signal; 4. A time-to-digital conversion circuit according to any one of claims 1 to 3. (Item 5) the latch circuit includes a plurality of D flip-flops that latch a plurality of clock signals that constitute the multi-phase clock signal; 4. A time-to-digital conversion circuit according to any one of claims 1 to 3. (Item 6) the pulse signal generator generates the pulse signal by a logical operation between the transition detection signal and a delayed signal obtained by delaying the transition detection signal; 6. A time-to-digital conversion circuit according to any one of claims 1 to 5. (Item 7) an upper TDC that latches a code whose value changes with the same period as that of the multi-phase clock signals in response to activation of a timing signal; a synchronization circuit, The latch circuit constitutes a lower TDC, the synchronization circuit receives the transition detection signal at a timing determined according to a signal generated by the lower TDC, and supplies the synchronized signal to the upper TDC as the timing signal; 7. A time-to-digital conversion circuit according to any one of claims 1 to 6. (Item 8) the synchronization circuit captures the transition detection signal in accordance with a clock signal selected from a plurality of clock signals constituting the multi-phase clock signal based on the signal generated by the lower TDC; 8. The time-to-digital conversion circuit according to item 7. (Item 9) the synchronization circuit selects, based on the signal generated by the lower TDC, a clock signal having a transition timing that does not overlap with an activation timing of the transition detection signal from among a plurality of clock signals constituting the multi-phase clock signal; 9. The time-to-digital conversion circuit according to item 8. (Item 10) the transition detection signal is supplied to the synchronization circuit via a delay device; 10. A time-to-digital conversion circuit according to any one of items 7 to 9. (Item 11) the synchronization circuit generates a pulse signal as the synchronized signal; 11. A time-to-digital conversion circuit according to any one of items 7 to 10. (Item 12) A first time-to-digital conversion circuit having the same configuration as the time-to-digital conversion circuit described in any one of items 7 to 11 and receiving a start signal as a trigger signal; A second time-to-digital conversion circuit having the same configuration as the time-to-digital conversion circuit described in any one of items 7 to 11 and receiving a stop signal as a trigger signal; a clock generating circuit that supplies multi-phase clock signals to the first time-to-digital conversion circuit and the second time-to-digital conversion circuit; a code generating circuit that supplies a code whose value changes with the same period as that of the multi-phase clock signal to the first time-to-digital conversion circuit and the second time-to-digital conversion circuit; A time-to-digital conversion device comprising: (Item 13) a pixel array having a plurality of pixels; A time-to-digital conversion device according to item 12, the second time-to-digital conversion circuit of the time-to-digital conversion device receives a stop signal from the pixel array; A distance measuring device comprising: (Item 14) Each of the plurality of pixels includes an avalanche photodiode. 14. A distance measuring device according to item 13, characterized in that (Item 15) each of the plurality of pixels includes an event detection pixel; 14. A distance measuring device according to item 13, characterized in that (Item 16) A light emitting portion; a control unit that transmits a synchronization signal to the light emitting unit and the time-to-digital conversion circuit; 16. The distance measuring device according to any one of items 13 to 15, further comprising: (Item 17) A mobile object, A distance measuring device according to any one of items 13 to 15, a control unit for controlling the moving object based on an output of the distance measuring device; A moving object comprising:

[0062] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0063] DS: transition detection signal, PS: pulse signal, 21: input circuit, 22: pulse signal generating circuit, 23: lower TDC (latch circuit), 25: synchronization circuit, 20: measurement block (TDC), TDCC: time-to-digital conversion device.

Claims

1. a pulse signal generator for generating a pulse signal in response to activation of the transition detection signal; a latch circuit for latching the multi-phase clock signals in response to a trailing edge of the pulse signal; A time-to-digital conversion circuit comprising:

2. 2. The time-to-digital conversion circuit according to claim 1, further comprising an input circuit for activating the transition detection signal in response to activation of a trigger signal.

3. the input circuit includes an SR latch; 3. The time-to-digital conversion circuit according to claim 2.

4. the latch circuit includes a plurality of D latches that latch a plurality of clock signals that constitute the multi-phase clock signal; 2. The time-to-digital conversion circuit according to claim 1 .

5. the latch circuit includes a plurality of D flip-flops that latch a plurality of clock signals that constitute the multi-phase clock signal; 2. The time-to-digital conversion circuit according to claim 1 .

6. the pulse signal generator generates the pulse signal by a logical operation between the transition detection signal and a delayed signal obtained by delaying the transition detection signal; 2. The time-to-digital conversion circuit according to claim 1 .

7. an upper TDC that latches a code whose value changes with the same period as that of the multi-phase clock signals in response to activation of a timing signal; a synchronization circuit, The latch circuit constitutes a lower TDC, the synchronization circuit receives the transition detection signal at a timing determined in accordance with a signal generated by the lower TDC, and supplies the synchronized signal to the upper TDC as the timing signal; 7. A time-to-digital conversion circuit according to claim 1,

8. the synchronization circuit acquires the transition detection signal in accordance with a clock signal selected from a plurality of clock signals constituting the multi-phase clock signal based on the signal generated by the lower TDC; 8. The time-to-digital conversion circuit according to claim 7.

9. the synchronization circuit selects, based on the signal generated by the lower TDC, a clock signal having a transition timing that does not overlap with an activation timing of the transition detection signal from among a plurality of clock signals constituting the multi-phase clock signal; 9. The time-to-digital conversion circuit according to claim 8.

10. the transition detection signal is supplied to the synchronization circuit via a delay device; 10. The time-to-digital conversion circuit according to claim 7,

11. the synchronization circuit generates a pulse signal as the synchronized signal; 11. The time-to-digital conversion circuit according to claim 7,

12. A first time-to-digital conversion circuit having the same configuration as the time-to-digital conversion circuit according to any one of claims 7 to 11 and receiving a start signal as a trigger signal; a second time-to-digital conversion circuit having the same configuration as the time-to-digital conversion circuit according to any one of claims 7 to 11 and receiving a stop signal as a trigger signal; a clock generating circuit that supplies multi-phase clock signals to the first time-to-digital conversion circuit and the second time-to-digital conversion circuit; a code generating circuit that supplies a code whose value changes with the same period as a period of the multi-phase clock signals to the first time-to-digital conversion circuit and the second time-to-digital conversion circuit; A time-to-digital conversion device comprising:

13. a pixel array having a plurality of pixels; and the time-to-digital conversion device according to claim 12, the second time-to-digital conversion circuit of the time-to-digital conversion device receives a stop signal from the pixel array; A distance measuring device comprising:

14. Each of the plurality of pixels includes an avalanche photodiode.

14. A distance measuring device according to claim 13.

15. each of the plurality of pixels includes an event detection pixel; 14. A distance measuring device according to claim 13.

16. A light emitting portion; a control unit that transmits a synchronization signal to the light emitting unit and the time-to-digital conversion circuit; 14. The distance measuring device according to claim 13, further comprising:

17. A mobile object, A distance measuring device according to claim 13; a control unit for controlling the moving object based on an output of the distance measuring device; A moving object comprising:

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