Power conversion device

Abstract

To provide a power conversion device that can materialize high switching frequencies.SOLUTION: A power conversion device according to an embodiment includes a plurality of power conversion phases that output AC powers of different phases at output terminals. The output terminals of the plurality of power conversion phases are connected to each other. Each of the plurality of power conversion phases includes a first sub-switching leg and a second sub-switching leg connected in parallel between a positive DC terminal and a negative DC terminal, and a first inductor and a second inductor. Each of the first sub-switching leg and the second sub-switching leg outputs AC power at an output node. The first inductor is connected between an output node of the first sub-switching leg and the output terminal. The second inductor is connected between an output node of the second sub-switching leg and the output terminal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a power conversion device. [Background technology]

[0002] In recent years, the use of electric motors for power has been progressing in fields where internal combustion engines were previously used, particularly in the field of mobile vehicles. Electric motors in the mobile field need to be made smaller, and as they become smaller, it is expected that the leakage inductance generated in the motor will become smaller. Since inverters that drive electric motors output a large amount of harmonic voltage, the current driving a small electric motor will contain a large amount of pulsating components if the motor's leakage inductance is small. This leads to the generation of torque pulsation and an increase in the temperature of the motor's iron core.

[0003] One way to suppress harmonic voltages output by an inverter is to increase the switching frequency of the inverter. However, the larger the capacity of the semiconductor switches used in a large-capacity inverter, the slower the switching operation of the semiconductor switches between on and off, resulting in a lower switching frequency of the inverter.

[0004] Another method for increasing the switching frequency of an inverter is to use a semiconductor switch that uses a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of a semiconductor with a wide bandgap, such as SiC. However, this method only replaces the semiconductor switch and does not incorporate any circuit improvements. For this reason, the highest switching frequency currently achieved is around 3 kHz. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6783419 Summary of the Invention [Problem to be solved by the invention]

[0006] A power conversion device capable of realizing a high switching frequency is provided. [Means for solving the problem]

[0007] A power conversion device according to one embodiment includes a plurality of power conversion phases that output AC powers of different phases at output terminals. The output terminals of the plurality of power conversion phases are connected to each other. Each of the plurality of power conversion phases includes a first sub-switching leg and a second sub-switching leg connected in parallel between a positive DC terminal and a negative DC terminal, and a first inductor and a second inductor. Each of the first sub-switching leg and the second sub-switching leg outputs AC power at an output node. The first inductor is connected between the output node of the first sub-switching leg and the output terminal. The second inductor is connected between the output node of the second sub-switching leg and the output terminal. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 shows an example of the configuration of a power conversion device according to the first embodiment. [Figure 2] FIG. 2 shows an example of an outline of the configuration of the power conversion phase of the power conversion device according to the first embodiment. [Figure 3] FIG. 3 shows an example of the configuration of the power conversion phases of the power conversion device according to the first embodiment. [Figure 4] FIG. 4 shows an example of the configuration of a gate driver of a power conversion device according to the second embodiment. [Figure 5] FIG. 5 shows an example of the circuit configuration of a gate driver of a power conversion device according to the second embodiment. [Figure 6] FIG. 6 shows the configuration of a portion of the power conversion phase of a power conversion device according to the third embodiment. [Figure 7] FIG. 7 shows an example of the configuration of a sub-switching leg of a power conversion device according to the fourth embodiment. [Figure 8] FIG. 8 shows connections of some of the components of the power conversion device according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. A plurality of components having substantially the same functions and configurations may be distinguished from one another by adding an additional number or letter to the end of the reference numeral. In an embodiment following a certain described embodiment, differences from the described embodiment will be mainly described. Any description of one embodiment also applies to a description of another embodiment unless explicitly or obviously excluded.

[0010] 1. First embodiment FIG. 1 shows an example of the configuration of a power conversion device according to a first embodiment. In one example, the power conversion device 1 is mounted on a moving body such as an electric vehicle. The power conversion device 1 is a device that receives a DC voltage, generates AC power from the applied DC voltage, and outputs the generated AC power at an output terminal. The AC power is supplied to a load 2. In one example, the load 2 is a traction motor.

[0011] The power conversion device 1 receives a control signal from the control circuit 3 and operates based on the control signal. In one example, the power conversion device 1 includes a printed wiring board and semiconductor chips and wiring arranged on the printed wiring board. In one example, the power conversion device 1 converts an applied DC voltage into three-phase AC power. The following description is based on this example.

[0012] As shown in FIG. 1 , the power conversion device 1 includes three power conversion phases 5 (5_1, 5_2, and 5_3). The three power conversion phases 5 have the same configuration. Each power conversion phase 5 outputs one phase of AC power. In one example, the power conversion phase 5_1 outputs U-phase AC power, the power conversion phase 5_2 outputs V-phase AC power, and the power conversion phase 5_3 outputs W-phase AC power. Each power conversion phase 5 includes a switching leg 6 (6_1, 6_2, and 6_3).

[0013] The control circuit 3 is a circuit that controls the operation of the power conversion device 1. The control circuit 3 receives a command value and operates in accordance with the command value. In one example, the command value is supplied from a user of the power conversion device 1 or from a control circuit higher than the control circuit 3 that controls the control circuit 3. The control circuit 3 controls the power conversion device 1 in accordance with the command value so that the output power of the power conversion device 1 has a magnitude based on the command value. In one example, the control circuit 3 is an arithmetic device that includes at least one processor and a memory in which a program executed by the processor is recorded.

[0014] Fig. 2 shows an example of the outline of the configuration of the power conversion phase of the power conversion device according to the first embodiment. As shown in Fig. 2, the power conversion phase 5 includes a switching leg 6, a gate driver 7, and inductors 8a and 8b.

[0015] The power conversion phase 5 supplies AC power to the load 2 at an output terminal AC.

[0016] The switching leg 6 includes sub-switching legs 9a and 9b. The sub-switching legs 9a and 9b are circuits that receive a DC voltage, generate AC power from the applied DC voltage, and output the generated AC power at an output node.

[0017] The gate driver 7 is a circuit that receives a control signal from the control circuit 3 and controls the sub-switching legs 9a and 9b based on the control signal.

[0018] The inductor 8a is connected between the sub-switching leg 9a and the output terminal AC of the power conversion phase 5. The inductor 8b is connected between the sub-switching leg 9b and the output terminal AC. In one example, the inductors 8a and 8b are each a reactor.

[0019] Fig. 3 shows an example of the configuration of power conversion phases of the power conversion device according to the first embodiment. Fig. 3 shows only one power conversion phase 5. As shown in Fig. 3, the sub-switching legs 9a and 9b are connected in parallel between a positive-side DC terminal 13 and a negative-side DC terminal 14. The positive-side DC terminal 13 is a terminal that receives a positive DC power supply voltage. The negative-side DC terminal 14 is a terminal that receives a negative DC power supply voltage.

[0020] The gate driver 7 includes a gate driver 7a and a gate driver 7b.

[0021] The sub-switching leg 9a includes arms 11a and 12a. The arm 11a is connected between the positive DC terminal 13 and the output node N1. In one example, the arm 11a is configured as a single semiconductor chip. The arm 11a includes a semiconductor switch T1 and a diode D1.

[0022] The semiconductor switch T1 is formed using a semiconductor and turns on or off based on the voltage of its gate terminal, electrically connecting or disconnecting two terminals of the semiconductor switch T1. In one example, the semiconductor switch T1 is an n-channel MOSFET (Field Effect Transistor). The semiconductor switch T1 may also be an IGBT (Insulated Gate Bipolar Transistor). The semiconductor switch T1 has a capacity of 50 A to 100 A, i.e., it can pass a rated current of 50 A to 100 A. The semiconductor switch T1 is composed of a single semiconductor element having such a capacity. In other words, a semiconductor switch that handles a large current, such as 1 kA or more, is generally realized by connecting multiple independent small-capacity semiconductor elements in parallel. Therefore, a semiconductor chip including such a semiconductor switch includes multiple independent small-capacity semiconductor elements connected in parallel. On the other hand, the semiconductor switch T1 does not include multiple independent semiconductor elements connected in parallel. Therefore, when the arm 11a is one semiconductor chip, the semiconductor chip does not include a plurality of independent semiconductor elements connected in parallel, but includes one semiconductor element as the semiconductor switch T1.

[0023] The semiconductor switch T1 has a source terminal connected to the output node N1. The semiconductor switch T1 has a drain terminal connected to the positive DC terminal 13. The semiconductor switch T1 receives a gate signal S1 from the gate driver 7a at its gate terminal. The gate signal S1 has a pulse shape.

[0024] The diode D1 has an anode connected to the output node N1 and a cathode connected to the positive DC terminal 13.

[0025] The arm 12a is connected between the output node N1 and the negative DC terminal 14. In one example, the arm 12a is configured as a single semiconductor chip. The arm 12a has substantially the same characteristics as the arm 11a. In this specification and claims, "substantially the same (identical)" means that two or more elements that are "substantially the same (identical)" are intended to be identical, but are not completely identical due to limitations in manufacturing technology and / or measurement technology. In one example, the arm 12a is the same semiconductor chip as the arm 11a. The arm 12a includes a semiconductor switch T2 and a diode D2.

[0026] The semiconductor switch T2 is formed using a semiconductor and is a switch that turns on or off based on the voltage of the gate terminal, electrically connecting or disconnecting two terminals of the semiconductor switch T2. In one example, the semiconductor switch T2 is an n-channel MOSFET. The semiconductor switch T2 may also be an IGBT. The semiconductor switch T2 has a capacity of 50 A or more and 100 A or less. Like the semiconductor switch T1, the semiconductor switch T2 is formed by a single semiconductor element having such a capacity and does not include multiple independent semiconductor elements connected in parallel. Therefore, when the arm 12a is a single semiconductor chip, the semiconductor chip does not include multiple independent semiconductor elements connected in parallel, but includes a single semiconductor element as the semiconductor switch T2.

[0027] The semiconductor switch T2 has a source terminal connected to the negative DC terminal 14. The semiconductor switch T2 has a drain terminal connected to the output node N1. The semiconductor switch T2 receives a gate signal S2 from the gate driver 7b at its gate terminal. The gate signal S2 is an inverted version of the gate signal S1.

[0028] The diode D2 has an anode connected to the negative DC terminal 14. The diode D2 has a cathode connected to the output node N1.

[0029] The sub-switching leg 9b includes arms 11b and 12b. The arm 11b is connected between the positive DC terminal 13 and the output node N2. In one example, the arm 11b is configured as a single semiconductor chip. In one example, the arm 11b is the same semiconductor chip as the arm 11a. The arm 11b includes a semiconductor switch T3 and a diode D3.

[0030] The semiconductor switch T3 is formed using a semiconductor and is a switch that turns on or off based on the voltage of the gate terminal, electrically connecting or disconnecting the two terminals of the semiconductor switch T3. In one example, the semiconductor switch T3 is an n-channel MOSFET. The semiconductor switch T3 may also be an IGBT. The semiconductor switch T3 has a capacity of 50 A or more and 100 A or less. Like the semiconductor switch T1, the semiconductor switch T3 is configured by a single element having such a capacity and does not include multiple independent semiconductor elements connected in parallel. Therefore, when the arm 11b is a single semiconductor chip, the semiconductor chip does not include multiple independent semiconductor elements connected in parallel, but includes a single semiconductor element as the semiconductor switch T3.

[0031] The semiconductor switch T3 has a source terminal connected to the output node N2. The semiconductor switch T3 has a drain terminal connected to the positive DC terminal 13. The semiconductor switch T3 receives a gate signal S3 from the gate driver 7a at its gate terminal. The gate signal S3 is substantially the same signal as the gate signal S1.

[0032] The diode D3 has an anode connected to the output node N2 and a cathode connected to the positive DC terminal 13.

[0033] The arm 12b is connected between the output node N2 and the negative DC terminal 14. The arm 12b has substantially the same characteristics as the arm 11b. In one example, the arm 12b is the same semiconductor chip as the arm 11a. The arm 12b includes a semiconductor switch T4 and a diode D4.

[0034] The semiconductor switch T4 is formed using a semiconductor and is a switch that turns on or off based on the voltage of the gate terminal, electrically connecting or disconnecting the two terminals of the semiconductor switch T4. In one example, the semiconductor switch T4 is an n-channel MOSFET. The semiconductor switch T4 may also be an IGBT. The semiconductor switch T4 has a capacity of 50 A or more and 100 A or less. Like the semiconductor switch T1, the semiconductor switch T4 is configured by a single element having such a capacity and does not include multiple independent semiconductor elements connected in parallel. Therefore, when the arm 12b is a single semiconductor chip, the semiconductor chip does not include multiple independent semiconductor elements connected in parallel, but includes a single semiconductor element as the semiconductor switch T4.

[0035] The semiconductor switch T4 has a source terminal connected to the negative DC terminal 14. The semiconductor switch T4 has a drain terminal connected to the output node N2. The semiconductor switch T4 receives a gate signal S4 from the gate driver 7b at its gate terminal. The gate signal S4 is substantially the same signal as the gate signal S2.

[0036] The diode D4 has an anode connected to the negative DC terminal 14. The diode D4 has a cathode connected to the output node N2.

[0037] Each of the gate drivers 7a and 7b is a circuit that drives a semiconductor switch based on a received signal. The gate driver 7a receives a control signal S5 from the control circuit 3 and generates gate signals S1 and S3 based on the control signal S5. The gate driver 7b receives a control signal S6 from the control circuit 3 and generates gate signals S2 and S4 based on the control signal S6.

[0038] The inductor 8a is connected between the output node N1 and the output terminal AC, and the inductor 8b is connected between the output node N2 and the output terminal AC.

[0039] Inductors 8a and 8b are intentionally added to the power conversion phase 5. For this reason, it is desirable that the inductance of each of inductors 8a and 8b be small. In one example, when the voltage applied to load 2 by power conversion phase 5 is 1150 V and the power consumption of load 2 is 800 kVA, the load impedance is 1.65 Ω. In this example, when the frequency of the AC output of power conversion device 1 is 500 Hz, the effect described below can be obtained if inductors 8a and 8b have an inductance of approximately 7.5 μH. This is equivalent to approximately 1.5% of the percent impedance of power conversion device 1. This small inductance is sufficiently small for practical use as an inductor value intentionally added to power conversion phase 5.

[0040] In the power conversion device 1 according to the first embodiment, each switching leg 6 includes two sub-switching legs 9a and 9b connected in parallel. The sub-switching leg 9a includes two semiconductor switches T1 and T2 connected in series, and the sub-switching leg 9b includes two semiconductor switches T3 and T4 connected in series. The semiconductor switches T1, T2, T3, and T4 have small capacitances, and therefore have high switching frequencies. Therefore, the power conversion device 1 has a high switching frequency and can switch at frequencies as high as 10 kHz. Because the power conversion device 1 has a high switching frequency, it can be used to drive a low-inductance motor.

[0041] Since the gate signals S1 and S3 are substantially the same signal, and the gate signals S2 and S4 are substantially the same signal, the sub-switching legs 9a and 9b theoretically operate at the same timing. However, in reality, the operation timings of the sub-switching legs 9a and 9b are shifted due to unavoidable variations in the characteristics of the semiconductor switches T1, T2, T3, and T4. During the period when this shift occurs, a cross current (or circulating current) may occur between the sub-switching legs 9a and 9b. According to the first embodiment, the inductors 8a and 8b are provided, thereby suppressing the cross current.

[0042] Generally, the faster a semiconductor switch operates, the smaller the time lag between their operation timings. Since the semiconductor switches T1, T2, T3, and T4 have small capacitance and high switching frequencies, the lag between their operation timings is also small. Therefore, the inductances of inductors 8a and 8b can be kept low, and as described above, the inductance of each of inductors 8a and 8b can be reduced to approximately 1.5% of the percent impedance of power conversion device 1.

[0043] 2. Second embodiment The second embodiment is based on and applied to the first embodiment. The second embodiment relates to details of the gate driver.

[0044] FIG. 4 shows an example of the configuration of the gate driver of the power conversion device according to the second embodiment. As shown in FIG. 4, the gate driver 7a includes sub-gate drivers 16a and 16b. The sub-gate drivers 16a and 16b have the same configuration and substantially the same characteristics. The sub-gate driver 16a receives a control signal S5 and generates a gate signal S1 based on the control signal S5. The sub-gate driver 16b receives a control signal S5 and generates a gate signal S2 based on the control signal S5.

[0045] The gate driver 7b includes sub-gate drivers 17a and 17b. The sub-gate drivers 17a and 17b have the same configuration and substantially the same characteristics. The sub-gate driver 17a receives a control signal S6 and generates a gate signal S2 based on the control signal S6. The sub-gate driver 17b receives a control signal S6 and generates a gate signal S4 based on the control signal S6.

[0046] FIG. 5 shows an example of the circuit configuration of a gate driver of a power conversion device according to the second embodiment. FIG. 5 illustrates a gate driver 7a. As shown in FIG. 5, a sub-gate driver 16a includes an npn bipolar transistor TN1, a pnp bipolar transistor TP1, and a resistor R1. The transistor TN1 receives a power supply voltage at its collector. The transistor TN1 is connected to one end of the resistor R1 at its emitter. The transistor TN1 receives a control signal S5 at its base.

[0047] The transistor TP1 has a collector connected to one end of the resistor R1, an emitter connected to the source of the semiconductor switch T1 in the arm 11a, and a base connected to a control signal S5.

[0048] The other end of the resistor R1 is connected to the gate of the semiconductor switch T1 of the arm 11a.

[0049] Since the transistor TP1 is connected to the source of the semiconductor switch T1 of the arm 11a, the sub-gate driver 16a operates using the potential of the source of the semiconductor switch T1 as the ground potential.

[0050] The sub-gate driver 16b includes an npn bipolar transistor TN2, a pnp bipolar transistor TP2, and a resistor R2. The transistor TN2 receives a power supply voltage at its collector. The transistor TN2 is connected to one end of the resistor R2 at its emitter. The transistor TN2 receives a control signal S5 at its base.

[0051] The transistor TP2 has a collector connected to one end of the resistor R2, an emitter connected to the source of the semiconductor switch T3 in the arm 11b, and a base connected to a control signal S5.

[0052] The other end of the resistor R2 is connected to the gate of the semiconductor switch T3 of the arm 11b.

[0053] Since the transistor TP2 is connected to the source of the semiconductor switch T3 of the arm 11b, the sub-gate driver 16b operates using the potential of the source of the semiconductor switch T3 as the ground potential.

[0054] The sub-gate driver 17a has the same circuit configuration and substantially the same characteristics as the sub-gate driver 16a, and the sub-gate driver 17b has the same circuit configuration and substantially the same characteristics as the sub-gate driver 16b. However, the sub-gate drivers 17a and 17b differ from the sub-gate drivers 16a and 16b in the following respects: The gate terminals of transistors TN1, TP1, TN2, and TP2 receive a control signal S6. The emitter of transistor TP1 is connected to the source terminal of the semiconductor switch T2 in the arm 12a. The emitter of transistor TP2 is connected to the source terminal of the semiconductor switch T4 in the arm 12b. The other end of resistor R1 is connected to the gate terminal of the semiconductor switch T2 in the arm 12a. The other end of resistor R2 is connected to the gate terminal of the semiconductor switch T4 in the arm 12b.

[0055] According to the second embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, according to the second embodiment, transistors belonging to different sub-switching legs are driven by different sub-gate drivers. That is, the semiconductor switch T1 is driven by the sub-gate driver 16a, and the semiconductor switch T3 is driven by the sub-gate driver 16b. The semiconductor switch T2 is driven by the sub-gate driver 17a, and the semiconductor switch T4 is driven by the sub-gate driver 17b. Due to the provision of the inductors 8a and 8b, the negative potential of the arm 11a (i.e., the potential of the source of the semiconductor switch T1) differs from the negative potential of the arm 11b (i.e., the potential of the source of the semiconductor switch T3). Therefore, by providing the sub-gate driver 16a that drives the semiconductor switch T1 using the source of the semiconductor switch T1 as the ground potential and the sub-gate driver 16b that drives the semiconductor switch T3 using the source of the semiconductor switch T3 as the ground potential, the two semiconductor switches T1 and T3 can be appropriately driven by a common control signal S5.

[0056] 3. Third embodiment Fig. 6 shows the configuration of a portion of the power conversion phase of the power conversion device according to the third embodiment, showing one power conversion phase 5.

[0057] As shown in FIG. 6, the power conversion phase 5 includes signal isolators 21a, 21b, 22a, and 22b, based on one switching leg 6 including two sub-switching legs 9a and 9b. Each of the signal isolators 21a, 21b, 22a, and 22b has an input terminal and an output terminal that are isolated from each other, and is a device that outputs a signal received at the input terminal from the output terminal. Examples of the signal isolators 21a, 21b, 22a, and 22b include a combination of a media converter and optical fiber, a combination of a photocoupler and a power supply voltage, and a pulse transformer. Examples of the signal isolators 21a, 21b, 22a, and 22b include a combination of a media converter and optical fiber, a combination of a photocoupler and a power supply voltage, and a pulse transformer.

[0058] The signal isolator 21a receives the control signal S5 at an input terminal and provides the control signal S5 to the sub-gate driver 16a at an output terminal.

[0059] The signal isolator 21b receives the control signal S5 at an input terminal and provides the control signal S5 to the sub-gate driver 16b at an output terminal.

[0060] The signal isolator 22a receives the control signal S6 at an input terminal and provides the control signal S5 to the sub-gate driver 17a at an output terminal.

[0061] The signal isolator 22b receives the control signal S6 at an input terminal and provides the control signal S5 to the sub-gate driver 16b at an output terminal.

[0062] According to the third embodiment, the same effects as those of the first embodiment can be obtained.

[0063] 4. Fourth embodiment A fourth embodiment relates to the use of a neutral point clamped (NPC) three-level power converter.

[0064] Fig. 7 shows an example of the configuration of the sub-switching legs of the power conversion device according to the fourth embodiment. Fig. 7 shows only the sub-switching legs 9a and 9b of one power conversion phase 5.

[0065] 7, each of the sub-switching legs 9a and 9b of the fourth embodiment includes capacitors C1 and C2 and semiconductor switches T11, T12, T13, T14, T15, and T16. In one example, the semiconductor switches T11, T12, T13, T14, T15, and T16 are all n-type MOSFETs.

[0066] The capacitor C1 is connected between the positive side DC terminal 13 and a neutral point (neutral node) CP. The capacitor C2 is connected between the neutral point CP and the negative side DC terminal .

[0067] The semiconductor switch T11 has a source terminal connected to the node N11 and a drain terminal connected to the positive DC terminal 13. The semiconductor switch T11 receives a gate signal from the gate driver 7 at its gate terminal.

[0068] The diode D11 has an anode connected to the node N11 and a cathode connected to the positive DC terminal 13.

[0069] The semiconductor switch T12 has a source terminal connected to the neutral point CP, a drain terminal connected to the node N11, and a gate terminal receiving a gate signal from the gate driver 7.

[0070] The diode D12 has an anode connected to the neutral point CP and a cathode connected to the node N11.

[0071] The semiconductor switch T13 has a source terminal connected to the node N12, a drain terminal connected to the neutral point CP, and a gate terminal receiving a gate signal from the gate driver 7.

[0072] The diode D13 has an anode connected to the node N12 and a cathode connected to the neutral point CP.

[0073] The semiconductor switch T14 has a source terminal connected to the negative DC terminal 14. The semiconductor switch T14 has a drain terminal connected to the node N12. The semiconductor switch T14 receives a gate signal from the gate driver 7 at its gate terminal.

[0074] The diode D14 has an anode connected to the negative DC terminal 14. The diode D14 has a cathode connected to the node N12.

[0075] The semiconductor switch T15 has a source terminal connected to an output node N15. The semiconductor switch T15 has a drain terminal connected to a node N11. The semiconductor switch T15 receives a gate signal from the gate driver 7 at its gate terminal. The output node N15 is connected to one end of the inductor 8a or 8b.

[0076] The diode D15 has an anode connected to the output node N15 and a cathode connected to the node N11.

[0077] The semiconductor switch T16 has a source terminal connected to the node N12, a drain terminal connected to the output node N15, and a gate terminal receiving a gate signal from the gate driver 7.

[0078] The diode D16 has an anode connected to the node N12 and a cathode connected to the output node N15.

[0079] Fig. 8 shows connections of some components of a power conversion device according to the fourth embodiment. As shown in Fig. 8, the neutral points CP of the sub-switching legs 9a or 9b are connected to each other across different power conversion phases 5. That is, the neutral point CP of the sub-switching leg 9a of the switching leg 6_1 of the power conversion phase 5_1, the neutral point CP of the sub-switching leg 9a of the switching leg 6_2 of the power conversion phase 5_2, and the neutral point CP of the sub-switching leg 9a of the switching leg 6_3 of the power conversion phase 5_3 are connected to each other. Also, the neutral point CP of the sub-switching leg 9b of the switching leg 6_1 of the power conversion phase 5_1, the neutral point CP of the sub-switching leg 9b of the switching leg 6_2 of the power conversion phase 5_2, and the neutral point CP of the sub-switching leg 9b of the switching leg 6_3 of the power conversion phase 5_3 are connected to each other.

[0080] On the other hand, in each power conversion phase 5, the neutral point CP of the sub-switching leg 9a and the neutral point CP of the sub-switching leg 9b do not need to be connected for operation, so by not making a connection, the circuit configuration can be simplified.

[0081] According to the fourth embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, according to the fourth embodiment, the sub-switching legs 9a and 9b are configured by an NPC three-level power converter. Therefore, each switching leg 6 can output an intermediate potential between the positive power supply potential and the negative power supply potential at the neutral point CP. Therefore, when there is a mismatch in the switching timing between the switching legs 6, the magnitude of the voltage applied to the inductors 8a and 8b is at most the intermediate potential. Therefore, the magnitude of the cross current generated when there is a mismatch in the switching timing between the switching legs 6 is smaller than when only two power supply potentials, positive and negative, are used.

[0082] Furthermore, conventional NPC three-level power converters include clamping diodes between the neutral point CP and node N11 of the sub-switching legs 9a and 9b in FIG. 7, and between the neutral point CP and node N12. In this clamping method, the wiring between the capacitors C1 and C2 is long because the switches are located far from the capacitors C1 and C2. This means that the semiconductor switches T15 and T16, which have large parasitic inductances, must be switched at a high frequency. This increases losses in the power converter in order to suppress surge voltages that frequently occur when switching at high frequencies. This prevents the power converter from increasing its switching frequency.

[0083] According to the fourth embodiment, only the semiconductor switches T11, T12, T13, and T14 switch at a high frequency in the sub-switching legs 9a and 9b. The semiconductor switches T15 and T16 switch only at the fundamental frequency of the output of the power conversion phase 5 and therefore do not affect the switching frequency of the power conversion phase 5. Furthermore, the semiconductor switches T11, T12, T13, and T14 are located close to the capacitors C1 and C2 and therefore have low parasitic inductance. Therefore, the switching frequency of the semiconductor switches T11, T12, T13, and T14 can be increased without being restricted by the semiconductor switches T15 and T16.

[0084] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0085] 1...power conversion device, 2...load, 3...control circuit, 5...power conversion phase, 6...switching leg, 7, 7a, 7b...gate driver, 8a, 8b...inductor, 9a, 9b...sub-switching leg, 11a, 11b, 12a, 12b...arm, 13...positive side DC terminal, 14...negative side DC terminal, T1, T2, T3, T4...semiconductor switch, 16a, 16b, 17a, 17b...sub-gate driver

Claims

1. A power converter includes a plurality of power conversion phases that output AC powers of different phases at output terminals, The output terminals of the plurality of power conversion phases are connected to each other, Each of the plurality of power conversion phases includes a first sub switching leg and a second sub switching leg connected in parallel between a positive side DC terminal and a negative side DC terminal, and a first inductor and a second inductor, each of the first sub-switching leg and the second sub-switching leg outputs AC power at an output node; the first inductor is connected between the output node of the first sub-switching leg and the output terminal; the second inductor is connected between the output node of the second sub-switching leg and the output terminal. Power conversion equipment.

2. The first sub switching leg includes: a first semiconductor switch connected between the positive DC terminal and the output node of the first sub-switching leg and operated based on a first gate signal; a second semiconductor switch connected between the output node of the first sub switching leg and the negative DC terminal and operated based on a second gate signal; Including, The second sub switching leg includes: a third semiconductor switch connected between the positive DC terminal and the output node of the second sub switching leg and operated based on a third gate signal; a fourth semiconductor switch connected between the output node of the second sub switching leg and the negative DC terminal and operated based on a fourth gate signal; Including, The power conversion device according to claim 1 .

3. The first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are each included in a single semiconductor chip separate from one another. The power conversion device according to claim 2 .

4. The inductance of the first inductor and the inductance of the second inductor are 1.5% of a percent impedance of the power conversion device. The power conversion device according to claim 1 .

5. Each of the plurality of power conversion phases is a first driver that receives a first control signal and outputs the first gate signal based on the first control signal; a second driver that receives a second control signal and outputs the second gate signal based on the second control signal; a third driver that receives the first control signal and outputs the third gate signal based on the first control signal; a fourth driver that receives the second control signal and outputs the fourth gate signal based on the second control signal; Further comprising: The power conversion device according to claim 2 .

6. Each of the plurality of power conversion phases is a first signal isolator that receives the first control signal at an input terminal and outputs the first control signal at an output terminal that is electrically isolated from the input terminal; a second signal isolator that receives the second control signal at an input terminal and outputs the second control signal at an output terminal that is electrically isolated from the input terminal; a third signal isolator that receives the first control signal at an input terminal and outputs the first control signal at an output terminal that is electrically isolated from the input terminal; a fourth signal isolator receiving the second control signal at an input terminal and outputting the second control signal at an output terminal electrically isolated from the input terminal; Including, The power conversion device according to claim 5 .

7. Each of the first sub switching leg and the second sub switching leg comprises: A first capacitor connected between the positive DC terminal and a neutral point; a second capacitor connected between the neutral point and the negative DC terminal; a first transistor connected between the positive DC terminal and a first node; a second transistor connected between the first node and the neutral point; a third transistor connected between the neutral point and a second node; a fourth transistor connected between the second node and the negative DC terminal; a fifth transistor connected between the first node and the output node; a sixth transistor connected between the output node and the second node; The power converter of claim 1 .

8. each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor is a MOSFET; The power converter according to claim 7.

9. the neutral points of the first sub-switching legs of each of the plurality of power conversion phases are connected to each other; the neutral points of the second sub-switching legs of each of the plurality of power conversion phases are connected to each other; In each of the plurality of power conversion phases, the neutral point of the first sub-switching leg and the neutral point of the second sub-switching leg are not connected to each other. The power converter according to claim 7.

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