Power conversion device

Abstract

To suppress imbalance in current flowing through a plurality of switching elements resulting from difference of wiring inductance.SOLUTION: A power conversion device includes: a plurality of switching elements arranged along low-potential wiring; and a drive circuit for supplying a gate voltage to the plurality of switching element simultaneously through gate wiring having a predetermined gate resistance. Wiring inductance arises on the low-potential wiring to which the plurality of switching elements is connected, and the gate resistance of the gate wiring connected to a switching element is set to a larger resistance value for a switching element having a smaller wiring inductance to a merge point to which respective currents outputted from the plurality of switching elements to the low-potential wiring join together.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a power conversion device. [Background technology]

[0002] A power conversion device converts DC power into AC power by switching an inverter circuit configured with upper and lower arms. In some cases, each phase of the upper and lower arms of the inverter circuit is used by connecting multiple switching elements in parallel. In this case, if the switching elements are connected in parallel along the wiring, the wiring inductance generated in the wiring to each switching element will be different, and the difference in wiring inductance will cause a difference in switching speed, resulting in an imbalance in the current flowing through each switching element.

[0003] Patent Document 1 discloses a power conversion device that includes a gate drive circuit that drives each semiconductor module on / off, and a first gate wiring that is provided for each semiconductor module and connects the semiconductor module to the gate drive circuit or another semiconductor module for use during off operation, and in which semiconductor modules with lower gate threshold voltages are connected to the gate drive circuit or another semiconductor module by a first gate wiring with lower impedance so that the gate current values ​​of each semiconductor module during off operation are the same. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-156304 A Summary of the Invention [Problem to be solved by the invention]

[0005] The technique described in Patent Document 1 cannot suppress imbalances in currents flowing through a plurality of switching elements that are caused by differences in wiring inductance. [Means for solving the problem]

[0006] The power conversion device vehicle according to the present invention comprises a plurality of switching elements arranged along a low-potential wiring, and a drive circuit which simultaneously supplies a gate voltage to each of the plurality of switching elements via a gate wiring having a predetermined gate resistance, and the wiring inductance generated in the low-potential wiring to which the plurality of switching elements are connected is such that the smaller the wiring inductance of a switching element to a junction where the currents output from each of the plurality of switching elements to the low-potential wiring join, the larger the resistance value of the gate resistance of the gate wiring connected to that switching element is set. Effect of the Invention

[0007] According to the present invention, it is possible to suppress imbalance in currents flowing through a plurality of switching elements caused by differences in wiring inductance. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit configuration diagram of a power conversion device according to a first embodiment. [Diagram 2] 1A and 1B are top views of a first and second layer of a multilayer wiring board in which an inverter circuit of a power conversion device according to a first embodiment is arranged. [Diagram 3] 1A and 1B are top views of a first and second layer of a multilayer wiring board in which an inverter circuit of a power conversion device according to a first embodiment is arranged. [Figure 4] 1(A) to 1(E) are diagrams illustrating switching elements of a power conversion device according to a first embodiment. [Diagram 5] FIG. 11 is a circuit configuration diagram of a power conversion device according to a second embodiment. [Figure 6] 13 is a top view of a first layer of a multilayer wiring board on which an inverter circuit of a power conversion device according to a second embodiment is arranged. FIG. [Figure 7] FIG. 11 is a circuit configuration diagram of a power conversion device according to a third embodiment. [Figure 8] 13 is a top view of a first layer of a multilayer wiring board on which an inverter circuit of a power conversion device according to a third embodiment is arranged. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following description and drawings are examples for explaining the present invention, and appropriate omissions and simplifications have been made for clarity of explanation. The present invention can be implemented in various other forms. Unless otherwise specified, each component may be singular or plural.

[0010] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings.

[0011] [First embodiment] 1 is a circuit configuration diagram of a power conversion device 100 according to a first embodiment of the present invention. The power conversion device 100 includes an inverter circuit 200 and a drive circuit 300.

[0012] The inverter circuit 200 drives, for example, an electric motor mounted on an electric vehicle. The electric motor has, for example, a three-phase coil. In this case, the inverter circuit 200 includes upper and lower arms for three phases for applying a predetermined current pattern to the three-phase coil. Each phase of the upper and lower arms of the inverter circuit 200 is configured by connecting four switching elements in parallel. FIG. 1 shows the upper and lower arms for one phase. That is, the upper arm is configured by connecting four switching elements P1, P2, P3, and P4 in parallel, and the lower arm is configured by connecting four switching elements N1, N2, N3, and N4 in parallel. In the following, an example will be described in which four switching elements are connected in parallel, but the present invention can be similarly applied to a case in which a plurality of switching elements are connected in parallel, not limited to four.

[0013] The switching elements P1, P2, P3, and P4 of the upper arm and the switching elements N1, N2, N3, and N4 of the lower arm are power semiconductor elements such as IGBT, Si-MOSFET, and GaN-HEMT. Note that Fig. 1 shows an example in which MOSFETs are used for the switching elements P1, P2, P3, and P4 and the switching elements N1, N2, N3, and N4. When the switching elements P1, P2, P3, P4, N1, N2, N3, and N4 are MOSFETs, a freewheeling diode (freewheeling diode) is connected in inverse parallel.

[0014] The drain terminals of the switching elements P1, P2, P3, and P4 of the upper arm are connected to a high-potential wiring PL. The source terminals of the switching elements P1, P2, P3, and P4 of the upper arm are connected to an AC wiring AL. The drain terminals of the switching elements N1, N2, N3, and N4 of the lower arm are connected to the AC wiring AL. The source terminals of the switching elements N1, N2, N3, and N4 of the lower arm are connected to a low-potential wiring NL. Note that the AC wiring AL may be referred to as a high-potential wiring when focusing on the switching elements N1, N2, N3, and N4 of the lower arm. Furthermore, the AC wiring AL may be referred to as a low-potential wiring when focusing on the switching elements P1, P2, P3, and P4 of the upper arm.

[0015] The high potential wiring PL is connected to the positive electrode of a DC power supply (not shown) via a high potential terminal P, and the low potential wiring NL is connected to the negative electrode of the DC power supply via a low potential terminal N. The AC wiring AL is connected to a load via an AC terminal AC. The load is, for example, one phase of a winding of an electric motor.

[0016] A gate wiring GLP is connected to the gate terminals of the upper arm switching elements P1, P2, P3, and P4 by the drive circuit 300. The source terminals of the switching elements P1, P2, P3, and P4 for applying a gate voltage between the gate and source are connected to an upper arm source wiring PSL.

[0017] The drive circuit 300 simultaneously supplies a gate voltage between the upper arm source line PSL and the gate line GLP to turn on the switching elements P1, P2, P3, and P4, and stops the supply of the gate voltage to turn off the switching elements P1, P2, P3, and P4.

[0018] A gate wiring GLN is connected to the gate terminals of the lower arm switching elements N1, N2, N3, and N4 by the drive circuit 300. The source terminals of the switching elements N1, N2, N3, and N4 for applying a gate voltage between the gate and source are connected to the lower arm source wiring NSL.

[0019] The drive circuit 300 simultaneously supplies a gate voltage between the lower arm source line NSL and the gate line GLN to turn on the switching elements N1, N2, N3, and N4, and stops the supply of the gate voltage to turn off the switching elements N1, N2, N3, and N4.

[0020] The drive circuit 300 controls the on / off of the upper arm switching elements P1, P2, P3, and P4 and the lower arm switching elements N1, N2, N3, and N4 based on a drive command input from a control circuit (not shown). As a result, the inverter circuit 200 converts DC power supplied from a DC power source into AC power and outputs the converted AC power to a load such as an electric motor.

[0021] As shown in Fig. 1, a plurality of switching elements are connected in parallel for one phase of the upper and lower arms of the inverter circuit 200. In this case, as will be described later in detail with reference to Fig. 2, the switching elements are connected in parallel and arranged along the low-potential wiring NL, so that the wiring inductances from the points where the switching elements are connected to the low-potential wiring NL to the junction point A where the currents output from the switching elements to the low-potential wiring NL join are different. Specifically, a wiring inductance L2 is generated from the connection point between the switching element N1 and the low-potential wiring NL to the connection point between the switching element N2 and the low-potential wiring NL. A wiring inductance L3 is generated from the connection point between the switching element N2 and the low-potential wiring NL to the connection point between the switching element N3 and the low-potential wiring NL. A wiring inductance L4 is generated from the connection point between the switching element N3 and the low-potential wiring NL to the connection point between the switching element N4 and the low-potential wiring NL.

[0022] If this embodiment is not applied, the switching speed of the switching elements having small wiring inductances L2, L3, and L4 when they are turned on will be faster, and the drain-source current of the switching elements when they are turned on will be larger. For example, when comparing the drain-source currents of switching element N1 and switching element N4, since switching element N4 has wiring inductance L2+L3+L4, the drain-source current of switching element N1 will be larger than the drain-source current of switching element N4.

[0023] In this embodiment, the smaller the wiring inductance L2, L3, and L4 to the joining point A where the currents output from the multiple switching elements N1 to N4 to the low potential wiring NL join, the larger the gate resistance of the gate wiring GL connected to the switching element is set to. Specifically, as shown in FIG. 1, the resistance values ​​of the gate resistors R1 to R4 of the switching elements N1 to N4 are set to R1>R2>R3>R4. As a result, the difference in switching speed caused by the difference in the wiring inductances L2, L3, and L4 is adjusted by the gate resistors, thereby suppressing the imbalance of the currents flowing through the switching elements. If the imbalance of the currents can be suppressed, the variation in the losses of the switching elements can be suppressed, and the output density of the power conversion device 100 can be improved.

[0024] 2(A), 2(B), 3(A), and 3(B) are top views of a multilayer wiring board 400 on which an inverter circuit 200 of a power conversion device 100 according to this embodiment is arranged, with Fig. 2(A) showing the first layer, Fig. 2(B) showing the second layer, Fig. 3(A) showing the third layer, and Fig. 3(B) showing the fourth layer. Note that, although a four-layer multilayer wiring board 400 will be described as an example, any number of layers may be used, not limited to four layers, and hereinafter, will be referred to as wiring board 400.

[0025] In addition, while Figures 2(A), 2(B), 3(A), and 3(B) illustrate an example in which one phase of the inverter circuit 200 is arranged on the wiring board 400, three phases may be arranged on one wiring board 400, and the present invention can be similarly applied in this case as well.

[0026] 2A, on the first layer of the wiring board 400, four switching elements P1 to P4 of the upper arm are arranged in a straight line, and in the illustrated example, are arranged in a vertical row from top to bottom. Four switching elements N1 to N4 of the lower arm are arranged in a vertical row from top to bottom in parallel with the arrangement of the switching elements P1 to P of the upper arm. On both sides of the arrangement of the switching elements P1 to P4, gate wiring GLP of the switching elements P1, P2, P3, P4 and high potential wiring PL are arranged extending on the wiring board 400. On both sides of the arrangement of the switching elements N1 to N4, low potential wiring NL and gate wiring GLN of the switching elements N1 to N4 are arranged extending on the wiring board 400.

[0027] The low-potential wiring NL is arranged extending along the row of the switching elements N1 to N4, so that the low-potential wiring NL between each of the switching elements N1 to N4 generates wiring inductances L2, L3, and L4, respectively, when each of the switching elements N1 to N4 is turned on. Note that in Fig. 2(A), the wiring inductances L2, L3, and L4 are illustrated as coils, but they are not actually coils, and are merely pseudo-illustrations to make it easier to understand the wiring inductance generated by current flow.

[0028] The gates of the switching elements N1 to N4 are connected to a gate line GLN via gate resistors R1 to R4, respectively, and the gates of the switching elements P1 to P4 are connected to a gate line GLP.

[0029] As shown in FIG. 2(A), the high potential wiring PL is connected to a high potential terminal P in the first layer of the wiring board 400. The low potential wiring NL is connected to a low potential terminal N in the second layer of the wiring board 400 via a through hole as shown in FIG. 2(B). The source terminals of the switching elements P1, P2, P3, and P4 in the upper arm are connected to the AC wiring AL via a through hole as shown in FIG. 3(A). The drain terminals of the switching elements N1, N2, N3, and N4 in the lower arm are connected to the AC wiring AL shown in FIG. 3(A) via a through hole. The AC wiring AL is connected to the AC terminal AC in the first layer of the wiring board 400 via a through hole as shown in FIG. 2(A).

[0030] The source terminals of the switching elements P1, P2, P3, and P4 for applying a gate voltage between the gate and source are connected via through holes to the upper arm source wiring PSL in the fourth layer of the wiring board 400, as shown in Fig. 3(B). The source terminals of the switching elements N1, N2, N3, and N4 for applying a gate voltage between the gate and source are connected via through holes to the lower arm source wiring NSL in the fourth layer of the wiring board 400, as shown in Fig. 3(B).

[0031] 4(A), 4(B), 4(C), 4(D) and 4(E) are diagrams showing the switching element P1 of the power conversion device 100 according to this embodiment. Figure 4(A) is a top view of the switching element P1, Figure 4(B) is a top view of the low potential electrode plate KL inside the switching element P1, Figure 4(C) is a top view of the high potential electrode plate KH inside the switching element P1, Figure 4(D) is a cross-sectional view showing the low potential electrode plate KL inside the switching element P1, and Figure 4(E) is a cross-sectional view showing the high potential electrode plate KH inside the switching element P1.

[0032] The switching element P1 will be described as an example, but the same applies to the switching elements P2, P3, and P4. The same applies to the switching elements N1, N2, N3, and N4, but the diagrams arranged in Figure 2 are diagrams obtained by rotating the diagrams shown in Figures 4(A), 4(B), and 4(C) by 180 degrees and are diagrams obtained by flipping the diagrams shown in Figures 4(D) and 4(E) horizontally.

[0033] As shown in FIG. 4(A), a drain terminal D1 having a high potential and a source terminal S1 having a low potential protrude from one side of a switching element P1 sealed with a molded resin, and a gate terminal G1 and a source terminal S2 for applying a gate voltage protrude from the other side of the switching element P1.

[0034] Fig. 4(B) is a top view of the switching element P1 with the molding resin and other layers above the low potential electrode plate KL removed, and the source terminal S1 is derived from the low potential electrode plate KL. Fig. 4(D) is a cross-sectional view taken along the line A-A' in this figure, and Fig. 4(E) is a cross-sectional view taken along the line B-B'.

[0035] 4(C) is a top view of the low potential side of element Q, with the upper layer members including the low potential electrode plate KL of switching element P1 removed. The source terminal S2 is connected to the source electrode of element Q on the substrate via a bonding wire. The gate terminal G1 is connected to the gate electrode of element Q on the substrate via a bonding wire. In addition, the drain terminal D1 is led out from the high potential electrode plate KH.

[0036] As shown in Fig. 4(D), a low potential electrode plate KL and a high potential electrode plate KH are soldered to both sides of element Q. The low potential electrode plate KL is connected to the source terminal S1. The gate electrode of element Q is connected to the gate terminal G1 via a bonding wire. 4(E), the high potential electrode plate KH is connected to the drain terminal D1, and the source electrode of the element Q is connected to the source terminal S2 via a bonding wire.

[0037] According to the first embodiment, it is possible to suppress imbalance in currents flowing through multiple switching elements caused by differences in wiring inductances L2, L3, and L4, eliminate variations in losses among the switching elements, and improve the output density of the power conversion device 100.

[0038] The wiring inductances L2, L3, and L4 are not limited to the case where the low-potential wiring NL is arranged on the wiring board 400, but also occur, for example, when the wiring board 400 is not used and a lead wire is used instead of the low-potential wiring NL. Even in such a case, the embodiment can be similarly applied.

[0039] [Second embodiment] Fig. 5 is a circuit diagram of a power conversion device 100 according to a second embodiment of the present invention. The connection of the gate resistors R1 to R4 is different from that of the first embodiment shown in Fig. 1. The other configuration is the same as in Fig. 1, and the same parts are denoted by the same reference numerals and will be described briefly.

[0040] In this embodiment, the gate resistors R1 to R4 are connected in series to the gate wiring GLN. Specifically, as shown in FIG. 5, a gate resistor R1 is provided on the gate wiring GLN between the switching element N1 and the switching element N2. A gate resistor R2 is provided on the gate wiring GLN between the switching element N2 and the switching element N3. A gate resistor R3 is provided on the gate wiring GLN between the switching element N3 and the switching element N4. A gate resistor R4 is provided on the gate wiring GLN between the switching element N4 and the drive circuit 300.

[0041] The smaller the wiring inductance L2, L3, L4 to the junction A where the currents output from the multiple switching elements N1 to N4 to the low potential wiring NL join, the larger the gate resistance of the gate wiring GL connected to that switching element is set to. Specifically, the resistance values ​​of the gate resistance applied to each switching element N1 to N4 are set as follows: R1+R2+R3+R4>R2+R3+R4>R3+R4>R4. This allows the gate resistance to adjust the difference in switching speed caused by the difference in wiring inductance L2, L3, L4, thereby suppressing imbalance in current flowing through the switching elements.

[0042] 6 is a top view of a multilayer wiring board 400 on which the inverter circuit 200 of the power conversion device 100 according to this embodiment is arranged, showing the first layer. The second to fourth layers are the same as those shown in FIGS. 2(B), 3(A), and 3(B) in the first embodiment, and therefore are not shown. As in the first embodiment, a multilayer wiring board 400 having any number of layers, not limited to four layers, may be used, and will be referred to as wiring board 400 below. Alternatively, the wiring board 400 may not be used, and a lead wire may be used instead of the low-potential wiring NL. This embodiment differs from the first embodiment shown in Fig. 2(A) in the arrangement of the gate resistors R1 to R4. The other configurations are the same as those in Fig. 2(A), and the same parts are denoted by the same reference numerals and will be described briefly.

[0043] As described with reference to Fig. 5, in this embodiment, the gate resistors R1 to R4 are connected in series to the gate wiring GLN. Specifically, as shown in Fig. 6, a gate resistor R1 is provided on the gate wiring GLN between the switching element N1 and the switching element N2. A gate resistor R2 is provided on the gate wiring GLN between the switching element N2 and the switching element N3. A gate resistor R3 is provided on the gate wiring GLN between the switching element N3 and the switching element N4. A gate resistor R4 is provided on the gate wiring GLN between the switching element N4 and the drive circuit 300.

[0044] 2A, in this embodiment, gate resistors R1 to R4 are arranged on the gate wiring GLN. Therefore, the distance between the arrangement of the switching elements N1 to N4 and the gate wiring GLN can be narrowed, and the occupied area can be reduced, making it possible to miniaturize the power conversion device 100. In particular, when three phases are arranged on one wiring board 400, the occupied area can be reduced.

[0045] According to the second embodiment, it is possible to suppress the imbalance of the currents flowing through the multiple switching elements caused by the difference in the wiring inductances L2, L3, and L4, and to eliminate the variation in the losses of the switching elements, thereby improving the output density of the power conversion device 100. Furthermore, it is possible to reduce the size of the power conversion device 100.

[0046] [Third embodiment] Fig. 7 is a circuit diagram of a power conversion device 100 according to a third embodiment of the present invention. Compared with the second embodiment shown in Fig. 5, this embodiment is different in that it includes a bypass wiring NdL having diodes d1, d2, and d3 that bypass the gate resistors R1, R1, and R3. The other configurations are the same as those in Fig. 5, and the same parts are denoted by the same reference numerals and will be described briefly.

[0047] 7, in the bypass wiring NdL that bypasses the gate resistance R1, the anode of the diode d1 is connected to the gate side of the switching element N1. In the bypass wiring NdL that bypasses the gate resistance R2, the anode of the diode d2 is connected to the gate side of the switching element N2. In the bypass wiring NdL that bypasses the gate resistance R3, the anode of the diode d3 is connected to the gate side of the switching element N3. Note that the bypass wiring NdL is not limited to the one that includes all of the diodes d1, d2, and d3 that bypass all of the gate resistances R1, R1, and R3, but may include a bypass wiring NdL having diodes that bypass some of the gate resistances R1, R1, and R3 depending on the characteristics of the switching elements, the gate wiring GLN, and the like.

[0048] The bypass wiring NdL changes the current path so that the switching speed is not adjusted when the switching elements N1 to N4 are turned off. That is, when the switching elements N1 to N4 are turned on, the gate wiring GLN is used as the current path, and when the switching elements N1 to N4 are turned off, the bypass wiring NdL is used as the current path. This makes it possible to eliminate the influence of the gate resistances R1 to R4 when the switching elements N1 to N4 are turned off.

[0049] 8 is a top view of a multilayer wiring board 400 on which an inverter circuit 200 of a power conversion device 100 according to this embodiment is arranged, showing the first layer. The second to fourth layers are the same as those in FIG. 6 shown in the second embodiment, and therefore are not shown. As in the second embodiment, a multilayer wiring board 400 having any number of layers, not limited to four layers, may be used, and will be referred to as wiring board 400 below. Alternatively, the wiring board 400 may not be used, and a lead wire may be used instead of the low-potential wiring NL. This embodiment differs from the second embodiment shown in Fig. 6 in that a bypass wiring NdL is added to the arrangement. The other configurations are the same as those in Fig. 6, and the same parts are denoted by the same reference numerals and their description will be simplified.

[0050] As described with reference to Fig. 7, this embodiment includes a bypass wiring NdL having diodes d1, d2, and d3 that bypass the gate resistors R1, R1, and R3. Specifically, as shown in Fig. 8, a connection point between the switching element N1 and the gate resistor R1 is connected to the bypass wiring NdL via a diode d1. A connection point between the switching element N2 and the gate resistor R2 is connected to the bypass wiring NdL via a diode d2. A connection point between the switching element N3 and the gate resistor R3 is connected to the bypass wiring NdL via a diode d3.

[0051] According to the third embodiment, it is possible to suppress the imbalance of the currents flowing through the multiple switching elements caused by the difference in the wiring inductances L2, L3, and L4, eliminate the variation in the losses of the switching elements, and improve the output density of the power conversion device 100. Furthermore, it is possible to eliminate the influence of the multiple gate resistors when the multiple switching elements are turned off.

[0052] According to the embodiment described above, the following advantageous effects can be obtained. (1) The power conversion device 100 includes a plurality of switching elements N1, N2, N3, and N4 arranged along a low-potential wiring NL, and a drive circuit 300 that simultaneously supplies gate voltages to each of the plurality of switching elements N1, N2, N3, and N4 via a gate wiring GLN having predetermined gate resistances R1, R2, R3, and R4, and the wiring inductances L2, L3, and L4 generated in the low-potential wiring NL to which the plurality of switching elements N1, N2, N3, and N4 are connected are smaller in the wiring inductances L2, L3, and L4 to a joining point A where the currents output from the plurality of switching elements N1, N2, N3, and N4 to the low-potential wiring NL join together, and the gate resistances R1, R2, R3, and R4 of the gate wiring GLN connected to the switching elements N1, N2, N3, and N4 are set to larger resistance values. This makes it possible to suppress imbalance of currents flowing through the plurality of switching elements caused by differences in wiring inductance.

[0053] The present invention is not limited to the above-described embodiment, and other embodiments that are conceivable within the scope of the technical concept of the present invention are also included in the scope of the present invention as long as they do not impair the characteristics of the present invention. Also, the above-described embodiments may be combined to form a configuration. [Explanation of symbols]

[0054] 100...power conversion device, 200...inverter circuit, 300...drive circuit, 400...wiring board, PL...high potential wiring, P...high potential terminal, NL...low potential wiring, N...low potential terminal, AL...AC wiring, AC...AC terminal, P1, P2, P3, P4...switching elements, N1, N2, N3, N4...switching elements, L2, L3, L4...wiring inductance, R1 , R2, R3, R4...Gate resistor, PSL...Upper arm source wiring, NSL...Lower arm source wiring, GLN, GLP...Gate wiring, A...Current junction where currents join, Q...Element, S1, S2...Source terminal, G1...Gate terminal, D1...Drain terminal, KH...High potential electrode plate, KL...Low potential electrode plate, NdL...Bypass wiring, d1, d2, d3...Diode.

Claims

1. a plurality of switching elements arranged along a low potential wiring; and a drive circuit for simultaneously supplying a gate voltage to each of the plurality of switching elements via a gate wiring having a predetermined gate resistance; A power conversion device in which the gate resistance of the gate wiring connected to a switching element is set to a larger resistance value for a switching element having a smaller wiring inductance generated in the low-potential wiring to which the currents output from each of the switching elements to the low-potential wiring join together.

2. 2. The power conversion device according to claim 1, The gate resistor is connected in series to the gate wiring of the power conversion device.

3. 3. The power conversion device according to claim 2, a bypass wiring having a diode that bypasses at least a part of the plurality of gate resistors; The bypass wiring is a power conversion device in which an anode of the diode is connected to a gate side of the switching element, and bypasses at least a portion of the plurality of gate resistors when the plurality of switching elements are turned off.

4. 2. The power conversion device according to claim 1, a high-potential wiring to which the plurality of switching elements are connected; a wiring substrate on which the switching elements, the gate wiring, the low potential wiring, and the high potential wiring are arranged, The power conversion device, wherein the gate wiring, the low potential wiring, and the high potential wiring are arranged on the wiring board to extend along an arrangement of the plurality of switching elements.

5. 2. The power conversion device according to claim 1, The drive circuit supplies the gate voltage simultaneously to each of the multiple switching elements via the gate wiring having the gate resistor having the resistance value set, thereby turning on the multiple switching elements.

6. In the power conversion device according to any one of claims 1 to 4, The parallel connection of the multiple switching elements constitutes each phase of the upper and lower arms of an inverter circuit, and constitutes the lower arm of each phase in this power conversion device.

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