Semiconductor element and manufacturing method therefor

Abstract

To provide a semiconductor element in which the diffusion of Al in an electrode on an insulating film into the insulating film via a surface protective film is suppressed.SOLUTION: A semiconductor element includes a semiconductor layer, an insulating film (gate insulating film 14) located on the semiconductor layer, an electrode (gate electrode 17) located on the insulating film, and a surface protective film 18 that covers the semiconductor layer, the insulating film, and the electrode. The electrode includes a first barrier layer 17A that prevents Al from diffusing into the insulating film, a metal layer 17B that is provided on the first barrier layer 17A and is made of Al or an alloy mainly composed of Al, and a second barrier layer 17C that is provided on the metal layer 17B and protects the metal layer 17B. The side surface 17Ba of the metal layer 17B is located inside the side surface 17Aa of the first barrier layer 17A and the side surface 17Ca of the second barrier layer 17C.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A structure in which TiN, Al, and TiN are layered in this order from the gate insulating film side is known as the gate electrode of a MISFET (Patent Document 1). The TiN on the gate insulating film side is a layer that prevents Al from diffusing to the gate insulating film side, and the TiN on the Al is a layer that protects Al from oxidation, etc. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-54250 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, according to the inventor's research, it was found that if the gate electrode has a layered structure of TiN, Al, TiN as in Patent Document 1 and the element surface is covered with a surface protection film, there is a risk that Al of the gate electrode will diffuse into the gate insulating film through the surface protection film during heat treatment in the subsequent process steps or under the operating environment. If Al diffuses into the gate insulating film, it will cause unstable operation, such as fluctuations in threshold voltage and generation of leakage current.

[0005] The present invention has been made in view of the above background, and aims to provide a semiconductor element in which diffusion of Al in an electrode on an insulating film into the insulating film via a surface protective film is suppressed, and a method for manufacturing the same. [Means for solving the problem]

[0006] One aspect of the present invention is A semiconductor layer; an insulating film located on the semiconductor layer; an electrode located on the insulating film; a surface protection film covering the semiconductor layer, the insulating film, and the electrode; The electrode is a first barrier layer that prevents diffusion of Al into the insulating film; a metal layer formed on the first barrier layer and made of Al or an alloy mainly composed of Al; a second barrier layer provided on the metal layer to protect the metal layer; A side surface of the metal layer is in the semiconductor element, the side surface being inward from a side surface of the first barrier layer and a side surface of the second barrier layer.

[0007] Another aspect of the present invention is an insulating film forming step of forming an insulating film on the semiconductor layer; an electrode formation step of laminating, on the insulating film, in this order from the insulating film side, a first barrier layer for preventing diffusion of Al into the insulating film, a metal layer made of Al or an alloy mainly containing Al, and a second barrier layer for protecting the metal layer to form an electrode; an etching step of dry-etching the electrode in a direction perpendicular to the main surface of the semiconductor layer to form a predetermined pattern, and dry-etching a side surface of the metal layer so that the side surface of the metal layer is located inside side surfaces of the first barrier layer and the second barrier layer; and forming a surface protective film so as to cover the semiconductor layer and the electrodes. Effect of the Invention

[0008] In the above embodiment, the side surface of the metal layer is located inside the side surfaces of the first barrier layer and the second barrier layer, which makes it possible to suppress diffusion of Al from the metal layer into the insulating film, thereby making it possible to suppress unstable operation. [Brief description of the drawings]

[0009] [Figure 1]1 is a cross-sectional view showing the configuration of a semiconductor element in embodiment 1, taken along a direction perpendicular to a main surface of a substrate. [Diagram 2] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor element according to the first embodiment. [Diagram 3] 2A to 2C are diagrams illustrating a manufacturing process of the semiconductor element according to the first embodiment. [Figure 4] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor element in accordance with a second embodiment, taken along a direction perpendicular to a main surface of a substrate. [Diagram 5] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor element in embodiment 3, taken along a direction perpendicular to the main surface of the substrate. [Figure 6] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor element in embodiment 4, taken along a direction perpendicular to the main surface of the substrate. [Figure 7] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor element in a first modified example of the fourth embodiment, taken along a direction perpendicular to a main surface of a substrate. [Figure 8] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor element in a second modified example of the fourth embodiment, taken along a direction perpendicular to the main surface of the substrate. [Figure 9] FIG. 11 is a cross-sectional view showing the configuration of a semiconductor element in embodiment 5, taken along a direction perpendicular to the main surface of the substrate. [Figure 10] 5A to 5C are diagrams showing a modified example of the manufacturing process of the semiconductor element according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] The semiconductor element has a semiconductor layer, an insulating film located on the semiconductor layer, an electrode located on the insulating film, and a surface protection film covering the semiconductor layer, the insulating film, and the electrode. The electrode has a first barrier layer that prevents Al from diffusing into the insulating film, a metal layer that is provided on the first barrier layer and is made of Al or an alloy mainly composed of Al, and a second barrier layer that is provided on the metal layer and protects the metal layer. Furthermore, the side surface of the metal layer is located inside the side surfaces of the first barrier layer and the second barrier layer.

[0011] In the semiconductor element, the side surface of the metal layer may be covered with an oxide film made of aluminum oxide, which can further suppress the diffusion of Al into the insulating film.

[0012] In the semiconductor element, a gap may exist between the side surface of the metal layer and the surface protective film, which can further suppress the diffusion of Al into the insulating film.

[0013] In the above semiconductor element, the semiconductor element may have an insulated gate structure, the insulating film may be a gate insulating film, and the electrode may be a gate electrode.

[0014] In the above semiconductor element, the semiconductor layer has a trench, the insulating film is a gate insulating film provided continuously on the bottom surface, side surface, and semiconductor surface of the trench near the trench, and the electrode may be a gate electrode provided continuously on the bottom surface, side surface, and semiconductor surface of the trench near the trench via the insulating film.

[0015] The method for manufacturing a semiconductor element includes an insulating film formation step of forming an insulating film on a semiconductor layer, an electrode formation step of forming an electrode by stacking on the insulating film, in that order from the insulating film side, a first barrier layer that prevents diffusion of Al into the insulating film, a metal layer made of Al or an alloy mainly composed of Al, and a second barrier layer that protects the metal layer, an etching step of dry etching the electrode in a direction perpendicular to the main surface of the substrate to form a predetermined pattern and dry etching the side surfaces of the metal layer so that the side surfaces of the metal layer are more inward than the side surfaces of the first barrier layer and the second barrier layer, and a surface protective film formation step of forming a surface protective film to cover the semiconductor layer and the electrode.

[0016] In the above-mentioned method for manufacturing a semiconductor element, the method may include a trench formation step of forming a trench in the semiconductor layer prior to the insulating film formation step, in which the insulating film formation step is a step of forming an insulating film in the form of a continuous film on the bottom surface, side surfaces, and surface of the semiconductor layer of the trench in a region adjacent to the trench, and the electrode formation step may be a step of forming an electrode, via the insulating film, that is continuous on the bottom surface, side surfaces, and surface of the semiconductor layer of the trench in a region adjacent to the trench.

[0017] In the above-mentioned method for manufacturing a semiconductor element, the etching step may include a vertical etching step of dry etching the electrode in a direction perpendicular to the main surface of the substrate to form a predetermined pattern, and a lateral etching step of dry etching a side surface of the metal layer after the vertical etching step by applying an etching pressure higher than that in the vertical etching step.

[0018] In the method for manufacturing the semiconductor element, the etching step may be a step of simultaneously performing dry etching of the electrode in a direction perpendicular to the main surface of the substrate and dry etching of the side surface of the metal layer. Since there is no need to change the etching pressure, the manufacturing process can be made easier and the productivity can be improved.

[0019] In the above-mentioned method for manufacturing a semiconductor element, the etching step may include a second barrier layer etching step of dry etching the second barrier layer in a direction perpendicular to the main surface of the substrate until the metal layer is exposed to form a predetermined pattern, a metal layer etching step of dry etching the metal layer in a direction perpendicular to the main surface of the substrate after the second barrier layer etching step until the first barrier layer is exposed and dry etching the side surfaces of the metal layer, and a first barrier layer etching step of dry etching the first barrier layer in a direction perpendicular to the main surface of the substrate after the metal layer etching step until the insulating film is exposed. By dry etching each layer of the electrode individually, the accuracy of the dimensions and shape of each layer can be improved.

[0020] The method for manufacturing a semiconductor element may include an oxidation treatment step of oxidizing the side surface of the metal layer to form an oxide film after the etching step and before the surface protection film forming step. By forming the oxide film, the diffusion of Al into the insulating film can be further suppressed.

[0021] In the method for manufacturing a semiconductor element, the surface protection film forming step may be a step of forming the surface protection film so as to leave a gap between the side surface of the metal layer and the surface protection film. The gap can further suppress the diffusion of Al into the insulating film.

[0022] (Embodiment 1) 1. Structure of semiconductor elements Fig. 1 is a cross-sectional view showing the configuration of a semiconductor element 1 in embodiment 1, taken along a direction perpendicular to the main surface of a substrate. As shown in Fig. 1, the semiconductor element 1 in embodiment 1 is a MISFET having a vertical planar structure, and includes a substrate 10, an n-type layer 11, a p-type region 12, an n-type source region 13, a gate insulating film 14, a source electrode 15, a drain electrode 16, a gate electrode 17, and a surface protective film 18.

[0023] The substrate 10 is a Si-doped n-type semiconductor having a c-plane as its principal surface. + The substrate 10 is made of GaN. The Si concentration of the substrate 10 is 1×10 18 / cm 3 The substrate 10 may be made of any material other than GaN, as long as it is conductive and allows growth of a Group III nitride semiconductor. For example, Si, SiC, ZnO, etc. may be used.

[0024] The n-type layer 11 is provided on the substrate 10. The n-type layer 11 is a Si-doped n - The n-type layer 11 is made of GaN. The thickness of the n-type layer 11 is 8 to 15 μm. The Si concentration of the n-type layer 11 is 1×10 15 ~5×10 16 / cm 3 It is.

[0025] The p-type region 12 is provided in a partial region of the surface of the n-type layer 11 to a depth shallower than that of the n-type layer 11. The p-type region 12 is made of Mg-doped p-GaN. As described later, the p-type region 12 is a region formed by ion implantation of Mg into the surface of the n-type layer 11. The thickness of the p-type region 12 is 0.5 to 1 μm. A region on the surface of the p-type region 12, which is sandwiched between the surface of the n-type layer 11 and the surface of the n-type source region 13, becomes a channel. The Mg concentration of the p-type region 12 is 1×10 18 ~1×10 19 / cm 3 It is.

[0026] The n-type source region 13 is provided in a region inside the p-type region 12 in a plan view, to a depth shallower than that of the p-type region 12. The n-type source region 13 is a Si-doped n + As described later, the n-type source region 13 is a region formed by ion implantation of Si into the surface of the p-type region 12. The thickness of the n-type source region 13 is 0.1 to 0.5 μm. The Si concentration of the n-type source region 13 is 1×10 18 ~1×10 19 / cm 3 It is.

[0027] The gate insulating film 14 is provided continuously across the surface of the n-type layer 11, the surface of the p-type region 12, and the surface of the n-type source region 13. The material of the gate insulating film 14 is SiO2, SiN, SiON, or the like.

[0028] Source electrode 15 is provided continuously across the surface of p-type region 12 and the surface of n-type source region 13. The material of source electrode 15 is, for example, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0029] The drain electrode 16 is provided over the entire back surface of the substrate 10. The material of the drain electrode 16 is, for example, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0030] The gate electrode 17 is provided on the gate insulating film 14. The gate electrode 17 has a structure in which a first barrier layer 17A, a metal layer 17B, and a second barrier layer 17C are laminated in this order from the gate insulating film 14 side.

[0031] The first barrier layer 17A is a layer for preventing the metal of the metal layer 17B from diffusing into the gate insulating film 14. The material of the first barrier layer 17A is TiN. Other materials that can be used include Ta, TaN, Mo, and W. The thickness of the first barrier layer 17A is, for example, 50 to 300 nm.

[0032] Metal layer 17B is a layer for ensuring the conductivity of gate electrode 17. The material of metal layer 17B is Al. An alloy containing Al as a main component may be used. Examples of alloys containing Al as a main component include AlSi and AlCu. The thickness of metal layer 17B is, for example, 50 to 400 nm.

[0033] The second barrier layer 17C is a layer for protecting the metal layer 17B. The material of the second barrier layer 17C is TiN. Other materials that can be used include Ta, TaN, Mo, and W. The material may be different from that of the first barrier layer 17A. The thickness of the second barrier layer 17C is, for example, 20 to 100 nm.

[0034] Side surface 17Ba of metal layer 17B is formed to be more inward than side surface 17Aa of first barrier layer 17A and side surface 17Ca of second barrier layer 17C. In embodiment 1, side surface 17Aa of first barrier layer 17A and side surface 17Ca of second barrier layer 17C are on the same plane, but they do not have to be on the same plane.

[0035] By recessing the side surface 17Ba of the metal layer 17B on the inner side than the side surface 17Aa of the first barrier layer 17A and the side surface 17Ca of the second barrier layer 17C in this manner, the distance from the side surface 17Ba of the metal layer 17B to the gate insulating film 14 via the surface protective film 18 becomes longer. Furthermore, Al is trapped in the recess and is less likely to diffuse out of the recess. As a result, less Al diffuses from the side surface 17Ba of the metal layer 17B and reaches the gate insulating film 14. Therefore, the diffusion of Al from the side surface 17Ba of the metal layer 17B to the gate insulating film 14 can be suppressed.

[0036] The side surface 17Ba of the metal layer 17B is preferably located 10 to 500 nm inward from the side surface 17Aa of the first barrier layer 17A and the side surface 17Ca of the second barrier layer 17C. This can further suppress the diffusion of Al from the side surface 17Ba of the metal layer 17B to the gate insulating film 14.

[0037] The side surfaces 17Aa, 17Ba, and 17Ca may be perpendicular to the main surface of the substrate 10, or may be inclined. In this case, the angle is preferably in the range of 65 to 85 degrees with respect to the main surface of the substrate.

[0038] Furthermore, the gate insulating film 14 and the first barrier layer 17A, the first barrier layer 17A and the metal layer 17B, and the metal layer 17B and the second barrier layer 17C do not need to be in contact with each other, and a layer made of metal may be interposed between them. Also, a further layer made of metal may be provided on the second barrier layer 17C.

[0039] The surface protective film 18 is provided so as to cover the entire upper surface of the element, and is in contact with the surface and side of the gate electrode 17, the surface of the gate insulating film 14, the surface of the n-type source region 13, and the surface of the source electrode 15. However, holes penetrating the surface protective film 18 are provided at positions of the surface protective film 18 that correspond to partial regions of the surface of the source electrode 15 and at positions that correspond to partial regions of the gate electrode 17. The source electrode 15 and the gate electrode 17 are connected to the outside through these holes. The material of the surface protective film 18 is SiO2, SiN, SiON, etc., and may be a laminate of multiple materials.

[0040] Among the side surfaces of the gate electrode 17, a recess occurs near the side surface 17Ba of the metal layer 17B, but the surface protective film 18 is formed so as to fill the recess, and the side surface 17Ba of the metal layer 17B contacts the surface protective film 18. By making the side surface 17Ba of the metal layer 17B contact the surface protective film 18 in this manner, the operation of the element can be stabilized.

[0041] As described above, in the semiconductor device 1 of the first embodiment, the side surface 17Ba of the metal layer 17B of the gate electrode 17 is located inside the side surface 17Aa of the first barrier layer 17A and the side surface 17Ca of the second barrier layer 17C. This makes it possible to suppress diffusion of Al of the metal layer 17B into the gate insulating film 14.

[0042] 2. Manufacturing method of semiconductor devices Next, a manufacturing process for the semiconductor device 1 according to the first embodiment will be described with reference to the drawings.

[0043] First, a substrate 10 is prepared, and after the surface of the substrate 10 is cleaned, an n-type layer 11 is formed on the substrate 10 by MOCVD (see FIG. 2(a)).

[0044] Next, Mg ions are implanted to a predetermined depth into a predetermined region on the surface of the n-type layer 11 to form a p-type region 12 (see FIG. 2(b)). Note that the Mg ion-implanted region will become p-type after a heat treatment in a subsequent process, but for ease of explanation, it will be called the p-type region 12 even before it becomes p-type.

[0045] Next, Si is ion-implanted to a predetermined depth into a predetermined region on the surface of p-type region 12 to form n-type source region 13 (see FIG. 2(c)). Note that the Si ion-implanted region will become n-type after a heat treatment in a subsequent process, but for ease of explanation, it will be called n-type source region 13 even before it becomes n-type.

[0046] Next, a heat treatment is performed in an atmosphere of an inert gas such as nitrogen gas to convert the p-type region 12 to a p-type and the n-type source region 13 to an n-type.

[0047] In the first embodiment, the p-type region 12 and the n-type source region 13 are formed by ion implantation, but they may be formed by regrowth using MOCVD. That is, after the n-type layer 11 is formed, a predetermined region of the n-type layer 11 may be etched to form a groove, the p-type region 12 may be epitaxially grown so as to fill the groove, a predetermined region of the p-type region 12 may be etched to form a groove, and the n-type source region 13 may be epitaxially grown so as to fill the groove. Epitaxial growth of the p-type region 12 and the n-type source region 13 is superior in terms of dimensional controllability and impurity concentration controllability.

[0048] Next, the gate insulating film 14 is formed successively on the n-type layer 11, the p-type region 12, and the n-type source region 13 (see FIG. 3(a)).

[0049] Next, a first barrier layer 17A, a metal layer 17B, and a second barrier layer 17C are formed in this order on the gate insulating film 14 from the gate insulating film 14 side by vapor deposition or sputtering to form the gate electrode 17 (see FIG. 3(b)).

[0050] Next, a part of the gate electrode 17 is etched vertically (perpendicular to the main surface of the substrate 10 and the n-type layer 11) by dry etching to form the gate electrode 17 into a predetermined pattern (see FIG. 3(c)). A chlorine-based gas is used as the etching gas, for example, a mixed gas of BCl3 and Cl2. The etching pressure is, for example, 0.6 Pa or less.

[0051] Next, the side surface 17Ba of the metal layer 17B of the gate electrode 17 is etched laterally (in a direction parallel to the main surfaces of the substrate 10 and the n-type layer 11) by dry etching (see FIG. 3(d)). A chlorine-based gas is used as the etching gas, for example, the same mixed gas of BCl3 and Cl2 as in the previous process. The etching pressure is set higher than that in the previous process, for example, 1 to 5 Pa. By increasing the etching pressure in this manner, the molecular weight per unit volume increases, making scattering of the etching gas more likely to occur. As a result, etching in the lateral direction can be promoted.

[0052] Here, the etching speed of the side surface 17Aa of the first barrier layer 17A and the side surface 17Ca of the second barrier layer 17C is sufficiently slower than that of the side surface 17Ba of the metal layer 17B. This is because Al, which is the material of the metal layer 17B, is more easily etched than TiN, which is the material of the first barrier layer 17A and the second barrier layer 17C. As a result, the side surface 17Ba of the metal layer 17B is located inside the side surface 17Aa of the first barrier layer 17A and the side surface 17Ca of the second barrier layer 17C, and a recess is formed.

[0053] In the first embodiment, the etching pressure is changed to change the etching rate and promote the lateral etching, but the etching rate may be changed by applying a bias to the substrate 10.

[0054] Next, the gate insulating film 14 is formed into a predetermined pattern by dry etching. Then, the source electrode 15 is formed in predetermined regions on the surface of the p-type region 12 and the surface of the n-type source region 13 by vapor deposition or sputtering, and the drain electrode 16 is formed on the back surface of the substrate 10 by vapor deposition or sputtering. Furthermore, a surface protective film 18 is formed so as to cover the entire upper surface of the element. In this manner, the semiconductor element 1 of the first embodiment is manufactured.

[0055] The surface protection film 18 is preferably formed by the ALD method. The ALD method has excellent coverage, and can form the surface protection film 18 so as to fill even the recesses near the side surface 17Ba of the metal layer 17B. As a result, the side surface 17Ba of the metal layer 17B can be brought into contact with the surface protection film 18, and the operation of the element can be stabilized.

[0056] (Embodiment 2) Fig. 4 is a cross-sectional view showing the configuration of the semiconductor element 2 in embodiment 2, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 2, the semiconductor element 2 in embodiment 2 is the semiconductor element 1 in embodiment 1, except that an oxide film 20 is provided between the side surface 17Ba of the metal layer 17B and the surface protective film 18. The other configuration is the same as that of the semiconductor element in embodiment 1.

[0057] The oxide film 20 is a film obtained by oxidizing the side surface of the metal layer 17B of the gate electrode 17, and is a film made of aluminum oxide. The thickness of the oxide film 20 is 1 to 50 nm. The thickness of the oxide film 20 is equal to or less than the depth of the recess on the side surface of the gate electrode 17 (the distance from the side surface 17Ba of the metal layer 17B to the side surface 17Aa of the first barrier layer 17A or the side surface 17Ca of the second barrier layer 17C). By providing the oxide film 20 made of aluminum oxide on the side surface of the metal layer 17B in this manner, the diffusion of Al from the metal layer 17B to the gate insulating film 14 via the surface protective film 18 can be further suppressed. In the second embodiment, the oxide film 20 is in contact with the surface protective film 18, but there may be a gap between the oxide film 20 and the surface protective film 18 as in the third embodiment described later.

[0058] The oxide film 20 is formed by adding an oxidation treatment step after etching the side surface 17Ba of the metal layer 17B in the lateral direction and before patterning the gate insulating film 14. The oxidation treatment step is a step of performing oxygen plasma treatment in an oxygen atmosphere. The oxygen plasma treatment is performed for 20 minutes at 150 W, for example. This oxidation treatment step oxidizes the side surface 17Ba of the metal layer 17B, and an oxide film 20 made of aluminum oxide is formed.

[0059] (Embodiment 3) Fig. 5 is a cross-sectional view showing the configuration of a semiconductor element 3 in embodiment 3, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 5, the semiconductor element in embodiment 3 is the same as the semiconductor element 1 in embodiment 1 except that a gap 30 is provided between the side surface 17Ba of the metal layer 17B and the surface protective film 18. The other configuration is the same as that of the semiconductor element 1 in embodiment 1.

[0060] In the first embodiment, the side surface of the metal layer 17B is in contact with the surface protective film 18, but in the third embodiment, the side surface of the metal layer 17B is not in contact with the surface protective film 18, and a gap 30 is present. The gap 30 is filled with the atmospheric gas used when the surface protective film 18 is formed.

[0061] Since the gap 30 exists between the side surface of the metal layer 17B and the surface protective film 18 in this manner, diffusion of Al from the metal layer 17B to the gate insulating film 14 via the surface protective film 18 does not occur. Therefore, the diffusion of Al from the metal layer 17B to the gate insulating film 14 can be further suppressed.

[0062] The formation of the voids 30 is made possible by forming the surface protection film 18 by sputtering. Since sputtering preferentially forms a film in the direction perpendicular to the main surface of the substrate, the surface protection film 18 is not formed in the recessed portion near the side surface 17Ba of the metal layer 17B, and the recessed portion is left behind as the voids 30.

[0063] (Embodiment 4) Fig. 6 is a cross-sectional view showing the configuration of the semiconductor element 4 in the embodiment 4, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 6, the semiconductor element 4 in the embodiment 4 is a vertical MISFET having a trench gate structure, and includes a substrate 110, an n-type layer 111, a p-type layer 112, an n-type source region 113, a gate insulating film 114, a source electrode 115, a drain electrode 116, a gate electrode 117, and a surface protective film 118.

[0064] The substrate 110 is similar to the substrate 10 in the first embodiment.

[0065] The n-type layer 111 is provided on the substrate 110. The n-type layer 111 is a Si-doped n - The n-type layer 111 is made of GaN. The thickness of the n-type layer 111 is 8 to 15 μm. The Si concentration of the n-type layer 111 is 1×10 15 ~5×10 16 / cm 3 It is.

[0066] The p-type layer 112 is provided on the n-type layer 111. The p-type layer 112 is made of Mg-doped p-GaN. The thickness of the p-type layer 112 is 0.5 to 1 μm. The Mg concentration of the p-type layer 112 is 1×10 18 ~1×10 19 / cm 3 It is.

[0067] The n-type source region 113 is provided in a partial region of the surface of the p-type layer 212 to a depth shallower than that of the p-type region 12. The n-type source region 113 is a Si-doped n + The n-type source region 113 is made of -GaN. The n-type source region 113 is a region formed by ion implantation of Si into the surface of the p-type layer 112. The thickness of the n-type source region 113 is 0.1 to 0.5 μm. The Si concentration of the n-type source region 113 is 1×10 18 ~1×10 19 / cm 3 It is.

[0068] A trench 119 having a depth reaching the n-type layer 111 is provided in a portion of the surface of the n-type source region 113. The side surface of the p-type layer 112 exposed at the side surface of the trench 119 acts as a channel.

[0069] The gate insulating film 114 is provided as a continuous film along the bottom, side and top surfaces (surfaces of the n-type source regions 113 in the vicinity of the trenches 119) of the trenches 119. The material of the gate insulating film 114 is the same as that of the gate insulating film 14 in the first embodiment.

[0070] Source electrode 115 is provided continuously across the surface of p-type layer 112 and the surface of n-type source region 113. The material of source electrode 115 is, for example, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0071] The drain electrode 116 is provided over the entire back surface of the substrate 10. The material of the drain electrode 116 is, for example, Ti / Al / Ti, V / Al / Ti, or Pd / Al / Ti.

[0072] The gate electrode 117 is provided continuously along the bottom, side and top surfaces of the trench 119 via the gate insulating film 114. The gate electrode 117 has a structure in which a first barrier layer 117A, a metal layer 117B and a second barrier layer 117C are laminated in this order from the gate insulating film 114 side.

[0073] The materials of the first barrier layer 117A, the metal layer 117B, and the second barrier layer 117C are similar to those of the first barrier layer 17A, the metal layer 17B, and the second barrier layer 17C in the first embodiment, respectively.

[0074] Similarly to the side surfaces of metal layer 17B in the first embodiment, the side surfaces of metal layer 117B are also formed to be more inward than the side surfaces of first barrier layer 117A and second barrier layer 117C.

[0075] The surface protection film 118 is provided so as to cover the entire upper surface of the element and to fill the recesses near the side surfaces of the metal layer 117 B. Therefore, the side surfaces of the metal layer 117 B and the surface protection film 118 are in contact with each other.

[0076] As described above, in the semiconductor element 4 of the embodiment 4, similarly to the semiconductor element 1 of the embodiment 1, the side surface of the metal layer 117B of the gate electrode 117 is located inside the side surfaces of the first barrier layer 117A and the second barrier layer 117C. Therefore, the diffusion of Al from the metal layer 117B to the gate insulating film 114 can be suppressed.

[0077] In addition, since the semiconductor element in the fourth embodiment has a trench gate structure, the etching speed when etching the side surface of the metal layer 117B in the lateral direction can be made faster than that in the first embodiment. Therefore, the etching time can be shortened. In this etching, the gate insulating film 114 is also etched, but the amount of the gate insulating film 114 etched can be reduced by shortening the etching time, and the reliability of the element can be improved. In addition, the etching pressure can be made lower than that in the first embodiment, and can be set to, for example, 0.6 to 3 Pa. By keeping the etching pressure low, scattering of the etching gas can be suppressed, and the controllability and reproducibility of the etching shape can be improved.

[0078] The reason why the lateral etching of the side of the metal layer 117B in the trench gate structure is accelerated is presumed to be as follows. During dry etching, positive ions ionized by plasma are implanted into the metal layer, and the metal layer 117B is positively charged. At this time, when the planar distribution of positive ions is viewed from the upper side of the trench, the density of positive ions is higher on the side of the trench than in other regions. Here, etching occurs when chlorine ions react with the metal layer 117B. Therefore, negative ions, that is, chlorine ions, are attracted to the metal layer near the side of the trench, where the density of positive charges is high. As a result, the lateral etching of the side of the metal layer 117B is accelerated.

[0079] (Variation 1 of embodiment 4) 7 is a cross-sectional view showing the configuration of a semiconductor element 5 in a first modified form of the fourth embodiment, taken along a cross section perpendicular to the main surface of the substrate. The semiconductor element 5 in the first modified form of the fourth embodiment is configured such that an oxide film 120 is provided on the side surface of the metal layer 117B in the semiconductor element 4 in the fourth embodiment, as in the second embodiment. By providing the oxide film 120, the diffusion of Al from the metal layer 117B to the gate insulating film 114 can be further suppressed.

[0080] (Modification 2 of embodiment 4) 8 is a cross-sectional view showing the configuration of a semiconductor element 6 in a second modified form of the fourth embodiment, taken along a cross section perpendicular to the main surface of the substrate. The semiconductor element 6 in a first modified form of the fourth embodiment is the semiconductor element 4 in the fourth embodiment, except that a gap 130 is provided between the metal layer 117B and the surface protective film 18, as in the third embodiment. By providing the gap 130, the diffusion of Al from the metal layer 117B to the gate insulating film 114 can be further suppressed.

[0081] (Embodiment 5) Fig. 9 is a cross-sectional view showing the configuration of the semiconductor element in embodiment 5, taken along a direction perpendicular to the main surface of the substrate. As shown in Fig. 9, the semiconductor element in embodiment 5 is a lateral MISFET, and includes a substrate 210, a p-type layer 212, an n-type source region 213, a gate insulating film 214, a source electrode 215, a drain electrode 216, and a gate electrode 217.

[0082] The substrate 210 is made of sapphire. Other materials that can be used include Si, GaN, and ScAlMgO4 (SAM).

[0083] The p-type layer 212 is provided on the substrate 210. The p-type layer 212 is made of Mg-doped p-GaN. The thickness of the p-type layer 212 is 0.5 to 1 μm. The surface of the p-type layer 212 sandwiched between the surfaces of the two n-type source regions 213 serves as a channel. The Mg concentration of the p-type layer 212 is 1×10 18 ~1×10 19 / cm 3 It is.

[0084] The n-type source region 213 is provided in two regions spaced apart from each other in a partial region of the surface of the p-type layer 212, and is provided in a range shallower than the thickness of the p-type layer 212. The n-type source region 213 is a Si-doped n + The n-type source region 213 is made of -GaN. The n-type source region 213 is a region formed by ion implantation of Si into the surface of the p-type layer 212. The thickness of the n-type source region 213 is 0.1 to 0.5 μm. The Si concentration of the n-type source region 213 is 1×10 18 ~1×10 19 / cm 3 It is.

[0085] The gate insulating film 214 is provided in the form of a continuous film extending over one surface of the two separated n-type source regions 213, a region of the surface of the p-type layer 212 sandwiched between the two n-type source regions 213, and the other surface of the n-type source region 213. The material of the gate insulating film 214 is the same as that of the gate insulating film 14 in the first embodiment.

[0086] The source electrode 215 is provided on the surface of one of the two separated n-type source regions 213. The material of the source electrode 215 is the same as that of the source electrode 15 in the first embodiment.

[0087] The drain electrode 216 is provided on the surface of the other of the two separated n-type source regions 213 (the one on which the source electrode 215 is not provided). The material of the drain electrode 216 is the same as the material of the drain electrode 16 in the first embodiment.

[0088] The gate electrode 217 is provided on the gate insulating film 214. The gate electrode 217 has a structure in which a first barrier layer 217A, a metal layer 217B, and a second barrier layer 217C are laminated in this order from the gate insulating film 214 side.

[0089] The materials of the first barrier layer 217A, the metal layer 217B, and the second barrier layer 217C are similar to those of the first barrier layer 17A, the metal layer 17B, and the second barrier layer 17C in the first embodiment, respectively.

[0090] Similarly to the side surfaces of the metal layer 17B in the first embodiment, the side surfaces of the metal layer 217B are also formed to be more inward than the side surfaces of the first barrier layer 217A and the second barrier layer 217C.

[0091] The surface protection film 218 is provided so as to cover the entire upper surface of the element and to fill the recesses near the side surfaces of the metal layer 217 B. Therefore, the side surfaces of the metal layer 217 B and the surface protection film 218 are in contact with each other.

[0092] In the semiconductor element 7 of the embodiment 5, similarly to the semiconductor element 1 of the embodiment 1, the side surface of the metal layer 217B is located inside the side surfaces of the first barrier layer 217A and the second barrier layer 217C. Therefore, the diffusion of Al from the metal layer 217B to the gate insulating film 214 can be suppressed.

[0093] In the semiconductor element 7 of embodiment 5, an oxide film may be provided on the side surface of the metal layer 217B as in embodiment 2, or a gap may be provided between the side surface of the metal layer 217B and the surface protection film 218 as in embodiment 3.

[0094] (Modification 1 of embodiments 1 to 5) In the first to fifth embodiments, the gate electrode 17 is etched in a direction perpendicular to the main surface of the substrate to pattern it, and then the side surface of the metal layer 17B is etched, but these steps may be performed simultaneously by controlling the lateral etching rate to be sufficiently fast.

[0095] The lateral etching rate can be controlled by the etching pressure. For example, by using a mixed gas of BCl3 and Cl2 as the etching gas and setting the etching pressure to 1 to 5 Pa, the etching of the gate electrode 17 in the direction perpendicular to the main surface of the substrate and the etching of the side surface of the metal layer 17B can be performed simultaneously.

[0096] According to this method, it is not necessary to change the etching pressure, and the manufacturing process can be simplified, thereby improving productivity.

[0097] (Modification 2 of embodiments 1 to 5) In the semiconductor elements according to the first to fifth embodiments, the method of manufacturing the gate electrode 17 may be as shown in Fig. 10. Fig. 10 shows the manufacturing process of the gate electrode 17 of the semiconductor element 1 according to the first embodiment as an example, but the same can be applied to the other embodiments.

[0098] As shown in FIG. 3(b), the process is similar up to the step of forming a gate electrode 17 by stacking a first barrier layer 17A, a metal layer 17B, and a second barrier layer 17C on the gate insulating film 14 in this order from the gate insulating film 14 side.

[0099] Next, the second barrier layer 17C is etched by dry etching until the metal layer 17B is exposed (see FIG. 10(a)).

[0100] Next, the metal layer 17B is vertically etched by dry etching until the first barrier layer 17A is exposed, and then the side surface 17Ba of the metal layer 17B is horizontally etched by dry etching (see FIG. 10(b)). This makes the side surface 17Ba of the metal layer 17B more inward than the side surface 17Ca of the second barrier layer 17C. As shown in Modification 1 of the first to fifth embodiments, the vertical etching of the metal layer 17B and the horizontal etching of the side surface 17Ba of the metal layer 17B may be performed simultaneously.

[0101] Next, the first barrier layer 17A is vertically etched by dry etching until the gate insulating film 14 is exposed (see FIG. 10(c)). The side surface 17Aa of the first barrier layer 17A is positioned outside the side surface 17Ba of the metal layer 17B.

[0102] In this way, the accuracy of the dimensions and shapes of each layer can be improved by dry etching each layer constituting the gate electrode 17 individually. Also, the amount of etching of the gate insulating film 14 can be reduced, and the stability of the element operation can be further improved.

[0103] (Other variations) Although the first to fifth embodiments are MISFETs, the present invention can be applied to any semiconductor element having a structure in which an electrode is provided on a semiconductor layer via an insulating film, and can also be applied to electrodes other than gate electrodes. For example, the present invention can be applied to SBDs, IGBTs, HFETs, etc. As shown in the first to fifth embodiments, the present invention can be applied to vertical or horizontal types, and can also be applied to trench gate types.

[0104] Although the first to fifth embodiments use a group III nitride semiconductor as the semiconductor material, the present invention can be applied to other semiconductor materials, such as group III-V semiconductors such as GaAs, AlGaAs, and AlGaP, and gallium oxide semiconductors. [Explanation of symbols]

[0105] 10, 110: Substrate 11, 111: n-type layer 12:p-type region 13, 113: n-type source region 14, 114: Gate insulating film 15, 115: source electrode 16, 116: Drain electrode 17, 117: gate electrode 17A, 117A: First barrier layer 17B, ​​117B: Metal layer 17C, 117C: Second barrier layer 18, 118: Surface protective film 20, 120: oxide film 30, 130: void 119: Trench

Claims

1. A semiconductor layer; an insulating film located on the semiconductor layer; an electrode located on the insulating film; a surface protection film covering the semiconductor layer, the insulating film, and the electrode; The electrode is a first barrier layer for preventing diffusion of Al into the insulating film; a metal layer formed on the first barrier layer and made of Al or an alloy mainly composed of Al; a second barrier layer provided on the metal layer to protect the metal layer; A semiconductor element, wherein a side surface of the metal layer is located inside a side surface of the first barrier layer and a side surface of the second barrier layer.

2. The semiconductor device according to claim 1 , wherein a side surface of the metal layer is covered with an oxide film made of aluminum oxide.

3. The semiconductor device according to claim 1 , wherein a gap exists between a side surface of the metal layer and the surface protection film.

4. 2. The semiconductor device according to claim 1, wherein the semiconductor device has an insulated gate structure, the insulating film is a gate insulating film, and the electrode is a gate electrode.

5. the semiconductor layer has a trench; the insulating film is a gate insulating film provided continuously on a bottom surface, a side surface, and a semiconductor surface in the vicinity of the trench; 2 . The semiconductor element according to claim 1 , wherein the electrode is a gate electrode provided continuously, via the insulating film, on a bottom surface and a side surface of the trench and on a portion of the semiconductor surface near the trench.

6. an insulating film forming step of forming an insulating film on the semiconductor layer; an electrode formation step of laminating, on the insulating film, in this order from the insulating film side, a first barrier layer for preventing diffusion of Al into the insulating film, a metal layer made of Al or an alloy mainly containing Al, and a second barrier layer for protecting the metal layer to form an electrode; an etching step of dry-etching the electrode in a direction perpendicular to the main surface of the semiconductor layer to form a predetermined pattern, and dry-etching a side surface of the metal layer so that the side surface of the metal layer is located inside side surfaces of the first barrier layer and the second barrier layer; and forming a surface protective film so as to cover the semiconductor layer and the electrodes.

7. A trench forming step of forming a trench in the semiconductor layer before the insulating film forming step, the insulating film forming step is a step of forming the insulating film in the form of a continuous film on the bottom surface and side surfaces of the trench and on the surface of the semiconductor layer in a region near the trench; 7. The method for manufacturing a semiconductor element according to claim 6, wherein the electrode formation step is a step of forming the electrode continuous with the bottom and side surfaces of the trench and the surface of the semiconductor layer in a region near the trench via the insulating film.

8. The etching step includes: a vertical etching step of dry etching the electrode in a direction perpendicular to the main surface of the semiconductor layer to form a predetermined pattern; 8. The method for manufacturing a semiconductor device according to claim 6, further comprising a lateral etching step of dry-etching a side surface of the metal layer by applying an etching pressure higher than that applied in the vertical etching step, after the vertical etching step.

9. 8. The method for manufacturing a semiconductor element according to claim 6, wherein the etching step comprises simultaneously performing dry etching of the electrode in a direction perpendicular to the main surface of the semiconductor layer and dry etching of a side surface of the metal layer.

10. The etching step includes: a second barrier layer etching step of dry-etching the second barrier layer in a direction perpendicular to the main surface of the semiconductor layer until the metal layer is exposed to form a predetermined pattern; a metal layer etching step of dry-etching the metal layer in a direction perpendicular to the main surface of the semiconductor layer until the first barrier layer is exposed, after the second barrier layer etching step, and dry-etching a side surface of the metal layer; 7. The method for manufacturing a semiconductor device according to claim 6, further comprising: after the metal layer etching step, a first barrier layer etching step of dry-etching the first barrier layer in a direction perpendicular to the main surface of the semiconductor layer until the insulating film is exposed.

11. 8. The method for manufacturing a semiconductor element according to claim 6, further comprising an oxidation treatment step of oxidizing a side surface of the metal layer to form an oxide film after the etching step and before the surface protection film forming step.

12. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the surface protection film forming step is a step of forming the surface protection film so as to leave a gap between a side surface of the metal layer and the surface protection film.

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