Manufacturing method of semiconductor device

Abstract

To reduce residual stress in a semiconductor device caused by a dicing process in a manufacturing method of a semiconductor device using a semiconductor material harder than silicon.SOLUTION: One surface of a semiconductor wafer 30 made of a semiconductor material harder than silicon is ground to form a fractured layer 32 having a larger surface roughness than that before the grinding of the one surface. After that, a crack C is formed through the fractured layer 32 in the semiconductor wafer 30 having the fractured layer 32 formed therein. As a result, the crack C can be formed with smaller force than in a semiconductor wafer in a mirror state, and the residual stress generated in the semiconductor wafer 30 can be reduced.SELECTED DRAWING: Figure 6C

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] Conventional semiconductor devices are formed by forming a plurality of element regions each having a semiconductor element on a semiconductor wafer, and then cutting the semiconductor wafer with a blade to separate the plurality of element regions into individual pieces. In the dicing process for dividing the semiconductor wafer into individual pieces, cracks may occur in the semiconductor chips, and burrs may occur on the back surface electrodes that the blade contacts.

[0003] As a manufacturing method of a semiconductor device that suppresses the occurrence of cracks in the semiconductor chip and burrs on the back electrode in such a dicing process, for example, the one described in the following Patent Document 1 has been proposed. In this manufacturing method of a semiconductor device, a V-shaped V groove and a back electrode are formed in this order on the back surface of a semiconductor wafer, and then a V groove is formed on the front surface of the semiconductor wafer in a portion located above the V groove on the back surface. Then, a laser beam is irradiated onto the semiconductor wafer to form a modified layer inside the semiconductor wafer and between the V grooves on the front surface and back surface. Thereafter, a dicing tape is attached to the semiconductor wafer, and the semiconductor wafer is stretched together with the dicing tape, so that the V groove and the modified layer are used as cleavage points to divide the wafer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2007-165371 A Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, in the field of power semiconductor devices such as IGBTs and MOSFETs, development of devices using silicon carbide (SiC) as a semiconductor material has been progressing. SiC has a lower on-resistance and a higher breakdown voltage than silicon (Si), and is therefore expected to improve the performance of power semiconductor devices. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0006] However, in the case of semiconductor devices using SiC, the load on the blade is large in the dicing process because SiC is harder than silicon. Therefore, a dicing process consisting of a scribing process and a breaking process has been proposed as a manufacturing method for semiconductor devices using a semiconductor material harder than Si. The scribing process is a process in which a blade is pressed against a semiconductor wafer to form a vertical crack on the surface. The breaking process is a process in which a plate or the like is pressed against the surface of the semiconductor wafer opposite to the surface on which the vertical crack is formed, and the semiconductor wafer is cleaved and divided from the vertical crack in a manner similar to three-point bending. Hereinafter, for ease of explanation, the dicing process consisting of the scribing process and the breaking process may be referred to as the "scribing and breaking process."

[0007] As a result of intensive research by the inventors into the manufacturing method of this type of semiconductor device, it was found that the semiconductor chips separated by the scribe-and-break process have a larger residual stress near the end face due to separation than those separated by a blade cutting method. It was also found that if this residual stress is large, cracks will occur due to thermal stress in the semiconductor chips mounted on other members by soldering or the like.

[0008] On the other hand, when the manufacturing method described in Patent Document 1 is applied to this type of semiconductor device, the blade cuts the surface layer of the hard semiconductor wafer, so the load on the blade is large. Also, a process of forming a V-groove on the front surface of the semiconductor wafer in addition to the back surface of the wafer using the blade and a process of forming a modified layer by irradiating laser light are required, which increases the number of processes and increases manufacturing costs. Furthermore, there is a concern that the process of forming the modified layer by irradiating laser light will increase residual stress inside the semiconductor wafer.

[0009] In view of the above, an object of the present invention is to reduce residual stress in a semiconductor device caused by a dicing process in a manufacturing method of a semiconductor device using a semiconductor material harder than silicon. [Means for solving the problem]

[0010] In order to achieve the above object, the manufacturing method of a semiconductor device described in claim 1 includes preparing a semiconductor wafer (30) using a semiconductor material harder than silicon, grinding one side (30b) of the semiconductor wafer to form a fractured layer (32) having a surface roughness greater than that before the one side was ground, forming a crack (C) in a surface layer of the semiconductor wafer through the fractured layer, removing the fractured layer after the crack is formed, forming a back electrode (33) on the back side (30c) of the semiconductor wafer where the crack is formed, and after the back electrode is formed, pressing the surface of the semiconductor wafer opposite to the back side, and cleaving the semiconductor wafer using the crack as a starting point to separate the semiconductor wafer into individual pieces.

[0011] In this method for manufacturing a semiconductor device, a fracture layer is formed by grinding a hard semiconductor wafer, and cracks are formed in the semiconductor wafer through the fracture layer before forming a back electrode. This allows cracks to be formed with less pressure than when cracks are formed on a mirror-finished surface, making it possible to manufacture a semiconductor device in which residual stress caused by the crack shaping process is reduced after singulation. In addition, by removing the fracture layer after forming the cracks, it is possible to suppress the decrease in flexural strength caused by the fracture layer, and it is also possible to suppress the decrease in reliability.

[0012] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0013] [Figure 1] 1 is a top view showing an example of a layout of a semiconductor module using a semiconductor device according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a cross-sectional view showing a cross-sectional configuration taken along line II-II in FIG. [Diagram 3] FIG. 1 is an explanatory diagram of a conventional scribe-and-break process. [Figure 4] FIG. 13 is a diagram showing the measurement results of residual stress in semiconductor devices obtained by a conventional cutting method and a scribe-and-break process. [Diagram 5] FIG. 3 corresponds to an enlarged view of region V in FIG. 2, and is an explanatory diagram of crack generation due to residual stress in a semiconductor device resulting from a conventional scribe-and-break process. [Figure 6A] 4A to 4C are cross-sectional views showing a step of attaching to a support substrate in a dicing process of the semiconductor device according to the embodiment. [Figure 6B] FIG. 6B is a cross-sectional view showing a step following FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing a step following FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing a step following FIG. 6C. [Figure 6E] FIG. 6B is a cross-sectional view showing a step following FIG. 6D. [Figure 6F] FIG. 6B is a cross-sectional view showing a step following FIG. 6E. [Figure 6G] FIG. 6C is a cross-sectional view showing a step following FIG. 6F. [Figure 6H] FIG. 6C is a cross-sectional view showing a step following FIG. 6G. [Figure 6I] FIG. 6C is a cross-sectional view showing a step following FIG. 6H. [Figure 7]6C is a diagram showing the results of observation of a cross section of the back surface side formed in the step shown in FIG. 6B by a transmission electron microscope (TEM). FIG. [Figure 8] FIG. 6F is a diagram showing the results of TEM observation of a cross section of the rear surface electrode after the process shown in FIG. 6E. [Figure 9A] FIG. 6D is a cross-sectional view showing another example of a step subsequent to FIG. 6C. [Figure 9B] FIG. 9B is a cross-sectional view showing a step following FIG. 9A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (Embodiment) A semiconductor module using a semiconductor device according to an embodiment will be described with reference to the drawings. This semiconductor device is, for example, a power semiconductor element made of a semiconductor material harder than silicon, such as SiC, and can be applied to an inverter or the like. In this specification, a case in which the semiconductor device is applied to a semiconductor module constituting an inverter will be described as a representative example, but the present invention is not limited to this example and can be applied to other uses.

[0016] In Figure 1, in order to make the configuration of the semiconductor module 100 easier to understand, the outer contour of the sealing resin 8, which will be described later, is shown by a two-dot chain line, and the parts of the outer contours of the components of the semiconductor module 100 that overlap with other components other than the sealing resin 8 are shown by dashed lines.

[0017] For ease of explanation, the direction along the left-right direction of the plane of the paper in Fig. 1 will be referred to as the "x direction," the direction perpendicular to the x direction on the same plane will be referred to as the "y direction," and the direction perpendicular to the same plane, i.e., the xy plane, will be referred to as the "z direction," as shown by arrows in Fig. 1 and subsequent figures. The x, y, and z directions shown by arrows in Fig. 1 and subsequent figures correspond to the x, y, and z directions in Fig. 1, respectively.

[0018] [Semiconductor Module] As shown in FIG. 1, the semiconductor module 100 includes a first lead frame 1, a second lead frame 2, a semiconductor device 3 arranged between the lead frames 1 and 2 in the z direction, a conductor block 4 and connecting members 6 and 7, a wire 5, and a sealing resin 8.

[0019] The first lead frame 1 is made of a conductive material such as copper, and includes a positive plate 11 having a positive terminal P, an output plate 12 having an output terminal O, a negative plate 13 having a negative terminal N, and a plurality of signal terminals 14. The first lead frame 1 is formed, for example, by removing the connecting portions of the positive plate 11, the output plate 12, the negative plate 13, and the signal terminals 14, which were previously connected by a bus bar or the like (not shown), during the manufacturing process of the semiconductor module 100, and being separated from each other.

[0020] The positive electrode plate 11 has a positive electrode terminal P protruding from the sealing resin 8 along the y direction, for example, and is disposed apart from the output plate 12 in the x direction, and the first semiconductor device 3a is mounted thereon via a bonding material (not shown). The positive electrode plate 11 is electrically connected to a first connection plate 21 (described later) via a first conductor block 4a disposed on the first semiconductor device 3a. The island portion of the positive electrode plate 11 on which the first semiconductor device 3a is mounted has a surface opposite to the surface facing the first semiconductor device 3a exposed from the sealing resin 8, and can be cooled by contact with a cooler (not shown). At this time, an insulating member (not shown) is disposed between the cooler (not shown) and the exposed portion of the island portion, and electrical insulation between the cooler and the semiconductor module 100 is ensured.

[0021] The output plate 12 has an output terminal O that is arranged in parallel with the positive terminal P and protrudes from the sealing resin 8 in the same direction as the positive terminal P, and the second semiconductor device 3b is mounted on the output plate 12. The output plate 12 has a protruding portion 121 that extends toward the positive plate 11 and approaches the first connection plate 21 described later in the z direction, and is electrically connected to the first connection plate 21 via a first connection member 6 that is arranged on the protruding portion 121. The output plate 12 is electrically connected to a second connection plate 22 described later via a second conductor block 4b that is arranged on the second semiconductor device 3b. As with the positive plate 11, the output plate 12 has a surface on the opposite side to the second semiconductor device 3b of the island portion on which the second semiconductor device 3b is mounted that is exposed from the sealing resin 8, and can be cooled by a cooler not shown.

[0022] The negative electrode plate 13 is disposed between the positive electrode plate 11 and the output plate 12 and separated from them. The negative electrode plate 13 is disposed in parallel with the positive electrode terminal P and the output terminal O, and has a negative electrode terminal N protruding from the sealing resin 8 in the same direction as the positive electrode terminal P and the output terminal O. The negative electrode plate 13 has an extension portion 131 that is disposed in the gap between the positive electrode plate 11 and the output plate 12 and extends in the opposite direction to the negative electrode terminal N, and is electrically connected to the second connection plate 22 via the second connection member 7 that is disposed on the extension portion 131.

[0023] The signal terminals 14 include a plurality of first signal terminals 14a connected to the first semiconductor device 3a via wires 5, and a plurality of second signal terminals 14b connected to the second semiconductor device 3b via wires 5. The signal terminals 14 are disposed between the positive electrode plate 11 and the output plate 12, on the opposite side to the terminals P, O, and N, and away from other members.

[0024] The second lead frame 2 includes, for example, a first connection plate 21 and a second connection plate 22, and is disposed opposite the first lead frame 1 across the semiconductor device 3 and the conductor block 4 in the z direction. The first connection plate 21 is disposed opposite the positive electrode plate 11 and is disposed apart from the second connection plate 22. The first connection plate 21 has, for example, a protruding portion 211 that protrudes toward the second connection plate 22 and is partially bent toward the output plate 12. When the first semiconductor device 3a is turned on, the first connection plate 21 forms a current path connecting the positive electrode plate 11, the first semiconductor device 3a, the first conductor block 4a, and the output plate 12. The second connection plate 22 has, for example, a shape similar to that of the first connection plate 21, and has a protruding portion 221 that protrudes toward the first connection plate 21. The second connection plate 22 is electrically connected to the negative electrode plate 13 via the protruding portion 221 and the second connection member 7 disposed directly below it. When the second semiconductor device 3b is turned on, the second connecting plate 22 constitutes a current path connecting the output plate 12, the second semiconductor device 3b, the second conductor block 4b, and the negative electrode plate 13. The first connecting plate 21 and the second connecting plate 22 are exposed from the sealing resin 8 on the surface opposite to the surface on the conductor block 4 side, except for the protruding parts 211 and 221, and can be cooled by a cooler (not shown) like the positive electrode plate 11 and the output plate 12.

[0025] The semiconductor device 3 is configured using a semiconductor substrate made of a semiconductor material harder than silicon, such as SiC, gallium nitride (GaN), or gallium oxide (Ga2O3). Hereinafter, for convenience of explanation, a semiconductor material harder than silicon is referred to as a "hard semiconductor material". The semiconductor device 3 configures, for example, a power semiconductor element in which a switching element such as an IGBT or MOSFET and a free wheel diode (FWD) are formed. In this specification, a case in which the semiconductor device 3 has an IGBT and an FWD will be described as a representative example, but is not limited to this example. The semiconductor device 3 has a structure in which, for example, the anode and cathode of the FWD are electrically connected to the emitter that is the front electrode of the switching element and the collector that is the back electrode, respectively. In the semiconductor device 3, a wire 5 is connected to a gate electrode (not shown) of the switching element, and on / off control is performed via a signal terminal 14.

[0026] The semiconductor device 3 is mounted on a positive electrode plate 11 or an output plate 12 via a bonding material 9 made of solder or the like, as shown in Fig. 2. A plurality of semiconductor devices 3 are formed on a semiconductor wafer made of a highly rigid hard semiconductor material, and are manufactured by being diced into individual pieces through a scribe-and-break process described later, so that residual stress caused by dicing is reduced. The reduction in residual stress and its effects will be described in detail later.

[0027] The conductor block 4 is made of a conductive material such as copper, and is disposed on the opposite side of the semiconductor device 3 from the positive electrode plate 11 or the output plate 12, and is joined to the semiconductor device 3 by a joining material 9. As shown in FIG. 1, for example, the conductor block 4 has a smaller planar size than the semiconductor device 3, and is connected to a portion of the semiconductor device 3 other than the portion to which the wire 5 is connected. The conductor block 4 is disposed between the positive electrode plate 11 and the first connecting plate 21, and between the output plate 12 and the second connecting plate 22, respectively, and serves to secure gaps between them and prevent the wire 5 from contacting the connecting plates 21, 22.

[0028] The wires 5 are made of a conductive material such as gold or aluminum, and are connected to the signal terminals 14 and the semiconductor device 3 by wire bonding.

[0029] The first connection member 6 and the second connection member 7 are made of a conductive material such as copper, and are respectively arranged between the protrusion 121 and the protrusion 211, and between the extension portion 131 and the protrusion 221, to electrically connect them.

[0030] The sealing resin 8 is made of a thermosetting resin material such as an epoxy resin, and is formed by any resin molding method.

[0031] The above is the basic configuration of the semiconductor module 100 when used as an inverter. The semiconductor device 3 used in the semiconductor module 100 is obtained by dividing a semiconductor wafer made of a hard semiconductor material into individual pieces by an improved scribe-and-break process, and is in a state in which residual stress is reduced compared to the conventional scribe-and-break process.

[0032] [Residual Stress in Semiconductor Device] As a result of intensive research by the inventors, it was found that when a semiconductor wafer made of a hard semiconductor material such as SiC is diced into individual chips using a conventional scribe-and-break process, the resulting semiconductor chips have large residual stress.

[0033] Here, the conventional scribe-and-break process will be described with reference to FIG. 3. The conventional scribe-and-break process includes a scribing process in which a vertical crack C of a predetermined depth is formed in the semiconductor wafer W, and a breaking process in which the semiconductor wafer W is cleaved in a manner similar to three-point bending, starting from the vertical crack C. In the scribing process, for example, the front surface Wa of the semiconductor wafer W is temporarily fixed to a suction table or the like, and a blade B is pressed against the back surface Wb to form a vertical crack C in the surface layer of the back surface Wb. In the breaking process, for example, the semiconductor wafer W is placed on a pedestal with a tape T attached to the front surface Wa and a protective film PF attached to the back surface Wb, and a position on the front surface Wa above the vertical crack C is pressed with a break plate BP. At this time, the semiconductor wafer W is in a hollow state with the portion where the vertical crack C is formed being separated from the pedestal, and both ends sandwiching the portion pressed by the break plate BP are supported by the pedestal, and the semiconductor wafer W is cleaved and divided in a manner similar to three-point bending, starting from the vertical crack C. The conventional scribing process is performed after the back surface Wb of the semiconductor wafer W is polished by a polishing process such as CMP to have a mirror-like surface with very small surface roughness, and a back surface electrode made of a metal material is formed on the back surface Wb. CMP is an abbreviation for Chemical Mechanical Polishing.

[0034] Through careful investigation by the present inventors, it has been found that when the semiconductor wafer W is made of a hard semiconductor material, the blade pressure in the scribing process, i.e., the scribing pressure, becomes large, and the residual stress in the semiconductor chips after singulation becomes high.

[0035] Specifically, for example, as shown in Figure 4, a semiconductor chip sample S1, which is obtained by cutting a semiconductor wafer W made of SiC with a blade B, had a maximum residual stress of approximately 23 MPa in the dicing region. Note that the residual stress of sample S1 was maximum at a position approximately 2 μm away from the chip end face due to dicing.

[0036] In contrast, the maximum residual stress in the dicing region of sample S2, a semiconductor chip obtained by dividing a semiconductor wafer W made of SiC by the conventional scribe-and-break process described above, was approximately 68 MPa. This is believed to be due to the fact that, in the formation of vertical cracks, the back surface Wb of the semiconductor wafer W is mirror-finished and covered with a back surface electrode made of a metal material, so the required scribing pressure is large at approximately 6 N, and this pressure remains as distortion in the vicinity of the scribe line of the semiconductor wafer W. Note that the maximum residual stress in sample S2 was at a position approximately 6 μm away from the chip end surface due to dicing. Note that the residual stress of the semiconductor chip shown in Figure 4 was measured by Raman scattering spectroscopy.

[0037] When the residual stress of the semiconductor chip is large, the semiconductor chip is subjected to thermal stress due to the difference in thermal expansion coefficient between the semiconductor chip and the surrounding members when mounted on another member. When the above-mentioned semiconductor module 100 is configured using a semiconductor chip SC (corresponding to the semiconductor device 3) with large residual stress, cracks may occur in the semiconductor chip SC starting from the points where the residual stress is large due to thermal stress, as shown in Fig. 5 for example. When such cracks occur, they progress toward element regions such as IGBTs, reducing the reliability of the semiconductor module 100.

[0038] In order to reduce the residual stress in the semiconductor chips after singulation, it is possible to adopt a cutting method using a blade. However, when the semiconductor wafer W is made of a hard semiconductor material, the blade cutting method places a large load on the blade and takes longer to singulate than the scribe-and-break process, which increases the manufacturing cost. Therefore, the present inventors have devised a method for reducing the residual stress in the semiconductor chips after singulation while still singulating the semiconductor wafer W by the scribe-and-break process.

[0039] [Scribe and break process] Next, a scribe-and-break process that is a dicing process for dividing a semiconductor wafer into individual pieces among the manufacturing processes for the semiconductor device 3 according to the embodiment will be described, which can reduce the residual stress described above. Note that a process for forming an element region 31 including switching elements, FWDs, etc. in a semiconductor wafer 30, which will be described later, can be performed by a known semiconductor process, and therefore a detailed description thereof will be omitted in this specification.

[0040] First, as shown in FIG. 6A, the other surface 30a of the semiconductor wafer 30 made of a hard semiconductor material such as SiC, on which the element region 31 is formed, is covered with an adhesive 201 to be protected, and is attached to a support substrate 200 for temporary fixation. The support substrate 200 is, for example, a glass substrate having an adhesive film (not shown) made of LTHC manufactured by 3M, but may be a protective tape as long as it can support the semiconductor wafer 30. It is preferable that the support substrate 200 is made of a material having a higher rigidity than a resin material, such as a glass substrate. This is because the pressing force of the blade applied to the semiconductor wafer 30 is less likely to escape in the subsequent scribing process, and the scribing pressure can be reduced. The adhesive 201 is, for example, made of any resin material having ultraviolet curing and thermoplasticity.

[0041] Next, as shown in FIG. 6B, one surface 30b of the semiconductor wafer 30 opposite to the support substrate 200 is ground by a grinding device such as a grinder (not shown) to thin the semiconductor wafer 30. This grinding process is a process of roughly grinding the semiconductor wafer 30 with a grindstone to thin it, and is different from the polishing process for forming a mirror surface. Therefore, the surface layer of the back surface 30c obtained by grinding the one surface 30b is a fractured layer 32 having a larger surface roughness than the one surface 30b before grinding. Specifically, as a result of observing a cross section of the back surface 30c of the semiconductor wafer 30 after this grinding process by a transmission electron microscope (TEM), it was found that the fractured layer 32 had an uneven shape of about 50 nm formed from the surface layer in the thickness direction of the wafer, as shown in FIG. 7, for example.

[0042] 6C, the semiconductor wafer 30 attached to the support substrate 200 is placed on the base 300, and the blade B is pressed against the crush layer 32 to form a vertical crack C in the dicing region located between the element regions 31. At this time, the blade B is aligned with the dicing region of the semiconductor wafer 30 by, for example, an alignment camera (not shown). The vertical crack C is a crack provided in the surface layer on the back surface 30c side of the semiconductor wafer 30 and runs along the thickness direction of the semiconductor wafer 30.

[0043] The scribing pressure required to perform the same scribing process on a mirror-finished SiC wafer before the back electrode was formed was about 2 N. In contrast, the semiconductor wafer 30 having the fracture layer 32 is more brittle than the base made of SiC, so the scribing pressure required in the scribing process is at least less than 2 N. As a result, the distortion generated in the semiconductor wafer 30 when the vertical crack is formed is reduced, and the residual stress in the vicinity of the scribe line is reduced.

[0044] Then, as shown in FIG. 6D, a back electrode 33 is formed on the back surface 30c of the semiconductor wafer 30 by sputtering or the like. The back electrode 33 is mainly composed of at least one of conductive metal materials that can be silicided, such as Ni (nickel), Ti (titanium), Mo (molybdenum), Ta (tantalum), Pt (platinum), and Co (cobalt), at least in a portion in contact with the fracture layer 32. The main component here means a component that exceeds 50 vol%. For example, the back electrode 33 has a laminated structure such as Ni / Ti / Ni / Au (gold) from the fracture layer 32 side, and at least the region in contact with the fracture layer 32 is silicided by the next thermal oxidation process. The back electrode 33 is at least thicker than the fracture layer 32, for example, the thickness is 100 nm when the depth of the fracture layer 32 is 50 nm. This is to prevent an excessive decrease in bending strength caused by the crushed layer 32 by silicidation of the entire crushed layer 32 with the back electrode 33 in the next process, removing the crushed layer 32. If the back electrode 33 formed in the process of FIG. 6D has a structure of Ni / Ti / Ni / Au from the crushed layer 32 side, it becomes NiSi / Ti / Ni / Au after thermal oxidation.

[0045] Thereafter, as shown in FIG. 6E, the semiconductor wafer 30 is heat-treated to silicidize the fracture layer 32 with the back electrode 33. This heat treatment may be a method of heating the entire semiconductor wafer 30 using a heating furnace or the like, or a method of laser annealing in which a laser beam is irradiated onto the back electrode 33 to locally heat the back surface 30c, and may be performed by a known method. After this heat treatment, the semiconductor wafer 30 is in a state in which the back electrode 33 is silicidized with the fracture layer 32 to a thickness of about 150 nm, and the fracture layer 32 is removed, as shown in FIG. 8, for example. This suppresses excessive reduction in the bending strength of the semiconductor wafer 30 due to the fracture layer 32 remaining, and improves reliability.

[0046] Next, as shown in Fig. 6F, a dicing tape DT is attached to the surface of the semiconductor wafer 30 on the side of the back electrode 33. Then, for example, by irradiating with laser light, the semiconductor wafer 30 is peeled off from the adhesive 201 and the support substrate 200, and the other surface 30a is exposed, as shown in Fig. 6G.

[0047] 6H, a protective tape PT is attached to the other surface 30a of the semiconductor wafer 30, and the semiconductor wafer 30 is placed on the stage 400. At this time, the semiconductor wafer 30 is aligned by an alignment camera (not shown) or the like so that the portion where the vertical crack C is formed is located above a gap provided in the stage 400. Then, a portion of the other surface 30a located above the portion where the vertical crack C is formed is pressed by a break plate BP, and the vertical crack C is advanced in the thickness direction of the semiconductor wafer 30 in a manner similar to three-point bending, and the semiconductor wafer 30 is cleaved. This breaking process is repeated as many times as the number of scribe lines where the vertical crack C is formed, so that the semiconductor wafer 30 is divided into a plurality of semiconductor devices 3.

[0048] After the above-mentioned breaking process, the protective tape PT is peeled off, and the adhesive strength of the dicing tape DT is reduced, for example, by irradiating it with ultraviolet light, and the separated semiconductor devices 3 (semiconductor chips) are picked up by a pick-up device not shown, as shown in FIG. 6I.

[0049] By dividing the semiconductor wafer 30 made of a hard semiconductor material into individual pieces by the above-mentioned scribe-break process, the scribe pressure is reduced compared to the conventional method, and semiconductor devices 3 having reduced residual stress near the edge obtained by dividing can be obtained. This method reduces the load on the blade B and shortens the time required for dividing, compared to the cutting method using the blade B. In addition, it is not necessary to form a modified layer by irradiating laser light, and the manufacturing cost of the semiconductor device 3 can be reduced.

[0050] In the above, silicidation with the back electrode 33 is given as an example of the process of removing the fracture layer 32, but the present invention is not limited thereto. For example, after the scribing process shown in FIG. 6C, the fracture layer 32 may be removed by a mechanical polishing process such as CMP as shown in FIG. 9A. In this case, the back electrode 33 is formed on the back surface 30c of the polished semiconductor wafer 30 as shown in FIG. 9B, and heat treatment is performed. The subsequent processes are the same as those described above. Even after such a process, the scribing pressure in the scribing process is reduced and the fracture layer 32 is removed, so that the semiconductor device 3 in the same state as that after the dicing process shown in FIG. 6A to FIG. 6I is obtained.

[0051] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one, or less than one, are also within the scope and concept of the present disclosure.

[0052] In each of the above embodiments, it goes without saying that the elements constituting the embodiment are not necessarily essential, except when it is specifically stated that they are essential or when it is clearly considered essential in principle. In addition, in each of the above embodiments, when the numbers, values, amounts, ranges, etc. of the components of the embodiment are mentioned, they are not limited to the specific numbers, except when it is specifically stated that they are essential or when it is clearly limited to a specific number in principle. In addition, in each of the above embodiments, when the shapes, positional relationships, etc. of the components are mentioned, they are not limited to the shapes, positional relationships, etc., except when it is specifically stated that they are essential or when it is clearly limited to a specific shape, positional relationship, etc. in principle. [Explanation of symbols]

[0053] 30 Semiconductor Wafers 30a Other side of semiconductor wafer 30b One side of a semiconductor wafer 30c Backside of semiconductor wafer 32 Crushed Layer 33 Back electrode C Vertical crack

Claims

[Claim 1] Providing a semiconductor wafer (30) using a semiconductor material harder than silicon; grinding one surface (30b) of the semiconductor wafer to form a fractured layer (32) having a surface roughness greater than that before the one surface was ground; forming a crack (C) in a surface layer of the semiconductor wafer through the fracture layer; removing the fractured layer after forming the crack; forming a back surface electrode (33) on the back surface (30c) of the semiconductor wafer where the crack is formed; A method for manufacturing a semiconductor device comprising: after forming the back electrode, pressing a surface of the semiconductor wafer opposite to the back surface, and cleaving the semiconductor wafer using the cracks as starting points to separate the semiconductor wafer.

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