Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device in which degradation of a gate insulating layer is suppressed.SOLUTION: A semiconductor device 100a includes a semiconductor substrate 1, a gate insulating film 2a, a gate electrode 2b, first electrical wiring 5a, and a semiconductor insulating layer 3. The gate insulating film 2a is formed on the semiconductor substrate 1. The gate electrode 2b is formed on the semiconductor substrate 1 through the gate insulating film 2a. The first electrical wiring 5a is connected to the gate electrode 2b. The semiconductor insulating layer 3 is connected to at least one of the gate electrode 2b and the first electrical wiring 5a.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In order to suppress charging of the gate insulating layer during the manufacturing process of the semiconductor device, an amorphous carbon film that releases charges to the semiconductor substrate is formed (see, for example, Japanese Patent Application Laid-Open No. 7-245390). By forming such an amorphous carbon film, charge-up during ion implantation during the manufacturing process of the semiconductor device is suppressed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 7-245390 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the amorphous carbon film as described above is removed after the ion implantation, and therefore the gate insulating layer may become charged in the process after the ion implantation, which may cause the gate insulating layer to deteriorate.

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device in which deterioration of a gate insulating layer is suppressed. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate, a gate insulating film, a gate electrode, a first electrical wiring, and a semiconductive insulating layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the semiconductor substrate via the gate insulating film. The first electrical wiring is connected to the gate electrode. The semiconductive insulating layer is connected to at least one of the gate electrode and the first electrical wiring.

[0007] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of preparing a semiconductor substrate, forming a first semiconductive insulating layer on the semiconductor substrate, and rotating the semiconductor substrate after the step of forming the first semiconductive insulating layer. Effect of the Invention

[0008] According to the above, a semiconductor device in which deterioration of the gate insulating layer is suppressed can be obtained. [Brief description of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Diagram 3] 4 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Diagram 5] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 6] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 7] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 8] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 9]1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 10] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 11] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 12] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 13] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 14] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 15] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 16] 1 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a first embodiment. [Figure 17] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 18] 11 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] 11 is a schematic cross-sectional view showing a step of a method for manufacturing a semiconductor device according to a second embodiment. [Figure 20] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 21] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present disclosure will be described. Note that unless otherwise specified, the same or corresponding parts in the following drawings are given the same reference numerals, and the description thereof will not be repeated.

[0011] Embodiment 1 <Configuration of Semiconductor Device> Fig. 1 is a schematic cross-sectional view of the semiconductor device 100a according to the first embodiment. Fig. 2 is a schematic plan view of the semiconductor device 100a according to the first embodiment.

[0012] The semiconductor device 100a shown in Fig. 1 is, for example, a semiconductor device 100a for an integrated circuit (IC), and mainly includes a semiconductor substrate 1, a gate insulating film 2a, a gate electrode 2b, a semiconductive insulating layer 3, an interlayer insulating layer 4, and electrical wiring 5. Note that the electrical wiring 5 is not shown in Fig. 2. In Fig. 2, the outline of the semiconductive insulating layer 3 is indicated by a dotted line.

[0013] As shown in FIG. 1, the semiconductor substrate 1 has a first main surface 11 and a second main surface 12. The second main surface 12 is a surface located on the opposite side of the first main surface 11. The first main surface 11 and the second main surface 12 each extend in the x direction and the y direction perpendicular to the x direction. The z direction is the thickness direction of the semiconductor substrate 1. The normal direction of the first main surface 11 is the z direction perpendicular to the x direction and the y direction. The first main surface 11 faces the +z direction. The second main surface 12 faces the -z direction. The material constituting the semiconductor substrate 1 is, for example, silicon. The material constituting the semiconductor substrate 1 may be, for example, any of wide band gap semiconductor substrates such as silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3).

[0014] The concentration of impurities contained in the semiconductor substrate 1 may be adjusted according to the withstand voltage of the semiconductor device 100a. The conductivity type of the semiconductor substrate 1 may be n-type or p-type. A plurality of diffusion layers 13 are formed on the first main surface 11. When the conductivity type of the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layers 13 may be p-type. When the conductivity type of the semiconductor substrate 1 is p-type, the conductivity type of the diffusion layers 13 may be n-type. As shown in FIG. 1, the plurality of diffusion layers 13 are formed on the first main surface 11 and spaced apart from each other.

[0015] 1, the gate insulating film 2a is formed on a first main surface 11 of a semiconductor substrate 1. In a plan view of the first main surface 11, the gate insulating film 2a is disposed at a position sandwiched between a pair of diffusion layers 13. In a plan view of the first main surface 11, a portion of the gate insulating film 2a overlaps with the diffusion layer 13. A material constituting the gate insulating film 2a is, for example, silicon dioxide (SiO2).

[0016] 1, the gate electrode 2b is formed on the gate insulating film 2a. From a different perspective, the gate electrode 2b is formed on the semiconductor substrate 1 via the gate insulating film 2a. The material constituting the gate electrode 2b may be, for example, polysilicon.

[0017] As shown in FIG. 1, the semiconductive insulating layer 3 is formed on the semiconductor substrate 1 so as to cover the first main surface 11 and the gate electrode 2b in a plan view of the first main surface 11. The semiconductive insulating layer 3 does not have to be directly connected to the gate electrode 2b. As will be described later, the semiconductive insulating layer 3 may be formed on the surface 41 of the interlayer insulating layer 4 and disposed between the surface 41 and the first electrical wiring 5a in the z direction. The semiconductive insulating layer 3 may be formed so as to cover the surface 41 and the first electrical wiring 5a in a plan view of the surface 41 of the interlayer insulating layer 4.

[0018] The material constituting the semiconductive insulating layer 3 is, for example, a material containing at least one of semiconductive silicon nitride (SInSiN: Semi Insulating Silicon Nitride) and silicon dioxide (SiO2). As described later, the semiconductive insulating layer 3 is formed by plasma CVD (Chemical Vapor Deposition).

[0019] The semiconductive insulating layer 3 made of the above-mentioned materials has high insulation at low temperatures and high conductivity at high temperatures. From a different perspective, the electrical resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 27° C. (room temperature) is greater than the electrical resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 150° C. Specifically, when the electrical resistivity of the semiconductive insulating layer 3 at room temperature (27° C.) is about 1×10 12 The electrical resistivity of the semiconductive insulating layer 3 at 150° C. may change to 1 / 1000 or less of the electrical resistivity at room temperature (27° C.).

[0020] When the temperature of the semiconductive insulating layer 3 is 27° C., the electrical resistivity of the semiconductive insulating layer 3 is 1×10 11 Ωcm or more 1×10 13 When the temperature of the semiconductive insulating layer 3 is 150° C., the electrical resistivity of the semiconductive insulating layer 3 may be 1×10 10 It may be Ωcm or less. Thus, the electrical resistivity of the semiconductive insulating layer 3 is temperature dependent and reversibly changes depending on the temperature of the semiconductive insulating layer 3. In other words, by adjusting the temperature of the semiconductive insulating layer 3, the electrical resistivity of the semiconductive insulating layer 3 can be adjusted.

[0021] As shown in FIG. 1, the interlayer insulating layer 4 is disposed on the semiconductor substrate 1. The interlayer insulating layer 4 has a front surface 41 and a back surface 42. The back surface 42 faces the semiconductor substrate 1 and the gate electrode 2b. In the present embodiment 1, the back surface 42 of the interlayer insulating layer 4 is connected to the semiconductive insulating layer 3. The front surface 41 is the surface located opposite to the back surface 42. The material constituting the interlayer insulating layer 4 may be, for example, either silicon dioxide (SiO2) or tetraethyl orthosilicate (TEOS).

[0022] As shown in FIG. 1 and FIG. 2, a plurality of contact holes H are formed in the interlayer insulating layer 4. As shown in FIG. 2, the contact holes H have a plurality of first contact holes h1 and a plurality of second contact holes. The first contact hole h1 reaches the gate electrode 2b from the surface 41. The second contact hole h2 reaches the first main surface 11 of the semiconductor substrate 1 from the surface 41. As shown in FIG. 2, the first contact hole h1 and the second contact hole h2 are arranged spaced apart from each other. From a different perspective, on the surface 41 of the interlayer insulating layer 4, the first contact hole h1 is arranged at a position overlapping the gate electrode 2b. The second contact hole h2 is arranged at a position not overlapping the gate electrode 2b.

[0023] As shown in FIG. 1, the electrical wiring 5 is formed to fill the contact hole H. The electrical wiring 5 has a first electrical wiring 5a and a second electrical wiring 5b (not shown). The first electrical wiring 5a is electrically connected to the gate electrode 2b. The second electrical wiring 5b is electrically connected to the semiconductor substrate 1. The first electrical wiring 5a is connected to the gate electrode 2b, the inner peripheral surface hs1 of the first contact hole h1, and the surface 41 of the interlayer insulating layer 4 via the barrier metal 6. The second electrical wiring 5b is connected to the first main surface 11 of the semiconductor substrate 1, the inner peripheral surface hs2 of the second contact hole h2 (see FIG. 20), and the surface 41 of the interlayer insulating layer 4 via the barrier metal 6.

[0024] By forming the second contact hole h2 that reaches the first main surface 11 of the semiconductor substrate 1 from the surface 41, it is possible to form the second electrical wiring 5b that is electrically connected to the semiconductor substrate 1. In this way, it is possible to more efficiently flow charges to the semiconductor substrate 1. As a result, it is possible to more efficiently suppress deterioration of the gate insulating film 2a, as will be described later.

[0025] The material constituting the electrical wiring 5 may be, for example, a metal. The electrical wiring 5 may be a single layer, or may have a structure in which multiple layers are laminated in the z direction. Specifically, the electrical wiring 5 is formed by depositing an aluminum alloy (for example, an Al-Si alloy) on the surface 41 of the interlayer insulating layer 4 and the inner surface of the contact hole H using PVD (Physical Vapor Deposition) such as sputtering and deposition. A nickel alloy (Ni alloy) may be formed on the aluminum alloy using an electroless plating process or an electrolytic plating process. In this way, the electrical wiring 5 may be formed by laminating the aluminum alloy and the nickel alloy.

[0026] The electrical wiring 5 is formed on a barrier metal 6. That is, the barrier metal 6 is formed on the contact interface between the electrical wiring 5 and the interlayer insulating layer 4, on the contact interface between the electrical wiring 5 and the gate electrode 2b, and on the contact interface between the electrical wiring 5 and the semiconductor substrate 1. The material constituting the barrier metal 6 is, for example, either titanium (Ti) or titanium nitride (TiN).

[0027] 1, the semiconductor device 100a according to the first embodiment is characterized in that the semiconductor device 100a includes a semiconductive insulating layer 3. By forming the semiconductive insulating layer 3, charges generated during the manufacturing process of the semiconductor device 100a can be passed through the semiconductive insulating layer 3 to the outer periphery (not shown) of the semiconductor substrate 1. As a result, charges are not accumulated in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be suppressed.

[0028] Moreover, the electrical resistivity of the semiconductive insulating layer 3 is temperature dependent. Therefore, in a high temperature state such as an etching process and an ion implantation process, the semiconductive insulating layer 3 has high conductivity. Therefore, during the manufacturing process of the semiconductor device 100a, the generated charge can be passed to the semiconductor substrate 1. On the other hand, at room temperature or at the operating temperature of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulation. Therefore, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may be left after the manufacturing of the semiconductor device 100a is completed. In other words, since the semiconductive insulating layer 3 remains without being removed until the manufacturing of the semiconductor device 100a is completed, even after the ion implantation process is completed, the charge can be passed to the semiconductor substrate 1 when a high temperature process is performed. As a result, the charge is not accumulated in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be suppressed.

[0029] There is no particular restriction on the deposition range of the semiconductive insulating layer 3, and the semiconductive insulating layer 3 may be formed on the entire first main surface 11 of the semiconductor substrate 1. However, the semiconductive insulating layer 3 has a high dielectric constant. Therefore, if the semiconductive insulating layer 3 is formed on the entire first main surface 11 of the semiconductor substrate 1, the load capacitance of the semiconductor device 100a may increase.

[0030] As shown in FIG. 2, the semiconductive insulating layer 3 may be formed in a stripe shape. The semiconductive insulating layer 3 has a plurality of layers. In a plan view of the first main surface 11, the plurality of layers are arranged to be spaced apart from each other in the y direction. Specifically, the semiconductive insulating layer 3 may have a first layer 31 and a second layer 32. In a plan view of the first main surface 11, the first layer 31 and the second layer 32 may be arranged to be spaced apart from each other in the y direction. In this way, it is possible to flow charges to the semiconductor substrate 1 while suppressing an increase in the load capacitance of the semiconductor device 100a. In addition, the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed in a stripe shape is smaller than the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed over the entire first main surface 11. As a result, it is possible to suppress warping of the semiconductor substrate 1.

[0031] In a plan view of the first main surface 11, the semiconductive insulating layer 3 may be formed to extend to an end face (not shown) connecting the first main surface 11 and the second main surface 12 of the semiconductor substrate 1. In this way, charges can be made to flow from the end face of the semiconductor substrate 1. As a result, charges are not accumulated in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be further suppressed.

[0032] As described above, the semiconductive insulating layer 3 may be formed on the semiconductor substrate 1 so as to cover the first main surface 11 and the gate electrode 2b in a plan view of the first main surface 11. This increases the contact area between the semiconductive insulating layer 3 and the semiconductor substrate 1, allowing more charge to flow to the semiconductor substrate 1. As a result, charge is not accumulated in the gate insulating film 2a, and deterioration of the gate insulating film 2a can be suppressed.

[0033] The thickness t in the z direction of the semiconductive insulating layer 3 may be 50 nm or more. This allows for stable control of the film thickness of the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a.

[0034] The thickness t of the semiconductive insulating layer 3 in the z direction may be 100 nm or less. In this way, an increase in the load capacitance of the semiconductor device 100a can be suppressed. In addition, stress applied to the underlayer of the semiconductive insulating layer 3 is reduced, and the occurrence of cracks in the underlayer can be suppressed. In addition, stress applied to the semiconductor substrate 1 is reduced, and warping of the semiconductor substrate 1 can be suppressed. As a result, the semiconductor device 100a can be stably manufactured.

[0035] <Method of Manufacturing Semiconductor Device> A method for manufacturing the semiconductor device 100a according to the present embodiment will be described below. Fig. 3 is a flowchart of the method for manufacturing the semiconductor device 100a according to the first embodiment. Figs. 4 to 16 are schematic cross-sectional views showing a process of the method for manufacturing the semiconductor device 100a according to the first embodiment.

[0036] First, a step (S1a) of preparing a semiconductor substrate 1 is performed. In this step (S1a), as shown in Fig. 4, the semiconductor substrate 1 is prepared as a silicon wafer, which is a semiconductor material. The conductivity type of the semiconductor substrate 1 may be either n-type or p-type. In the method for manufacturing the semiconductor device 100a according to the first embodiment, the conductivity type of the semiconductor substrate 1 is assumed to be n-type.

[0037] Next, a step (S2a) of forming a first semiconductive insulating layer 3a is performed. In this step (S2a), as shown in FIG. 5, the first semiconductive insulating layer 3a is formed on the semiconductor substrate 1. The first semiconductive insulating layer 3a is formed by plasma CVD. The material constituting the first semiconductive insulating layer 3a may be, for example, a material containing at least one of semiconductive silicon nitride (SInSiN) and silicon dioxide (SiO2).

[0038] Next, a step (S3a) of rotating the semiconductor substrate 1 is performed. In this step (S3a), as shown in FIG. 6, the semiconductor substrate 1 is rotated while flowing either gas or water to clean the semiconductor substrate 1. The first semiconductive insulating layer 3a is charged by friction between the surface of the semiconductor substrate 1 on which the first semiconductive insulating layer 3a is formed and either gas, water, or a coating film. Conventionally, carbon dioxide (CO2) is added to increase the conductivity of the gas and suppress charging due to electric charges, but in the manufacturing method of the semiconductor device 100a according to the first embodiment, it is not necessary to add carbon dioxide (CO2) in this step (S3). In other words, charging in the first semiconductive insulating layer 3a can be suppressed without flowing carbon dioxide (CO2).

[0039] Next, a step (S4a) of injecting impurities into the semiconductor substrate 1 is performed. In this step (S4a), as shown in FIG. 7, a resist 71 is formed on the first semiconductive insulating layer 3a. Thereafter, the impurities are injected into the semiconductor substrate 1. In this way, as shown in FIG. 8, a diffusion layer 13 is formed on the first main surface 11 of the semiconductor substrate 1. As shown in FIG. 8, in a plan view of the first main surface 11, the diffusion layer 13 is formed in an area where the resist 71 is not formed. When the conductivity type of the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layer 13 may be p-type. When the conductivity type of the semiconductor substrate 1 is p-type, the conductivity type of the diffusion layer 13 may be n-type. In this step as well, the charge resulting from the impurity injection step can be removed via the first semiconductive insulating layer 3a.

[0040] Next, a step (S5a) of removing the first semi-conductive insulating layer 3a is performed. In this step (S5a), as shown in FIG. 9, the resist 71 and the first semi-conductive insulating layer 3a are removed by etching. In this step (S5a), as described later, it is also possible to remove only the resist 71 and not the first semi-conductive insulating layer 3a (not shown). If the first semi-conductive insulating layer 3a is not removed in this step (S5a), the first semi-conductive insulating layer 3a constitutes the semi-conductive insulating layer 3.

[0041] Next, a step (S6a) of forming a gate insulating film 2a is performed. In this step (S6a), as shown in FIG. 10, the semiconductor substrate 1 is heated in an atmosphere containing oxygen to form the gate insulating film 2a on the first main surface 11. The material constituting the gate insulating film 2a is, for example, silicon dioxide (SiO2). In order to ensure the insulating properties of the gate insulating film 2a, the first semiconductive insulating layer 3a located between the gate insulating film 2a and the first main surface 11 of the semiconductor substrate 1 may be removed in the step (S4a) of implanting impurities into the semiconductor substrate 1.

[0042] Next, a step (S7a) of forming a gate electrode 2b is performed. In this step (S7a), as shown in Fig. 11, polysilicon is deposited on the gate insulating film 2a by CVD to form the gate electrode 2b. The polysilicon is doped with n-type or p-type impurities.

[0043] Next, a step (S8a) of forming a second semiconductive insulating layer 3b is performed. In this step (S8a), as shown in FIG. 12, the second semiconductive insulating layer 3b is formed on the semiconductor substrate 1. The second semiconductive insulating layer 3b is formed by plasma CVD. The material constituting the second semiconductive insulating layer 3b may be, for example, the same as the material constituting the first semiconductive insulating layer 3a, or may be different from the material constituting the first semiconductive insulating layer 3a.

[0044] The second semi-conductive insulating layer 3b constitutes the semi-conductive insulating layer 3. When the step (S5a) of removing the first semi-conductive insulating layer 3a is not performed, the semi-conductive insulating layer 3 disposed between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 has a two-layer structure of the first semi-conductive insulating layer 3a and the second semi-conductive insulating layer 3b.

[0045] If the material constituting the second semiconductive insulating layer 3b is the same as the material constituting the first semiconductive insulating layer 3a, it becomes difficult to confirm the boundary between the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b. As a result, the semiconductive insulating layer 3 appears as a single layer structure. However, the thickness t2 in the z direction of the semiconductive insulating layer 3 arranged between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 is thinner than the thickness t1 in the z direction of the semiconductive insulating layer 3 arranged between the gate electrode 2b and the interlayer insulating layer 4. Therefore, by comparing the thickness t2 in the z direction of the semiconductive insulating layer 3 arranged between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 with the thickness t1 in the z direction of the semiconductive insulating layer 3 arranged between the gate electrode 2b and the interlayer insulating layer 4, it is possible to determine whether the semiconductive insulating layer 3 has a two-layer structure of the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b.

[0046] The thickness (t1 and t2) of the semiconductive insulating layer 3 in the z direction may be, for example, not less than 50 nm and not more than 100 nm.

[0047] Next, a step (S9a) of forming an interlayer insulating layer 4 is performed. In this step (S9a), as shown in Fig. 13, an interlayer insulating layer 4 is formed on the semiconductive insulating layer 3. The material constituting the interlayer insulating layer 4 may be, for example, either silicon dioxide (SiO2) or tetraethyl orthosilicate (TEOS).

[0048] Next, a step (S10a) of forming a contact hole H is performed. In this step (S10a), as shown in FIG. 14, a resist 72 is formed on surface 41 of interlayer insulating layer 4. Resist 72 has an opening 72a. In a plan view of surface 41, opening 72a is disposed at a position overlapping gate electrode 2b. By etching interlayer insulating layer 4 and semiconductive insulating layer 3 using resist 72 as a mask, a first contact hole h1 is formed as shown in FIG. 15. First contact hole h1 reaches gate electrode 2b from surface 41.

[0049] Although not shown, the resist 72 may have an opening 72b. In a plan view of the surface 41, the opening 72b is disposed at a position different from the opening 72a. The interlayer insulating layer 4 and the semiconductive insulating layer 3 are etched using the resist 72 as a mask to form a second contact hole h2. The second contact hole h2 extends from the surface 41 to the first main surface 11 of the semiconductor substrate 1. The resist 72 is then removed.

[0050] Next, a step (S11a) of forming electrical wiring 5 is performed. In this step (S11a), electrical wiring 5 is formed to fill contact hole H, as shown in Fig. 16. First electrical wiring 5a is connected to gate electrode 2b, inner circumferential surface hs1 of first contact hole h1, and surface 41 of interlayer insulating layer 4 via barrier metal 6. Although not shown, second electrical wiring 5b is connected to first main surface 11 of semiconductor substrate 1, inner circumferential surface hs2 of second contact hole h2, and surface 41 of interlayer insulating layer 4 via barrier metal 6.

[0051] The material constituting the electrical wiring 5 may be, for example, a metal. The electrical wiring 5 may be a single layer, or may have a structure in which multiple layers are laminated in the z direction. Specifically, the electrical wiring 5 is formed by laminating an aluminum alloy (for example, an Al-Si alloy) on the surface 41 of the interlayer insulating layer 4 and the inner surface of the contact hole H using PVD (Physical Vapor Deposition) such as sputtering and deposition. A nickel alloy (Ni alloy) may be formed on the aluminum alloy using an electroless plating process or an electrolytic plating process. In this manner, the electrical wiring 5 may be formed by laminating the aluminum alloy and the nickel alloy.

[0052] By using plating, it is easy to form thick electrical wiring 5. Therefore, by forming thick electrical wiring 5, the heat capacity of the electrical wiring 5 increases, and the heat resistance of the semiconductor device 100a is improved.

[0053] The electrical wiring 5 is formed on a barrier metal 6. That is, the barrier metal 6 is formed on the contact interface between the electrical wiring 5 and the interlayer insulating layer 4, on the contact interface between the electrical wiring 5 and the gate electrode 2b, and on the contact interface between the electrical wiring 5 and the semiconductor substrate 1. The material constituting the barrier metal 6 is, for example, either titanium (Ti) or titanium nitride (TiN).

[0054] The thickness t of the semiconductive insulating layer 3 in the z direction may be 100 nm or less.

[0055] Next, a dicing step (S12a) is performed. In this step (S12a), the semiconductor substrate 1 is divided into individual pieces by either laser dicing or blade dicing, thereby manufacturing the semiconductor devices 100a shown in Fig. 1. The semiconductor substrate 1 is cut into a matrix shape to manufacture a plurality of semiconductor devices 100a.

[0056] In this way, charges generated during the manufacturing process of the semiconductor device 100a can be made to flow to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, during the manufacturing process of the semiconductor device 100a, charging of the first semiconductive insulating layer 3a due to friction between the first main surface 11 of the semiconductor substrate 1 and any of gas, water, and coating film in the step (S3a) of rotating the semiconductor substrate 1, and charging due to an ion beam in the step (S4a) of implanting impurities into the semiconductor substrate 1, that is, charging due to positive charges generated by the transfer of positive ions from the ion beam to the semiconductor substrate 1, are suppressed. Also, the addition of carbon dioxide (CO2) is not required in the step (S3a) of rotating the semiconductor substrate 1.

[0057] As a result, it is possible to obtain a semiconductor device 100a in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0058] Moreover, the electrical resistivity of the semiconductive insulating layer 3 is temperature dependent. Therefore, in a high temperature state such as an etching process and an ion implantation process, the semiconductive insulating layer 3 has high conductivity. Therefore, during the manufacturing process of the semiconductor device 100a, the generated charge can flow to the semiconductor substrate 1. On the other hand, in a low temperature state that is a relatively low temperature such as room temperature or the temperature during operation of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulation properties. Therefore, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the manufacturing of the semiconductor device 100a is completed.

[0059] <Action and effect> A semiconductor device 100a according to the present disclosure includes a semiconductor substrate 1, a gate insulating film 2a, a gate electrode 2b, a first electrical wiring 5a, and a semiconductive insulating layer 3. The gate insulating film 2a is formed on the semiconductor substrate 1. The gate electrode 2b is formed on the semiconductor substrate 1 via the gate insulating film 2a. The first electrical wiring 5a is connected to the gate electrode 2b. The semiconductive insulating layer 3 is connected to at least one of the gate electrode 2b and the first electrical wiring 5a.

[0060] In this way, the charge generated during the manufacturing process of the semiconductor device 100a can be flowed to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, during the manufacturing process of the semiconductor device 100a, charging of the first semiconductive insulating layer 3a due to friction between the first main surface 11 of the semiconductor substrate 1 and any of gas, water, and coating film in the step (S3a) of rotating the semiconductor substrate 1, charging due to an ion beam in the step (S4a) of implanting impurities into the semiconductor substrate 1, and the like are suppressed. Also, the addition of carbon dioxide (CO2) is not required in the step (S3a) of rotating the semiconductor substrate 1. As a result, it is possible to obtain the semiconductor device 100a in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0061] Moreover, the electrical resistivity of the semiconductive insulating layer 3 is temperature dependent. Therefore, in high temperature conditions such as etching and ion implantation, the semiconductive insulating layer 3 has high conductivity. Therefore, during the manufacturing process of the semiconductor device 100a, the generated charge can flow to the semiconductor substrate 1. On the other hand, at room temperature or in a low temperature condition such as during the operation of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulating properties. Therefore, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the manufacturing of the semiconductor device 100a is completed.

[0062] In the semiconductor device 100a, the electrical resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 27°C is greater than the electrical resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 150°C.

[0063] In this way, the semiconductive insulating layer 3 has high conductivity during the manufacturing process of the semiconductor device 100a. Therefore, the charge generated during the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, in a low temperature state, such as during the operation of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulating properties. Therefore, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the manufacturing of the semiconductor device 100a is completed.

[0064] In the semiconductor device 100a, the electrical resistivity of the semiconductive insulating layer 3 at a temperature of 27° C. is 1×10 11 Ωcm or more 1×10 13 It is less than Ωcm.

[0065] In this way, the semiconductive insulating layer 3 has high insulating properties at room temperature during operation of the semiconductor device 100a, etc. Therefore, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the manufacturing of the semiconductor device 100a is completed.

[0066] In the semiconductor device 100a, the electrical resistivity of the semiconductive insulating layer 3 at a temperature of 150° C. is 1×10 10 It is less than Ωcm.

[0067] In this way, the semiconductive insulating layer 3 can have high conductivity during the manufacturing process of the semiconductor device 100a. Therefore, the electric charge generated during the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1.

[0068] In the above-described semiconductor device 100a, the material constituting the semiconductive insulating layer 3 includes at least one of semiconductive silicon nitride and silicon dioxide.

[0069] In this way, the semiconductive insulating layer 3 can have high conductivity during the manufacturing process of the semiconductor device 100a. Therefore, the charge generated during the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, in a low temperature state, such as during the operation of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulating properties. Therefore, it is not necessary to remove the semiconductive insulating layer 3 during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the manufacturing of the semiconductor device 100a is completed.

[0070] In the semiconductor device 100a, the thickness t of the semiconductive insulating layer 3 is not less than 50 nm and not more than 100 nm.

[0071] In this way, the film thickness of the semiconductive insulating layer 3 can be stably controlled during the manufacturing process of the semiconductor device 100a. Furthermore, an increase in the load capacitance of the semiconductor device 100a can be suppressed. Furthermore, stress applied to the underlayer of the semiconductive insulating layer 3 is reduced, and the occurrence of cracks in the underlayer can be suppressed. Furthermore, stress applied to the semiconductor substrate 1 is reduced, and warping of the semiconductor substrate 1 can be suppressed. As a result, the semiconductor device 100a can be stably manufactured.

[0072] The semiconductor device 100a further includes an interlayer insulating layer 4. The interlayer insulating layer 4 is disposed on the semiconductor substrate 1. The interlayer insulating layer 4 has a surface 41. The surface 41 is located on the opposite side to the surface facing the semiconductor substrate 1 and the gate electrode 2b. A first contact hole h1 is formed in the interlayer insulating layer 4. The first contact hole h1 reaches the gate electrode 2b from the surface 41. The first electrical wiring 5a is connected to an inner circumferential surface hs1 of the first contact hole h1 and the surface 41.

[0073] In this manner, charges generated during the manufacturing process of the semiconductor device 100a can be flowed to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, it is possible to obtain the semiconductor device 100a in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0074] In the above-described semiconductor device 100a, the semiconductive insulating layer 3 has a first layer 31 and a second layer 32. In a plan view of the semiconductor substrate 1, the first layer 31 and the second layer 32 are disposed spaced apart from each other.

[0075] In this way, charge can be passed through the semiconductor substrate 1 while suppressing an increase in the load capacitance of the semiconductor device 100a. Furthermore, the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed in a stripe shape is smaller than the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed over the entire first main surface 11. As a result, warping of the semiconductor substrate 1 can be suppressed.

[0076] A manufacturing method of a semiconductor device 100a according to the present disclosure includes a step (S1a) of preparing a semiconductor substrate 1, a step (S2a) of forming a first semi-conductive insulating layer 3a on the semiconductor substrate 1, and a step (S3a) of rotating the semiconductor substrate 1 after the step (S2a) of forming the first semi-conductive insulating layer 3a.

[0077] In this way, charges generated during the manufacturing process of the semiconductor device 100a can be flowed to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, charging of the first semiconductive insulating layer 3a due to friction between the surface of the semiconductor substrate 1 on which the first semiconductive insulating layer 3a is formed and any of gas, water, and coating film in the step (S3a) of rotating the semiconductor substrate 1 is suppressed. Also, in the step (S3a) of rotating the semiconductor substrate 1, it is not necessary to add carbon dioxide (CO2) to the gas. As a result, it is possible to obtain a semiconductor device 100a in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0078] The manufacturing method of the above-mentioned semiconductor device 100a further includes a step (S4a) of injecting impurities into the semiconductor substrate 1 after the step (S2a) of forming the first semi-conductive insulating layer 3a, a step (S5a) of removing the first semi-conductive insulating layer 3a after the step (S4a) of injecting the impurities, a step (S7a) of forming a gate electrode 2b on the semiconductor substrate 1 after the step (S5a) of removing the first semi-conductive insulating layer 3a, and a step (S8a) of forming a second semi-conductive insulating layer 3b to cover the gate electrode 2b after the step (S7a) of forming the gate electrode 2b.

[0079] In this manner, charges generated during the manufacturing process of the semiconductor device 100a can be flowed to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. Specifically, charging by an ion beam in the step (S4a) of implanting impurities into the semiconductor substrate 1 is suppressed. As a result, it is possible to obtain the semiconductor device 100a in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0080] Embodiment 2 <Configuration of Semiconductor Device> Fig. 17 is a schematic cross-sectional view of a semiconductor device 100b according to a second embodiment. Fig. 17 corresponds to Fig. 1. The semiconductor device 100b shown in Fig. 17 basically has the same configuration as the semiconductor device 100a shown in Fig. 1, but differs in that it is a semiconductor device 100b for a power semiconductor, not the semiconductor device 100a for an integrated circuit. When the semiconductor device 100b is a power semiconductor, a drain electrode 8 may be formed on the second main surface 12 of the semiconductor substrate 1, as necessary.

[0081] The material constituting the drain electrode 8 may include at least one of an aluminum silicon alloy, titanium, nickel, and gold, for example. The drain electrode 8 may be formed by stacking a plurality of metals such as an aluminum silicon alloy, titanium, nickel, and gold. Also, a metal film may be further formed on a metal film formed by PVD by electroless plating or electrolytic plating. In this way, the drain electrode 8 may be formed by stacking a metal film formed by PVD and a metal film formed by electroless plating or electrolytic plating.

[0082] The semiconductive insulating layer 3 may be formed on a surface 41 of the interlayer insulating layer 4. From a different perspective, the semiconductive insulating layer 3 may be disposed at a position sandwiched between the first electrical wiring 5a and the interlayer insulating layer 4 in the z direction, as shown in FIG.

[0083] <Method of Manufacturing Semiconductor Device> A method for manufacturing the semiconductor device 100b according to the present embodiment will now be described. FIG. 18 is a flowchart of the method for manufacturing the semiconductor device 100b according to the second embodiment. FIG. 19 is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device 100b according to the second embodiment. First, steps similar to those shown in FIG. 4 to FIG. 11 in the method for manufacturing the semiconductor device 100a according to the first embodiment are performed. That is, steps from the step (S1b) of preparing a semiconductor substrate 1 to the step (S7b) of forming a gate electrode 2b are performed.

[0084] Next, a step (S8b) of forming an interlayer insulating layer 4 is performed. Specifically, the interlayer insulating layer 4 is formed so as to cover the first main surface 11 and the gate electrode 2b of the semiconductor substrate 1. That is, the back surface 42 of the interlayer insulating layer 4 is connected to the first main surface 11 and the gate electrode 2b.

[0085] Next, a step (S9b) of forming a second semiconductive insulating layer 3b is performed. Specifically, the second semiconductive insulating layer 3b is formed so as to cover the surface 41 of the interlayer insulating layer 4. The second semiconductive insulating layer 3b may be formed on an end face 45 connecting the surface 41 and the back surface 42 of the interlayer insulating layer 4 and on an end face 15 connecting the first main surface 11 and the second main surface 12 of the semiconductor substrate 1 (see FIG. 19). The shape of the semiconductive insulating layer 3 may be a stripe shape in which a plurality of layers are arranged spaced apart from each other in the y direction in a plan view of the surface 41. Each of the plurality of layers may be formed on the end face 45 of the interlayer insulating layer 4 and the end face 15 of the semiconductor substrate 1.

[0086] Next, a step (S10b) of forming a contact hole H is performed. In this step (S10b), a resist 72 is formed on the second semi-conductive insulating layer 3b. The resist 72 has an opening 72a. In a plan view of the surface 41, the opening 72a is disposed at a position overlapping the gate electrode 2b. The interlayer insulating layer 4 and the semi-conductive insulating layer 3 are etched using the resist 72 as a mask, thereby forming a first contact hole h1. The first contact hole h1 reaches the gate electrode 2b from the surface 41.

[0087] In the step (S9b) of forming the second semi-conductive insulating layer 3b, when the second semi-conductive insulating layer 3b is formed on the end face 45 of the interlayer insulating layer 4 and on the end face 15 of the semiconductor substrate 1 as shown in FIG. 19, the second contact hole h2 reaching the first main surface 11 of the semiconductor substrate 1 from the upper surface of the semi-conductive insulating layer 3 does not need to be formed as described later.

[0088] Next, a step (S11b) of forming electrical wiring 5 is performed. In this step (S11b), electrical wiring 5 is formed to fill contact hole H. First electrical wiring 5a is connected via barrier metal 6 to gate electrode 2b, inner circumferential surface hs1 of first contact hole h1, and an upper surface of second semi-conductive insulating layer 3b.

[0089] The material constituting the electrical wiring 5 may be, for example, a metal. The electrical wiring 5 may be a single layer, or may have a structure in which multiple layers are laminated in the z direction. Specifically, the electrical wiring 5 is formed by depositing an aluminum alloy (for example, an Al-Si alloy) on the surface 41 of the interlayer insulating layer 4 and the inner surface of the contact hole H using PVD (Physical Vapor Deposition) such as sputtering and deposition. A nickel alloy (Ni alloy) may be formed on the aluminum alloy using electroless plating or electrolytic plating. In this way, the aluminum alloy and the nickel alloy may be laminated to form the electrical wiring 5.

[0090] By using plating, it is easy to form thick electrical wiring 5. Therefore, by forming thick electrical wiring 5, the heat capacity of the electrical wiring 5 increases, and the heat resistance of the semiconductor device 100a is improved.

[0091] The formation of the nickel alloy by plating may be carried out after the step (S12b) of forming the drain electrode 8, which will be described later.

[0092] Next, a step (S12b) of forming a drain electrode 8 is performed. In this step (S12b), as shown in Fig. 19, the drain electrode 8 is formed on the second main surface 12 of the semiconductor substrate 1. When the semiconductor device 100b is manufactured for use as a power semiconductor, this step (S12b) is performed. The drain electrode 8 is formed by depositing an aluminum silicon alloy, titanium, or the like on the second main surface 12 by PVD such as sputtering or vapor deposition.

[0093] The second semi-conductive insulating layer 3b is connected to the drain electrode 8. In this manner, even in the semiconductor device 100b in which the second contact hole h2 connected to the semiconductor substrate 1 is not formed, it is possible to allow electric charges to flow to the drain electrode 8.

[0094] The material constituting the drain electrode 8 may include at least one of an aluminum silicon alloy, titanium, nickel, and gold, for example. The drain electrode 8 may be formed by stacking a plurality of metals such as an aluminum silicon alloy, titanium, nickel, and gold. Also, a metal film may be further formed on a metal film formed by PVD by electroless plating or electrolytic plating. In this way, the drain electrode 8 may be formed by stacking a metal film formed by PVD and a metal film formed by electroless plating or electrolytic plating.

[0095] Next, a dicing step (S13b) is carried out. In this manner, the semiconductor device 100b according to the second embodiment as shown in FIG.

[0096] Embodiment 3 <Configuration of Semiconductor Device> FIG. 20 is a schematic cross-sectional view of a semiconductor device 100c according to a third embodiment. FIG. 20 corresponds to FIG. 1. The semiconductor device 100c shown in FIG. 20 basically has the same configuration as the semiconductor device 100a shown in FIG. 1, but is different in that the semiconductive insulating layer 3 is formed on the surface 41 of the interlayer insulating layer 4. The semiconductive insulating layer 3 is not directly connected to the semiconductor substrate 1. Therefore, a second contact hole h2 is formed from the upper surface of the semiconductive insulating layer 3 to reach the first main surface 11 of the semiconductor substrate 1. Specifically, as shown in FIG. 20, the first contact hole h1 and the second contact hole h2 are arranged to be spaced apart from each other.

[0097] The second electrical wiring 5b is electrically connected to the semiconductor substrate 1. The second electrical wiring 5b is connected to the first main surface 11 of the semiconductor substrate 1, the inner circumferential surface hs2 of the second contact hole h2, and the upper surface of the semiconductive insulating layer 3 via a barrier metal 6.

[0098] When the semiconductive insulating layer 3 is formed on the surface 41 of the interlayer insulating layer 4, a second contact hole h2 that reaches the first main surface 11 of the semiconductor substrate 1 from the upper surface of the semiconductive insulating layer 3 can be formed to form a second electrical wiring 5b that is electrically connected to the semiconductor substrate 1. In this way, charges can be caused to flow to the semiconductor substrate 1. As a result, deterioration of the gate insulating film 2a can be further suppressed.

[0099] <Action and effect> In the semiconductor device 100c, the semiconductive insulating layer 3 is connected to the first electrical wiring 5a and the surface 41.

[0100] In this manner, charges generated during the manufacturing process of the semiconductor device 100c can be flowed to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, the semiconductor device 100c can be obtained in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0101] The semiconductor device 100c further includes a second electrical wiring 5b. The second electrical wiring 5b is connected to the semiconductive insulating layer 3. A second contact hole h2 is formed in the interlayer insulating layer 4. The second contact hole h2 reaches the semiconductor substrate 1 from the surface 41. The second electrical wiring 5b is connected to an inner surface hs2 of the second contact hole h2 and the surface 41.

[0102] In this manner, charges generated during the manufacturing process of the semiconductor device 100c can be flowed to the outer periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, the semiconductor device 100c can be obtained in which charges are not accumulated in the gate insulating film 2a and deterioration of the gate insulating film 2a is suppressed.

[0103] Embodiment 4 <Configuration of Semiconductor Device> FIG. 21 is a schematic cross-sectional view of a semiconductor device 100d according to a fourth embodiment. FIG. 21 corresponds to FIG. 1. The semiconductor device 100d shown in FIG. 21 basically has the same configuration as the semiconductor device 100a shown in FIG. 1, but is different in that the semiconductive insulating layer 3 is formed so as to cover the surface 41 and the first electrical wiring 5a in a plan view of the surface 41 of the interlayer insulating layer 4. In this way, a part of the electric charge can be made to flow from the upper surface of the first electrical wiring 5a to the outside. As a result, deterioration of the gate insulating film 2a can be further suppressed.

[0104] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. Unless inconsistent, at least two of the embodiments disclosed herein may be combined. The basic scope of the present disclosure is indicated by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0105] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate via the gate insulating film; a first electrical wiring connected to the gate electrode; a semiconductive insulating layer connected to at least one of the gate electrode and the first electrical wiring. (Appendix 2) 2. The semiconductor device of claim 1, wherein the electrical resistivity of the semiconductive insulating layer when the temperature of the semiconductive insulating layer is 27°C is greater than the electrical resistivity of the semiconductive insulating layer when the temperature of the semiconductive insulating layer is 150°C. (Appendix 3) The electrical resistivity of the semiconductive insulating layer at a temperature of 27° C. is 1×10 11 Ωcm or more 1×10 13 3. The semiconductor device according to claim 1, wherein the resistivity is Ωcm or less. (Appendix 4) The electrical resistivity of the semiconductive insulating layer at a temperature of 150° C. is 1×10 10 4. The semiconductor device according to claim 1, wherein the resistance of the semiconductor device is Ωcm or less. (Appendix 5) 5. The semiconductor device according to claim 1, wherein a material constituting the semiconductive insulating layer includes at least one of semiconductive silicon nitride and silicon dioxide. (Appendix 6) 6. The semiconductor device according to claim 1, wherein the semiconductive insulating layer has a thickness of 50 nm or more and 100 nm or less. (Appendix 7) An interlayer insulating layer disposed on the semiconductor substrate, the interlayer insulating layer has a surface located opposite a surface facing the semiconductor substrate and the gate electrode; a first contact hole is formed in the interlayer insulating layer, the first contact hole extending from the surface to the gate electrode; 7. The semiconductor device according to claim 1, wherein the first electrical wiring is connected to an inner circumferential surface and the front surface of the first contact hole. (Appendix 8) 8. The semiconductor device of claim 7, wherein the semiconductive insulating layer is connected to the first electrical wiring and the surface. (Appendix 9) Further comprising a second electrical wiring connected to the semiconductive insulating layer; a second contact hole is formed in the interlayer insulating layer, the second contact hole extending from the surface to the semiconductor substrate; 9. The semiconductor device according to claim 7, wherein the second electrical wiring is connected to an inner circumferential surface and the front surface of the second contact hole. (Appendix 10) the semiconductive insulating layer has a first layer and a second layer; 10. The semiconductor device according to claim 1, wherein the first layer and the second layer are spaced apart from each other in a plan view of the semiconductor substrate. (Appendix 11) Providing a semiconductor substrate; forming a first semiconductive insulating layer on the semiconductor substrate; a step of rotating the semiconductor substrate after the step of forming the first semiconductive insulating layer. (Appendix 12) implanting ions into the semiconductor substrate after the step of forming the first semiconductive insulating layer; removing the first semiconductive insulating layer after the step of implanting ions; forming a gate electrode on the semiconductor substrate after removing the first semiconductive insulating layer; 12. The method for manufacturing a semiconductor device according to claim 11, further comprising, after the step of forming the gate electrode, forming a second semiconductive insulating layer so as to cover the gate electrode. [Explanation of symbols]

[0106] 1 semiconductor substrate, 2a gate insulating film, 2b gate electrode, 3 semiconductive insulating layer, 3a first semiconductive insulating layer, 3b second semiconductive insulating layer, 4 interlayer insulating layer, 5 electrical wiring, 5a first electrical wiring, 5b second electrical wiring, 6 barrier metal, 8 drain electrode, 11 first main surface, 12 second main surface, 13 diffusion layer, 15, 45 end surface, 31 first layer, 32 second layer, 41 front surface, 42 back surface, 71, 72 resist, 72a, 72b opening, 100a, 100b, 100c, 100d semiconductor device, H contact hole, h1 first contact hole, h2 second contact hole, hs1, hs2 inner peripheral surface.

Claims

1. A semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate via the gate insulating film; a first electrical wiring connected to the gate electrode; a semiconductive insulating layer connected to at least one of the gate electrode and the first electrical wiring.

2. 2. The semiconductor device according to claim 1, wherein the electrical resistivity of said semiconductive insulating layer when the temperature of said semiconductive insulating layer is 27° C. is greater than the electrical resistivity of said semiconductive insulating layer when the temperature of said semiconductive insulating layer is 150° C.

3. The electrical resistivity of the semiconductive insulating layer at a temperature of 27° C. is 1×10 １１ Ωcm or more 1×10 １３ The semiconductor device according to claim 2 , wherein the resistivity is Ωcm or less.

4. The electrical resistivity of the semiconductive insulating layer at a temperature of 150° C. is 1×10 １０ The semiconductor device according to claim 3 , wherein the resistivity is Ωcm or less.

5. 5. The semiconductor device according to claim 1, wherein a material constituting said semiconductive insulating layer includes at least one of semiconductive silicon nitride and silicon dioxide.

6. 5. The semiconductor device according to claim 1, wherein the semiconductive insulating layer has a thickness of 50 nm or more and 100 nm or less.

7. An interlayer insulating layer disposed on the semiconductor substrate, the interlayer insulating layer has a surface located opposite a surface facing the semiconductor substrate and the gate electrode; a first contact hole is formed in the interlayer insulating layer, the first contact hole extending from the surface to the gate electrode; 5. The semiconductor device according to claim 1, wherein the first electrical wiring is connected to an inner circumferential surface and the front surface of the first contact hole.

8. The semiconductor device according to claim 7 , wherein the semiconductive insulating layer is connected to the first electrical wiring and the front surface.

9. A second electrical wiring connected to the semiconductive insulating layer, a second contact hole is formed in the interlayer insulating layer, the second contact hole extending from the surface to the semiconductor substrate; The semiconductor device according to claim 7 , wherein the second electrical wiring is connected to an inner circumferential surface and the front surface of the second contact hole.

10. the semiconductive insulating layer has a first layer and a second layer; The semiconductor device according to claim 1 , wherein the first layer and the second layer are spaced apart from each other in a plan view of the semiconductor substrate.

11. Providing a semiconductor substrate; forming a first semiconductive insulating layer over the semiconductor substrate; a step of rotating the semiconductor substrate after the step of forming the first semiconductive insulating layer.

12. implanting ions into the semiconductor substrate after the step of forming the first semiconductive insulating layer; removing the first semiconductive insulating layer after the step of implanting ions; forming a gate electrode on the semiconductor substrate after removing the first semiconductive insulating layer; 12. The method for manufacturing a semiconductor device according to claim 11, further comprising the step of forming a second semiconductive insulating layer so as to cover the gate electrode after the step of forming the gate electrode.

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