Method for manufacturing semiconductor device

Abstract

To improve the performance capability of a semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes a step in which after a wire bonding step, determination of acceptability is made as to whether or not the whole of an end 51E of a wire 51 is located within a bonding region BR. A semiconductor chip 10 includes a plurality of opening patterns AP1, AR2 for position determination which are arranged in a region located in the periphery of a main opening OPM including the bonding region BR in a plan view. The bonding region BR forms a square whose area is smaller than the opening area of the main opening OPM in a plan view. The bonding region BR is defined by the plurality of opening patterns AP1, AR2 for position determination.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2-90634 (Patent Document 1) describes a technique relating to a semiconductor device having a bonding pad having an alignment mark made of a slit or protrusion corresponding to the positioning cross mark of a wire bonder. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2-90634 Summary of the Invention [Problem to be solved by the invention]

[0004] One of the performance indices required for a semiconductor device is reliability, which is the ability of the semiconductor device to continue to perform a function that is predetermined in specifications, etc., for a predetermined period of time.

[0005] For example, in a semiconductor device having wires connected to pads formed on the main surface of a semiconductor chip, variations in characteristics may occur due to misalignment of the bonding positions where the wires are connected.

[0006] If the misalignment of the bonding position can be detected quickly, it is possible to selectively eliminate semiconductor devices in which the characteristics have changed due to the misalignment. As a result, only semiconductor devices whose misalignment is within an allowable range, in other words, highly reliable semiconductor devices, can be selected as non-defective products.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A method for manufacturing a semiconductor device according to one embodiment includes, after a wire bonding process, a process for determining whether or not the entire bond of the wire is located within a bonding region. The semiconductor chip includes a plurality of position determination opening patterns arranged in a region located around a main opening including the bonding region in a plan view. The bonding region is a quadrangle having an area smaller than the opening area of ​​the main opening in a plan view. The bonding region is defined by the plurality of position determination opening patterns and a second position determination opening pattern.

[0009] A semiconductor device according to another embodiment has a main surface, a pad formed on the main surface, an insulating film having a main opening exposing a portion of the pad, and a plurality of opening patterns for position determination arranged in a region surrounding the main opening in a plan view, the plurality of opening patterns for position determination including a first opening pattern for position determination arranged at a position closest to a first corner among a first corner, a second corner, a third corner, and a fourth corner of the main opening, and a second opening pattern for position determination arranged at a position closest to the third corner or the fourth corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening. Effect of the Invention

[0010] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram showing an example of a circuit configuration of a semiconductor device including a power transistor and a control circuit for controlling the power transistor; [Diagram 2] 2 is a perspective plan view showing a structural example of the semiconductor device shown in FIG. 1. [Diagram 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. [Figure 4] 4 is a flow chart showing an example of a manufacturing process for the semiconductor device shown in FIGS. 1 to 3. FIG. [Diagram 5] 5 is an enlarged plan view showing a part of the lead frame prepared in the lead frame preparing step shown in FIG. 4. [Figure 6] 5 is a plan view (top view) of a semiconductor chip prepared in the semiconductor chip preparation step of FIG. 4. [Figure 7] 7 is a plan view (top view) of a semiconductor chip different from that in FIG. 6 prepared in the semiconductor chip preparation step in FIG. 4. [Figure 8] FIG. 7 is an enlarged cross-sectional view taken along line BB in FIG. 6. [Figure 9] 5 is an explanatory diagram showing an example of detailed steps of the wire bonding step shown in FIG. 4. FIG. [Figure 10] 5 is an explanatory diagram illustrating a schematic configuration example of a wire bonding apparatus used in the wire bonding step illustrated in FIG. 4. [Figure 11] FIG. 4 is an enlarged cross-sectional view showing a first bonding step in a wire forming process. [Figure 12] 11 is a plan view showing a schematic operation of a wedge tool in a bent portion forming step of a wire forming process. FIG. [Figure 13] 10 is an explanatory diagram showing an example of an image displayed on a monitor during "teaching" performed in the bonding region specifying step of FIG. 9; FIG. [Figure 14] 5 is an explanatory diagram showing an example of an image displayed on a monitor in the pass / fail determination step shown in FIG. 4. [Figure 15] 5 is an explanatory diagram showing details of a pass / fail determining step shown in FIG. 4. [Figure 16] 14 is an enlarged plan view showing the periphery of a main opening of a semiconductor chip which is a modified example of the semiconductor chip shown in FIG. 13. [Figure 17] FIG. 7 is an enlarged cross-sectional view taken along line CC in FIG. 6. [Figure 18] FIG. 18 is an enlarged cross-sectional view showing a modification of FIG. [Figure 19] FIG. 14 is an enlarged plan view showing another modified example of FIG. [Figure 20]FIG. 14 is an enlarged plan view showing another modified example of FIG. [Figure 21] FIG. 14 is an enlarged plan view showing another modified example of FIG. [Figure 22] 11 is a block diagram showing an example of the configuration of a determination unit shown in FIG. 10. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] (Description format, basic terms and usage in this application) In this application, the description of the embodiment is conveniently divided into multiple sections, etc., as necessary, but unless otherwise specified, these are not mutually independent and separate, and regardless of the description, each part of a single example, one is a partial detail of the other, or a partial or complete modified example, etc. In addition, as a general rule, repeated explanations of similar parts will be omitted. In addition, each component in the embodiment is not essential, unless otherwise specified, when it is theoretically limited to that number, or when it is clearly not from the context.

[0013] Similarly, in the description of the embodiments, when a material, composition, etc. is described as "X made of A," it does not exclude those containing elements other than A, unless otherwise specified or clearly indicated from the context. For example, when it comes to components, it means "X containing A as a main component." For example, when it comes to "silicon components," it goes without saying that it is not limited to pure silicon, but also includes SiGe (silicon germanium) alloys and other multi-component alloys whose main component is silicon, and components containing other additives. In addition, when it comes to gold plating, Cu layer, nickel plating, etc., it includes not only pure ones, but also components whose main components are gold, Cu, nickel, etc., unless otherwise specified.

[0014] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, it may be a number greater than that specific number, or a number less than that specific number, unless it is theoretically limited to that number or unless it is clearly different from the context.

[0015] In addition, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated as a general rule.

[0016] In the accompanying drawings, hatching and the like may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, the background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the explanation, etc. Furthermore, hatching or dot patterns may be added even if the drawing is not a cross section in order to clearly indicate that it is not a void or to clearly indicate the boundaries of the area.

[0017] In the embodiments described below, a semiconductor device called a power device or a power semiconductor device that is incorporated in a power control circuit such as a power supply circuit will be taken up as an example of a semiconductor device. The semiconductor device described below is incorporated in a power conversion circuit and functions as a switching element. A transistor incorporated in a switching circuit for power conversion is called a power transistor.

[0018] <Example of power transistor and control circuit configuration> 1 is a diagram showing an example of a circuit configuration of a semiconductor device including a power transistor and a control circuit for controlling the power transistor. The power transistor shown in FIG 1 is, for example, a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0019] As the power transistor, in addition to the power MOSFET, modified examples can be applied. For example, the technology described below can be widely applied to a semiconductor device using an IGBT (Insulated Gate Bipolar Transistor) as the power transistor. In this case, the "source" described below is applied by reading it as "emitter".

[0020] 1, the semiconductor device PKG1 has a switching circuit CSW and a control circuit CCT. The switching circuit CSW has a main transistor TrM which is a power transistor, a sense transistor TrS, and a temperature sensor TS.

[0021] In the switching circuit CSW, the main transistor TrM is provided between a lead 44 which is a power supply terminal that supplies a power supply potential and a lead 41 (or a lead 47) which is an output terminal. This main transistor TrM functions as a switching element for turning on and off a current flowing between the power supply terminal and the output terminal.

[0022] On the other hand, the sense transistor TrS has a function of detecting the current value of the current flowing through the main transistor TrM, and the temperature sensor TS has a function of detecting the temperature of the switching circuit CSW.

[0023] Next, the control circuit CCT has a function of controlling the switching circuit CSW. This control circuit CCT includes, for example, a pre-driver that applies a gate voltage to the gate electrode of the main transistor TrM and the gate electrode of the sense transistor TrS. In Fig. 1, the control circuit CCT is electrically connected to the leads 43 and 46 that are input terminals of the semiconductor device PKG1, the lead 42 that is a ground terminal, and the lead 45 that is an output terminal for outputting the output from the control circuit CCT to the outside of the semiconductor device PKG1.

[0024] The control circuit CCT is configured to control the on / off of the main transistor TrM included in the switching circuit CSW based on a control signal input from the lead 43. That is, the control circuit CCT controls the on / off of the main transistor TrM by switching the gate voltage applied to the gate electrode of the main transistor TrM. By controlling the on / off of the main transistor TrM in this manner, it is possible to control the current supplied from the lead 41, which is an output terminal electrically connected to the source of the main transistor TrM, to a load connected to the outside of the semiconductor device PKG1.

[0025] <Semiconductor device> Next, a structural example of the semiconductor device PKG1 shown in FIG. 1 will be described. FIG. 2 is a perspective plan view showing a structural example of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view taken along the line AA in FIG. 2. In FIG. 2, in order to show an example of the layout of the components of the semiconductor device PKG1, the sealing body 60 shown in FIG. 3 is shown as a transparent plan view. In addition, the semiconductor chip 30 shown in FIG. 2 is not in the cross section taken along the line AA in FIG. 2, but in FIG. 3, the outline of the semiconductor chip 30 and the insulating adhesive material DT that adheres and fixes the semiconductor chip 30 onto the semiconductor chip 10 is shown by a dotted line. Furthermore, in FIG. 2 and FIG. 3, the position where the sense transistor TrS shown in FIG. 1 is formed is shown by a two-dot chain line.

[0026] In Fig. 2 and Fig. 3, any one of the X direction (see Fig. 2), the Y direction, and the Z direction (see Fig. 3) is described. The Y direction is a side that intersects with the X direction, and in the following description, the X direction and the Y direction are mutually perpendicular. The Z direction is a direction perpendicular to each of the X direction and the Y direction. In other words, the Z direction is a normal direction to the XY plane that includes the X direction and the Y direction. In the following description, "thickness" basically means the length in the Z direction. Also, in the following description, "planar view" basically means a planar view of the XY plane.

[0027] As shown in Figures 2 and 3, the semiconductor device PKG1 of this embodiment has a semiconductor chip 10, a die pad (metal plate, chip mounting portion, heat sink) 20 on which the semiconductor chip 10 is mounted, a semiconductor chip 30 (see Figure 2) mounted on the semiconductor chip 10, a plurality of leads (terminals) 40 which are external terminals, and a plurality of wires 50.

[0028] 3, the semiconductor device PKG1 further has a sealing body 60. The semiconductor chip 10, the semiconductor chip 30, and the multiple wires 50 are each sealed in the sealing body 60. In addition, the semiconductor chip 10, the upper surface 20t of the die pad 20, and inner lead portions (sealed portions) 40M of the multiple leads 40 (see FIG. 4) are sealed with the sealing body 60.

[0029] The die pad 20 has an upper surface (surface) 20t and a lower surface 20b opposite to the upper surface 20t. The die pad 20 is a chip mounting member for mounting a semiconductor chip 10. In the example shown in FIG. 3, the lower surface 20b of the die pad 20 is exposed from the sealing body 60. Of the die pad 20, the lower surface 20b exposed from the sealing body 60 is covered with a metal film 22. The metal film 22 is made of, for example, solder. In the case of this embodiment, the die pad 20 is connected to one of the multiple leads 40 (lead 44) ​​as shown in FIG. 2. More specifically, the lead 44 is formed integrally with the die pad 20.

[0030] The semiconductor chip 10 is mounted on an upper surface 20t of the die pad 20 via a die bond material DB. The semiconductor chip 10 includes a power transistor (in the present embodiment, a main transistor TrM shown in FIG. 1).

[0031] As shown in Fig. 3, the semiconductor chip 10 has an upper surface (main surface, front surface, face) 10t and a lower surface (main surface, back surface, face) 10b opposite to the upper surface 10t. As shown in Fig. 2, the semiconductor chip 10 has four sides (chip sides) 10s in a plan view. The four sides 10s are a side 10s1 extending in the X direction, a side 10s2 extending in the Y direction intersecting with the side 10s1 and intersecting with the X direction, a side 10s3 extending in the Y direction and positioned opposite the side 10s2, and a side 10s4 extending in the X direction and positioned opposite the side 10s1. The side 10s1 is the side that is located closest to each of the multiple leads 40 and extends in the X direction among the four sides 10s of the semiconductor chip 10. In the example shown in FIG. 2, the semiconductor chip 10 has a rectangular shape in a plan view, and is disposed so that the longer sides, 10s1 and 10s4, extend along the X direction.

[0032] 2, the semiconductor chip 10 has a plurality of pads (electrodes, electrode pads) 10P. A portion of each of the plurality of pads 10P is exposed from an insulating film IF of the semiconductor chip 10, which will be described later, on the upper surface 10t of the semiconductor chip 10.

[0033] The pads 10P include a source pad 10P1 connected to the source of the power transistor. In the example shown in Fig. 2, a part of the source pad 10P1 is exposed from the insulating film IF at two places on the upper surface 10t. The source pad 10P1 is connected to the lead 40 (the lead 41 and the lead 47 in the example shown in Fig. 2) via a wire 51. A detailed structure around the source pad 10P1 will be described later.

[0034] The pads 10P include a plurality of pads 10P2 electrically connected to the semiconductor chip 30 via wires 53. The pads 10P2 include a gate pad connected to the gate of a power transistor. At least some of the pads 10P2 are electrically connected to the sense transistor TrS. Some of the pads 10P2 are electrically connected to the temperature sensor TS shown in FIG.

[0035] 2, among the pads 10P, the exposed area of ​​the source pad 10P1 is larger than the exposed areas of the other pads 10P2. More specifically, the source pad 10P1 and the other pads 10P2 are each exposed from the insulating film IF at an opening formed in the insulating film IF. The opening area of ​​the opening exposing the source pad 10P1 from the insulating film IF is larger than the opening area of ​​the opening exposing the other pads 10P2 from the insulating film IF.

[0036] The source pad 10P1 constitutes a current path through which a large current flows, compared to the other pads 10P2. From the viewpoint of increasing the cross-sectional area of ​​the path through which the large current flows and reducing the resistance value, it is preferable to use a wire 51 connected to the source pad 10P1 having a larger wire diameter than the other wires 52. Also, from the viewpoint of reducing the resistance of the connection portion between the wire 51 and the source pad 10P1, it is preferable to increase the area of ​​the joint portion between the wire 51 and the source pad 10P1. For this reason, it is preferable that the exposed area of ​​the source pad 10P1 is large.

[0037] As shown in FIG. 3, the semiconductor chip 10 has a drain electrode DE formed on the lower surface 10b. In the present embodiment, as described above, the die pad 20 is connected to one (lead 44) ​​of the multiple leads 40. The die bond material DB is made of solder or conductive resin (for example, so-called silver paste), and the die pad 20 is electrically connected to the drain electrode DE. For this reason, in the case of the semiconductor device PKG1, the die pad 20 can be used as a current path. By using the drain electrode DE and the die pad 20 formed over the entire lower surface 10b of the semiconductor chip 10 as the current path, the resistance value of the current path connected to the drain of the power transistor can be reduced even if a large current flows.

[0038] 2 and 3, a semiconductor chip 30 is mounted on an upper surface 10t of the semiconductor chip 10. The semiconductor chip 30 is adhesively fixed onto the upper surface 10t of the semiconductor chip 10 via an insulating adhesive material DT (see FIG. 3).

[0039] The semiconductor chip 30 has a control circuit CCT (see FIG. 1) that controls a power transistor (main transistor TrM shown in FIG. 1).

[0040] 2, the semiconductor chip 30 is disposed between two openings for the source pad 10P1 in a plan view. In addition, in the example shown in Fig. 2, the position where the semiconductor chip 30 is mounted includes the center of the upper surface 10t in a plan view.

[0041] The semiconductor chip 30 has a plurality of pads (electrodes, electrode pads) 30P. Some of the plurality of pads 30P (plurality of pads 30P2 shown in FIG. 7 described later) are electrically connected to pads 10P2 of the semiconductor chip 10 via wires 52. Other parts of the plurality of pads 30P (plurality of pads 30P3 shown in FIG. 7 described later) are connected to leads 40 (each of leads 42, 43, 45, and 46 in the example shown in FIG. 2) via wires 53.

[0042] As shown in FIG. 3, the semiconductor chip 30 has an upper surface (main surface, front surface, face) 30t and a lower surface (main surface, back surface, face) 30b opposite to the upper surface 30t.

[0043] The multiple leads 40 are arranged along a side 10s1 extending along the X direction among multiple sides 10s of the semiconductor chip 10. Each of the multiple leads 40 is connected to the semiconductor chip 10 or the semiconductor chip 30 via a wire 50.

[0044] Each of the multiple leads 40 shown in FIG. 2 includes an inner lead portion 40M sealed in the sealing body 60, and an outer lead portion (outer portion, exposed portion) 40X exposed from the sealing body 60, as shown in FIG.

[0045] Each of the multiple leads 40 has an upper surface 40t and a lower surface 40b. The upper surface 40t and the lower surface 40b of the outer lead portion 40X are each covered with a metal film 48. The metal film 48 is made of, for example, solder.

[0046] The multiple wires 50 shown in FIG. 2 include a wire 51 connected to a source pad 10P1 and a lead 41 (or a lead 47) of the semiconductor chip 10. One end of each of the multiple wires 51 is connected to the source pad 10P1, and the other end is connected to a wire bonding portion 40W (see FIG. 3) of the lead 41 (or the lead 47). The wire 51 is made of, for example, aluminum. The wire 51 has a larger wire diameter than the other wires 50 (wires 52 and 53). In other words, the wire 51 is wider than the other wires 50 (wires 52 and 53). The width of the wire 50 is the length in a direction perpendicular to the direction in which the wire 50 extends.

[0047] The multiple wires 50 include multiple wires 52 connected to the pad 10P2 of the semiconductor chip 10 and the pad 30P of the semiconductor chip 30. Each of the multiple wires 52 has one end connected to the pad 10P2 and the other end connected to the pad 30P.

[0048] The multiple wires 50 include multiple wires 53 connected to the pad 30P of the semiconductor chip 30 and any one of the leads 42, 43, 45, and 46. One end of each of the multiple wires 53 is connected to the pad 30P, and the other end is connected to a wire bonding portion 40W (see FIG. 3) of any one of the leads 42, 43, 45, and 46.

[0049] Signal currents such as a control signal current and a signal current output from the sense transistor TrS flow through the wires 52 and 53. Therefore, since the current values ​​flowing through the wires 52 and 53 are smaller than those through the wire 51, the wire 50 has a smaller diameter than the wire 51.

[0050] The sealing body 60 is mainly composed of a thermosetting resin such as an epoxy resin. In this embodiment, in order to improve the characteristics of the sealing body 60 (for example, the expansion characteristics due to the thermal effect), filler particles such as silica (silicon dioxide; SiO2) particles are mixed into the resin material.

[0051] <Method of Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device shown in Figures 1 to 3 will be described. Figure 4 is a flow diagram showing an example of a manufacturing process of the semiconductor device shown in Figures 1 to 3. In the example shown in Figure 4, the manufacturing method of the semiconductor device of this embodiment includes a lead frame preparation step, a semiconductor chip preparation step, a first semiconductor chip mounting step, a second semiconductor chip mounting step, a wire bonding step, a quality determination step, a sealing step, a solder film formation step, and a singulation step.

[0052] <Lead frame preparation process> First, in the lead frame preparation step shown in Fig. 4, a lead frame LF shown in Fig. 5 is prepared. Fig. 5 is an enlarged plan view showing a part of the lead frame prepared in the lead frame preparation step shown in Fig. 4.

[0053] As shown in Fig. 5, the leadframe LF prepared in this process has a plurality of device forming parts LFd connected to a frame part (frame part) LFf. Eight device forming parts LFd are shown in Fig. 5. Each of the plurality of device forming parts LFd corresponds to one semiconductor device PKG1 shown in Fig. 1. The leadframe LF is a so-called multi-piece substrate in which a plurality of device forming parts LFd are arranged in a matrix. In this way, by using a leadframe LF having a plurality of device forming parts LFd, a plurality of semiconductor devices PKG1 (see Fig. 1) can be manufactured collectively, thereby improving manufacturing efficiency.

[0054] The lead frame LF is made of a metal material mainly composed of copper (Cu), for example. Each of the device formation parts LFd is connected to a frame part LFf. The frame part LFf is a support part that supports each member formed in the device formation part LFd until the singulation process shown in FIG.

[0055] 3 are formed in the device formation portion LFd. The die pad 20 is connected to the frame portion LFf via one of the leads 40 and is supported by the frame portion LFf. Each of the leads 40 is connected to the frame portion LFf and is supported by the frame portion LFf.

[0056] Focusing on one of the device formation portions LFd, this step can be expressed as a step of preparing a die pad having an upper surface 20t, that is, a die pad preparation step.

[0057] Further, each of the multiple leads 40 is connected to one another via a tie bar LFt1. Further, in the example shown in Fig. 5, each of the multiple die pads 20 is connected to one another via a tie bar LFt2. As shown in Fig. 5, the tie bar LFt2 is disposed on the opposite side of the multiple leads 40 with the die pad 20 interposed therebetween in the device formation section LFd.

[0058] FIG. 5 shows an example of a lead frame, and there are various modifications of the shape of the lead frame. For example, in the example shown in FIG. 5, each of the multiple leads 40 is connected to the frame portion LFf. In other words, the multiple die pads 20 are arranged at a position farther from the frame portion LFf than the multiple leads 40. As a modification of the lead frame shown in FIG. 5, the frame portion LFf may be arranged between the device forming portions LFd adjacent to each other in the Y direction. In this case, in the Y direction, the multiple leads 40 of the first device forming portion LFd are connected to one side of one frame portion LFf, and the multiple leads 40 of the second device forming portion LFd are connected to the other side of the one frame portion LFf (the side opposite to the one side in the Y direction). In this case, the tie bar LFt2 is arranged at the position of the frame portion LFf shown in FIG. 5, and the multiple device forming portions LFd are arranged between the two tie bars LFt2.

[0059] <Semiconductor chip preparation process> In the lead frame preparation step shown in Fig. 4, a semiconductor chip 10 shown in Fig. 6 and a semiconductor chip 30 shown in Fig. 7 are prepared. Each of Fig. 6 and Fig. 7 is a plan view (top view) of a semiconductor chip prepared in the semiconductor chip preparation step of Fig. 4. Fig. 8 is an enlarged cross-sectional view taken along line BB in Fig. 6.

[0060] A duplicated description of the semiconductor chip 10 shown in Fig. 6 and the semiconductor chip 30 shown in Fig. 8 will be omitted. In addition, in Fig. 6, an extension line VL1 of the side OPS2 of the opening where a part of the source pad 10P1 is exposed, and an extension line VL2 of the side OPS3 are shown by two-dot chain lines. In addition, in Fig. 6, the extension lines (extension lines HL1 and HL2) of the sides OPS1 and OPS4 are shown by two-dot chain lines. These will be described later.

[0061] As shown in FIG. 7, the semiconductor chip 30 has four sides (chip sides) 30s in a plan view. The four sides 30s are a side 30s1 extending in the X direction, a side 30s2 extending in the Y direction intersecting with the side 30s1 and intersecting with the X direction, a side 30s3 extending in the Y direction and positioned opposite the side 30s2, and a side 30s4 extending in the X direction and positioned opposite the side 30s1. The side 30s1 is the side that is disposed closest to each of the multiple leads 40 shown in FIG. 2 and extends in the X direction among the four sides 30s of the semiconductor chip 30. In the example shown in FIG. 7, the semiconductor chip 30 is rectangular in a plan view, and is disposed so that the long sides 30s2 and 30s3 extend along the Y direction.

[0062] As shown in FIG. 8, the semiconductor chip 10 has a main surface 11t, a pad 10P (eg, a source pad 10P1) formed on the main surface 11t, and an insulating film IF formed on the main surface 11t.

[0063] In the example shown in FIG. 8, the upper surface of the insulating layer 11, which is the underlying layer of the source pad 10P1, corresponds to the main surface 11t. The insulating layer 11 is formed on the main surface of the semiconductor substrate. The insulating layer 11 is made of, for example, silicon oxide. Although not shown, each of the multiple pads 10P2 shown in FIG. 6 is formed on the insulating layer 11. Moreover, the semiconductor chip 30 shown in FIG. 7 has an insulating layer corresponding to the insulating layer 11 shown in FIG. 8, and each of the multiple pads 30P is formed on the insulating layer.

[0064] In the present embodiment, the insulating film IF has an inorganic insulating film CF formed on the main surface 11t and an organic insulating film OF formed on the inorganic insulating film CF. The inorganic insulating film CF is, for example, a silicon oxide film, a silicon nitride film, or a laminated film of these. On the other hand, the organic insulating film OF is, for example, a resin film such as a polyimide resin film.

[0065] As a modification of this embodiment, the organic insulating film OF shown in FIG. 8 is not formed, and the insulating film IF is simply composed of the inorganic insulating film CF.

[0066] The organic insulating film OF has a higher fluidity during formation than the inorganic insulating film CF, and is therefore more likely to be embedded in the unevenness of the underlayer. For this reason, when the organic insulating film OF is formed to cover the inorganic insulating film CF, the upper surface of the organic insulating film OF (in other words, the upper surface 10t of the semiconductor chip 10) becomes a flat surface. As shown in FIG. 2, in this embodiment, a semiconductor chip 30 is mounted on the upper surface 10t of the semiconductor chip 10. When another device is mounted on the upper surface 10t of the semiconductor chip 10 in this manner, it is preferable that the upper surface 10t of the semiconductor chip 10 is flat.

[0067] In the case where the insulating film has an inorganic insulating film CF and an organic insulating film OF as in the present embodiment, an opening for exposing the source pad 10P1 from the insulating film IF is formed in each of the inorganic insulating film CF and the organic insulating film OF. An opening OPC is formed in the inorganic insulating film CF, and an opening OPO is formed in the organic insulating film OF.

[0068] The opening OPC formed in the inorganic insulating film CF is exposed from the organic insulating film OF at an opening OPO formed in the organic insulating film. In other words, as shown in Fig. 8, the opening OPC and the opening OPO overlap each other in the thickness direction of the semiconductor chip 10. Therefore, a portion of the source pad 10P1 is exposed from the insulating film IF consisting of the inorganic insulating film CF and the organic insulating film OF at the opening OPC.

[0069] 2 is connected to a part (wire bonding region) of the region of the source pad 10P1 exposed from the insulating film IF in the wire bonding step shown in FIG.

[0070] In this embodiment, the source pad 10P1 is exposed from the insulating film IF at a plurality of locations (two locations in FIGS. 6 and 7). In this manner, in the case of a structure in which a plurality of locations of one source pad 10P1 are exposed from the insulating film IF, the area of ​​the source pad 10P1 can be increased. During operation of the power transistor, a large current may flow through the source pad 10P1. For this reason, by increasing the area of ​​the source pad 10P1, the cross-sectional area of ​​the current path can be increased, which is preferable from the viewpoint of reducing the resistance of the current path.

[0071] However, although not shown, as a modification of the example shown in FIG. 8, there is also a case where source pads 10P1 separated from each other are formed at the positions where the openings OPC and OPO are formed.

[0072] <First semiconductor chip mounting process> Next, in a first semiconductor chip mounting step shown in Fig. 4, the semiconductor chip 10 is mounted on the die pad 20 via the die bond material DB as shown in Fig. 2. In the step of mounting the semiconductor chip 10, processes are performed, for example, in the following order.

[0073] First, a die bond material DB is applied to the chip mounting area of ​​the die pad 20 (i.e., the area where the semiconductor chip 10 is to be mounted) (die bond material application process). When the die bond material DB is made of solder, a paste material containing a solder component, a flux component, and a resin component (called solder paste) is applied in the die bond material application process. On the other hand, when the die bond material DB is a conductive resin, a paste material made of a resin mixed with a large number of conductive particles (called conductive resin paste) is applied in the die bond material application process.

[0074] Next, the semiconductor chip 10 is pressed onto the applied paste material to bond the semiconductor chip 10 to the paste material (first semiconductor chip bonding process). In this process, as shown in Fig. 2, among the multiple sides 10s of the semiconductor chip 10, the side 10s1 is arranged along the arrangement direction of the multiple leads 40 (X direction in Fig. 2).

[0075] Next, the die bond material DB is hardened to fix the semiconductor chip 10 onto the die bond material DB (die bond material hardening step). When the paste material applied in the die bond material application step is a solder paste, a reflow process is performed in this step. The reflow process is a process in which the die bond material DB is heated until its temperature reaches or exceeds the melting point of the solder component, and then cooled. The reflow process allows the solder component to be bonded to the metal material to which the die bond material DB is in close contact (the die pad 20 and the drain electrode DE of the semiconductor chip in this embodiment). Furthermore, since the solder component after the reflow process is hardened in the state shown in FIG. 4, the semiconductor chip 10 is fixed onto the die pad 20 via the die bond material DB.

[0076] The above-mentioned flux component is an interface-activating component used to improve the interface activity of the solder component in the reflow process.

[0077] On the other hand, if the paste material applied in the die bond material application process is a conductive resin paste, a cure bake process is performed in this process. The cure bake process is a process of heating the die bond material DB until the temperature of the die bond material DB reaches or exceeds the hardening temperature of the thermosetting resin contained in the conductive resin. After the cure bake process, a cooling process is performed. By performing the cure bake process, the thermosetting resin component contained in the die bond material DB hardens, so that the entire die bond material DB hardens. As a result, the semiconductor chip 10 is fixed onto the die pad 20 via the die bond material DB.

[0078] <Second semiconductor chip mounting process> Next, in a second semiconductor chip mounting process shown in Fig. 4, a semiconductor chip 30 is mounted on the semiconductor chip 10 via an insulating adhesive material DT as shown in Fig. 3. In the process of mounting the semiconductor chip 30, processes are performed, for example, in the following order.

[0079] An insulating adhesive material DT (see FIG. 3) is attached to the lower surface 30b (see FIG. 3) of the semiconductor chip 30 (see FIG. 3) prepared in the semiconductor chip preparation step shown in FIG. 4. The insulating adhesive material DT contains a sticky resin component that can be attached to each of the semiconductor chip 30 and the semiconductor chip 10 (see FIG. 3), and a thermosetting resin component that can be hardened by heating. The adhesive material that can be attached to the semiconductor chip 30 in advance in this way is called a die attach film.

[0080] In the second semiconductor chip mounting step, as shown in FIG. 3, the insulating adhesive material DT attached to the lower surface 30b of the semiconductor chip 30 is attached onto the upper surface 10t of the semiconductor chip 10 together with the semiconductor chip 30 (second semiconductor chip attaching step).

[0081] In this step, as shown in FIG. 2, among the multiple sides 30s (see FIG. 7) of the semiconductor chip 30, the side 30s1 (see FIG. 7) is arranged along the side 10s1 of the semiconductor chip 10.

[0082] Next, the insulating adhesive material DT is cured to fix the semiconductor chip 30 onto the semiconductor chip 10 (insulating adhesive curing process). In this process, a cure bake process is performed. The cure bake process is a process of heating the insulating adhesive material DT until the temperature of the insulating adhesive material DT reaches or exceeds the curing temperature of the thermosetting resin contained in the insulating adhesive material DT. After the cure bake process, a cooling process is performed. By performing the cure bake process, the thermosetting resin component contained in the insulating adhesive material DT is cured, so that the entire insulating adhesive material DT is cured. As a result, the semiconductor chip 30 is fixed onto the semiconductor chip 10 via the insulating adhesive material DT.

[0083] The cure bake process described in the first semiconductor chip mounting process and the cure bake process described in this process (second semiconductor chip mounting process) may be performed together after the second semiconductor chip mounting process. For example, as shown by the dotted line in FIG. 4, the cure bake process may be performed as a cure bake process after the wire bonding process shown in FIG. 4 (more specifically, after the pass / fail judgment process and before the sealing process). In particular, as shown in FIG. 2, the semiconductor chip 30 is mounted near a plurality of pads 10P1 of the semiconductor chip 10. When the cure bake process is performed, if gas is generated from the insulating adhesive material DT and adheres to the surface of the pad 10P1, it may affect the electrical characteristics of the bonded portion between the wire 51 and the pad 10P1. For this reason, from the viewpoint of improving the electrical reliability between the wire 51 and the pad 10P1, it is preferable to perform the cure bake process after the wire bonding process.

[0084] <Wire bonding process> 4, wires 50 are connected to each of the multiple pads 10P of the semiconductor chip 10 and the multiple pads 30P of the semiconductor chip 30, as shown in FIG. 2. The wire bonding process includes a step of connecting the source pad 10P1 and the lead 40 (the lead 41 or the lead 47) via a wire 51, a step of connecting the pad 10P2 and the pad 30P via a wire 52, and a step of connecting the pad 30P and the lead 40 (the lead 42, the lead 43, the lead 45, or the lead 46) via a wire 53.

[0085] As already explained, since a signal current flows through wire 52 and wire 53, wire 50 having a smaller diameter is used than wire 51 through which a large current flows. For this reason, a ball bonding method using a capillary tool as a bonding tool (bonding head) can be used in the process of bonding wire 52 and wire 53. On the other hand, a wedge bonding method using a wedge bonding tool is used as the bonding method for wire 51.

[0086] The details of the wire bonding process, particularly the process of connecting the wire 51 to the source pad 10P1 and the subsequent pass / fail determination process will be described later.

[0087] <Good / bad judgment process> Next, in the pass / fail judgment step shown in Fig. 4, it is judged whether the end of the wire 51 shown in Fig. 2 is located within the bonding region in a plan view. In this step, pass / fail judgment is performed on the position of the end of the wire 51 connected to the source pad 10P1 on the source pad 10P1 side among the multiple wires 50 connected to the semiconductor chip 10 or the semiconductor chip 30 in the wire bonding step. Details of this step will be described later.

[0088] <Sealing process> Next, in the sealing process shown in FIG. 4, the semiconductor chip 10, a portion of the die pad 20, a portion of each of the multiple leads 40 (inner lead portion 40M shown in FIG. 3), and the multiple wires 50 shown in FIG. 2 are sealed with insulating resin to form the sealing body 60 shown in FIG. 3.

[0089] In this process, for example, a molding die including an upper die (first die) and a lower die (second die) (not shown) is used to form the sealing body 60 by a so-called transfer molding method. The lead frame LF is arranged so that the die pad 20 of the device forming portion LFd shown in FIG. 5 and the inner lead portions 40M (see FIG. 3) of each of the leads 40 are located within the cavity of the molding die. Then, the lead frame LF is sandwiched between the upper and lower dies. In this state, when a softened (plasticized) thermosetting resin (insulating resin) is pressed into the cavity of the molding die, the insulating resin is molded to follow the shape of the cavity.

[0090] At this time, a part of the upper surface 20t of the die pad 20 and the lower surface 20b of the die pad 20 are in close contact with the molding die. Therefore, after this step, a part of the upper surface 20t and the lower surface 20b of the die pad 20 are exposed from the sealing body 60, as shown in FIG.

[0091] After the sealing body 60 is molded, the sealing body 60 is heated until a part of the thermosetting resin contained in the sealing body 60 is hardened (called temporary hardening). When this temporary hardening makes it possible to remove the lead frame LF from the molding die, the lead frame LF is removed from the molding die. Then, the lead frame LF is transported to a heating furnace and further heat-treated (cure bake). As a result, the remaining part of the thermosetting resin is hardened, and the sealing body 60 is obtained.

[0092] <Solder film formation process> Next, in the solder film formation process shown in FIG. 4, the lead frame LF is immersed in a plating solution not shown, and a metal film (metal film 22 and metal film 48 shown in FIGS. 6 to 6) is formed on the surface of the metal portion (outer portion) exposed from the sealing body 60.

[0093] <Singulation process> Next, the singulation process shown in FIG. 4 includes a tie bar cutting process of cutting the tie bar LFt1 shown in FIG. 5, and a lead cutting process of cutting the tip portions of each of the multiple leads 40 shown in FIG.

[0094] In the tie bar cutting process, the tie bar LFt1 shown in Fig. 5 is cut. Also, in the tie bar cutting process, the tie bar LFt2 is cut to divide the multiple die pads 20 connected via the tie bar LFt2 into each of them. After this process, the multiple leads 40 are in a state of being connected via the frame portion LFf.

[0095] The tie bars LFt1 and LFt2 can be cut by pressing (cutting) using a punch and die (not shown). This step is performed after the solder film formation step, so the side surfaces newly formed by cutting in this step are not covered with the metal film 48.

[0096] In the lead cutting process, the multiple leads 40 are separated from the frame portion LFf, thereby separating each of the multiple leads 40. In this process, the tip portion of each of the multiple leads 40 is cut by pressing (cutting) using a punch and die (not shown). The tip surface newly formed by cutting in this process is not covered with the metal film 48. By this process, the device formation portion LFd shown in FIG. 5 is divided into individual pieces, and the semiconductor device shown in FIG. 1 is obtained.

[0097] Through the above steps, the semiconductor device PKG1 shown in Fig. 1 to Fig. 4 is obtained. After that, tests and inspections such as electrical tests and visual inspections are performed as necessary, and those determined to be non-defective are transported to the next process, such as packaging of semiconductor devices.

[0098] <Details of the wire bonding process> Next, the wire bonding process and the pass / fail judgment process will be described in detail. The process of connecting the wire 51 shown in FIG. 2 to the source pad 10P1 will be described in particular detail below. FIG. 9 is an explanatory diagram showing an example of the detailed steps of the wire bonding process shown in FIG. 4. FIG. 10 is an explanatory diagram showing a schematic configuration example of a wire bonding device used in the wire bonding process shown in FIG. 4.

[0099] As shown in FIG. 9, the wire bonding process of this embodiment includes a semiconductor chip identifying step, an opening position specifying step, a bonding region specifying step, and a wire forming step.

[0100] In the example shown in FIG. 10, the wire bonding apparatus 700 includes a camera (image sensor, imaging processing unit) 701, a camera conveying unit 702, a monitor 703, a semiconductor chip identification unit 704, a bonding processing unit 705, and a judgment unit 706. The wire bonding apparatus 700 shown in FIG. 10 is an example, and various modified examples are applicable. For example, in the case of the wire bonding apparatus 700 shown in FIG. 10, the camera 701 and the bonding processing unit 705 are configured to operate independently. As a modified example of FIG. 10, the camera 701 and the bonding processing unit 705 may be driven by the same driving unit. Also, for example, in FIG. 10, the monitor 703 is attached to the wire bonding apparatus 700. The position of the monitor 703 is not limited to the example shown in FIG. 10, and may be disposed at a position away from the wire bonding apparatus 700.

[0101] The camera 701 is configured to be able to capture an image of a semiconductor chip mounted on a lead frame LF that has been transported onto a stage 707. The camera 701 is configured to be movable in position by a camera transport unit 702. The image captured by the camera 701 is displayed on a monitor 703. The monitor 703 is capable of displaying the image captured by the camera 701. In addition to the image captured by the camera 701, the monitor 703 may also display a line that serves as a guide for an operator to visually check the positional relationship between the opening and the wire.

[0102] In the wire bonding process shown in Figure 9, first, the semiconductor chip is identified by recognizing a unique pattern present on the semiconductor chip 10 (see Figure 6) using a camera 701 (see Figure 10) provided in a wire bonding apparatus 700 (see Figure 10) (semiconductor chip identification process).

[0103] 10 is configured to identify a semiconductor chip based on an image captured by a camera 701 and displayed on a monitor 703. For example, the semiconductor chip identification unit 704 is configured to identify the semiconductor chip by specifying a unique pattern from the image displayed on the monitor 703.

[0104] The unique pattern may be, for example, one or more of the pads 10P of the semiconductor chip 10 shown in Fig. 6, or a visible mark for identification may be formed in advance on the top surface 10t of the semiconductor chip 10. In this embodiment, the opening for the source pad 10P1 may be used as the unique pattern.

[0105] Next, using the unique pattern as the origin, based on the previously acquired coordinate data of the opening, the position of the opening that exposes a portion of the source pad 10P1 of the semiconductor chip 10 is identified among the multiple openings formed in the insulating film IF shown in FIG. 6 (opening position identification process).

[0106] Next, in the opening formed in the insulating film IF, a region for connecting a wire 51 (see FIG. 2) (a bonding region BR shown in FIG. 12 to be described later) is specified (a bonding region specifying step). This step is performed after the semiconductor chip preparing step shown in FIG. 4 and before the wire forming step shown in FIG.

[0107] 6 is formed in order to expose, from the insulating film IF, a bonding region of the source pad 10P1 for connecting the wire 51. However, in consideration of the versatility of the semiconductor chip 10, the opening range of the opening does not necessarily match the bonding region, and there are cases in which the source pad 10P1 is exposed over a range wider than the bonding region to which the wire 51 is connected.

[0108] From the viewpoint of suppressing the characteristic fluctuation of the semiconductor device, it is preferable that the wire 51 is connected to a bonding region of the source pad 10P1 that is preset by design. For this reason, it is preferable that the wire bonding process includes a bonding region specifying process.

[0109] The bonding region specification process is called "teaching." This "teaching" is performed to improve the accuracy of the position where the wire 51 is connected, from the viewpoint of suppressing the characteristic fluctuation of the semiconductor device caused by the positional deviation of the bonding position where the bonding wire is connected. The details of "teaching" will be described later.

[0110] As described with reference to Fig. 4, this embodiment includes a pass / fail judgment step that is performed after the wire bonding step. Therefore, if the pass / fail judgment result can be fed back to fine-tune the settings of the wire bonding apparatus 700 (see Fig. 10), the bonding region specification step may be omitted.

[0111] Next, a wire 51 (see FIG. 2) is connected to the source pad 10P1 shown in FIG. 6 (wire forming step). When a bonding area specifying step is performed before this step, in the wire forming step, an end of the wire 51 (see FIG. 2) is connected to the bonding area of ​​the source pad 10P1 based on information specified by "teaching". Details of the wire forming step shown in FIG. 9 will be described below with reference to FIGS. 3, 11, and 12. FIG. 11 is an enlarged cross-sectional view showing a first bonding step in the wire forming step. FIG. 12 is a plan view showing a schematic operation of a wedge tool in a bent portion forming step in the wire forming step.

[0112] A bonding processing section 705 of a wire bonding apparatus 700 shown in FIG. 10 includes a wire guide 751, a cutting blade 752, and a wedge tool 753 shown in FIG.

[0113] 9, first, as shown in Fig. 11, an end of a wire 51 is brought into contact with a portion of the source pad 10P1 that is exposed from the insulating film IF at the opening OP1, and the wire 51 is sandwiched between a wedge tool 753 and the source pad 10P1. At this time, the wedge tool 753 applies ultrasonic waves to the wire 51 while pressing it toward the source pad 10P1 (first bonding step).

[0114] In the first bonding step, the bonding portion 51B of the end of the wire 51 is bonded to the source pad 10P1. The bonding portion 51B is a portion of the wire 51 that includes a bonding surface 51Bb that is a bonding interface with the source pad 10P1 and a portion that overlaps with the bonding surface 51Bb in the thickness direction of the wire 51.

[0115] 11, among the ends of the wire 51, the tip portion 51A located closer to the tip side than the joint portion 51B may not come into contact with the wedge tool 753 in the first bonding step. In this case, the tip portion 51A that is not joined to the source pad 10P1 is formed at the tip of the wire 51.

[0116] Next, wire guide 751 is pulled upward while wire 51 is being fed out from wire supply hole 751H formed in wire guide 751 shown in Fig. 11. Thereafter, as shown diagrammatically with an arrow in Fig. 12, wire guide 751 (see Fig. 11) is rotated along the XY plane, whereby bent portion (section) 51C is formed (bent portion forming step).

[0117] In this specification, the tip portion 51A, the joint portion 51B, and the bent portion 51C shown in FIG.

[0118] In Fig. 12, the boundaries between the bent portion 51C and the joint portion 51B and between the bent portion 51C and the extending portion 51L are indicated by dotted lines to make them easier to distinguish. The bent portion 51C extends in a direction different from any of the X direction, the Y direction, and the θ direction. However, the boundaries between the bent portion 51C and the extending portion 51L formed in the bent portion forming step may be difficult to distinguish. For example, when the bent portion 51C extends in the θ direction like the extending portion 51L, it is difficult to identify the boundaries between the bent portion 51C and the extending portion 51L.

[0119] Next, while the wire 51 is being fed out from a wire supply hole 751H formed in the guide 751 shown in Fig. 11, the wire guide 751 is moved toward the lead 47 shown in Fig. 3 and bonded to the wire bonding portion 40W of the lead 47 (second bonding step). In the second bonding step, similarly to the first bonding step, the wire 51 is pressed against the upper surface 40t of the lead 47 with a wedge tool 753 (see Fig. 11) and bonded by applying ultrasonic waves.

[0120] Next, the wire 51 is cut by a cutting blade 752 shown in FIG. 11 (wire cutting step).

[0121] The wire 51 shown in Fig. 2 is obtained by the above steps. As shown in Fig. 12, the wire 51 includes an end 51E including a joint 51B having a joint surface that is a joint interface with the pad 10P1, and an extension 51L that is connected to the end 51E and extends in a θ direction that intersects with both the X direction and the Y direction in a plan view. In a plan view, the extension 51L intersects with the side OPS1. As described above, the end 51E of the wire 51 includes a tip 51A, a joint 51B, and a bent portion 51C.

[0122] <About teaching> Next, details of the "teaching" performed in the bonding region specifying step of Fig. 9 will be described. Fig. 13 is an explanatory diagram showing an example of an image displayed on a monitor during the "teaching" performed in the bonding region specifying step of Fig. 9. In Fig. 13, the outer edge of the bonding region BR and the outer edges of each of the corners OPC1, OPC2, OPC3, and OPC4 are shown with two-dot chain lines, but in "teaching", the lines of the bonding region BR and the corners OPC1, OPC2, OPC3, and OPC4 are not displayed on the monitor 703 (see Fig. 10).

[0123] 13, first, the positional relationship between the lead frame LF (see FIG. 10) on which the semiconductor chip 10 is mounted and the camera 701 (see FIG. 10) is adjusted so that the opening OP1 (more specifically, the main opening OPM) including the bonding region BR is located directly under the camera 701 (see FIG. 10). As a result, as shown in FIG 13, an image of the opening OP1 captured by the camera 701 is displayed on a monitor 703 (see FIG. 10) of the wire bonding apparatus 700 (see FIG. 10). For example, the opening OP1 shown in FIG 13 has the main opening OPM including the bonding region BR.

[0124] The bonding region BR is a region where the end 51E of the wire 51 shown in Fig. 12 is to be disposed. In the case of this embodiment, in the pass / fail judgment step shown in Fig. 4, when at least the entire joint 51B of the wire 51 shown in Fig. 12 is located within the range of the bonding region BR in a plan view, the wire is judged to be a non-defective product. Preferably, when the entire end 51E including the joint 51B and the bent portion 51C of the wire 51 is located within the range of the bonding region BR, the wire is judged to be a non-defective product.

[0125] In a plan view, the main opening OPM has a side OPS1 extending in the X direction, a side OPS2 extending in the Y direction intersecting the X direction, a side OPS3 extending in the Y direction and positioned opposite side OPS2, and a side OPS4 extending in the X direction and positioned opposite side OPS1.

[0126] As shown in FIG. 12, in the wire bonding step, the wire 51 (specifically, the extension portion 51L of the wire 51) is disposed so as to straddle the side OPS1 of the main opening OPM in plan view.

[0127] In addition, the main opening OPM has a corner OPC1 including the intersection of side OPS1 and an extension line of side OPS2, a corner OPC2 including the intersection of side OPS1 and side OPS3, a corner OPC3 including the intersection of side OPS4 and side OPS2, and a corner OPC4 including the intersection of side OPS4 and an extension line of side OPS3.

[0128] In the example shown in Fig. 12, the definitions of the corners OPC1 to OPC4 are as described above, but the definitions of the corners are appropriately modified according to the positional relationship between the main opening OPM and the position determination aperture pattern. For example, in the case of a modified example shown in Fig. 16 described later, the main opening OPM has a corner OPC1 including an intersection of a side OPS1 and a side OPS2, a corner OPC2 including an intersection of a side OPS1 and a side OPS3, a corner OPC3 including an intersection of a side OPS4 and a side OPS2, and a corner OPC4 including an intersection of a side OPS4 and a side OPS3. For example, in the case of a modified example shown in Figure 19 described later, the main opening OPM has a corner OPC1 including the intersection of side OPS1 and the extension line of side OPS2, a corner OPC2 including the intersection of side OPS1 and the extension line of side OPS3, a corner OPC3 including the intersection of side OPS4 and the extension line of side OPS2, and a corner OPC4 including the intersection of side OPS4 and the extension line of side OPS3.

[0129] Furthermore, although not shown, as a modified example of Fig. 12, there is a case where the position determination aperture pattern AP1 is arranged at the corner OPC2 instead of the corner OPC1. In this case, the corner OPC2 includes an intersection point between the side OPS1 and an extension line of the side OPS3. Moreover, when the position determination aperture pattern AR2 shown in Fig. 12 is arranged at the corner OPC3, the corner OPC3 includes an intersection point between the side OPS4 and an extension line of the side OPS2.

[0130] The main opening OPM has a rectangular planar shape having long and short sides, with the long sides (sides OPS2 and OPS3) measuring approximately 1200 μm, while the short sides (sides OPS1 and OPS4) measuring approximately 600 μm.

[0131] Next, while looking at the image displayed on the monitor 703 (see FIG. 10), the operator moves the camera 701 (see FIG. 10) so that the bonding region BR is at the center of the image, adjusts the position visually, and then identifies the bonding region BR.

[0132] For example, as shown in Fig. 13, a crosshair consisting of horizontal lines 400A and vertical lines 400B is displayed on the monitor 703 (see Fig. 10), and the bonding region BR is specified based on this crosshair. Each of the horizontal lines 400A and vertical lines 400B has scale marks at regular intervals, and the center of the crosshair is moved to the vicinity of the center of the main opening OPM, and the center position of the crosshair is adjusted so that the number of scale marks from the center of the crosshair to each side of the main opening OPM on the top, bottom, left, and right sides is the same. For example, the interval between the scale marks on each of the horizontal lines 400A and vertical lines 400B that make up the crosshair is, for example, about 100 µm.

[0133] However, when only the above-mentioned "teaching" is performed, there is a limit to the accuracy with which the bonding region BR can be specified, or the positional accuracy of the joint portion 51B of the wire 51 that is actually connected.

[0134] For example, the dimensions (width and length) of the main opening OPM of the source pad 10P1 to which the wire 51 is connected vary depending on the type of semiconductor device. For this reason, the dimensions of the main opening OPM may not be an integer multiple of the scale intervals of the horizontal line 400A and the vertical line 400B constituting the crosshairs of the wire bonding device 700 (see FIG. 10) used. In such a case, the operator visually checks "1 scale × integer + α scale (α is a decimal)" to align the intersection of the crosshairs with the center of the main opening OPM. At this time, it is difficult for the operator to accurately adjust the center position of the crosshairs so that "1 scale × integer + α scale" is the same from the center of the crosshairs to each side of the main opening OPM on the top, bottom, left and right sides. For this reason, only with the above-mentioned "teaching", for example, a deviation of about 10% of one scale (about several tens of μm) occurs when identifying the bonding region BR.

[0135] Furthermore, for example, since "teaching" is an alignment process performed before connecting wire 51 (see FIG. 12) to source pad 10P1, depending on the settings and characteristics of wire bonding apparatus 700 (see FIG. 10), the position of wire 51 after it is actually bonded may deviate from the planned position.

[0136] Therefore, the position of the bonding region BR can be specified by "teaching", but as described above, there is a limit to the positional accuracy of the bonded portion 51B of the wire 51 that is actually connected by "teaching" alone.

[0137] Incidentally, if only the presence or absence of electrical conduction is considered, it is sufficient that at least a portion of the wire 51 shown in Fig. 12 is connected to the source pad 10P1. In this case, as long as the joint portion 51B of the wire 51 is disposed within the main opening OPM, electrical conduction is possible even if other portions of the wire 51 (for example, the tip portion 51A and the bent portion 51C) are located outside the main opening OPM in a plan view.

[0138] On the other hand, when considering the characteristics of the semiconductor device, the characteristics may vary depending on the position where the bonding portion 51B of the wire 51 is disposed in the source pad 10P1.

[0139] For example, in the case of a semiconductor device PKG1 having a sense transistor TrS as shown in Fig. 2, the distance L1 between the sense transistor TrS and a junction 51B (see Fig. 12) of a wire 51 correlates with the detection value. As described above, the sense transistor TrS has a function of detecting the current value of the current flowing through the main transistor TrM. The detected current value correlates with the distance L1.

[0140] Therefore, even when the joint 51B is disposed in the main opening OPM, different current values ​​are detected depending on the position of the joint 51B in the main opening OPM. Therefore, in order to improve the accuracy of the current value detected by the sense transistor TrS, it is preferable to improve the positional accuracy of the joint 51B in the main opening OPM. In other words, by improving the positional accuracy of the joint 51B in the main opening OPM, the accuracy of the current value detected by the sense transistor TrS can be improved.

[0141] In the example shown in Fig. 6, if an extension line of the side OPS2 extended in the Y direction in a plan view is defined as an extension line VL1, and an extension line of the side OPS3 extended in the Y direction is defined as an extension line VL2, then the sense transistor TrS is located between the extension lines VL1 and VL2 in a transparent plan view. Therefore, in order to keep the value of the separation distance L1 shown in Fig. 6 within the allowable range, the positions of the sides BRS4 and BRS1 are particularly important among the sides BRS1, BRS2, ​​BRS3, and BRS4 of the bonding region BR shown in Fig. 13.

[0142] Furthermore, as described above, in consideration of the versatility of the semiconductor chip 10, the opening range of the main opening OPM does not necessarily coincide with the bonding region BR, and the source pad 10P1 may be exposed over a range wider than the bonding region BR to which the wire 51 is connected. Therefore, in order to improve the positional accuracy of the bonding portion 51B in the main opening OPM, a technique is required to accurately position the bonding portion 51B in the bonding region BR, which has a small opening area of ​​the main opening OPM.

[0143] Based on the above findings, the inventors of the present application have investigated techniques for improving the positional accuracy of bonding portion 51B in actually connected wire 51, and have discovered a method for manufacturing a semiconductor device according to the present embodiment.

[0144] <Details of the quality inspection process> FIG. 14 is an explanatory diagram showing an example of an image displayed on a monitor in the pass / fail judgment process shown in FIG. 4. In FIG. 14, the outer edge of the bonding region BR and the outer edges of the corners OPC1, OPC2, OPC3, and OPC4 are shown by two-dot chain lines, but in the pass / fail judgment process, the lines of the bonding region BR are not displayed on the monitor 703 (see FIG. 10). Also, in FIG. 14, dotted lines are added to the boundary between the tip portion 51A and the joint portion 51B, the boundary between the joint portion 51B and the bent portion 51C, and the boundary between the bent portion 51C and the extended portion 51L. However, in the pass / fail judgment process, the lines of each boundary shown by dotted lines in FIG. 14 are not displayed. FIG. 15 is an explanatory diagram showing details of the pass / fail judgment process shown in FIG. 4.

[0145] As shown in Fig. 15, the quality determination process includes a bonding position specifying process, a quality determination process, and an adjustment process. First, in the bonding position specifying process, the positional relationship between the joint 51B (see Fig. 14) or the end 51E (see Fig. 14) of the wire 51 (see Fig. 14) and the bonding region BR (see Fig. 14) is specified based on an image displayed on a monitor 703 (see Fig. 10) of the wire bonding apparatus 700 (see Fig. 10).

[0146] 14, the semiconductor chip 10 includes a plurality of aperture patterns for position determination arranged in a region located around the main opening OPM in a plan view. In each of the sides OPS1 and OPS4 of the main opening OPM, if an extension line extending in a direction from the side OPS3 toward the side OPS2 in a plan view is defined as an extension line HL1 (see FIG. 6) and an extension line extending in a direction from the side OPS2 toward the side OPS3 is defined as an extension line HL2 (see FIG. 6), the positions of the plurality of aperture patterns for position determination can be defined as follows. That is, the plurality of aperture patterns for position determination include an aperture pattern AP1 for position determination arranged between the extension line HL1 (see FIG. 6) of the side OPS1 and the extension line HL1 of the side OPS4 in the Y direction and arranged at a position closest to the corner OPC1 among the corners OPC1, OPC2, OPC3, and OPC4 of the main opening OPM. In addition, the multiple position determination opening patterns include a position determination opening pattern AP2 that is located between the extension line HL2 of side OPS1 (see Figure 6) and the extension line HL2 of side OPS4 in the Y direction, and is arranged at a position closest to corner OPC3 or corner OPC4 among corner OPC1, corner OPC2, corner OPC3, and corner OPC4 of the main opening OPM.

[0147] The bonding region BR has a rectangular shape smaller than the area of ​​the main opening OPM in plan view. The bonding region BR is defined by a position determination opening pattern AP1, a position determination opening pattern AP2, a side OPS2, and a side OPS3.

[0148] As shown in Fig. 14, an image of the opening OP1 including the main opening OPM and the wire 51 is displayed on the monitor 703 (see Fig. 10). If no image processing or the like is performed to display the bonding region BR, the monitor 703 does not display a line indicating the outer edge of the bonding region BR. However, in the case of this embodiment, a position determination opening pattern AP1 and a position determination opening pattern AP2 for defining the range of the bonding region BR are provided at each of the corners OPC1 and OPC4. Therefore, by using the position determination opening pattern AP1 and the position determination opening pattern AP2 as guides, the boundary of the bonding region BR can be easily identified visually.

[0149] Next, in the pass / fail determination step, the pass / fail is determined based on whether at least the entire joint 51B is located within the bonding region BR. Preferably, the pass / fail is determined based on whether the entire end 51E including the joint 51B and the bent portion 51C is located within the bonding region BR. For example, if a part of the end 51E (e.g., a part of the bent portion 51C or a part of the tip 51A) is located outside the bonding region BR, it is determined as NO (i.e., defective) and proceeds to the adjustment step described below. On the other hand, if the entire end 51E is located within the bonding region BR, it is determined as YES (i.e., pass) and proceeds to the next step (e.g., bonding of another wire or the sealing step shown in FIG. 4).

[0150] As a modification of this embodiment, in the pass / fail determination step, the pass / fail determination may be made depending on whether or not the entire joint 51B is located within the bonding region BR. In this case, if at least the entire joint 51B is located within the bonding region BR, even if a part of the end 51E (e.g., a part of the bent portion 51C or a part of the tip 51A) is located outside the bonding region BR, it is determined as YES (i.e., pass) and the process proceeds to the next process (e.g., bonding of another wire or the sealing process shown in FIG. 4). On the other hand, if a part of the joint 51B is located outside the bonding region BR, it is determined as NO (i.e., fail) and the process proceeds to the adjustment process described below.

[0151] However, from the viewpoint of further improving the accuracy of the current value detected by the sense transistor TrS, it is preferable to judge pass / fail based on whether or not the entire end 51E of the wire 51, including not only the joint portion 51B but also the tip portion 51A and the bent portion 51C, is located within the bonding region BR, as in the present embodiment.

[0152] As described above, in FIG. 14, the boundary between the tip portion 51A and the joint portion 51B, the boundary between the joint portion 51B and the bent portion 51C, and the boundary between the bent portion 51C and the extending portion 51L are indicated by dotted lines. However, in the pass / fail determination process, the lines of the boundaries illustrated by dotted lines in FIG. 14 are not displayed on the monitor 703 (see FIG. 10). For this reason, when the shape of the wire 51 is as shown in FIG. 14, it is difficult to identify the boundary between the tip portion 51A and the joint portion 51B and the boundary between the bent portion 51C of the end portion 51E of the wire 51 based on the displayed image in a plan view. On the other hand, the boundary between the bent portion 51C and the extending portion 51L is easy to identify based on the planar image. For example, even when an operator visually checks the image on the monitor 703, it is possible to identify the boundary between the bent portion 51C and the extending portion 51L.

[0153] As described in the bent portion forming step of the wire bonding process, the boundary between bent portion 51C and extended portion 51L formed in the bent portion forming step may be difficult to distinguish. In this case, it is preferable to set the position range of bent portion 51C as follows.

[0154] 14, the length of the bent portion 51C in the Y direction is length L51C. This length L51C is 8 percent to 12 percent of the length L51B of the joint portion 51B in the Y direction. More specifically, the length L51C is a preset value within the range of 8 percent to 12 percent of the length L51B.

[0155] When the bent portion 51C extends in the θ direction like the extending portion 51L, the bent portion 51C appears to be integrated with the extending portion 51L. Therefore, it is difficult to identify the boundary between the bent portion 51C and the extending portion 51L. On the other hand, when the bent portion 51C extends in a direction different from the θ direction, it is easy to identify the boundary between the bent portion 51C and the extending portion 51L.

[0156] Therefore, when it is difficult to identify the boundary between the bent portion 51C and the extending portion 51L, as described above, the length 51C is set proportional to the length L51B of the joint 51B in the Y direction, and the portion of the wire 51 that is within the range of the length 51C is regarded as the bent portion 51C. As a result, even if the boundary between the bent portion 51C and the extending portion 51L is unclear, it is possible to perform a pass / fail judgment using the same criteria as when the boundary between the bent portion 51C and the extending portion 51L is easy to identify.

[0157] If the product is judged defective in the pass / fail judging step, the wire bonding apparatus 700 shown in FIG. 10 is adjusted.

[0158] According to the inventors' investigations, after the wire bonding process, it is often detected that a portion of the bonding portion 51B or a portion of the end portion 51E of the wire 51 deviates from the range of the bonding region BR in one of the following three cases.

[0159] First, after starting up the wire bonding apparatus 700 (see FIG. 10) for performing the wire bonding process and bonding the first wire, a positional deviation of the end 51E may be detected. Second, after replacing a jig (e.g., a wedge tool 753 shown in FIG. 11) attached to the wire bonding apparatus 700 (see FIG. 10) in the wire bonding process, a positional deviation of the end 51E may be detected. Third, after changing the wire bonding conditions for performing wire bonding in the wire bonding process, a positional deviation of the joint 51B (or end 51E) may be detected.

[0160] On the other hand, if the above three cases do not apply, it is difficult to detect the positional deviation of the joint 51B (or the end 51E). In other words, the cause of the positional deviation of the joint 51B (or the end 51E) is mainly due to the setting conditions of the wire bonding apparatus 700 (see FIG. 10) and the installation state of the jig.

[0161] Therefore, the adjustment of the wire bonding apparatus 700 (see FIG. 10) performed in the adjustment process involves adjusting one or more of the following items. First, the adjustment of the wire bonding apparatus 700 includes adjustment of the settings of the wire bonding conditions. The settings of the wire bonding conditions include, for example, adjustment of the pressing force when bonding the wire, adjustment of the settings of the ultrasonic output, or adjustment of the settings of the operation timing of the bonding processing unit 705 (see FIG. 10). The adjustment of the wire bonding apparatus 700 also includes checking and adjusting the attachment state of a jig (for example, a wedge tool 753 shown in FIG. 11) attached to the wire bonding apparatus 700 (see FIG. 10).

[0162] After the adjustment process, another wire is bonded, and then the quality judgment process is performed again. In this manner, by repeatedly performing the adjustment process and the quality judgment process, it is possible to adjust the settings to obtain a pass judgment in the quality judgment.

[0163] The pass / fail judgment step shown in Fig. 15 can be omitted. In this case, the pass / fail judgment step is performed every time the wire bonding step is completed. However, from the viewpoint of improving manufacturing efficiency, the mode shown in Fig. 15 is more preferable.

[0164] In the example shown in FIG. 15, after the wire bonding process and before the quality judgment process, a process for judging whether or not quality judgment should be performed (a quality judgment execution necessity judgment process) is included. The judgment criterion in the quality judgment execution necessity judgment process is judged based on whether or not the immediately preceding wire bonding process corresponds to any of the three cases described above. If the timing corresponds to any of the three cases described above, it is judged as YES (i.e., the quality judgment process is necessary) and the quality judgment process proceeds. On the other hand, if the timing does not correspond to any of the three cases described above, it is judged as NO (i.e., the quality judgment process is not necessary) and the quality judgment process is omitted and the process proceeds to the next process (e.g., bonding of another wire, or the sealing process shown in FIG. 4).

[0165] In other words, in the example shown in FIG. 15, the pass / fail determination process is selectively performed after starting up the wire bonding apparatus 700 (see FIG. 10) for performing the wire bonding process and bonding the first wire, after replacing the jig (e.g., the wedge tool 753 shown in FIG. 11) attached to the wire bonding apparatus 700 (see FIG. 10) in the wire bonding process, or after changing the wire bonding conditions for performing wire bonding in the wire bonding process.

[0166] If the pass / fail judgment process is performed in at least one of the above three cases, the possibility of a large number of defective products being generated is low even if the pass / fail judgment process is omitted in other cases. Even if defective products are generated, they can be eliminated by performing an electrical test after the singulation process shown in FIG. 4 is completed.

[0167] The quality determination process is positioned as an inspection process for quickly correcting misalignment that occurs due to the settings of the wire bonding apparatus 700 (see FIG. 10) or the mounting conditions of the jig.

[0168] <Opening shape> Next, detailed structures of the main opening OPM, the position determination opening pattern AP1, and the position determination opening pattern AP2 shown in FIG. 14 and their positional relationships with the bonding region BR will be described, including modified examples.

[0169] 13, in a plan view, the position determination aperture pattern AP1 has an inner side AS11 extending in the X direction, and an outer side AS12 extending in the X direction and positioned closer to the side OPS1 than the inner side AS11. In a plan view, the position determination aperture pattern AP2 has an inner side AS21 extending in the X direction, and an outer side AS22 extending in the X direction and positioned closer to the side OPS4 than the inner side AS21.

[0170] In the bonding position specifying step shown in FIG. 15, the bonding region BR is defined by an extension of an inner side AS11 of the position determination opening pattern AP1, an extension of an inner side AS21 of the position determination opening pattern AP2, a side OPS2, and a side OPS3.

[0171] The structure shown in Fig. 13 can be expressed as follows. The bonding region BR has a side BRS1 extending in the X direction, a side BRS2 extending in the Y direction and intersecting with the side BRS1, a side BRS3 extending in the Y direction and intersecting with the side BRS1 and located on the opposite side of the side BRS2, ​​and a side BRS4 extending in the X direction and intersecting with each of the sides BRS2 and BRS3 and located on the opposite side of the side BRS1. An extension line of the side BRS1 overlaps with the inner side AS11 of the position determination opening pattern AP1. An extension line of the side BRS4 overlaps with the inner side AS21 of the position determination opening pattern AP2.

[0172] From the standpoint of accurately determining the position of the bonding region BR, it is preferable to determine the position of the bonding region BR based on the positions of the inner sides AS11 and AS21 rather than determining the position of the bonding region BR based on any positions of the position determination opening pattern AP1 and the position determination opening pattern AP2.

[0173] In this embodiment, since it is possible to accurately identify the position of the bonding region BR based on the positions of the inner side AS11 and the inner side AS21, in the bonding region identification process shown in FIG. 9, the cross lines (horizontal line 400A and vertical line 400B) shown in FIG. 13 may not be displayed on the monitor 703 (see FIG. 10).

[0174] 13, the opening area of ​​each of the position determination opening pattern AP1 and the position determination opening pattern AP2 is smaller than the opening area of ​​the main opening OPM. This structure is preferable from the viewpoint of improving the accuracy of identifying the outer edge of the bonding region BR.

[0175] As described with reference to Fig. 8, the insulating film IF may have an inorganic insulating film CF formed on the main surface 11t and an organic insulating film OF formed on the inorganic insulating film CF. The main opening OPM shown in Fig. 13 is formed in both the inorganic insulating film CF and the organic insulating film OF shown in Fig. 8. For example, as shown in Fig. 17 described later, each of the position determination opening patterns AP1 and AP2 is formed in both the inorganic insulating film CF and the organic insulating film OF. Alternatively, as shown in Fig. 18 described later, each of the position determination opening patterns AP1 and AP2 is formed only in the organic insulating film OF out of the inorganic insulating film CF and the organic insulating film OF.

[0176] Here, the organic insulating film OF is more likely to shrink due to thermal effects than the inorganic insulating film CF. For this reason, when the opening edge of the opening OPO formed in the organic insulating film OF is defined as the outer edge (side OPS1, side OPS2, side OPS3, and side OPS4) of the main opening OPM shown in FIG. 13, the position of the outer edge of the main opening OPM may be shifted due to thermal effects.

[0177] In the present embodiment, each of the position determination opening patterns AP1 and AP2 shown in Fig. 17 and Fig. 18 is formed at least in the organic insulating film OF. However, as shown in Fig. 13, the opening area of ​​each of the position determination opening patterns AP1 and AP2 is sufficiently smaller than the opening area of ​​the main opening OPM (for example, 5 percent or less). Therefore, even if the organic insulating film OF shrinks due to the influence of heat, the opening shapes of each of the position determination opening patterns AP1 and AP2 are hardly deformed.

[0178] In other words, in FIG. 13, by using the position determination opening pattern AP1 and the position determination opening pattern AP2 as landmarks for identifying the position of the bonding region BR, the positions of the particularly important sides BRS1 and BRS4 among the sides of the bonding region BR can be identified with high accuracy.

[0179] 13, each of the position determination aperture pattern AP1 and the position determination aperture pattern AP2 forms an aperture pattern that communicates with the main opening OPM. In other words, the opening OP1 has the main opening OPM and a plurality of position determination aperture patterns (position determination aperture patterns AP1, AR2) that are connected to the main opening OPM.

[0180] The position determination aperture pattern AP1 is connected to the main aperture OPM at a corner OPC1 of the main aperture OPM, and the position determination aperture pattern AP2 is connected to the main aperture OPM at a corner OPC4 of the main aperture OPM.

[0181] When each of the multiple position determination opening patterns is connected to the main opening OPM, patterning of the opening shape is easier compared to when each of the multiple position determination opening patterns is separated from the main opening OPM, as shown in Figure 16, which is a modified example of Figure 13.

[0182] Fig. 16 is an enlarged plan view showing the periphery of a main opening of a semiconductor chip which is a modification of Fig. 13. Note that in Fig. 16, the cross lines (horizontal line 400A and vertical line 400B) shown in Fig. 13 are omitted.

[0183] The semiconductor chip 10A shown in Fig. 16 differs from the semiconductor chip 10 shown in Fig. 13 in that the position determination opening pattern AP1 and the position determination opening pattern AP2 are each spaced apart from the main opening OPM. Other points are similar to the semiconductor chip 10 shown in Fig. 13, so duplicated explanations will be omitted.

[0184] It is preferable from the viewpoint of improving the accuracy of identifying the outer edge of the bonding region BR when the opening pattern AP1 for position determination and the opening pattern AP2 for position determination are separated from the main opening OPM as in the semiconductor chip 10A. That is, when the organic insulating film OF (see FIG. 8) shrinks due to the thermal influence as described above, the main opening OPM may be deformed. Since the opening pattern AP1 for position determination and the opening pattern AP2 for position determination are separated from the main opening OPM, even if the main opening OPM is deformed, the opening pattern AP1 for position determination and the opening pattern AP2 for position determination are less susceptible to the influence compared to the example shown in FIG.

[0185] 13 and 16, the position determination opening pattern AP1 includes an intersection between the side OPS1 and an extension of the side OPS2. In other words, the outer side AS12 of the position determination opening pattern AP1 overlaps with an extension of the side OPS1 of the main opening OPM. In this case, the distance from the opening edge of the main opening OPM to the bonding region BR can be easily visually recognized. Therefore, in the pass / fail determination step shown in FIG. 15, when an operator visually checks based on the image displayed on the monitor 703 (see FIG. 10), the positions of the sides BRS1 and BRS2 of the bonding region BR are less likely to be misidentified.

[0186] Figure 17 is an enlarged cross-sectional view taken along line CC in Figure 6. Figure 18 is an enlarged cross-sectional view showing a modification of Figure 17. Note that, although Figure 17 is an enlarged cross-sectional view taken along line CC in Figure 6, position determination aperture pattern AP1 and position determination aperture pattern AP2 shown in Figure 13 have similar structures, and therefore the reference characters for position determination aperture pattern AP1 and position determination aperture pattern AP2 are used in Figures 17 and 18.

[0187] In the example shown in Fig. 17, the position determination opening pattern AP1 and the position determination opening pattern AP2 are formed in both the inorganic insulating film CF and the organic insulating film OF. On the other hand, the semiconductor chip 10B shown in Fig. 18 differs from the semiconductor chip 10 in Fig. 17 in that the position determination opening pattern AP1 and the position determination opening pattern AP2 are formed only in the organic insulating film OF. Therefore, the source pad 10P1 is not exposed from the insulating film IF (more specifically, the inorganic insulating film CF) in the position determination opening patterns AP1 and AP2. The semiconductor chip 10B is similar to the semiconductor chip 10 except for the above-mentioned differences, so a duplicated description will be omitted.

[0188] Although not shown, as another modified example of FIG. 17, each of the position determination opening pattern AP1 and the position determination opening pattern AP2 may be formed only in the inorganic insulating film CF. In this modified example, however, if the organic insulating film OF has high fluidity when applied, the organic insulating film OF may be embedded in the opening OPC formed in the inorganic insulating film CF. Therefore, from the viewpoint of improving the visibility of an image displayed on the monitor 703 (see FIG. 10), the structure of the semiconductor chip 10 shown in FIG. 17 or the semiconductor chip 10B shown in FIG. 18 is preferable.

[0189] Fig. 19 is an enlarged plan view showing another modified example of Fig. 13. Note that in Fig. 19, the cross lines (horizontal line 400A and vertical line 400B) shown in Fig. 13 are omitted.

[0190] The semiconductor chip 10C shown in Fig. 19 differs from the semiconductor chip 10 shown in Fig. 13 in the following respects. The semiconductor chip 10C has a plurality of position determination opening patterns, which include a position determination opening pattern AP2 located between an extension line of the side OPS1 and an extension line of the side OPS4 in the Y direction, and arranged at a position closest to the corner OPC3 among the corners OPC1, OPC2, OPC3, and OPC4 of the main opening OPM. The plurality of position determination opening patterns also include a position determination opening pattern AP3 located between an extension line of the side OPS1 and an extension line of the side OPS4 in the Y direction, and arranged at a position closest to the corner OPC2 among the corners OPC1, OPC2, OPC3, and OPC4 of the main opening OPM. In addition, the multiple position determination opening patterns include a position determination opening pattern AP4 that is located between the extension line of side OPS1 and the extension line of side OPS4 in the Y direction and is arranged at a position closest to corner OPC4 among corners OPC1, OPC2, OPC3, and OPC4 of the main opening OPM.

[0191] The bonding region BR is defined by position determination opening pattern AP1, position determination opening pattern AP2, position determination opening pattern AP3, position determination opening pattern AP4, side OPS2, and side OPS3.

[0192] 19, in plan view, the position determination aperture pattern AP3 has an inner side AS31 extending in the X direction, and an outer side AS32 extending in the X direction and positioned closer to the side OPS1 than the inner side AS31. In plan view, the position determination aperture pattern AP4 has an inner side AS41 extending in the X direction, and an outer side AS42 extending in the X direction and positioned closer to the side OPS4 than the inner side AS41.

[0193] In the bonding position identification process shown in Figure 15, the bonding region BR is defined by a virtual line connecting the inner side AS11 of the position determination opening pattern AP1 and the inner side AS31 of the position determination opening pattern AP3, a virtual line connecting the inner side AS21 of the position determination opening pattern AP2 and the inner side AS41 of the position determination opening pattern AP4, side OPS2, and side OPS3.

[0194] In this modified example, a position determination opening pattern is provided at each of the four corners of the main opening OPM, which further improves visibility when identifying the outer edge of the bonding region BR from an image, compared to the example shown in FIG.

[0195] Furthermore, this modified example has the following advantages. That is, in the example shown in Fig. 12, extending portion 51L of wire 51 extends in a direction approaching side OPS3 from side OPS2. At this time, if a position determination opening pattern is formed at corner OPC2, the position determination opening pattern may be covered by extending portion 51L of wire 51 depending on the bending angle of bending portion 51C of wire 51. To avoid this, position determination opening pattern AP1 needs to be provided along the side opposite to the bending direction of wire 51 (i.e., side OPS2 in the example shown in Fig. 12).

[0196] On the other hand, in the example shown in Figure 19, a position determination opening pattern is provided at each of the four corners, so that at least three of the four position determination opening patterns can be visually recognized regardless of the bending direction of wire 51.

[0197] The semiconductor chip 10C shown in Fig. 19 is similar to the semiconductor chip 10 shown in Fig. 13 except for the above-mentioned differences, and therefore a duplicated description will be omitted. Although not shown in the drawings, the semiconductor chip 10C shown in Fig. 19 can be applied in combination with the various modified examples described above.

[0198] For example, each of the four position determination opening patterns of the semiconductor chip 10C shown in FIG. 19 may be spaced apart from the main opening OPM, similarly to the semiconductor chip 10A shown in FIG.

[0199] Also, for example, each of the four position determination opening patterns of the semiconductor chip 10C shown in Fig. 19 includes an opening OPC formed in the inorganic insulating film CF and an opening OPO formed in the organic insulating film OF, similar to the position determination opening patterns AP1 and AP2 of the semiconductor chip 10 shown in Fig. 17. However, as a modified example, each of the four position determination opening patterns may be formed only in the organic insulating film OF, similar to the semiconductor chip 10B shown in Fig. 18. Alternatively, the organic insulating film OF may not be formed.

[0200] Fig. 20 is an enlarged plan view showing another modified example of Fig. 13. Note that in Fig. 20, the cross lines (horizontal line 400A and vertical line 400B) shown in Fig. 13 are omitted.

[0201] The semiconductor chip 10D shown in Fig. 20 differs from the semiconductor chip 10 shown in Fig. 13 in that the position determination opening pattern AP1 is disposed between the corner OPC1 and the center S2C of the side OPS2. The semiconductor chip 10D is particularly effective when the area of ​​the bonding region BR is extremely small compared to the opening area of ​​the main opening OPM, as shown in Fig. 20.

[0202] Since the position determination opening pattern AP1 is disposed between the corner OPC1 and the center S2C of the side OPS2, even if the distance between the bonding region BR and the side OPS1 is long, the opening area of ​​the position determination opening pattern AP1 can be made sufficiently small (for example, 5 percent or less) compared to the opening area of ​​the main opening OPM.

[0203] The semiconductor chip 10D shown in Fig. 20 is similar to the semiconductor chip 10 shown in Fig. 13 except for the above-mentioned differences, so duplicated explanations will be omitted. Note that the semiconductor chip 10D shown in Fig. 20 can be applied in combination with the various modified examples described above.

[0204] 12, 16, 19, and 20 each show a rectangular pattern extending in the X direction as an example of the shape of the position determination aperture pattern. There are various modifications to the shape of the position determination aperture pattern. For example, the shape may be a square, a circle, an ellipse, or a combination of these.

[0205] Fig. 21 is an enlarged plan view showing another modified example of Fig. 13. The semiconductor chip 10E shown in Fig. 21 differs from the semiconductor chip 10 shown in Fig. 13 in that it has a mark for easily performing the above-mentioned "teaching" in the bonding region specifying step shown in Fig. 9.

[0206] The semiconductor chip 10E has a plurality of center position identifying opening patterns CAP extending in a direction perpendicular to the extension direction of each of at least three of the sides, namely side OPS1, side OPS2, side OPS3, and side OPS4, at the center of each of the three sides.

[0207] In the bonding area identification process, the position of the bonding area BR can be easily identified by superimposing multiple center position identifying opening patterns CAP on the crosshairs (horizontal lines 400A and vertical lines 400B) displayed on the monitor 703 (see FIG. 10) of the wire bonding apparatus 700 (see FIG. 10).

[0208] The semiconductor chip 10E shown in Fig. 21 is similar to the semiconductor chip 10 shown in Fig. 13 except for the above-mentioned differences, and therefore a duplicated description will be omitted. Note that the semiconductor chip 10E shown in Fig. 21 can be applied in combination with the various modified examples described above.

[0209] <Modification of the pass / fail judgment process> Next, a description will be given of a modified example of the pass / fail determination step shown in Fig. 4. In the above description, an embodiment has been described in which the pass / fail determination step is performed by an operator visually determining the pass / fail based on the image displayed on the monitor 703 shown in Fig. 10.

[0210] In the following, a modified example will be described in which the quality judgement is automatically performed by the judgement unit 706 provided in the wire bonding apparatus 700 shown in FIG.

[0211] Fig. 22 is a block diagram showing an example of the configuration of the determination unit shown in Fig. 10. In the example shown in Fig. 22, the determination unit 706 has a start determination unit 801, a mark recognition unit 802, an area definition unit 803, a wire shape grasping unit 804, and a pass / fail determination unit 805.

[0212] The start judging unit 801 is configured to be able to judge whether or not to start the pass / fail judgment process shown in Fig. 9. In detail, the start judging unit 801 shown in Fig. 22 is configured to be able to judge whether or not to start judging whether or not the connection position of the wire 51 is within an allowable range after the bonding processing unit 705 connects the wire 51 (see Fig. 2). The start judging unit 801 is configured to selectively start the pass / fail judgment process, for example, after starting the wire bonding apparatus 700 and bonding the first wire 51, after replacing a jig (for example, the wedge tool 753 shown in Fig. 11) attached to the wire bonding apparatus 700 in the wire bonding process, or after changing the wire bonding conditions for performing wire bonding in the wire bonding process.

[0213] The landmark recognition unit 802 is configured to recognize, for example, by using image recognition technology, a position determination opening pattern AP1 and a position determination opening pattern AP2 shown in FIG. 14 from an image captured by the camera 701 and displayed on the monitor 703.

[0214] 22 is configured to define a rectangular bonding area BR serving as a reference for the allowable range, based on the position determination opening pattern AP1 and the position determination opening pattern AP2 shown in Fig. 14 recognized by the mark recognition unit 802. The bonding area BR defined by the area definition unit 803 may be displayed on the monitor 703 shown in Fig. 22.

[0215] The wire shape grasping unit 804 is configured to identify the boundary between the bent portion 51C and the extending portion 51L of the wire 51 based on the image of the wire 51 in Fig. 14 displayed on the monitor 703. The wire shape grasping unit 804 is configured to be able to grasp the position of the joint 51B (or the end 51E) of the wire 51 based on data on the identified boundary between the bent portion 51C and the extending portion 51L.

[0216] The pass / fail judgment unit 805 is configured to judge whether or not the entire bonding portion 51B (or end portion 51E) of the wire 51 is located within the bonding area BR based on the bonding area BR defined by the area definition unit 803 and the position of the bonding portion 51B (or end portion 51E) of the wire 51 grasped by the wire shape grasping unit 804.

[0217] 14 is located within the bonding region BR, the quality determination unit 805 is configured to determine that the bonding position of the wire 51 is acceptable (YES in the quality determination step shown in FIG. 15). On the other hand, the quality determination unit 805 is configured to determine that the bonding position of the wire 51 is defective when a part of the bonding portion 51B (or a part of the end 51E) of the wire 51 is located outside the bonding region BR.

[0218] The result of the judgment is output to the monitor 703, and for example, if it is judged to be defective, a warning display is turned on. Upon seeing the warning display, an operator temporarily stops the work by the wire bonding apparatus 700 and adjusts the settings of the wire bonding apparatus 700.

[0219] On the other hand, if the test is determined to be successful, the next process is started automatically or in response to a command input by the operator.

[0220] For example, the structural features of the semiconductor chip 10 shown in Figures 12, 13, 17, etc. are possessed by the semiconductor chip 10 of the finished semiconductor device PKG1 shown in Figures 2 and 3. Therefore, although a duplicated description will be omitted, the structural features of the semiconductor chip 10 described in <Method of Manufacturing a Semiconductor Device> can be considered as the structural features of the finished semiconductor device PKG1. This point is also true for various modified examples including the semiconductor chip 10A shown in Figure 16, the semiconductor chip 10B shown in Figure 18, the semiconductor chip 10C shown in Figure 19, the semiconductor chip 10D shown in Figure 20, and the semiconductor chip 10E shown in Figure 21.

[0221] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0222] The features of the above-mentioned semiconductor device can be expressed as a technical concept as follows.

[0223] [Appendix 1] A main surface; A pad formed on the main surface; an insulating film having an opening for exposing a part of the pad; A plurality of position determination opening patterns arranged in a region located around the main opening in a plan view; having the opening includes the main opening, In a plan view, the main opening is A first side extending in a first direction; a second side extending in a second direction intersecting the first direction; a third side extending in the second direction and located opposite to the second side; a fourth side extending in the first direction and located opposite the first side; a first corner portion including an intersection point between the first side and an extension line of the second side; a second corner portion including an intersection point between the first side and an extension line of the third side; a third corner including an intersection point between the fourth side and an extension of the second side; a fourth corner including an intersection point between the fourth side and an extension of the third side; having Including, In each of the first side and the fourth side of the main opening, an extension line extending in a direction from the third side toward the second side in a plan view is defined as a first extension line, and an extension line extending in a direction from the second side toward the third side is defined as a second extension line. The plurality of position determination opening patterns are a first position determination opening pattern located between a first extension line of the first side and a first extension line of the fourth side in the second direction and arranged at a position closest to the first corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; a second position determination opening pattern located between a second extension line of the first side and a second extension line of the fourth side in the second direction and arranged at a position closest to the third corner or the fourth corner of the first corner, the second corner, the third corner, and the fourth corner of the main opening; 13. A semiconductor device comprising:

[0224] [Appendix 2] In Appendix 1: the first position determination opening pattern and the second position determination opening pattern each form an opening pattern communicating with the main opening.

[0225] [Appendix 3] In Appendix 1: The plurality of position determination opening patterns are the second position determination opening pattern being located between a second extension line of the first side and a second extension line of the fourth side in the second direction and being arranged at a position closest to the third corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; a third position determination opening pattern located between a first extension line of the first side and a first extension line of the fourth side in the second direction and arranged at a position closest to the second corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; a fourth position determination opening pattern located between a second extension line of the first side and a second extension line of the fourth side in the second direction and arranged at a position closest to the fourth corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; A semiconductor device comprising:

[0226] [Appendix 4] In Appendix 1: The insulating film is an inorganic insulating film formed on the main surface; an organic insulating film formed on the inorganic insulating film; having the first position determination opening pattern and the second position determination opening pattern are each formed in both the inorganic insulating film and the organic insulating film.

[0227] [Appendix 5] In Appendix 1: The insulating film is an inorganic insulating film formed on the main surface; an organic insulating film formed on the inorganic insulating film; having each of the first position determination opening pattern and the second position determination opening pattern is formed at least in the organic insulating film; an opening area of ​​each of the first position determination opening pattern and the second position determination opening pattern is smaller than an opening area of ​​the main opening.

[0228] [Appendix 6] In Appendix 1: the semiconductor device further having a plurality of center position identifying opening patterns extending in a direction perpendicular to the extension direction of each of at least three of the first side, the second side, the third side, and the fourth side of the main opening at the center of each of the three sides.

[0229] [Appendix 7] In Appendix 1: a power transistor consisting of a power MOSFET or an IGBT; a sense transistor for detecting a current flowing through the power transistor; and the pad is a source pad of the power MOSFET or an emitter pad of the IGBT, In a plan view, an extension line of the second side extending in the first direction from the first side toward the fourth side is defined as a third extension line, and an extension line of the third side extending in the second direction from the first side toward the fourth side is defined as a fourth extension line. In a transparent plan view, the sense transistor is located between the third extension line and the fourth extension line.

[0230] [Appendix 8] In Appendix 1: a wire connected to the bonding region of the pad; The wire is A first end portion including a bonding portion having a bonding surface that is a bonding interface with the pad; an extension portion connected to the first end portion, extending in a third direction intersecting each of the first direction and the second direction in a plan view, and intersecting the first side of the main opening in a plan view; Including, the bonding region has a rectangular shape in plan view that is smaller than an opening area of ​​the main opening, the bonding region is defined by the first position determination opening pattern, the second position determination opening pattern, the second side, and the third side; A semiconductor device, wherein the entire joint including the joint portion and the bent portion is located within the bonding region in a plan view. [Explanation of symbols]

[0231] 10, 10A, 10B, 10C, 10D, 10E, 30 Semiconductor chip (semiconductor device) 10b, 30b Bottom surface (main surface, back surface, surface) 10P, 10P2, 30P, 30P2, 30P3 Pads (electrodes, electrode pads) 10P1 Source Pad 10s, 10s1, 10s2, 10s3, 10s4, 30s, 30s1, 30s2, 30s3, 30s4 Side (chip side) 10t, 30t top surface (main surface, surface, surface) 11 Insulating layer 11t main surface 20 Die pad (metal plate, chip mounting area, heat sink) 20b,40b Bottom surface (surface) 20t, 40t top surface (surface) 22,48 Metal film 40, 41, 42, 43, 44, 45, 46, 47 Lead (Terminal) 40M Inner lead part (sealed part) 40W Wire bonding section 40X Outer lead part (outer part, exposed part) 50,51,52,53 Wire 51A Tip 51B Joint 51Bb Joint surface 51C Bend part 51E End 51L extension 60 Sealing body 400A horizontal line 400B Vertical line 700 Wire Bonding Machine 701 Camera (image sensor, imaging processing unit) 702 Camera transport section 703 Monitor (display unit) 704 Semiconductor chip identification unit 705 Bonding Processing Section 706 Judgment section 707 Stage 751 Wire Guide 751H Wire supply hole 752 Cutting blade 753 Wedge Tool 801 Start judgment section 802 Landmark recognition unit 803 Area definition section 804 Wire shape grasper 805 Good / bad judgement section AP1, AP2, AP3, AP4 Position determination aperture pattern AS11, AS21, AS31, AS41 inner edge AS12,AS22,AS32,AS42 Outer edge BR Bonding Area BRS1, BRS2, ​​BRS3, BRS4, OPS1, OPS2, OPS3, OPS4 side CAP center position identification opening pattern CCT control circuit CF Inorganic insulating film CSW Switching circuit DB Die bond material DE Drain electrode DT Insulating Adhesive IF insulating film L1 separation distance LF Lead Frame LFd Device Formation Department LFf Frame part LFt1, LFt2 tie bars OF Organic insulating film OP1,OPC,OPO opening OPC1, OPC2, OPC3, OPC4 corners OPM main opening PKG1 Semiconductor device S2C center TrM Main transistor (power MOSFET) TrS Sense Transistor TS Temperature Sensor VL1,VL2 extension line

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor chip having a main surface, a pad formed on the main surface, and an insulating film formed on the main surface; (b) bonding a wire to a bonding region of the pad exposed through an opening formed in the insulating film; and (c) after the step (b), determining whether or not the bonded portion of the wire is located within the bonding region in a plan view; Where: the opening includes a main opening including the bonding region; In a plan view, the main opening is A first side extending in a first direction; a second side extending in a second direction intersecting the first direction; a third side extending in the second direction and located opposite to the second side; a fourth side extending in the first direction and located opposite to the first side; a first corner portion including an intersection point between the first side and an extension line of the second side or an intersection point between the first side and the second side; a second corner portion including an intersection point between the first side and the third side or an intersection point between the first side and an extension line of the third side; a third corner portion including an intersection point between the fourth side and the second side or an intersection point between the fourth side and an extension line of the second side; a fourth corner portion including an intersection point between the fourth side and an extension line of the third side or an intersection point between the fourth side and the third side; having the insulating film includes a plurality of position determination opening patterns arranged in a region located around the main opening in a plan view, In each of the first side and the fourth side of the main opening, an extension line extending in a direction from the third side toward the second side in a plan view is defined as a first extension line, and an extension line extending in a direction from the second side toward the third side is defined as a second extension line. The plurality of position determination opening patterns are a first position determination opening pattern located between a first extension line of the first side and a first extension line of the fourth side in the second direction and disposed at a position closest to the first corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; a second position determination opening pattern located between a second extension line of the first side and a second extension line of the fourth side in the second direction and arranged at a position closest to the third corner or the fourth corner of the first corner, the second corner, the third corner, and the fourth corner of the main opening; Including, The wire is a first end portion including the bonding portion having a bonding surface that is a bonding interface with the pad; an extension portion connected to the first end portion, extending in a third direction intersecting each of the first direction and the second direction in a plan view, and intersecting the first side of the main opening in a plan view; Including, the bonding region has a rectangular shape in plan view that is smaller than an opening area of ​​the main opening, the bonding region is defined by the first position determination opening pattern, the second position determination opening pattern, the second side, and the third side; In the step (c), the quality is judged based on whether or not the entire joint is located within the bonding region.

2. In claim 1, In a plan view, the first position determination opening pattern has a first inner side extending in the first direction, and a first outer side extending in the first direction and disposed at a position closer to the first side than the first inner side, In a plan view, the second position determination opening pattern has a second inner side extending in the first direction, and a second outer side extending in the first direction and disposed at a position closer to the fourth side than the second inner side, A method for manufacturing a semiconductor device, wherein the bonding region is defined by an extension of the first inner side of the first position determination opening pattern, an extension of the second inner side of the second position determination opening pattern, the second side, and the third side.

3. In claim 1, a first opening pattern for position determination and a second opening pattern for position determination each forming an opening pattern communicating with the main opening;

4. In claim 1, The plurality of position determination opening patterns are the second position determination opening pattern being located between a second extension line of the first side and a second extension line of the fourth side in the second direction and being arranged at a position closest to the third corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; a third position determination opening pattern located between a first extension line of the first side and a first extension line of the fourth side in the second direction and arranged at a position closest to the second corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; a fourth position determination opening pattern located between a second extension line of the first side and a second extension line of the fourth side in the second direction and arranged at a position closest to the fourth corner among the first corner, the second corner, the third corner, and the fourth corner of the main opening; Including, A method for manufacturing a semiconductor device, wherein the bonding area is defined by the first position determination opening pattern, the second position determination opening pattern, the third position determination opening pattern, the fourth position determination opening pattern, the second side, and the third side.

5. In claim 1, The insulating film is an inorganic insulating film formed on the main surface; an organic insulating film formed on the inorganic insulating film; having a first insulating film formed on the insulating layer and a second insulating film formed on the insulating layer, the first opening pattern for position determination and the second opening pattern for position determination being formed in both the inorganic insulating film and the organic insulating film;

6. In claim 1, The insulating film is an inorganic insulating film formed on the main surface; an organic insulating film formed on the inorganic insulating film; having each of the first position determination opening pattern and the second position determination opening pattern is formed at least in the organic insulating film; an opening area of ​​each of the first position determination opening pattern and the second position determination opening pattern is smaller than an opening area of ​​the main opening.

7. In claim 1, The insulating film is an inorganic insulating film formed on the main surface; an organic insulating film formed on the inorganic insulating film; having a first insulating film formed on the insulating layer and a second insulating film formed on the insulating layer, the first opening pattern for position determination and the second opening pattern for position determination being formed in the organic insulating film;

8. In claim 1, The method for manufacturing a semiconductor device, wherein the step (c) is selectively performed after starting up a wire bonding apparatus for carrying out the step (b) and bonding a first wire, after replacing a jig attached to the wire bonding apparatus in the step (b), or after changing wire bonding conditions for performing wire bonding in the step (b).

9. In claim 1, (d) after the step (a) and before the step (b), identifying the bonding region in a portion of the pad exposed in the opening, the semiconductor chip has a plurality of center position specifying opening patterns extending in a direction perpendicular to an extension direction of each of at least three sides among the first side, the second side, the third side, and the fourth side at the center of each of the three sides; In the step (d), the bonding region is identified by superimposing the plurality of center position identifying opening patterns on crosshairs displayed on a monitor of a wire bonding device.

10. In claim 1, The semiconductor chip comprises: a power transistor formed of a power MOSFET or an IGBT; a sense transistor for detecting a current flowing through the power transistor; having The pad is a source pad of the power MOSFET or an emitter pad of the IGBT.

11. In claim 10, In a plan view, an extension line of the second side extending in the first direction from the first side toward the fourth side is defined as a third extension line, and an extension line of the third side extending in the second direction from the first side toward the fourth side is defined as a fourth extension line. In a transparent plan view, the sense transistor is located between the third extension line and the fourth extension line.

12. In claim 1, The method for manufacturing a semiconductor device, wherein in the step (b), the wire is arranged so as to straddle the first side of the main opening in a plan view.

13. In claim 1, A method for manufacturing a semiconductor device, wherein in the step (c), the quality is determined based on whether or not the entire joint and the entire first portion of the wire are located within the bonding region.

14. In claim 13, A method for manufacturing a semiconductor device, wherein the length of the first portion in the second direction is greater than or equal to 8 percent and less than or equal to 12 percent of the length of the joint in the second direction.

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