Semiconductor device

Abstract

To suppress generation of a region where no ions are implanted caused by a foreign material during impurity implantation for forming a buffer layer.SOLUTION: A semiconductor device includes: a semiconductor substrate 100 having a first conductivity-type drift layer 1 between a first main surface 101 on a front side and a second main surface 102 on a rear side; and a collector layer 2 formed in a surface layer part of the semiconductor substrate 100 on the second main surface 102 side, the collector layer being a second conductivity-type rear face impurity layer. A first conductivity-type first buffer layer 31 having a higher peak of the impurity concentration than that of the drift layer 1 and a second buffer layer 32 formed between the first buffer layer 31 and the collector layer 2 and having a higher peak of the impurity concentration than that of the drift layer 1 are provided between the drift layer 1 and the collector layer 2. In an impurity concentration profile with respect to a depth direction from the second main surface 102, a kurtosis of the peak of the impurity concentration of the second buffer layer 32 is lower than a kurtosis of the peak of the impurity concentration of the first buffer layer 31.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] For example, in a power control semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor), a structure is known in which a buffer layer of a first conductivity type having a higher impurity concentration than that of a drift layer is provided between a drift layer of a first conductivity type and a collector layer of a second conductivity type. For example, the following Patent Document 1 discloses a technology in which a plurality of buffer layers are provided to suppress adverse effects on the breakdown voltage characteristics and leakage current characteristics even if damage occurs on the collector layer side. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-188168 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the technology of Patent Document 1, a process of injecting impurities for forming a buffer layer in a semiconductor substrate is performed multiple times while changing the dose amount and acceleration voltage, thereby forming multiple buffer layers. In this method, if a foreign substance is present on the implantation surface of the semiconductor substrate, the foreign substance acts as a mask, resulting in an unimplanted region where the impurities are not implanted, and the adverse effects on the breakdown voltage characteristics and leakage current characteristics may not be sufficiently suppressed.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a technology that can suppress the occurrence of unimplanted regions where impurities are not implanted, even if foreign matter is present on the implantation surface of a semiconductor substrate during implantation of impurities to form a buffer layer. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate having a drift layer of a first conductivity type between a first main surface on a front side and a second main surface on a back side, a semiconductor element structure formed on the first main surface side of the semiconductor substrate, a back surface impurity layer of a second conductivity type formed in a surface layer portion on the second main surface side of the semiconductor substrate, a first buffer layer of the first conductivity type formed between the drift layer and the back surface impurity layer, having a peak of impurity concentration of the first conductivity type and having a higher impurity concentration peak than the drift layer, and a semiconductor element structure formed between the first buffer layer and the back surface impurity layer, having a peak of impurity concentration of the first conductivity type and having a higher impurity concentration peak than the drift layer. and a second buffer layer of a first conductivity type having a high peak of impurity concentration, wherein in an impurity concentration profile of only a first impurity which is a main impurity of the first buffer layer and an impurity concentration profile of only a second impurity which is a main impurity of the second buffer layer, in a depth direction from the second main surface, a kurtosis of the peak of the impurity concentration of the second impurity of the second buffer layer is lower than a kurtosis of the peak of the impurity concentration of the first impurity of the first buffer layer, and the peak of the impurity concentration of the second impurity of the second buffer layer is lower than the peak of the impurity concentration of the first impurity of the first buffer layer. Effect of the Invention

[0007] According to the present disclosure, even if foreign matter is present on the implantation surface of a semiconductor substrate during implantation of impurities to form a buffer layer, the occurrence of an unimplanted region into which impurities are not implanted can be suppressed. [Brief description of the drawings]

[0008] [Figure 1] 1 is a diagram showing the configuration of a semiconductor device according to a first embodiment, in particular the configuration of a second main surface side of a semiconductor substrate. [Diagram 2] 4 is a graph showing an impurity concentration profile in the vicinity of a second main surface of a semiconductor substrate in the semiconductor device according to the first embodiment. [Diagram 3] 4 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating a step of forming a first buffer layer. [Diagram 5] FIG. 11 is a diagram illustrating a step of forming a second buffer layer. [Figure 6] 10A to 10C are views for explaining a modified example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 13 is a flowchart showing a modified example of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 10 is a diagram showing the configuration of a semiconductor device according to a second embodiment, particularly the configuration of a second main surface side of a semiconductor substrate. FIG. [Figure 9] 10 is a graph showing an impurity concentration profile in the vicinity of a second main surface of a semiconductor substrate in a semiconductor device according to a second embodiment. [Figure 10] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 11] 10 is a graph showing an impurity concentration profile in the vicinity of a second main surface of a semiconductor substrate in a modified example of the semiconductor device according to the second embodiment. [Figure 12] 13 is a graph showing an impurity concentration profile in the vicinity of a second main surface of a semiconductor substrate in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] <Embodiment 1> Fig. 1 is a diagram showing the configuration of a semiconductor device according to embodiment 1. The semiconductor device according to embodiment 1 is formed using a semiconductor substrate 100. The semiconductor substrate 100 has a first main surface 101 which is the main surface on the front side, and a second main surface 102 which is the main surface on the back side, and Fig. 1 particularly shows the configuration of the second main surface side of the semiconductor substrate 100.

[0010] Although omitted in Fig. 1, a semiconductor element structure such as an IGBT, an RC-IGBT (Reverse Conducting IGBT), or a diode is formed on the first main surface 101 of the semiconductor substrate 100. In the following embodiments, it is assumed that the semiconductor element formed in the semiconductor device is an IGBT, but the semiconductor device may be something other than an IGBT. In addition, in the following description, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type.

[0011] 1, a drift layer 1 of a first conductivity type is formed between a first main surface 101 and a second main surface 102 of a semiconductor substrate 100. A collector layer 2, which is a back surface impurity layer of a second conductivity type, is formed in a surface layer portion on the second main surface 102 side of the semiconductor substrate 100. In addition, a collector electrode 4, which is a back surface electrode connected to the collector layer 2, is formed on the second main surface 102 of the semiconductor substrate 100.

[0012] A first buffer layer 31 and a second buffer layer 32, each of which has a higher peak impurity concentration than the drift layer 1, are formed between the drift layer 1 and the collector layer 2. The second buffer layer 32 is disposed at a position closer to the second main surface 102 than the first buffer layer 31. That is, the second buffer layer 32 is formed between the first buffer layer 31 and the collector layer 2.

[0013] The first buffer layer 31 and the second buffer layer 32 are preferably formed as shallow as possible because the withstand voltage performance of the semiconductor device can be improved as the depth from the second main surface 102 is shallower. Specifically, the peak of the impurity concentration of the first buffer layer 31 and the peak of the impurity concentration of the second buffer layer 32 are preferably located at a depth of within 1 μm from the second main surface 102.

[0014] Fig. 2 is a graph showing an impurity concentration profile near the second main surface 102 of the semiconductor substrate 100 in the semiconductor device according to the first embodiment. In the graph of Fig. 2, the horizontal axis represents the depth from the second main surface 102, and the vertical axis represents the impurity concentration. That is, the graph of Fig. 2 shows the impurity concentration profile in the depth direction from the second main surface 102.

[0015] 2, the solid line graph is an impurity concentration profile where the first buffer layer 31 and the second buffer layer 32 overlap, that is, an impurity concentration profile integrated without distinguishing between the impurity injected in the process of forming the first buffer layer 31 and the impurity injected in the process of forming the second buffer layer 32. On the other hand, the dotted line graph is an impurity concentration profile of only the impurity injected in the process of forming the first buffer layer 31, and the dashed line graph is an impurity concentration profile of only the impurity injected in the process of forming the second buffer layer 32.

[0016] Hereinafter, the “impurity concentration profile of the first buffer layer 31” and the “impurity concentration profile of the second buffer layer 32” refer to the impurity concentration profile (solid line graph) that combines the impurities injected in the formation process of the first buffer layer 31 and the impurities injected in the formation process of the second buffer layer 32.

[0017] 2, the impurity concentration profile (dashed line graph) of only the impurities implanted in the process of forming the second buffer layer 32 has a wider half-width than the impurity concentration profile (dotted line graph) of only the impurities implanted in the process of forming the first buffer layer 31. As a result, in the impurity concentration profiles (solid line graph) of the first buffer layer 31 and the second buffer layer 32 in the depth direction from the second main surface 102, the kurtosis of the impurity concentration peak of the second buffer layer 32 is lower than the kurtosis of the impurity concentration peak of the first buffer layer 31. In other words, the impurity concentration peak of the first buffer layer 31 is sharper than the kurtosis of the impurity concentration peak of the second buffer layer 32.

[0018] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. Hereinafter, the method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIG.

[0019] First, a first conductivity type semiconductor substrate 100 having a first main surface 101 on the front side and a second main surface 102 on the back side is prepared (step S101). In this embodiment, a silicon (Si) substrate is used as the semiconductor substrate 100. However, the material of the semiconductor substrate 100 is not limited to silicon, and may be a wide band gap semiconductor such as silicon carbide (SiC). When a wide band gap semiconductor is used, a semiconductor device that is superior in operation at high voltages, large currents, and high temperatures can be obtained as compared to conventional semiconductor devices that use silicon.

[0020] Next, a semiconductor element structure (not shown) such as an IGBT is formed on the first main surface 101 side of the semiconductor substrate 100 (step S102). Thereafter, the second main surface 102 of the semiconductor substrate 100 is polished to make the semiconductor substrate 100 have a desired thickness (step S103).

[0021] Next, a first buffer layer 31 is formed by implanting a first conductive type impurity into the second main surface 102 of the semiconductor substrate 100 (step S104). Furthermore, a second buffer layer 32 is formed at a position closer to the second main surface 102 than the first buffer layer 31 by implanting a first conductive type impurity into the second main surface 102 of the semiconductor substrate 100 (step S105). Then, laser annealing is performed as a first laser annealing for activating the impurities in the first buffer layer 31 and the second buffer layer 32 by laser heat (step S106).

[0022] In the present embodiment, phosphorus (P) is used as an impurity for forming the first buffer layer 31 and the second buffer layer 32, but arsenic (As), selenium (Se), etc. may also be used. When the semiconductor substrate 100 made of silicon carbide is used, nitrogen (N) is preferably used as an impurity for forming the first buffer layer 31 and the second buffer layer 32.

[0023] Here, the implantation amount, implantation angle, and acceleration voltage, which are the implantation conditions of the impurity in the process of forming the first buffer layer 31, are respectively set as a first implantation amount, a first implantation angle, and a first acceleration voltage. Also, the implantation amount, implantation angle, and acceleration voltage, which are the implantation conditions of the impurity in the process of forming the second buffer layer 32, are respectively set as a second implantation amount, a second implantation angle, and a second acceleration voltage.

[0024] In this embodiment, the second implantation angle is set to be larger than the first implantation angle. For example, the first implantation angle is set to about 5°, and the second implantation angle is set to be 30° or more and 60° or less. As a result, as shown in FIG. 2, the half-width of the impurity concentration profile of only the impurity implanted in the formation process of the second buffer layer 32 is wider than the half-width of the impurity concentration profile of only the impurity implanted in the formation process of the first buffer layer 31. As a result, in the impurity concentration profiles of the first buffer layer 31 and the second buffer layer 32, the kurtosis of the impurity concentration peak of the second buffer layer 32 is lower than the kurtosis of the impurity concentration peak of the first buffer layer 31.

[0025] Next, a collector layer 2, which is a backside impurity layer, is formed in the surface layer portion on the second main surface 102 side of the semiconductor substrate 100 by implanting a second conductive type impurity into the second main surface 102 of the semiconductor substrate 100 (step S107). Then, laser annealing is performed as a second laser annealing for activating the impurity in the collector layer 2 by the heat of a laser (step S108). As the impurity for forming the collector layer 2, for example, boron (B) can be used.

[0026] Finally, collector electrode 4, which is a back surface electrode, is formed on second main surface 102 of semiconductor substrate 100 (step S109). Thereby, a semiconductor device having the structure shown in FIG.

[0027] Here, it is assumed that a foreign substance exists on the second main surface 102, which is an implantation surface, during the implantation of impurities to form the first buffer layer 31 and the second buffer layer 32. In the process of forming the first buffer layer 31, the impurities are implanted at a relatively small first implantation angle θ1 as shown in FIG. 4, so that an unimplanted region occurs at a position almost directly below the foreign substance. On the other hand, in the process of forming the second buffer layer 32, the impurities are implanted at a relatively large second implantation angle θ2 as shown in FIG. 5, so that an unimplanted region occurs at a position shifted from the foreign substance (a position shifted from the unimplanted region of the first buffer layer 31). In this way, even if an unimplanted region is formed in both the first buffer layer 31 and the second buffer layer 32 by the foreign substance, the unimplanted region of the first buffer layer 31 and the unimplanted region of the second buffer layer 32 are positioned offset from each other, so that an unimplanted region penetrating the first buffer layer 31 and the second buffer layer 32 is unlikely to occur. Therefore, it is possible to stabilize the withstand voltage characteristics and the leakage current characteristics.

[0028] The first injection amount, which is the amount of impurities injected in the process of forming the first buffer layer 31, and the second injection amount, which is the amount of impurities injected in the process of forming the second buffer layer 32, may be equal to each other. In other words, the process of forming the first buffer layer 31 and the process of forming the second buffer layer 32 may be performed without changing the setting of the injection amount of the impurities. In that case, in the second buffer layer 32 into which the impurities are injected at a relatively large second injection angle, the injection depth varies widely, and therefore, as shown in FIG. 2, the peak of the impurity concentration in the second buffer layer 32 is lower than the peak of the impurity concentration in the first buffer layer 31.

[0029] In addition, the second buffer layer 32 is in contact with the collector layer 2, and depending on the conditions, the impurities in the second buffer layer 32 may act to substantially reduce the concentration of the impurities in the collector layer 2, which may cause problems such as an increase in the on-voltage of the semiconductor device and a decrease in the amount of hole injection during a short circuit. To prevent this, the second injection amount may be made smaller than the first injection amount.

[0030] The first acceleration voltage, which is the acceleration voltage for impurity implantation in the process of forming the first buffer layer 31, and the second acceleration voltage, which is the acceleration voltage for impurity implantation in the process of forming the second buffer layer 32, may be equal. In other words, the process of forming the first buffer layer 31 and the process of forming the second buffer layer 32 may be performed without changing the setting of the acceleration voltage for impurity implantation. Even in this case, the second buffer layer 32 into which impurities are implanted at a relatively large second implantation angle is formed shallow, so that the peak of the impurity concentration of the second buffer layer 32 is closer to the second main surface 102 than the peak of the impurity concentration of the first buffer layer 31, as shown in FIG. 2. By changing the acceleration voltage for impurity implantation, higher productivity can be obtained compared to forming the first buffer layer 31 and the second buffer layer 32 at different depths.

[0031] The impurity may be injected from a plurality of directions in the process of forming the first buffer layer 31. Similarly, the impurity may be injected from a plurality of directions in the process of forming the second buffer layer 32. Specifically, in the process of forming the first buffer layer 31 or the process of forming the second buffer layer 32, the impurity may be injected a plurality of times while changing the rotation angle θ3 of the wafer of the semiconductor substrate 100 as shown in FIG. 6. For example, the rotation angle θ3 may be set to 0°, 90°, 180°, and 270°, and four impurity injections may be performed. This further suppresses the occurrence of uninjected regions.

[0032] In addition, the flowchart shown in FIG. 3 shows an example in which, after the first buffer layer 31 and the second buffer layer 32 are formed, laser annealing is performed to activate the impurities in the first buffer layer 31 and the second buffer layer 32 (step S106), and, after the collector layer 2 is formed, laser annealing is performed to activate the impurities in the collector layer 2 (step S108). However, after all of the first buffer layer 31, the second buffer layer 32, and the collector layer 2 are formed, laser annealing to activate the impurities in the first buffer layer 31, the second buffer layer 32, and the collector layer 2 may be performed all at once. A flowchart in this case is shown in FIG. 7. The flowchart in FIG. 7 is obtained by omitting step S106 from the flowchart in FIG. 3 and replacing step S108 with step S110. In step S110, laser annealing is performed all at once to activate the impurities in the first buffer layer 31, the second buffer layer 32, and the collector layer 2. The other steps are the same as those in FIG. 3, so a description thereof will be omitted here.

[0033] <Embodiment 2> 8 is a diagram showing the configuration of a semiconductor device according to a second embodiment, and particularly shows the configuration of the second main surface side of semiconductor substrate 100. The semiconductor device according to the second embodiment is obtained by adding a third buffer layer 33 of the first conductivity type between drift layer 1 and first buffer layer 31, that is, at a position farther from second main surface 102 than first buffer layer 31, to the configuration of the first embodiment. The other elements are basically the same as those of the first embodiment.

[0034] 9 is a graph showing an impurity concentration profile near the second main surface 102 of the semiconductor substrate 100 in the semiconductor device according to the second embodiment, and shows the impurity concentration profile in the depth direction from the second main surface 102. As shown in FIG. 9, the peak of the impurity concentration of the third buffer layer 33 is higher than the peak of the impurity concentration of the drift layer 1 and is lower than the peaks of the impurity concentrations of the first buffer layer 31 and the second buffer layer 32.

[0035] By providing the third buffer layer 33, adverse effects on the breakdown voltage characteristics and leakage voltage characteristics caused by damage (unimplanted region, etc.) occurring in the structure on the collector layer 2 side of the drift layer 1 can be suppressed more than in the case of embodiment 1. Furthermore, the expansion of the depletion layer can be gradually stopped during switching operations of the semiconductor device, and jumps and oscillations of the voltage applied to the semiconductor device can be suppressed.

[0036] Fig. 10 is a flowchart showing a method for manufacturing a semiconductor device according to embodiment 2. The flowchart in Fig. 10 is obtained by adding step S111 after step S105 and step S112 after step S108 to the flowchart in Fig. 3.

[0037] In step S111, a first conductive type impurity is implanted into the second main surface 102 of the semiconductor substrate 100 to form a third buffer layer 33 at a position farther from the second main surface 102 than the first buffer layer 31. In step S112, a furnace anneal is performed to activate the impurity in the third buffer layer 33. In this embodiment, protons are used as the impurity for forming the third buffer layer 33, and the temperature of the furnace anneal to activate it is set to about 400° C. The other steps are the same as those in FIG. 3, and therefore will not be described here.

[0038] In this embodiment, similarly to the flow of FIG. 7, laser annealing for activating impurities in the first buffer layer 31, the second buffer layer 32, and the collector layer 2 may be performed collectively after the first buffer layer 31, the second buffer layer 32, and the collector layer 2 are all formed.

[0039] FIG. 9 shows an example in which the impurity concentration profile of the third buffer layer 33 has a single peak, but as shown in FIG. 11, the impurity concentration profile of the third buffer layer 33 may have multiple peaks at different depths from the second main surface 102.

[0040] <Embodiment 3> 12 is a graph showing an impurity concentration profile in the vicinity of the second main surface of the semiconductor substrate in the semiconductor device according to the third embodiment, and shows the impurity concentration profile in the depth direction from the second main surface 102. The configuration of the semiconductor device according to the third embodiment, particularly the configuration on the second main surface side of the semiconductor substrate, is similar to that in FIG. 1, and a first buffer layer 31 and a second buffer layer 32 are formed between the drift layer 1 and the collector layer 2.

[0041] 12, the second buffer layer 32 is located between the first buffer layer 31 and the collector layer 2, and in the impurity concentration profiles of the first buffer layer 31 and the second buffer layer 32 in the depth direction from the second main surface 102, the kurtosis of the impurity concentration peak of the second buffer layer 32 is lower than the kurtosis of the impurity concentration peak of the first buffer layer 31. Moreover, the impurity concentration peak of the second buffer layer 32 is lower than that of the first buffer layer 31, and the impurity concentration profile of the second buffer layer 32 has a flat region with a width of 100 nm or more near the peak, where the impurity concentration of the second buffer layer 32 is 95% or more of the maximum value.

[0042] When the impurity concentration profile of the second buffer layer 32 has a flat region near the peak, the expansion of the depletion layer is more likely to be stopped during switching operations of the semiconductor device, thereby achieving stable breakdown voltage characteristics and leakage current characteristics.

[0043] The manufacturing method of the semiconductor device according to the third embodiment may be basically the same as the manufacturing method shown in the first embodiment, and the desired impurity concentration profile can be obtained by performing laser annealing to activate the impurities in the first buffer layer 31 with an output sufficient to melt the semiconductor substrate 100.

[0044] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate. [Explanation of symbols]

[0045] 1 drift layer, 2 collector layer, 31 first buffer layer, 32 second buffer layer, 33 third buffer layer, 4 collector electrode, 100 semiconductor substrate, 101 first main surface, 102 second main surface.

Claims

1. a semiconductor substrate having a drift layer of a first conductivity type between a first main surface on a front side and a second main surface on a back side; a semiconductor element structure formed on the first main surface side of the semiconductor substrate; a second conductivity type back surface impurity layer formed in a surface layer portion on the second main surface side of the semiconductor substrate; a first buffer layer of a first conductivity type formed between the drift layer and the back surface impurity layer, the first buffer layer having a peak of an impurity concentration of a first conductivity type higher than that of the drift layer; a first conductivity type second buffer layer formed between the first buffer layer and the back surface impurity layer, the second buffer layer having a first conductivity type impurity concentration peak higher than that of the drift layer; Equipped with in an impurity concentration profile of only a first impurity which is a main impurity of the first buffer layer and an impurity concentration profile of only a second impurity which is a main impurity of the second buffer layer, in a depth direction from the second main surface, a kurtosis of a peak of the impurity concentration of the second impurity of the second buffer layer is lower than a kurtosis of a peak of the impurity concentration of the first impurity of the first buffer layer, a peak impurity concentration of the second impurity in the second buffer layer is lower than a peak impurity concentration of the first impurity in the first buffer layer; Semiconductor device.

2. a peak of the impurity concentration of the first impurity in the first buffer layer and a peak of the impurity concentration of the second impurity in the second buffer layer are located at a depth of within 1 μm from the second main surface; The semiconductor device according to claim 1 .

3. in an impurity concentration profile of only the second impurity in the second buffer layer in a depth direction from the second main surface, a region in which the impurity concentration of the second impurity in the second buffer layer is 95% or more of a maximum value exists with a width of 100 nm or more; 3. The semiconductor device according to claim 1 or 2.

4. a third buffer layer of the first conductivity type formed between the drift layer and the first buffer layer, the third buffer layer having a peak of an impurity concentration of the first conductivity type, the peak of the impurity concentration being higher than that of the drift layer and lower than that of the first buffer layer and the second buffer layer; The semiconductor device according to claim 1 .

5. the third buffer layer has a plurality of impurity concentration peaks at different depths from the second main surface; The semiconductor device according to claim 4.

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