Semiconductor device and method for manufacturing the same

Abstract

To provide a method for manufacturing a semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a substrate, the trench extending downward from a top surface of the substrate and having a sidewall and a bottom surface, in which the included angle between the sidewall and the bottom surface is 90 degrees or more; forming a well region on the top surface of the substrate, and the sidewall and the bottom surface of the trench; forming a source region on the bottom surface of the trench; forming a body contact region adjacent to the source region on the bottom surface of the trench; forming a gate structure along the top surface of the substrate and the sidewall and the bottom surface of the trench; and forming a source contact in the trench, the source contact penetrating the gate structure and electrically connecting the source region and the body contact region to each other.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] Some embodiments of the present disclosure relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Metal oxide semiconductor field effect transistors can be divided into horizontal channel MOSFETs and vertical channel MOSFETs according to their channel direction. Vertical channel MOSFETs can provide the same current with a small area and obtain a small on-resistance (Rdson), thus greatly reducing production costs. How to further improve the efficiency of vertical channel MOSFETs has also become an important issue. Summary of the Invention [Means for solving the problem]

[0003] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including forming a trench in a substrate, the trench extending downward from a top surface of the substrate, the trench having sidewalls and a bottom surface, the sidewalls and the bottom surface having an included angle of 90° or greater; forming a well region on the top surface of the substrate, the sidewalls and the bottom surface of the trench; forming a source region on the bottom surface of the trench; forming a body contact region on the bottom surface of the trench adjacent to the source region; forming a gate structure along the top surface of the substrate, the sidewalls and the bottom surface of the trench; and forming a source contact in the trench that penetrates the gate structure and electrically connects the source region and the body contact region.

[0004] In some embodiments, the trench is an inverted trapezoidal trench.

[0005] In some embodiments, forming a trench in a substrate includes forming a plurality of stepped dielectric layer stacks on the substrate and etching the substrate using the stepped dielectric layer stacks as a mask to form the trench.

[0006] In some embodiments, forming a graded dielectric layer stack on a substrate includes forming a dielectric layer stack on a substrate including a first dielectric layer made of a cross-stacked plurality of first materials and a second dielectric layer made of a second material different from the plurality of first materials, and patterning the dielectric layer stack multiple times with a photomask to form the graded dielectric layer stack.

[0007] In some embodiments, when a substrate is etched using the graded dielectric layer stack as a mask, the graded dielectric layer stack and the substrate are etched at the same etch rate.

[0008] In some embodiments, the lattice orientation of the substrate determines the included angle between the sidewall and the base.

[0009] Some embodiments of the present disclosure provide a semiconductor device that includes a substrate having a trench extending downward from a top surface of the substrate, the trench having sidewalls and a bottom surface, the included angle between the sidewalls and the bottom surface being 90° or greater; a gate structure in the substrate and along the top surface of the substrate, the sidewalls and the bottom surface of the trench; a source contact in the substrate trench and through the gate structure electrically connected to a source region of the substrate; and a drain electrode underlying the substrate.

[0010] In some embodiments, the trench is an inverted trapezoidal trench.

[0011] In some embodiments, the source region is at a bottom surface of the trench and the substrate further comprises a well region along a top surface of the substrate, sidewalls and a bottom surface of the trench, and a body contact region at the bottom surface of the trench and adjacent to the source region.

[0012] In some embodiments, the sidewalls of the trench extend in the same direction as the lattice alignment of the substrate. [Brief description of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Diagram 2] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Diagram 3] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Figure 4] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Diagram 5] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. [Figure 7] 11A and 11B are cross-sectional views illustrating semiconductor devices according to some further embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Some embodiments of the present disclosure relate to the formation of vertical channel power semiconductor devices. Power semiconductor devices having vertical channels can provide a large current in the same area and therefore a small on-resistance.

[0015] 1-6 show cross-sectional views of a semiconductor device according to some embodiments of the present disclosure. Referring to FIG. 1, a substrate 110 is provided. The substrate 110 may be any suitable semiconductor substrate. For example, the substrate 110 may be a silicon substrate or a silicon carbide substrate. In some embodiments, the substrate 110 is a lightly doped region having a first conductivity type, for example, the substrate 110 may be an N-type lightly doped region and includes N-type dopants such as arsenic, phosphorus, and nitrogen.

[0016] Subsequently, a dielectric layer stack is formed on the substrate 110, the dielectric layer stack including a plurality of first dielectric layers 210 and a plurality of second dielectric layers 220 cross-stacked, the first dielectric layer 210 being made of a first material, and the second dielectric layer 220 being made of a second material different from the first material. In some embodiments, the first dielectric layer 210 may be made of silicon oxide, and the second dielectric layer 220 may be made of silicon nitride. In some embodiments, the thickness of the first dielectric layer 210 and the second dielectric layer 220 may be between 0.1 microns and 0.5 microns. In some embodiments, the dielectric layer stack may include 2 to 10 layers of each of the first dielectric layers 210 and the second dielectric layers 220. In the following description, the present disclosure takes as an example a case where the dielectric layer stack includes three layers of the first dielectric layers 210A, 210B, 210C, and three layers of the second dielectric layers 220A, 220B, 220C.

[0017] Then, a first patterning process is performed by a photomask to pattern the dielectric layer stack having the first sidewall S1. Specifically, a first photoresist layer can be formed on the dielectric layer stack first, and the first photoresist layer can be patterned by the photomask, and then all the dielectric layers in the dielectric layer stack can be patterned by the first photoresist layer. At this time, the photomask is at a first position.

[0018] Then, the photomask is moved in the first direction D1, and a second patterning process is performed by the photomask to partially pattern the dielectric layer stack, so that the dielectric layer stack has a first sidewall S1 and a second sidewall S2 offset in the first direction D1, and the second sidewall S1 is on the first sidewall S1. Specifically, a second photoresist layer can be formed on the dielectric layer stack, and the photomask can be moved along the first direction D1 based on the first position to place the photomask in a second position, and the second photoresist layer can be patterned by the photomask. The second photoresist layer is offset by a distance along the first direction D1 from the first photoresist layer. Then, the second dielectric layer 220C is first etched using a first gas with the second photoresist layer as a mask, and then the first dielectric layer 210C is etched using a second gas with the second dielectric layer 220C as a mask. Since the second dielectric layer 220 and the first dielectric layer 210 are made of different materials, different etching gases can be selected to etch the first dielectric layer 210 and the second dielectric layer 220, respectively. In this disclosure, the first gas may be defined as a gas that has an etch rate for the second dielectric layer 220 that is greater than the etch rate for the first dielectric layer 210. The second gas may be defined as a gas that has an etch rate for the first dielectric layer 210 that is greater than the etch rate for the second dielectric layer 220.

[0019] Then, the photomask is moved in the first direction, and a third patterning process is performed by the photomask to partially pattern the dielectric layer stack, so that the dielectric layer stack further has a third sidewall S3, and the third sidewall S3 is offset in the first direction D1 from the second sidewall S2, and the third sidewall S3 is on the second sidewall S2. Specifically, a third photoresist layer can be formed on the dielectric layer stack, and the photomask can be moved along the first direction D1 based on the second position to position the photomask at a third position, and the third photoresist layer can be patterned by the photomask. The third photoresist layer is offset by a distance along the first direction D1 from the second photoresist layer. Then, the second dielectric layer 220C and the second dielectric layer 220B are respectively etched using a first gas, respectively, with the photoresist layer and the first dielectric layer 210C as masks. Then, the first dielectric layer 210C and the intermediate first dielectric layer 210B are etched using a second gas with the second dielectric layer 220C and the second dielectric layer 220B as masks, respectively.

[0020] Then, the photomask is moved in the first direction, and a fourth patterning process is performed by the photomask to partially pattern the dielectric layer stack, so that the dielectric layer stack further has a fourth sidewall S4, and the fourth sidewall S4 is offset in the first direction from the third sidewall S3, and the fourth sidewall S4 is on the third sidewall S3. Specifically, a fourth photoresist layer can be formed on the dielectric layer stack, and the photomask can be moved along the first direction based on the third position to place the photomask at a fourth position, and the fourth photoresist layer can be patterned by the photomask. The fourth photoresist layer is offset by a distance along the first direction D1 from the third photoresist layer. Then, the second dielectric layer 220C, the second dielectric layer 220B, and the second dielectric layer 220A are etched using the first gas, respectively, with the fourth photoresist layer, the first dielectric layer 210C, and the first dielectric layer 210B as masks. This results in a stepped sidewall on one side of the dielectric layer stack.

[0021] Subsequently, the other sidewall of the dielectric layer stack is also stepped (e.g., the photomask starts moving from the first position in the second direction D2) in the same manner as above, thus forming a plurality of stepped dielectric layer stacks 200 on the substrate 110. In the present disclosure, the photomask PM can be used to pattern the dielectric layer stack to form the stepped dielectric layer stack 200. The shape of the sidewall of the stepped dielectric layer stack 200 is determined by the amplitude of each movement of the photomask PM. Also, the offset distances of the second photoresist layer, the third photoresist layer, and the fourth photoresist layer correspond to the amplitude of each movement of the photomask. The stepped dielectric layer stack 200 includes sequentially shrunk sidewalls S1, S2, S3, and S4. In some embodiments, the horizontal distance between two adjacent sidewalls (e.g., the horizontal distance between sidewalls S1 and S2, the horizontal distance between sidewalls S2 and S3, and the horizontal distance between sidewalls S3 and S4) is between about 0.1 microns and 0.5 microns. The stepped dielectric layer stack 200 includes a plurality of cross-stacked first dielectric layers 210 and a plurality of second dielectric layers 220, where the first dielectric layers 210 are made of a first material and the second dielectric layers 220 are made of a second material different from the first material. In some embodiments, the first dielectric layers 210 may be made of silicon oxide and the second dielectric layers 220 may be made of silicon nitride. In some embodiments, the thickness of the first dielectric layers 210 and the second dielectric layers 220 may be between 0.1 microns and 0.5 microns. In some embodiments, the dielectric layer stack may include between 2 and 10 layers of each of the first dielectric layers 210 and the second dielectric layers 220.

[0022] 2, a trench T is formed in the substrate 110. Specifically, the substrate 110 can be etched using the stepped dielectric layer stack 200 as a mask to form the trench T. When the substrate 110 is etched using the stepped dielectric layer stack 200 as a mask, the stepped dielectric layer stack 200 and the substrate 110 are etched at the same etching rate until the stepped dielectric layer stack 200 is completely etched. Thus, a stepped trench T can be formed in the substrate 110.

[0023] After forming the stepped trench T, a smoothing process can be performed on the surface of the substrate 110, so that the surface of the trench T of the substrate 110 is smooth. In some embodiments, referring to FIG. 3, an oxidation process can be performed on the substrate 110 first to form an oxide layer 111 on the surface of the substrate 110, and then referring to FIG. 4, the oxide layer 111 is removed, so that the surface of the trench T of the substrate 110 is smooth. After the smoothing process, the trench T extends downward from the top surface 112 of the substrate 110, the trench T has a sidewall 114 and a bottom surface 116, and the included angle between the sidewall 114 and the bottom surface 116 is greater than 90°. That is, the trench T is an inverted trapezoid trench.

[0024] 5, a first ion implantation process is performed on the substrate 110 to form a well region 122 on the top surface 112 of the substrate 110, the sidewall 114 of the trench T, and the bottom surface 116 of the substrate 110. Specifically, when performing the first ion implantation process, a dopant of a second conductivity type may be implanted into the substrate 110 to form a well region 122 having the second conductivity type on the top surface 112 of the substrate 110, the sidewall 114 of the trench T, and the bottom surface 116 of the substrate 110. In some embodiments, the well region 122 may be a lightly doped region of the second conductivity type, for example, the well region 122 may be a lightly doped region of P type, and includes a P type dopant, such as boron, gallium, and aluminum. The remaining region not implanted with the dopant of the second conductivity type is still maintained as a doped region of the first semiconductor type, and the doped region having the first semiconductor type may be referred to as a drift region 121. The doping concentration of the well region 122 is higher than the doping concentration of the drift region 121 .

[0025] Subsequently, a second ion implantation process is performed on the substrate 110 to form a source region 124 at the bottom surface 116 of the trench T. Specifically, when performing the second ion implantation process, a dopant of a first conductivity type may be implanted into the substrate 110 to form a source region 124 having the first conductivity type at the bottom surface 116 of the trench T. In some embodiments, the source region 124 may be a heavily doped region of the first conductivity type, and the doping concentration of the source region 124 is higher than the doping concentration of the well region 122, for example, the source region 124 may be a heavily doped region of N type, and includes N type dopants such as arsenic, phosphorus, and nitrogen.

[0026] After forming the source region 124, a junction field-effect transistor (JFET) region 126 may also be formed on the top surface 112 of the substrate 110, such that the JFET region 126 and the source region 124 have the same conductivity type and doping concentration. In some embodiments, the JFET region 126 may be a heavily doped region of a first conductivity type, for example, the JFET region 126 may be a heavily doped region of N-type and include N-type dopants such as arsenic, phosphorous, and nitrogen.

[0027] Subsequently, a third ion implantation process is performed on the substrate 110 to form a body contact region 128 at the bottom surface 116 of the trench T adjacent to the source region 124. Specifically, when performing the third ion implantation process, a dopant of a second conductivity type may be implanted into the substrate 110 to form a body contact region 128 having the second conductivity type at the bottom surface 116 of the trench T. In some embodiments, the body contact region 128 may be a heavily doped region of the second conductivity type, and the doping concentration of the body contact region 128 is higher than the doping concentration of the well region 122, for example, the body contact region 128 may be a heavily doped region of P type, and includes a P type dopant, such as boron, gallium, and aluminum.

[0028] A gate structure 130 is then formed along the top surface 112 of the substrate 110, the sidewalls 114 and the bottom surface 116 of the trench T. In some embodiments, the gate structure 130 may have a first horizontal portion located on the top surface 112 of the substrate 110, a sloped portion located on the sidewalls 114 of the trench T, and a second horizontal portion located on the bottom surface 116 of the trench T. Specifically, a gate dielectric layer 132 may first be formed on the substrate 110 and along the top surface 112 of the substrate 110, the sidewalls 114 and the bottom surface 116 of the trench T. A gate layer 134 is then formed on the gate dielectric layer 132. The gate dielectric layer 132 and the gate layer 134 may be collectively referred to as the gate structure 130. An opening may then be formed in the gate structure 130 to expose the body contact region 128 and a portion of the source region 124. In some embodiments, the gate dielectric layer 132 may be made of silicon oxide and the gate layer 134 may be made of polycrystalline silicon.

[0029] Referring to FIG. 6, a dielectric layer 140 is formed on the substrate 110 and in the trench T. The dielectric layer 140 also completely fills the opening of the gate structure 130. Then, a source contact 150 is formed in the trench T, penetrating the gate structure 130 and contacting the source region 124 and the body contact region 128. Specifically, an opening exposing the source region 124 and the body contact region 128 can be formed in the dielectric layer 140 first, and then a contact material can be formed in the opening to form the source contact 150. Thus, the source contact 150 simultaneously penetrates the dielectric layer 140 and the gate structure 130, contacts the source region 124 and the body contact region 128, and the dielectric layer 140 surrounds the source contact 150. Then, a drain electrode 160 is formed under the substrate 110.

[0030] In this manner, the semiconductor device shown in FIG. 6 can be obtained. The semiconductor device may include a substrate 110, a gate structure 130, a source contact 150, and a drain electrode 160. The substrate 110 includes a trench T extending downward from a top surface 112 of the substrate 110, the trench T having a sidewall 114 and a bottom surface 116, and an included angle between the sidewall 114 and the bottom surface 116 is greater than 90°. The substrate 110 includes a drift region 121, a well region 122, a JFET region 126, a body contact region 128, and a source region 124. The well region 122 is on the drift region 121, and the well region 122 is along the top surface 112 of the substrate 110, the sidewall 114, and the bottom surface 116 of the trench T. The JFET region 126 is in the top surface 112 of the substrate 110. A source region 124 is at the bottom surface 116 of the trench T. A body contact region 128 is at the bottom surface 116 of the trench T and adjacent to the source region 124. A gate structure 130 is on the substrate 110 and along the top surface 112 of the substrate 110, the sidewalls 114 and the bottom surface 116 of the trench T. A source contact 150 is in the trench T of the substrate 110 and extends through the gate structure 130 and contacts the substrate 110, electrically connecting the source region 124 and the body contact region 128. A drain electrode 160 is below the substrate 110.

[0031] The semiconductor device of the present disclosure has a vertical channel, which is a well region 122 along the sidewall 114 of the trench T. When the semiconductor device has a vertical channel and, for example, the included angle between the sidewall 114 and the bottom surface 116 of the trench T is greater than 90°, a large current can be supplied in the same area, and therefore a large on-resistance can be provided. In addition, the included angle between the sidewall 114 and the bottom surface 116 is determined by the lattice arrangement direction of the substrate 110. Specifically, the included angle between the sidewall 114 and the bottom surface 116 can determine the extension direction of the well region 122 along the sidewall 114 of the trench, that is, the direction of the channel. When the direction of the channel is the same as the arrangement direction of the substrate 110, carriers can have the maximum carrier mobility in the channel. That is, the lattice orientation of the substrate 110 determines the included angle between the sidewall 114 and the bottom surface 116, ensuring that carriers have maximum carrier mobility in the channel and maximum current (e.g., when the extension direction of the trench sidewall 114 is the same as the lattice orientation of the substrate 110). A portion of the gate structure 130 is formed along the trench sidewall 114, so that when the extension direction of the trench sidewall 114 is the same as the lattice orientation of the substrate 110, the extension direction of the gate structure 130 on the trench sidewall 114 is also the same as the lattice orientation of the substrate 110.

[0032] FIG. 7 shows a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. The semiconductor device in FIG. 7 is similar to the semiconductor device in FIG. 6, with the difference being that the angle between the sidewall 114 and the bottom surface 116 of the trench in the semiconductor device in FIG. 7 is 90°. When manufacturing the semiconductor device in FIG. 7, the step-like dielectric layer stack in the process in FIG. 1 can be directly replaced with a hard mask layer having vertical sidewalls, and the hard mask layer having vertical sidewalls can be used to etch the substrate 110. Then, the process in FIG. 2 to FIG. 6 is performed to form the semiconductor device in FIG. 7. When the angle between the sidewall 114 and the bottom surface 116 of the trench in the semiconductor device is 90°, the semiconductor device can also provide a large current in the same area, and thus a small on-resistance.

[0033] The above are only some embodiments of the present disclosure, not all embodiments, and any equivalent changes made by those skilled in the art to the technical solutions of the present disclosure through reading the specification of the present disclosure are all included in the scope of the claims of the present disclosure. [Explanation of symbols]

[0034] 110: Substrate 111: Oxide layer 112:Top surface 114: Side wall 116: Bottom 121: Drift region 122: Well area 124: Source area 126: Junction Field Effect Transistor Area / JFET Area 128: Body contact area 130: Gate structure 132: Gate dielectric layer 134: Gate layer 140: Dielectric layer 150: Source contact 160: Drain electrode 210: First dielectric layer 220: second dielectric layer S1, S2, S3, S4: Side wall T: Trench

Claims

1. forming a trench in a substrate extending downwardly from a top surface of the substrate, the trench having sidewalls and a bottom surface, the included angle between the sidewalls and the bottom surface being greater than or equal to 90 degrees; forming a well region on the top surface of the substrate, the sidewalls and the bottom surface of the trench; forming a source region on the bottom surface of the trench; forming a body contact region on the bottom surface of the trench adjacent to the source region; forming a gate structure along the top surface of the substrate, the sidewalls and the bottom surface of the trench; forming a source contact in the trench, passing through the gate structure and electrically connecting the source region and the body contact region; A method for manufacturing a semiconductor device comprising the steps of:

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the trench is an inverted trapezoid trench.

3. The step of forming the trench in the substrate comprises: forming a plurality of graded dielectric layer stacks on the substrate; etching the substrate using the graded dielectric layer stack as a mask to form the trench; The method for manufacturing a semiconductor device according to claim 2 , further comprising:

4. forming the graded dielectric layer stack on the substrate, forming a dielectric layer stack on the substrate, the dielectric layer stack comprising a plurality of cross-stacked first dielectric layers made of a first material and a plurality of second dielectric layers made of a second material different from the first material; patterning the dielectric layer stack multiple times with a photomask to form the graded dielectric layer stack; The method for manufacturing a semiconductor device according to claim 3 , further comprising:

5. 4. The method of claim 3, wherein when the substrate is etched using the stepped dielectric layer stack as a mask, the stepped dielectric layer stack and the substrate are etched at the same etching rate.

6. 6. The method for manufacturing a semiconductor device according to claim 1, wherein an included angle between the sidewall and the bottom surface is determined by a lattice arrangement direction of the substrate.

7. a substrate having a trench extending downward from a top surface of the substrate, the trench having sidewalls and a bottom surface, the included angle between the sidewalls and the bottom surface being greater than or equal to 90 degrees; a gate structure on the substrate and along a top surface of the substrate, the sidewalls and the bottom surface of the trench; a source contact in the trench of the substrate and electrically connected through the gate structure to a source region of the substrate; a drain electrode underlying the substrate; A semiconductor device comprising:

8. The semiconductor device according to claim 7 , wherein the trench is an inverted trapezoid trench.

9. the source region is at the bottom surface of the trench; The substrate is a well region along a top surface of the substrate, the sidewalls and the bottom surface of the trench; a body contact region at the bottom surface of the trench and adjacent to the source region; The semiconductor device according to any one of claims 7 to 8, further comprising:

10. 9. The semiconductor device according to claim 7, wherein the extending direction of the sidewall of the trench is the same as the lattice arrangement direction of the substrate.

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