Bias control circuit

Abstract

To provide a bias control circuit in which an operating point of an amplifier circuit is not changed even when power supply voltage is fluctuated.SOLUTION: A comparator 231 compares divided voltage of power supply voltage Vcc with reference voltage Vref, and outputs a comparison result. A D flip-flop 232 captures output of the comparator 231 after supply of the power supply voltage Vcc is started, and holds the captured output of the comparator 231 until the power supply voltage Vcc is cut off. Bias voltage supplied from a bias circuit 2 of an amplifier circuit 1 is switched in accordance with the output of the D flip-flop 232 to switch an operating point of the amplifier circuit 1.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a bias control circuit. [Background technology]

[0002] A technology for switching the operating point of an amplifier circuit made of transistors depending on the power supply voltage is described in Patent Document 1. According to the transistor amplifier circuit (=amplifier circuit) of Patent Document 1, the operating point of the amplifier circuit is switched by the output of a comparator that compares the power supply voltage with a reference voltage. By using the above technology, the operating point of the transistor can be set appropriately even when transistor amplifier circuits are mounted on circuits supplied with different power supply voltages.

[0003] However, the power supply voltage may fluctuate between when the supply of the power supply voltage is started and when it is cut off. The transistor amplifier circuit of Patent Document 1 has a problem that when the power supply voltage fluctuates across the reference voltage, the operating point of the amplifier circuit switches, causing the output of the transistor amplifier circuit to fluctuate. To solve this problem, it has been considered to set an unusable power supply voltage range near the reference voltage. However, setting an unusable power supply voltage range limits the usable power supply voltage range. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-open No. 52-102657 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned circumstances, and an object of the present invention is to provide a bias control circuit in which the operating point of an amplifier circuit does not change even if the power supply voltage fluctuates. [Means for solving the problem]

[0006] In order to achieve the above-mentioned object, a bias control circuit according to the present invention has the following features [1] to [6]. [1] a comparator that compares a power supply voltage or a voltage corresponding to the power supply voltage with a reference voltage and outputs a comparison result; a latch circuit that receives an output of the comparator after the supply of the power supply voltage starts and holds the received output of the comparator until the power supply voltage is cut off; switching a bias voltage supplied from a bias circuit of an amplifier circuit in response to an output of the latch circuit, thereby switching an operating point of the amplifier circuit; It is a bias control circuit. [2] In the bias control circuit according to [1], a first switch for turning on and off a power supply to the comparator; After the latch circuit captures the output of the comparator, the first switch is turned off. It is a bias control circuit. [3] In the bias control circuit according to [1], a voltage dividing resistor that divides the power supply voltage and supplies the divided voltage to the comparator; a second switch that turns on and off the supply of the power supply voltage to the voltage dividing resistor; After the latch circuit captures the output of the comparator, the second switch is turned off. It is a bias control circuit. [4] In the bias control circuit according to [1], a current source that supplies a current to be passed through the bias circuit; a third switch connected in series to the current source for turning on and off the current supplied from the current source; The third switch is on / off controlled by the output of the latch circuit. It is a bias control circuit. [5] In the bias control circuit according to [1], The comparator is composed of a comparator. It is a bias control circuit. [6] In the bias control circuit according to [1], the comparator is configured as a comparator built in an analog-to-digital converter that converts the power supply voltage or a voltage corresponding to the power supply voltage into a digital value; The latch circuits are provided in the same number as the number of output bits of the analog / digital converter. It is a bias control circuit. Effect of the Invention

[0007] According to the present invention, it is possible to provide a bias control circuit in which the operating point of the amplifier circuit does not change even if the power supply voltage fluctuates.

[0008] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the following description of the embodiment of the present invention (hereinafter, referred to as "embodiment") with reference to the accompanying drawings. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram showing a transistor amplifier circuit incorporating a bias control circuit according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a circuit diagram showing an embodiment of the bias control circuit shown in FIG. 1 in the first embodiment. [Diagram 3] FIG. 3 is a time chart of the counter output shown in FIG. [Figure 4] FIG. 4 is a circuit diagram showing an embodiment of the bias control circuit shown in FIG. 1 in the second embodiment. [Diagram 5] FIG. 5 is a circuit diagram showing an amplifier circuit incorporating a bias control circuit according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0011] (First embodiment) Fig. 1 is a circuit diagram showing one embodiment of a transistor amplifier circuit incorporating a bias control circuit of the present invention. The transistor amplifier circuit 1 shown in Fig. 1 is a circuit that amplifies an input voltage VIN input to an input terminal TIN by a transistor Q1 and outputs the amplified voltage as an output voltage VOUT from an output terminal TOUT.

[0012] The transistor amplifier circuit 1 includes a transistor Q1, a resistor R1, and a bias circuit 2. In this embodiment, the transistor Q1 is an NPN bipolar transistor. The collector of the transistor Q1 is connected to a power supply terminal Tcc to which a power supply voltage Vcc is supplied via the resistor R1, and the emitter is grounded. The base of the transistor Q1 is connected to the input terminal TIN, and the collector is connected to the output terminal TOUT.

[0013] The base of the transistor Q1 is connected to a bias circuit 2, and a bias voltage is supplied from the bias circuit 2. The transistor amplifier circuit 1 amplifies an input voltage VIN to an output voltage VOUT centered on an operating point according to the bias voltage, and outputs the amplified output voltage VOUT.

[0014] The bias circuit 2 includes a constant voltage bias circuit 21, a resistor R2, a current source 22, and a bias control circuit 23 that switches the operating point by switching the current supplied by the current source 22. The constant voltage bias circuit 21 has a resistor R3 and a Zener diode ZD connected in series, and supplies a constant Zener voltage to the base of the transistor Q1 via the resistor R2.

[0015] The resistor R3 is connected between the power supply terminal Tcc and the cathode of a Zener diode ZD (described later). The Zener diode ZD has a cathode connected to the resistor R3 and an anode grounded. The connection point between the resistor R3 and the Zener diode ZD is connected to the base of the transistor Q1 via a resistor R2.

[0016] The current source 22 is connected between the base of the transistor Q1 and the ground. The current source 22 supplies a current that flows through the resistor R2. A value obtained by subtracting the voltage drop across the resistor R2 from the Zener voltage is supplied as a bias voltage for the transistor Q1. In this embodiment, the current source 22 can switch between two different types of current to flow through the resistor R2. By switching the current to flow through the resistor R2, the bias voltage of the transistor Q1 can be switched, and the operating point can be switched.

[0017] The bias control circuit 23 is a circuit that switches the output current Iout depending on whether the divided voltage obtained by dividing the power supply voltage Vcc is greater than the reference voltage Vref or equal to or less than the reference voltage Vref. The output current Iout thus switched is folded back and supplied to the resistor R2 by the current source 22, thereby switching the bias voltage of the transistor Q1 and switching the operating point.

[0018] Next, a detailed configuration of the bias control circuit 23 will be described with reference to Fig. 2. The bias control circuit 23 has resistors R41, R42, a comparator 231 as a comparator, a D flip-flop 232 as a latch circuit, a counter 233, a transistor Q2 as a third switch, current sources 234, 235, transistors Q31, Q32, and transistors Q41, Q42 as first and second switches.

[0019] The resistors R41 and R42 are connected in series between the power supply terminal Tcc and the ground terminal TGND, and divide the power supply voltage Vcc. A divided voltage (a voltage according to the power supply voltage Vcc) obtained by dividing the power supply voltage Vcc is output from the connection point of the resistors R41 and R42. A divided voltage obtained by dividing the power supply voltage Vcc and a reference voltage Vref are input to two input terminals of the comparator 231, respectively. The comparator 231 compares the divided voltage obtained by dividing the power supply voltage Vcc with the reference voltage Vref, and outputs the comparison result. In this embodiment, the comparator 231 outputs an L-level signal when the divided voltage obtained by dividing the power supply voltage Vcc is greater than the reference voltage Vref, and outputs an H-level signal when the divided voltage obtained by dividing the power supply voltage Vcc is equal to or less than the reference voltage Vref.

[0020] D flip-flop 232 takes in the output of comparator 231 only once after the supply of power supply voltage Vcc to transistor amplifier circuit 1 starts (after startup), and holds the taken-in output of comparator 231 until the power supply voltage Vcc is cut off. D flip-flop 232 has the output of comparator 231 connected to its D input, and the output of counter 233 connected to its CK input. Counter 233 receives a clock from an oscillator, and when the count value of the clock reaches a predetermined value, outputs a signal that is inverted from L level to H level from its Q output, and thereafter maintains the H level signal until the power supply voltage Vcc is cut off.

[0021] When the output of counter 233 is inverted from L level to H level, D flip-flop 232 captures the output of comparator 231 and outputs the output of comparator 231 from its Q output. D flip-flop 232 continues to output (hold) the captured output of comparator 231 even if the output of comparator 231 changes thereafter.

[0022] The transistor Q2 is composed of, for example, an N-channel field effect transistor. The gate of the transistor Q2 is connected to the Q output of the D flip-flop 232. The transistor Q2 is connected between a transistor Q31 (described later) and a current source 234. The current source 234 is connected between the source of the transistor Q2 and the ground terminal TGND, and supplies a current I1. The current source 235 is connected between the transistor Q31 and the ground terminal TGND, and supplies a current I2. The current sources 234 and 235 are connected in parallel.

[0023] The transistors Q31 and Q32 are, for example, P-channel field effect transistors. The source of the transistor Q31 is connected to the power supply terminal Tcc, and the drain is connected to the drain of the transistor Q2 and the current source 235. The drain and gate of the transistor Q31 are also connected. The transistor Q32 is current-mirror connected to the transistor Q31, and mirrors the current flowing through the transistor Q31. To explain in more detail, the gate of the transistor Q32 is connected to the drain and gate of the transistor Q31, and the source is connected to the power supply terminal Tcc.

[0024] According to the above configuration, when transistor Q2 is off, current I2 supplied from current source 235 flows through transistor Q31. Transistor Q32 reflects current I2 flowing through transistor Q31, and current I2 is output as output current Iout. On the other hand, when transistor Q2 is on, current (I1+I2) flows through transistor Q31, which is the sum of current I1 supplied from current source 234 and current I2 supplied from current source 235. Transistor Q32 reflects current (I1+I2) flowing through transistor Q31, and current (I1+I2) is output as output current Iout.

[0025] The transistors Q41 and Q42 are, for example, P-channel field effect transistors. The transistor Q41 is connected between the positive power supply terminal of the comparator 231 and the power supply terminal Tcc. More specifically, the source of the transistor Q41 is connected to the power supply terminal Tcc, and the drain is connected to the positive power supply terminal of the comparator 231. The transistor Q42 is connected between the resistor R41 and the power supply terminal Tcc. More specifically, the source of the transistor Q42 is connected to the power supply terminal Tcc, and the drain is connected to the resistor R41.

[0026] The gates of transistors Q41 and Q42 are connected to the output of counter 233. As a result, while the output of counter 233 is at L level, transistors Q41 and Q42 are turned on, and comparator 231 outputs the comparison result. When the output of counter 233 is inverted to H level, transistors Q41 and Q42 are turned off, and the current supplied to resistors R41 and R42 and comparator 231 is cut off.

[0027] Next, the operation of the above-mentioned transistor amplifier circuit 1 will be described with reference to the time chart of Fig. 3. First, the supply of the power supply voltage Vcc to the power supply terminal Tcc is started, and the transistor amplifier circuit 1 is started. After the start-up, the power supply voltage Vcc gradually increases, and the output of the counter 233 also gradually increases accordingly. When the power supply voltage Vcc remains stable above a certain value for a certain period of time due to the power-on reset function, the clock of the oscillator is deemed to be stable, and this stable clock is supplied to the counter 233. When the clock is supplied, the output of the counter 233 is inverted to L level, and the clock counting starts. When the clock count value reaches a predetermined value, the counter 233 inverts the output from L level to H level.

[0028] When the output of counter 233 switches from L level to H level, D flip-flop 232 takes in the output of comparator 231 and outputs it from the Q output. If the divided voltage obtained by dividing power supply voltage Vcc is greater than reference voltage Vref, comparator 231 outputs L level. Therefore, D flip-flop 232 outputs L level from its Q output and maintains this level until power supply voltage Vcc is cut off. When the L level is output from the Q output of D flip-flop 232, transistor Q2 turns off and current I2 is output as output current Iout.

[0029] On the other hand, when the divided voltage of the power supply voltage Vcc is equal to or lower than the reference voltage Vref, the comparator 231 outputs an H level. Therefore, the D flip-flop 232 outputs an H level from the Q output, and maintains this level until the power supply voltage Vcc is cut off. When the H level is output from the Q output of the D flip-flop 232, the transistor Q2 turns on, and a current (I1+I2) is output as the output current Iout. Since the output current Iout is folded back to the current source 22 as shown in FIG. 1, the current flowing through the resistor R2 can be switched between the current I2 and the current (I1+I2) depending on the power supply voltage Vcc, and the operating point of the transistor Q1 can be switched accordingly.

[0030] According to the above-described embodiment, even when the transistor amplifier circuit 1 is mounted on circuits supplied with different power supply voltages, the operating point of the transistor Q1 can be appropriately set. After startup, the D flip-flop 232 captures the output of the comparator 231 only once, and the output at that time is maintained by the D flip-flop 232 that captured the output. Therefore, the operating point of the transistor Q2 does not change even if the power supply voltage Vcc fluctuates, without setting an unusable power supply voltage range.

[0031] According to the embodiment described above, the output of counter 233 is connected to the gates of transistors Q41 and Q42. As a result, after D flip-flop 232 takes in the output of comparator 231, transistors Q41 and Q42 are turned off, cutting off the power supply to voltage-dividing resistors R41 and R42 and comparator 231, thereby reducing current consumption.

[0032] Second embodiment Next, a bias control circuit 23B according to a second embodiment will be described with reference to Fig. 4. In Fig. 4, the same parts as those in the bias control circuit 23 shown in Fig. 2 already described in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The bias control circuit 23B shown in Fig. 4 can be used in place of the bias control circuit 23 shown in Fig. 1.

[0033] The bias control circuit 23B has resistors R41 and R42, an ADC 231B as an analog / digital converter, a plurality of D flip-flops 232, a counter 233, a plurality of transistors Q2, a plurality of current sources 234, a current source 235, transistors Q31 and Q32, and transistors Q41 and Q42.

[0034] The resistors R41 and R42 are the same as those in the first embodiment, and therefore detailed description thereof will be omitted. The divided voltage of the power supply voltage Vcc output from the connection point of the resistors R41 and R42 is connected to the input of the ADC231B. In the second embodiment, the comparator is configured from a comparator built in the ADC231B. The ADC231B performs analog / digital conversion of the divided voltage of the power supply voltage Vcc to convert it into a digital value. The number of D flip-flops 232 is the same as the number of output bits of the ADC231B. For example, when the ADC231B converts into a 3-bit digital value, three D flip-flops 232 are provided.

[0035] Each bit of the output of the ADC 231B is connected to a corresponding D input of the D flip-flop 232 by a bus line BL1. The output of a counter 233 is connected to the CK input of the plurality of D flip-flops 232. The counter 233 is the same as in the first embodiment, and therefore a detailed description thereof will be omitted here.

[0036] The number of transistors Q2 provided is the same as the number of D flip-flops 232. For example, when three D flip-flops 232 are provided, three transistors Q2 are provided. The Q outputs of the multiple D flip-flops 232 are connected to the gates of the corresponding transistors Q2 by a bus line BL2. The multiple transistors Q2 are connected in parallel with each other.

[0037] The current sources 234 are provided in the same number as the transistors Q2 and are connected in series to each transistor Q2. The transistors Q31, Q32 and the transistors Q41, Q42 are the same as those in the first embodiment, and therefore detailed description thereof will be omitted.

[0038] According to the above configuration, by using the comparator built in the ADC231B as the comparator, it is possible to switch the operating point of the transistor Q1 between three or more stages with a simple configuration.

[0039] Third embodiment Next, a third embodiment will be described with reference to FIG. 5. FIG. 5 is a circuit diagram showing an amplifier circuit incorporating a bias control circuit according to the third embodiment of the present invention. An amplifier circuit 1C shown in the figure is a circuit that amplifies a signal from a MEMS (Micro Electro Mechanical Systems) microphone 3. The MEMS microphone 3 changes in capacitance according to sound pressure. The amplifier circuit 1C inputs a signal from the MEMS microphone 3 from an input terminal TINC, amplifies the signal, and outputs it from an output terminal TOUTC.

[0040] The amplifier circuit 1C includes a charge pump circuit 4, an amplifier circuit 5, a feedback capacitance Cf, a bias resistor Rb, and a bias circuit 2C. The charge pump circuit 4 is provided to apply a voltage to both ends of the MEMS microphone 3. Both ends of the MEMS microphone 3 are connected to an output terminal Tcp and an input terminal TINC, respectively, and a difference voltage between the voltage of the output terminal Tcp and the voltage of the input terminal TINC is input.

[0041] The amplifier circuit 5 has an inverting input connected to the input terminal TINC, a non-inverting input connected to the bias circuit 2C, and an output connected to the output terminal TOUTC. The feedback capacitance Cf is connected between the inverting input and the output of the amplifier circuit 5. The bias resistance Rb is connected between the inverting input and the output of the amplifier circuit 5. The feedback capacitance Cf and the bias resistance Rb are connected in parallel with each other.

[0042] The bias circuit 2C includes a bias control circuit 23 and a resistor R5 for voltage conversion. The bias control circuit 23 is the same as that in the first embodiment described above, and detailed description thereof will be omitted here. One end of the resistor R5 is connected to the non-inverting input of the amplifier circuit 5, and the other end is grounded. An output current Iout is supplied to the resistor R5 from the bias control circuit 23. The voltage Vp of the non-inverting input of the amplifier circuit 5 is expressed by the following equation (1). Vp = R5 × Iout … (1) R5: Resistance value of resistor R5

[0043] As described above, the inverting input of the amplifier circuit 5 is connected to the output via the bias resistor Rb. As a result, the amplifier circuit 5 outputs an output voltage VOUTC such that the voltage Vm of the inverting input is equal to the voltage Vp of the non-inverting input. Therefore, a voltage Vme shown in the following formula (2) is applied across the MEMS microphone 3. Vme=Vcp-Vm=Vcp-Vp=Vcp-R5×Iout …(2) Vcp: Output voltage of charge pump circuit 4

[0044] The change in capacitance (ΔC) of the MEMS microphone 3 is proportional to the change in charge (ΔQ) as shown in the following equations (3) and (4). Q+ΔQ=(C+ΔC)×Vme …(3) ΔQ = ΔC × Vme … ​​(4) Q: Amount of charge of MEMS microphone 3 in silence C: Capacitance of MEMS microphone 3 in silence

[0045] Now, if we assume that the bias resistor Rb has a high resistance and almost no current flows in response to the signal input from the input terminal TINC, the changing charge (ΔQ) becomes the charge that charges and discharges the feedback capacitance Cf. The output terminal TOUTC outputs the output signal VOUTC shown in the following equation (5). VOUTC=Vp+ΔQ / Cf =Vp+ΔC / Cf×Vme …(5) Cf: The capacitance value of the feedback capacitance Cf From equation (5), the amplifier circuit 1C can amplify with a capacitance ratio ΔC / Cf. In addition, the operating point of the amplifier circuit 1C can be controlled by the bias control circuit 23. Note that since the voltage Vp of the non-inverting input is switched by switching the operating point, it is preferable to appropriately adjust the output voltage Vcp of the charge pump circuit 4 as well.

[0046] Since the MEMS microphone 3 is used for various general-purpose applications, the operating power supply voltage is wide (for example, 1.5V to 3.6V). Therefore, if the operating point is fixed to, for example, 0.75V, a large amplitude audio signal can be amplified when a 1.5V power supply is connected, but if a 3.6V power supply is used, the large amplitude audio signal cannot be amplified. If the operating point is fixed to, for example, 1.8V, a large amplitude audio signal can be amplified with a 3.6V power supply, but operation with a 1.5V power supply is not possible. According to the above-mentioned embodiment, since the operating point can be set according to the power supply voltage, even if the application changes and the power supply voltage changes, the large amplitude audio signal can be amplified. Moreover, since the operating point is held according to the power supply voltage at the time of startup by the D flip-flop 232 as in the first embodiment, the operating point does not change even if the power supply voltage fluctuates after startup. Therefore, even if the device is used with a power supply voltage near the voltage at which the operating point switches, it is possible to prevent noise according to the change in the operating point from being mixed with the output signal VOUTC.

[0047] The present invention is not limited to the above-described embodiment, and can be appropriately modified, improved, etc. In addition, the material, shape, size, number, arrangement location, etc. of each component in the above-described embodiment are arbitrary as long as the present invention can be achieved, and are not limited.

[0048] According to the embodiment described above, the counter 233 is used to input the timing for capturing the outputs of the comparator 231 and the ADC 231B to the D flip-flop 232, but this is not limited to this. Instead of the counter 233, for example, a CR delay circuit, a timer, or other circuit that can input the timing for capturing the outputs of the comparator 231 and the ADC 231B to the D flip-flop 232 after waiting for the power supply voltage Vcc to stabilize after startup may be used.

[0049] According to the above-described embodiment, the operating point of the transistor Q2 is switched by switching the current flowing through the resistor R2 of the bias circuit 2, but this is not limiting. For example, the operating point of the transistor Q2 may be switched by switching the bias voltage through switching the resistor.

[0050] According to the second embodiment described above, the ADC 231B is used to switch the operating point of the transistor Q1 in three or more steps, but this is not limited to this. A plurality of comparators 231 may be provided to switch the operating point of the transistor Q1 in three or more steps.

[0051] According to the embodiment described above, after the D flip-flop 232 takes in the output of the comparator 231, the transistors Q41 and Q42 are turned off. However, if there is no need to reduce current consumption, the transistors Q41 and Q42 may be omitted. [Explanation of symbols]

[0052] 1,1C Amplification circuit 2,2C Bias circuit 23, 23B Bias control circuit 231 Comparator 231B ADC (Analog / Digital Converter) 232 D flip-flop (latch circuit) 234 Current Source Q1 Transistor Q2 Transistor (third switch) Q41 Transistor (first switch) Q42 Transistor (second switch) R41, R42 Voltage divider resistor Vcc power supply voltage Vref Reference voltage

Claims

1. a comparator that compares a power supply voltage or a voltage corresponding to the power supply voltage with a reference voltage and outputs a comparison result; a latch circuit that receives an output of the comparator after the supply of the power supply voltage starts and holds the received output of the comparator until the power supply voltage is cut off; switching a bias voltage supplied from a bias circuit of an amplifier circuit in response to an output of the latch circuit, thereby switching an operating point of the amplifier circuit; Bias control circuit.

2. 2. The bias control circuit according to claim 1, a first switch for turning on and off a power supply to the comparator; After the latch circuit captures the output of the comparator, the first switch is turned off. Bias control circuit.

3. 2. The bias control circuit according to claim 1, a voltage dividing resistor that divides the power supply voltage and supplies the divided voltage to the comparator; a second switch that turns on and off the supply of the power supply voltage to the voltage dividing resistor; After the latch circuit captures the output of the comparator, the second switch is turned off. Bias control circuit.

4. 2. The bias control circuit according to claim 1, a current source that supplies a current to be passed through the bias circuit; a third switch connected in series to the current source for turning on and off the current supplied from the current source; The third switch is on / off controlled by the output of the latch circuit. Bias control circuit.

5. 2. The bias control circuit according to claim 1, the comparator is configured as a comparator built in an analog-to-digital converter that converts the power supply voltage or a voltage corresponding to the power supply voltage into a digital value; The latch circuits are provided in the same number as the number of output bits of the analog-to-digital converter. Bias control circuit.

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