Electronic component built-in substrate and manufacturing method of electronic component built-in substrate

Abstract

To provide an electronic component built-in substrate capable of improving a heat dissipation.SOLUTION: An electronic component built-in substrate 1 includes: a first substrate 10; a second substrate 20 that is provided to an upper direction of the first substrate 10; and a spacer member 40 that electrically connects the first substrate 10 and the second substrate 20. The electronic component built-in substrate 1 includes: a semiconductor chip 30 that is arranged between the first substrate 10 and the second substrate 20, and is mounted on the first substrate 10; and a heat sink 50 that is arranged between the first substrate 10 and the second substrate 20. The electronic component built-in substrate 1 includes a sealing resin 60 that fills a space between the first substrate 10 and the second substrate 20, and seals the semiconductor chip 30. At least upper surface and a lower surface of the heat sink 50 are embedded to the sealing resin 60. The heat sink 50 is provided so as to be not overlapped in a pan view with the spacer member 40. The heat sink 50 includes an outer side surface 52S that is exposed from an outer side surface 60S of the sealing resin 60.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a substrate with built-in electronic components and a method for manufacturing the substrate with built-in electronic components.

Background Art

[0002] Conventionally, a substrate with built-in electronic components in which electronic components are built between a lower substrate and an upper substrate has been proposed (see, for example, Patent Documents 1 and 2). In this type of substrate with built-in electronic components, the upper substrate is fixed to the lower substrate via a spacer member in order to maintain the interval between the lower substrate and the upper substrate. Then, a sealing resin is filled between the lower substrate and the upper substrate.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above-described substrate with built-in electronic components, improvement in heat dissipation is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, there are provided a first substrate, a second substrate provided above the first substrate, a spacer member for electrically connecting the first substrate and the second substrate, an electronic component mounted on the first substrate, a heat sink disposed between the first substrate and the second substrate, and a sealing resin for filling a space between the first substrate and the second substrate and sealing the electronic component. At least the upper surface and the lower surface of the heat sink are embedded in the sealing resin. The heat sink is provided so as not to overlap with the spacer member in plan view, and the heat sink has a second outer surface exposed from a first outer surface of the sealing resin.

Advantages of the Invention

[0006] According to one aspect of the present invention, there is an effect that heat dissipation performance can be improved.

Brief Description of the Drawings

[0007]

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DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment will be described with reference to the accompanying drawings. Note that, for convenience, the accompanying drawings may show enlarged portions that are characteristic in order to make the features easier to understand, and the dimensional ratios of the respective components may differ in each drawing. Also, in cross-sectional views, in order to make the cross-sectional structures of the respective members easier to understand, the hatching of some members is shown replaced with a satin pattern, and the hatching of some members is omitted. In this specification, "plan view" means looking at an object from the vertical direction (the up-and-down direction in the drawing such as FIG. 1), and "planar shape" means the shape of an object when viewed from the vertical direction such as FIG. 1. The "up-and-down direction" and "left-and-right direction" in this specification are the directions when the reference signs indicating the respective members in each drawing are in the correct reading orientation. "Opposite" in this specification means that surfaces or members are in a front-to-front position relative to each other, including not only the case where they are completely in a front-to-front position but also the case where they are partially in a front-to-front position. Also, "opposite" in this specification includes both the case where a member different from the two parts is interposed between the two parts and the case where nothing is interposed between the two parts.

[0009] (Overall configuration of the substrate 1 with built-in electronic components) As shown in FIG. 1, the substrate 1 with built-in electronic components has a first substrate 10, a second substrate 20, a semiconductor chip 30, an underfill resin 35, a spacer member 40, a heat sink 50, a sealing resin 60, and external connection terminals 70.

[0010] (Configuration of the first substrate 10) The first substrate 10 has a substrate body 11, a wiring layer 12, and a wiring layer 13. As the substrate body 11, a wiring structure in which an insulating resin layer and a wiring layer are alternately laminated can be used. The wiring structure may have, for example, a core substrate or may not have a core substrate. As the material of the insulating resin layer, for example, a thermosetting insulating resin can be used. As the thermosetting insulating resin, for example, insulating resins such as epoxy resin, polyimide resin, and cyanate resin can be used. Also, as the material of the insulating resin layer, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The insulating resin layer may contain, for example, fillers such as silica and alumina. Note that, as the material of the wiring layer of the substrate body 11 and the wiring layers 12 and 13, for example, copper (Cu) or a copper alloy can be used.

[0011] As shown in FIG. 2, the planar shape of the substrate body 11 is formed, for example, in a rectangular shape. The planar size of the substrate body 11 is larger than the planar size of the semiconductor chip 30. The planar size of the substrate body 11 can be, for example, about 15 mm × 15 mm to 25 mm × 25 mm.

[0012] As shown in FIG. 1, the wiring layer 12 is formed on the lower surface of the substrate body 11. The wiring layer 12 is the lowermost wiring layer of the first substrate 10. The wiring layer 12 has a plurality of external connection pads P1 to which external connection terminals 70 used when mounting the electronic component built-in substrate 1 on a mounting substrate such as a mother board are connected. Although not shown in a plan view, the plurality of external connection pads P1 are arranged, for example, in a matrix in a plan view. The planar shape of each external connection pad P1 is formed, for example, in a circular shape.

[0013] On the surface (the lower surface and side surfaces, or only the lower surface) of the external connection pad P1, a surface treatment layer is formed as necessary. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order), and the like. Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating a Ni layer and a Pd layer in this order), a Pd / Au layer (a metal layer formed by laminating a Pd layer and an Au layer in this order), and the like. Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or a Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. As these Au layer, Ni layer, and Pd layer, for example, a metal layer (electroless plating layer) formed by an electroless plating method or a metal layer (electrolytic plating layer) formed by an electrolytic plating method can be used. Further, as the surface treatment layer, an OSP (Organic Solderability Preservative) film formed by performing an antioxidant treatment such as OSP treatment on the surface of the external connection pad P1 can also be used. As the OSP film, for example, an organic film such as an azole compound or an imidazole compound can be used. When a surface treatment layer is formed on the surface of the external connection pad P1, the surface treatment layer functions as the external connection pad P1.

[0014] In this example, the external connection terminal 70 is provided on the external connection pad P1. However, the external connection pad P1 itself (or, when a surface treatment layer is formed on the external connection pad P1, the surface treatment layer) may be used as the external connection terminal.

[0015] The wiring layer 13 is provided on the mounting surface side (the upper surface side in FIG. 1) where the semiconductor chip 30 is mounted. The wiring layer 13 is formed on the upper surface of the substrate body 11. The wiring layer 13 is electrically connected to the wiring layer 12 via the wiring layer and the through electrode in the substrate body 11.

[0016] The wiring layer 13 has a plurality of pads P2 for mounting electronic components that are electrically connected to the bumps 31 of the semiconductor chip 30, and a plurality of connection pads P3 for electrically connecting between the first substrate 10 and the second substrate 20.

[0017] As shown in FIG. 2, the plurality of pads P2 are arranged in a matrix in a plan view in a mounting region where the semiconductor chip 30 is mounted, for example, according to the arrangement form of the bumps 31 (see FIG. 1) of the semiconductor chip 30. The planar shape of each pad P2 is formed in a circular shape, for example.

[0018] The plurality of connection pads P3 are provided in a region outside the mounting region in a plan view. The plurality of connection pads P3 are provided so as to surround the outer peripheral edge of the semiconductor chip 30 in a plan view. The plurality of connection pads P3 are arranged along the outer peripheral edge of the substrate body 11, for example. The plurality of connection pads P3 are provided side by side along each of the four sides constituting the outer peripheral edge of the substrate body 11. The planar shape of each connection pad P3 is formed in a circular shape, for example.

[0019] A surface treatment layer is formed on the surface (upper surface and side surface, or only the upper surface) of the pad P2 and the surface (upper surface and side surface, or only the upper surface) of the connection pad P3 as required. As an example of the surface treatment layer, a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, a Pd / Au layer, or an OSP film can be used. When a surface treatment layer is formed on the surface of the pad P2 and the surface of the connection pad P3, the surface treatment layer functions as the pad P2 or the connection pad P3.

[0020] (Configuration of the semiconductor chip 30) As shown in FIG. 1, the semiconductor chip 30 has a plurality of bumps 31 formed on the circuit formation surface (here, the lower surface) of the semiconductor chip 30. The semiconductor chip 30 is mounted on the upper surface of the first substrate 10. The semiconductor chip 30 is flip-chip mounted on the upper surface of the first substrate 10. The semiconductor chip 30 is electrically connected to the pad P2 of the first substrate 10 via the bump 31. Thereby, the semiconductor chip 30 is electrically connected to the wiring layer 13 of the first substrate 10 via the bump 31.

[0021] As the semiconductor chip 30, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used. Also, as the semiconductor chip 30, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or a flash memory chip can be used. When a plurality of semiconductor chips 30 are mounted on the first substrate 10, a logic chip and a memory chip may be combined and mounted on the first substrate 10.

[0022] The planar shape of the semiconductor chip 30 is, for example, rectangular. The planar size of the semiconductor chip 30 can be, for example, about 3 mm × 3 mm to 12 mm × 12 mm. The thickness of the semiconductor chip 30 can be, for example, about 50 μm to 100 μm.

[0023] As the bump 31, for example, a gold bump or a solder bump can be used. As the material of the solder bump, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and silver (Ag), an alloy of Sn, Ag, and Cu, etc. can be used. The thickness of the bump 31 can be, for example, about 20 μm to 70 μm.

[0024] The underfill resin 35 is provided to fill the gap between the upper surface of the first substrate 10 and the lower surface of the semiconductor chip 30. As the material of the underfill resin 35, for example, an insulating resin such as an epoxy resin can be used.

[0025] (Configuration of the second substrate 20) The second substrate 20 has a substrate body 21, a wiring layer 22, and a wiring layer 23. The second substrate 20 is provided above the first substrate 10 at a distance from the first substrate 10.

[0026] As the substrate body 21, a wiring structure in which an insulating resin layer and a wiring layer are alternately laminated can be used. The wiring structure may have, for example, a core substrate or may not have a core substrate. As the material of the insulating resin layer, for example, a thermosetting insulating resin can be used. As the thermosetting insulating resin, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin can be used. Also, as the material of the insulating resin layer, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The insulating resin layer may contain, for example, fillers such as silica or alumina. As the material of the wiring layer of the substrate body 21 and the wiring layers 22 and 23, for example, copper or a copper alloy can be used.

[0027] The planar shape of the substrate body 21 is formed in the same shape as the planar shape of the substrate body 11. The planar shape of the substrate body 21 is formed, for example, in a rectangular shape. The planar size of the substrate body 21 is equal to the planar size of the substrate body 11. The planar size of the substrate body 21 can be, for example, about 15 mm × 15 mm to 25 mm × 25 mm.

[0028] The wiring layer 22 is formed on the lower surface of the substrate body 21 facing the first substrate 10. The wiring layer 22 is the lowermost wiring layer of the second substrate 20. The wiring layer 22 has a plurality of connection pads P4 for electrically connecting between the first substrate 10 and the second substrate 20. Each connection pad P4 is electrically connected to each connection pad P3 provided on the first substrate 10 via a spacer member 40.

[0029] The plurality of connection pads P4 are provided so as to face each of the plurality of connection pads P3 provided on the first substrate 10. The plurality of connection pads P4 are provided so as to surround the outer peripheral edge of the semiconductor chip 30 in a plan view. The planar shape of each connection pad P4 is formed, for example, in a circular shape.

[0030] A surface treatment layer is formed on the surface (lower surface and side surface, or only the lower surface) of the connection pad P4 as necessary. As an example of the surface treatment layer, a metal layer such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, a Pd / Au layer, or an OSP film can be used. When a surface treatment layer is formed on the surface of the connection pad P4, the surface treatment layer functions as the connection pad P4.

[0031] The wiring layer 23 is formed on the upper surface of the substrate body 21 on which an electronic component different from the semiconductor chip 30 is mounted. The wiring layer 23 is electrically connected to the wiring layer 22 via the wiring layer and the through electrode in the substrate body 21.

[0032] The wiring layer 23 has component connection pads P5 that are electrically connected to electronic components such as a semiconductor chip different from the semiconductor chip 30 and passive elements. The planar shape of each component connection pad P5 is formed, for example, in a circular shape.

[0033] On the surface (upper surface and side surfaces, or only the upper surface) of the component connection pad P5, a surface treatment layer is formed as required. As examples of the surface treatment layer, metal layers such as an Au layer, a Ni layer / Au layer, a Ni layer / Pd layer / Au layer, a Ni layer / Pd layer, a Pd / Au layer, or an OSP film can be used. When a surface treatment layer is formed on the surface of the component connection pad P5, the surface treatment layer functions as the component connection pad P5.

[0034] (Configuration of the spacer member 40) The spacer member 40 electrically connects the connection pad P3 of the first substrate 10 and the connection pad P4 of the second substrate 20 to each other. The spacer member 40 is joined to the connection pad P3 and is also joined to the connection pad P4. Specifically, the spacer member 40 is provided intervening between the first substrate 10 and the second substrate 20, with one end joined to the connection pad P3 and the other end joined to the connection pad P4. The spacer member 40 functions as a connection terminal for electrically connecting the connection pad P3 and the connection pad P4, and also functions as a spacer for maintaining the distance between the first substrate 10 and the second substrate 20, that is, the separation distance, at a specified value.

[0035] The spacer member 40 has a spherical copper core ball 41 and a solder layer 42 covering the periphery of the copper core ball 41. In the spacer member 40, the solder layer 42 functions as a joining material. More specifically, the spacer member 40 is joined to the connection pad P3 by the solder layer 42 and is also joined to the connection pad P4 by the solder layer 42. Also, in the spacer member 40, the copper core ball 41 functions as a spacer. For this reason, the height (diameter) of the copper core ball 41 sets the height of the space between the first substrate 10 and the second substrate 20. Such a height of the copper core ball 41 is set, for example, to be higher than the thickness of the semiconductor chip 30. Specifically, the height of the copper core ball 41 is set to be higher than the total thickness of the semiconductor chip 30 and the bump 31. The height of the copper core ball 41 can be, for example, about 100 μm to 200 μm.

[0036] (Configuration of the heat sink 50) The heat dissipation plate 50 is provided between the semiconductor chip 30 and the second substrate 20. The heat dissipation plate 50 is provided between the back surface (here, the upper surface) on the side opposite to the circuit formation surface of the semiconductor chip 30 and the lower surface of the substrate body 21 of the second substrate 20. The heat dissipation plate 50 is provided separately from the semiconductor chip 30 and separately from the second substrate 20 in the thickness direction (vertical direction in the figure) of the electronic component built-in substrate 1. The heat dissipation plate 50 is provided above the semiconductor chip 30. The heat dissipation plate 50 is provided on the upper surface of the semiconductor chip 30 via the encapsulating resin 60. That is, a gap is provided between the upper surface of the semiconductor chip 30 and the lower surface of the heat dissipation plate 50, and the gap is filled with the encapsulating resin 60. The heat dissipation plate 50 is supported above the semiconductor chip 30 by the encapsulating resin 60. The heat dissipation plate 50 is provided on the lower surface of the second substrate 20 via the encapsulating resin 60. That is, a gap is provided between the upper surface of the heat dissipation plate 50 and the lower surface of the substrate body 21, and the gap is filled with the encapsulating resin 60. The entire lower surface of the heat dissipation plate 50 is covered by the encapsulating resin 60, and the entire upper surface of the heat dissipation plate 50 is covered by the encapsulating resin 60. That is, at least the upper surface and the lower surface of the heat dissipation plate 50 are embedded in the encapsulating resin 60.

[0037] The heat dissipation plate 50 is also called a heat spreader. The heat dissipation plate 50 has, for example, a function of dispersing the density of heat generated by the semiconductor chip 30. The heat dissipation plate 50 has a higher thermal conductivity than the encapsulating resin 60. As the material of the heat dissipation plate 50, a material with good thermal conductivity can be used. For example, as the heat dissipation plate 50, a substrate made of copper, silver (Ag), aluminum (Al), or an alloy thereof can be used. As the heat dissipation plate 50, for example, a substrate made of ceramics such as alumina and aluminum nitride, or an insulating material or semiconductor material with high thermal conductivity such as silicon can also be used. Note that the thickness of the heat dissipation plate 50 can be about 100 μm to 200 μm.

[0038] As shown in FIG. 3, the heat sink 50 has a main body portion 51 and one or more (here, eight) lead portions 52. The heat sink 50 is formed such that the main body portion 51 and the plurality of lead portions 52 are continuously integrated. The heat sink 50 is provided so as not to overlap with the spacer member 40 in a plan view.

[0039] The main body portion 51 is formed, for example, in a flat plate shape. The main body portion 51 is provided so as to overlap with the semiconductor chip 30 in a plan view. The main body portion 51 is provided so as to overlap with the entire semiconductor chip 30 in a plan view, for example. The main body portion 51 is provided, for example, in the mounting region of the semiconductor chip 30. The main body portion 51 is provided, for example, in a region inside the spacer member 40. The planar shape of the main body portion 51 is formed, for example, in a shape similar to the planar shape of the semiconductor chip 30, here, a rectangular shape. The planar size of the main body portion 51 is formed to be slightly larger than the planar size of the semiconductor chip 30. The planar size of the main body portion 51 is formed to be slightly smaller than the planar size of the substrate body 11.

[0040] As shown in FIG. 1, the lower surface of the main body portion 51 is thermally coupled to the upper surface of the semiconductor chip 30 via the encapsulating resin 60. The entire lower surface of the main body portion 51 is covered by the encapsulating resin 60. The entire upper surface of the main body portion 51 is covered by the encapsulating resin 60. As shown in FIG. 3, the entire side surface of the main body portion 51 is covered by the encapsulating resin 60. The side surface of the main body portion 51 is covered by the encapsulating resin 60 over the entire circumferential direction of the main body portion 51.

[0041] Each lead portion 52 is formed, for example, so as to protrude outward from the side surface of the main body portion 51. Each lead portion 52 is formed, for example, so as to protrude from the side surface of the main body portion 51 toward the outer peripheral edge side of the electronic component-embedded substrate 1. Each lead portion 52 extends to the outer side surface of the electronic component-embedded substrate 1. Each lead portion 52 extends, for example, to the outer side surface 60S of the encapsulating resin 60. Each lead portion 52 is provided so as not to overlap with the spacer member 40 in a plan view. Each lead portion 52 extends to the outer side surface of the electronic component-embedded substrate 1 through a gap where the spacer member 40 is not provided in a plan view. In other words, the plurality of spacer members 40 are arranged so that a gap where each lead portion 52 can be disposed is provided.

[0042] The plurality of lead portions 52 are provided, for example, at intervals along the circumferential direction of the main body portion 51. The plurality of lead portions 52 are provided, for example, in the outer peripheral region of the electronic component-embedded substrate 1. The plurality of lead portions 52 are provided at a predetermined interval along the outer peripheral edge of the electronic component-embedded substrate 1. The plurality of lead portions 52 are provided on at least one of the four sides constituting the outer peripheral edge of the rectangular main body portion 51. The plurality of lead portions 52 of the present embodiment are provided on each of the four sides constituting the outer peripheral edge of the main body portion 51.

[0043] The plurality of lead portions 52 include, for example, one or more (here, four) lead portions 52A that extend linearly in a plan view and one or more (here, four) lead portions 52B that extend in an L shape in a plan view.

[0044] The four lead portions 52A of the present embodiment are provided one by one on each of the four sides constituting the outer peripheral edge of the main body portion 51. Each lead portion 52A extends linearly from the side surface of the main body portion 51 to the outer side surface of the electronic component-embedded substrate 1. Each lead portion 52A is formed, for example, in a strip shape.

[0045] The four lead portions 52B of this embodiment are provided in two each on each of the two sides located in the left - right direction in the figure among the four sides constituting the outer peripheral edge of the main body portion 51. The two lead portions 52B provided on the side of the main body portion 51 located on the left side in the figure are provided so as to sandwich one lead portion 52A provided on the same side from both sides in the up - down direction in the figure. The two lead portions 52B provided on the side of the main body portion 51 located on the right side in the figure are provided so as to sandwich one lead portion 52A provided on the same side from both sides in the up - down direction in the figure. Each lead portion 52B extends in an L - shape from the side surface of the main body portion 51 to the outer side surface of the electronic component - embedded substrate 1. Each lead portion 52B extends from the sides located in the left - right direction among the four sides constituting the outer peripheral edge of the main body portion 51 to the sides located in the up - down direction among the four sides constituting the outer peripheral edge of the electronic component - embedded substrate 1.

[0046] As shown in FIG. 1, the entire lower surface of each lead portion 52 is covered by the sealing resin 60. The entire upper surface of each lead portion 52 is covered by the sealing resin 60. Each lead portion 52 has an outer surface 52S exposed from the outer surface 60S of the sealing resin 60. The outer surface 52S of each lead portion 52 is provided at the outer peripheral edge of the electronic component - embedded substrate 1 of each lead portion 52. The outer surface 52S of each lead portion 52 is formed flush with, for example, the outer surface 60S of the sealing resin 60. As shown in FIG. 3, the outer surface 52S exposed from the outer surface 60S of the sealing resin 60 is provided partially at intervals in the circumferential direction of the electronic component - embedded substrate 1. Also, the side surfaces of each lead portion 52 except the outer surface 52S are covered by the sealing resin 60.

[0047] (Configuration of the Sealing Resin 60) As shown in FIG. 1, the encapsulation resin 60 is formed to fill the space between the first substrate 10 and the second substrate 20. The encapsulation resin 60 is formed to encapsulate the semiconductor chip 30 disposed between the first substrate 10 and the second substrate 20. The encapsulation resin 60 is formed to cover the heat sink 50 disposed between the semiconductor chip 30 and the second substrate 20. The encapsulation resin 60 functions as an adhesive member that bonds the first substrate 10, the second substrate 20, and the heat sink 50, and also functions as a protection member that protects the semiconductor chip 30. Further, the encapsulation resin 60 functions as a support member that supports the heat sink 50 on the first substrate 10.

[0048] The encapsulation resin 60 is formed, for example, to entirely cover the semiconductor chip 30 including the bumps 31. The encapsulation resin 60 is formed to cover the entire surface of the semiconductor chip 30. The encapsulation resin 60 is formed to cover the entire surface of the underfill resin 35. The encapsulation resin 60 is formed to cover the entire surface of the spacer member 40. The encapsulation resin 60 is formed to embed the heat sink 50. The encapsulation resin 60 is formed to cover the entire surface of the heat sink 50 except for the outer surface 52S.

[0049] The encapsulation resin 60 is formed to fill the space between the semiconductor chip 30 and the heat sink 50. Here, the shortest distance between the upper surface of the semiconductor chip 30 and the lower surface of the heat sink 50 can be, for example, about 50 μm to 100 μm. Only the encapsulation resin 60, for example, is provided in the space between the upper surface of the semiconductor chip 30 and the lower surface of the heat sink 50. In other words, the heat sink 50 is provided above the semiconductor chip 30 only via the encapsulation resin 60. The heat sink 50 is thermally coupled to the semiconductor chip 30 only via the encapsulation resin 60. The encapsulation resin 60 that fills the space between the semiconductor chip 30 and the heat sink 50 is formed to cover the lower surface of the main body portion 51 of the heat sink 50.

[0050] The sealing resin 60 is formed so as to fill the space between the first substrate 10 and the heat sink 50. In the space between the upper surface of the substrate body 11 of the first substrate 10 and the lower surface of the heat sink 50, for example, only the sealing resin 60 is provided. That is, in the area where the heat sink 50 is disposed in the outer peripheral area outside the mounting area of the semiconductor chip 30, only the sealing resin 60 is provided in the space between the upper surface of the substrate body 11 and the lower surface of the heat sink 50. In other words, the heat sink 50 is provided above the first substrate 10 only via the sealing resin 60. The heat sink 50 is supported above the first substrate 10 only by the sealing resin 60. The sealing resin 60 that fills the space between the substrate body 11 and the heat sink 50 is formed so as to cover the entire upper surface of the substrate body 11 exposed from the underfill resin 35 and the connection pads P3, and to cover the entire lower surface of the lead portion 52 of the heat sink 50.

[0051] The sealing resin 60 is formed so as to fill the space between the heat sink 50 and the second substrate 20. In the space between the upper surface of the heat sink 50 and the lower surface of the substrate body 21 of the second substrate 20, for example, only the sealing resin 60 is provided. That is, in the area where the heat sink 50 is disposed, only the sealing resin 60 is provided in the space between the upper surface of the heat sink 50 and the lower surface of the substrate body 21. In other words, the heat sink 50 is provided below the second substrate 20 only via the sealing resin 60. The sealing resin 60 that fills the space between the heat sink 50 and the second substrate 20 is formed so as to cover the entire upper surface of the heat sink 50 and to cover the entire lower surface of the substrate body 21 exposed from the connection pads P4.

[0052] As shown in FIG. 3, the sealing resin 60 formed in the outer peripheral area outside the mounting area is formed so as to embed the lead portion 52 of the heat sink 50. The sealing resin 60 is formed so as to cover the entire lower surface of the lead portion 52, the entire upper surface of the lead portion 52, and the entire side surface of the lead portion 52 excluding the outer side surface 52S. The sealing resin 60 is formed so as to cover the entire side surface of the main body portion 51.

[0053] As shown in FIG. 1, the outer surface 60S of the encapsulation resin 60 is formed so as to expose the outer surface 52S of the lead portion 52. The outer surface 60S of the encapsulation resin 60 is formed flush with, for example, the outer surface 52S of the lead portion 52 and the outer surfaces of the substrate bodies 11 and 21.

[0054] As the material of the encapsulation resin 60, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin can be used. As the material of the encapsulation resin 60, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which fillers such as silica and alumina are mixed into these resins can be used. As the encapsulation resin 60, for example, a mold resin can be used.

[0055] (Configuration of the external connection terminal 70) The external connection terminal 70 is formed on the external connection pad P1 of the first substrate 10. The external connection terminal 70 is, for example, a connection terminal that is electrically connected to a pad provided on a mounting substrate such as a motherboard (not shown). As the external connection terminal 70, for example, solder balls or lead pins can be used. The external connection terminal 70 in this example is a solder ball.

[0056] (Manufacturing method of the electronic component built-in substrate 1) Next, the manufacturing method of the electronic component built-in substrate 1 will be described. For convenience of explanation, the parts that will finally become the respective components of the electronic component built-in substrate 1 will be described with the reference numerals of the final components.

[0057] First, in the process shown in FIG. 4, a large-sized first substrate 80 is prepared. The first substrate 80 has a plurality of first product regions 81 and a first non-product region 82. In the first substrate 80, the plurality of first product regions 81 are arranged in a matrix. In each first product region 81, a structure corresponding to the first substrate 10 shown in FIG. 1 is formed. The first non-product region 82 is formed, for example, so as to surround each of the plurality of first product regions 81 in a plan view. The first non-product region 82 has, for example, a first outer peripheral region 83 that collectively surrounds the plurality of first product regions 81 and a first connection region 84 provided between the plurality of first product regions 81.

[0058] Here, after a structure corresponding to the electronic component-embedded substrate 1 shown in FIG. 1 is formed in each first product region 81, it is finally cut along the cutting line indicated by the dashed line and fragmented into individual pieces, each becoming an individual electronic component-embedded substrate 1. That is, the portion outside each first product region 81, that is, the first non-product region 82, is the portion that will ultimately be discarded. In other words, the first non-product region 82 is the portion that does not remain in the finally fragmented electronic component-embedded substrate 1. Note that the number of first product regions 81 in the first substrate 80 is not particularly limited. Hereinafter, for simplicity of explanation, the description will be made focusing on one first product region 81 and the first non-product region 82 provided around the one first product region 81.

[0059] As shown in FIG. 5, in each first product region 81 of the first substrate 80, a substrate body 11, a wiring layer 12 laminated on the lower surface of the substrate body 11, and a wiring layer 13 laminated on the upper surface of the substrate body 11 are formed. At this time, a conductive layer 15 laminated on the upper surface of the substrate body 11 is formed in the first non-product region 82 of the first substrate 80. As shown in FIG. 4, the pads P2 of the wiring layer 13 are arranged in a matrix in a plan view in the central region of each first product region 81. The connection pads P3 of the wiring layer 13 are arranged peripherally in a plan view in the outer peripheral region of each first product region 81. That is, the connection pads P3 are provided along the outer peripheral edge of each first product region 81. The conductive layer 15 is arranged peripherally in a plan view in the first outer peripheral region 83 of the first non-product region 82. That is, the plurality of conductive layers 15 provided in the first outer peripheral region 83 are provided along the outer peripheral edge of the first substrate 80. A plurality of conductive layers 15 are provided in the first connection region 84 of the first non-product region 82. The plurality of conductive layers 15 provided in the first connection region 84 are arranged side by side along the vertical direction in the drawing, for example, between two first product regions 81 adjacent in the left-right direction in the drawing. The plurality of conductive layers 15 provided in the first connection region 84 are arranged side by side along the horizontal direction in the drawing, for example, between two first product regions 81 adjacent in the vertical direction in the drawing.

[0060] Next, in the steps shown in FIGS. 6 and 7, a semiconductor chip 30 is prepared. As shown in FIG. 7, the semiconductor chip 30 has bumps 31 formed on a circuit formation surface (here, the lower surface). Subsequently, the semiconductor chip 30 is mounted on the upper surface of the pad P2 of each first product region 81. For example, the bumps 31 of the semiconductor chip 30 are flip-chip bonded onto the pads P2 of each first product region 81. Specifically, when the bumps 31 are solder bumps, a flux (not shown) is appropriately applied onto the pads P2, and after aligning the pads P2 and the bumps 31, a reflow process is performed at a temperature of about 230°C to 260°C. Thereby, the solder bumps 31 are melted, and the bumps 31 are electrically connected to the pads P2.

[0061] Also, in the process shown in FIG. 7, a solder layer 85 is formed on the upper surface of the conductive layer 15. The solder layer 85 can be formed, for example, by applying a solder paste on the conductive layer 15 by screen printing or the like. Next, a columnar metal post 86 is mounted (joined) on the conductive layer 15. For example, after mounting the metal post 86 on the solder layer 85, a reflow process is performed at a predetermined temperature. Thereby, the solder layer 85 is melted and the metal post 86 is fixed on the conductive layer 15. As the material of the metal post 86, for example, copper or a copper alloy can be used.

[0062] Note that the process of mounting the semiconductor chip 30 on the pad P2 and the process of mounting the metal post 86 on the conductive layer 15 may be performed simultaneously. Next, in the process shown in FIG. 8, an underfill resin 35 is filled and cured between the upper surface of the first substrate 10, specifically, between the upper surface of the substrate body 11 and the lower surface of the semiconductor chip 30.

[0063] Subsequently, in the process shown in FIG. 9, a large heat sink 90 is prepared. The heat sink 90 is, for example, a metal plate. The heat sink 90 of the present embodiment is a copper plate. The heat sink 90 has a plurality of second product regions 91 and a second non-product region 92. In the heat sink 90, the plurality of second product regions 91 are arranged in a matrix. In each second product region 91, a structure corresponding to the heat sink 50 shown in FIG. 1 is formed. The second non-product region 92 is formed, for example, so as to surround each of the plurality of second product regions 91 in a plan view. The second non-product region 92 has, for example, a second outer peripheral region 93 that collectively surrounds the plurality of second product regions 91 and a second connection region 94 provided between the plurality of second product regions 91.

[0064] Here, after a structure corresponding to the electronic component - incorporated substrate 1 shown in FIG. 1 is formed in each second product region 91, it is finally cut along the cutting line indicated by the dashed - dotted line and fragmented, and each becomes an individual electronic component - incorporated substrate 1. That is, the portion outside each second product region 91, namely the second non - product region 92, is the portion that is finally discarded. In other words, the second non - product region 92 is the portion that does not remain in the finally fragmented electronic component - incorporated substrate 1. Note that the number of second product regions 91 in the heat sink 90 is not particularly limited. Hereinafter, for the sake of simplicity of explanation, the description will be made focusing on one second product region 91 and the second non - product region 92 provided around the one second product region 91.

[0065] In each second product region 91 of the heat sink 90, a main body portion 51 and a plurality of lead portions 52 are formed. In other words, in each second product region 91, an opening 91X that defines the main body portion 51 and the lead portions 52 is formed. The opening 91X can be formed, for example, by etching or pressing.

[0066] The second connection region 94 of the second non - product region 92 connects the lead portions 52 formed in two adjacent second product regions 91. In other words, the lead portions 52 formed in each second product region 91 are connected to the lead portions 52 formed in the second product region 91 adjacent in the left - right direction in the figure via the second connection region 94. Also, the lead portions 52 formed in each second product region 91 are connected to the lead portions 52 formed in the second product region 91 adjacent in the up - down direction in the figure via the second connection region 94.

[0067] Subsequently, as shown in FIG. 10, a solder layer 95 is formed on the lower surface of the heat sink 90 in the second non-product area 92. In this example, the solder layer 95 is partially formed on a part of the lower surface of the heat sink 90 in the second non-product area 92. As shown in FIG. 9, the solder layer 95 is peripherally arranged in a plan view in the second outer peripheral area 93 of the second non-product area 92. That is, the solder layer 95 provided in the second outer peripheral area 93 is provided along the outer peripheral edge of the heat sink 90. A plurality of solder layers 95 are provided in the second connection area 94 of the second non-product area 92. The solder layers 95 provided in the second connection area 94 are arranged side by side along the vertical direction in the figure, for example, between two adjacent second product areas 91 in the left-right direction in the figure. The solder layers 95 provided in the second connection area 94 are arranged side by side along the horizontal direction in the figure, for example, between two adjacent second product areas 91 in the vertical direction in the figure. The plurality of solder layers 95 are provided at positions corresponding to the plurality of conductive layers 15 shown in FIG. 4 respectively. The solder layer 95 can be formed, for example, by applying a solder paste to the lower surface of the heat sink 90 by screen printing or the like.

[0068] Next, in the process shown in FIG. 11, the heat sink 90 is arranged above the first substrate 80. At this time, the first substrate 80 and the heat sink 90 are arranged so that the plurality of first product areas 81 and the plurality of second product areas 91 face each other respectively. That is, the first substrate 80 and the heat sink 90 are arranged so that the first product area 81 and the second product area 91 are vertically aligned. Further, the first substrate 80 and the heat sink 90 are arranged so that the conductive layer 15 and the metal post 86 of the first substrate 80 and the solder layer 95 of the heat sink 90 face each other.

[0069] Subsequently, the conductive layer 15 and the solder layer 95 are connected via the metal posts 86 and the solder layer 85, and the heat sink 90 is fixed onto the first substrate 80. For example, after appropriately applying flux onto the solder layer 95 of the heat sink 90, the heat sink 90 is disposed onto the first substrate 80 with the metal posts 86 sandwiched therebetween. The first substrate 80 and the heat sink 90 thus superposed are heated and pressurized at a temperature of about 230°C to 260°C. Thereby, the solder layers 85 and 95 are melted, and the metal posts 86 are joined to the conductive layer 15 and the heat sink 90 via the solder layers 85 and 95. By this step, the heat sink 90 is fixed to the first substrate 80 via the metal posts 86, and the conductive layer 15 and the heat sink 90 are electrically connected via the metal posts 86. The heat sink 90 after this step is supported above the first substrate 80 by the metal posts 86. At this time, in the first product region 81 and the second product region 91, the heat sink 90 is in a state of floating hollowly. That is, the heat sink 90 in the second product region 91 is in a state of floating above the semiconductor chip 30 and away from the semiconductor chip 30. Note that in this step, while pressing the heat sink 90 toward the first substrate 80, a reflow process is performed, and the metal posts 86 function as spacers. Therefore, the distance between the first substrate 80 and the heat sink 90 can be suitably maintained at a predetermined distance.

[0070] As shown in FIG. 12, when the heat sink 90 is fixed onto the first substrate 80, the connection pad P3 of the first substrate 80 is exposed in the opening 91X of the heat sink 90. In other words, the connection pad P3 is provided at a position that overlaps with the opening 91X in a plan view.

[0071] Next, in the process shown in FIG. 13, a large-sized second substrate 100 is prepared. The second substrate 100 has a plurality of third product regions 101 and a third non-product region 102. In the second substrate 100, the plurality of third product regions 101 are arranged in a matrix. In each third product region 101, a structure corresponding to the second substrate 20 shown in FIG. 1 is formed. The third non-product region 102 is formed, for example, so as to surround each of the plurality of third product regions 101 in a plan view. The third non-product region 102 has, for example, a third outer peripheral region 103 that collectively surrounds the plurality of third product regions 101 and a third connection region 104 provided between the plurality of third product regions 101.

[0072] Here, after a structure corresponding to the electronic component-embedded substrate 1 shown in FIG. 1 is formed in each third product region 101, it is finally cut along the cutting line indicated by the dashed line and fragmented into individual pieces, each becoming an individual electronic component-embedded substrate 1. That is, the portion outside each third product region 101, that is, the third non-product region 102, is the portion that is finally discarded. In other words, the third non-product region 102 is the portion that does not remain in the finally fragmented electronic component-embedded substrate 1. Note that the number of third product regions 101 in the second substrate 100 is not particularly limited. Hereinafter, for simplicity of explanation, the description will be made by focusing on one third product region 101 and the third non-product region 102 provided around the one third product region 101.

[0073] As shown in FIG. 14, in each third product region 101 of the second substrate 100, a substrate body 21, a wiring layer 22 laminated on the lower surface of the substrate body 21, and a wiring layer 23 laminated on the upper surface of the substrate body 21 are formed. At this time, as shown in FIG. 13, the connection pads P4 of the wiring layer 22 are arranged in a peripheral shape in a plan view in the outer peripheral region of each third product region 101. That is, the connection pads P4 are provided along the outer peripheral edge of each third product region 101.

[0074] Subsequently, in the process shown in FIG. 14, the spacer member 40 is mounted (joined) on the connection pad P4. For example, after appropriately applying flux on the connection pad P4, the spacer member 40 is mounted, and then reflow processing is performed at a temperature of about 230°C to 260°C to fix the spacer member 40 on the connection pad P4. Thereafter, the surface is cleaned to remove the flux.

[0075] Next, in the process shown in FIG. 15, the second substrate 100 is disposed above the first substrate 80 and the heat sink 90. At this time, the first substrate 80, the heat sink 90, and the second substrate 100 are arranged such that the plurality of first product regions 81 and the plurality of third product regions 101 face each other. That is, the first substrate 80, the heat sink 90, and the second substrate 100 are arranged such that the third product region 101 is vertically aligned with the first product region 81 and the second product region 91. Further, the first substrate 80, the heat sink 90, and the second substrate 100 are arranged such that the connection pad P3 of the first substrate 80, the connection pad P4 of the second substrate 100, and the spacer member 40 face each other.

[0076] Subsequently, the spacer member 40 is joined to the connection pad P3. For example, after appropriately applying flux on the upper surface of the connection pad P3, the second substrate 100 is disposed on the first substrate 80 with the spacer member 40 interposed therebetween. Then, a gap (space) is formed by the spacer member 40 between the substrate body 11 of the first substrate 80 and the substrate body 21 of the second substrate 100. Then, the structure superposed as described above is subjected to reflow processing at a temperature of about 230°C to 260°C. As a result, the solder layer 42 of the spacer member 40 melts, and the spacer member 40 is joined to the connection pad P3. In this way, the second substrate 100 is fixed to the first substrate 80 via the spacer member 40, and the connection pad P3 and the connection pad P4 are electrically connected via the spacer member 40. In this step, although the reflow processing is performed while pressing the second substrate 100 against the first substrate 80, since the copper core ball 41 of the spacer member 40 functions as a spacer, the distance between the second substrate 100 and the first substrate 80 is maintained at a predetermined distance.

[0077] Next, in the process shown in FIG. 16, a sealing resin 60 is formed to fill the space between the first substrate 80, the heat sink 90, and the second substrate 100. The sealing resin 60 is formed to fill the space between the first substrate 80 and the heat sink 90 and also to fill the space between the heat sink 90 and the second substrate 100. The sealing resin 60 is formed to seal the semiconductor chip 30 disposed between the first substrate 10 and the second substrate 20. The sealing resin 60 is formed to embed the heat sink 90 disposed between the semiconductor chip 30 and the second substrate 20. The sealing resin 60 is formed to seal the metal post 86 disposed between the first substrate 80 and the heat sink 90. The sealing resin 60 can be formed, for example, by a resin molding method. For example, when using a mold resin having thermosetting properties as the material of the sealing resin 60, the structure shown in FIG. 15 is housed in a mold, and a pressurized (e.g., 5 MPa to 10 MPa) and fluidized mold resin is introduced into the mold. Then, the mold resin is heated and cured at a temperature of about 180° C. to form the sealing resin 60. After completing the required sealing process, the structure with the sealing resin 60 formed is taken out of the mold. Note that, as a method for filling the mold resin, for example, methods such as a transfer molding method, a compression molding method, or an injection molding method can be used.

[0078] Subsequently, in the process shown in FIG. 17, an external connection terminal 70 is formed on the external connection pad P1. For example, after appropriately applying a flux on the external connection pad P1, the external connection terminal 70 (here, a solder ball) is mounted and fixed by a reflow process at a temperature of about 230° C. to 260° C. Then, the surface is cleaned to remove the flux.

[0079] Through the above manufacturing process, a structure corresponding to the electronic component - embedded substrate 1 can be formed in each first product region 81, each second product region 91, and each third product region 101. Next, using a dicing saw or the like, the first substrate 80, the heat sink 90, the second substrate 100, and the encapsulation resin 60 are cut along the cutting positions indicated by the dashed-dotted lines in the figure, that is, along the outer edges of the first product region 81, the second product region 91, and the third product region 101. Thereby, the individual electronic component-embedded substrates 1 are separated into individual pieces. By this step, as shown in FIG. 18, on the cutting surface, the outer surface 52S of the lead portion 52, the outer surface 60S of the encapsulation resin 60, and the outer surfaces of the substrate bodies 11 and 21 are formed flush. Also, by this step, the first non-product region 82, the second non-product region 92, and the third non-product region 102 including the metal post 86 shown in FIG. 17 are removed.

[0080] Through the above manufacturing process, a plurality of electronic component-embedded substrates 1 can be manufactured collectively. Note that the electronic component-embedded substrate 1 after separation can be used in an upside-down state or can be arranged at an arbitrary angle.

[0081] Next, the effects of the present embodiment will be described. (1) The electronic component-embedded substrate 1 includes a first substrate 10, a second substrate 20 provided above the first substrate 10, and a spacer member 40 that electrically connects the first substrate 10 and the second substrate 20. The electronic component-embedded substrate 1 is disposed between the first substrate 10 and the second substrate 20 and has a semiconductor chip 30 mounted on the first substrate 10 and a heat sink 50 disposed between the first substrate 10 and the second substrate 20. The electronic component-embedded substrate 1 fills the space between the first substrate 10 and the second substrate 20 and has an encapsulation resin 60 that encapsulates the semiconductor chip 30. The heat sink 50 has at least its upper surface and lower surface embedded in the encapsulation resin 60. The heat sink 50 is provided so as not to overlap with the spacer member 40 in plan view. The heat sink 50 has an outer surface 52S that is exposed from the outer surface 60S of the encapsulation resin 60.

[0082] According to this configuration, a heat sink 50 is provided between the first substrate 10 and the second substrate 20, and an outer surface 52S of the heat sink 50 is exposed from an outer surface 60S of the sealing resin 60. For this reason, heat generated in the semiconductor chip 30 is conducted to the heat sink 50 through the sealing resin 60, and the heat is radiated from the outer surface 52S of the heat sink 50 into the atmosphere. Thereby, heat generated in the semiconductor chip 30 can be efficiently radiated, and the heat dissipation performance of the substrate 1 with built-in electronic components can be improved. As a result, an increase in the temperature of the semiconductor chip 30 can be suppressed. Further, even when an electronic component is mounted on the component connection pad P5 of the second substrate 20, it is possible to suitably suppress heat generated in the semiconductor chip 30 from being conducted to the electronic component. Thereby, an increase in the temperature of the electronic component mounted on the component connection pad P5 can be suppressed.

[0083] (2) The heat sink 50 is disposed between the semiconductor chip 30 and the second substrate 20. The sealing resin 60 fills the space between the first substrate 10 and the heat sink 50, the space between the heat sink 50 and the second substrate 20, and the space between the semiconductor chip 30 and the heat sink 50. According to this configuration, a gap is formed between the semiconductor chip 30 and the heat sink 50, and the gap is filled with the sealing resin 60. For this reason, compared with the case where there is no gap between the semiconductor chip 30 and the heat sink 50, the filling property of the resin when forming the sealing resin 60 can be improved.

[0084] (3) The heat sink 50 is supported above the first substrate 10 only by the sealing resin 60. In other words, the substrate 1 with built-in electronic components is not provided with a connecting member such as a metal post 86 that connects the heat sink 50 and the first substrate 10. For this reason, compared with the case where a connecting member is provided, the substrate 1 with built-in electronic components can be miniaturized.

[0085] A metal post 86 for connecting the first substrate 80 and the heat sink 90 is provided in the first non-product area 82 provided outside the first product area 81 and the second non-product area 92 provided outside the second product area 91. Subsequently, the second substrate 100 is mounted on the first substrate 80 via the spacer member 40. Then, with the first substrate 80 and the heat sink 90 connected by the metal post 86, the space between the first substrate 80 and the heat sink 90 and the space between the heat sink 90 and the second substrate 100 are filled, and a sealing resin 60 for sealing the semiconductor chip 30 is formed.

[0086] According to this configuration, the sealing resin 60 can be formed while maintaining the distance between the first substrate 80 and the heat sink 90 at a desired distance by the metal post 86. Thereby, the distance between the first substrate 10 and the heat sink 50 in the electronic component built-in substrate 1 after singulation can be suitably set to a desired distance. Also, the distance between the semiconductor chip 30 and the heat sink 50 in the electronic component built-in substrate 1 after singulation can be suitably set to a desired distance. Furthermore, since the metal post 86 does not remain in the electronic component built-in substrate 1 after singulation, the electronic component built-in substrate 1 can be miniaturized.

[0087] (5) The first substrate 80 and the heat sink 90 are connected via the metal post 86. According to this configuration, compared with the case where the first substrate 80 and the heat sink 90 are connected by solder balls, the connecting member for connecting the first substrate 80 and the heat sink 90, that is, the metal post 86, can be miniaturized in the planar direction.

[0088] (Other embodiments) The above embodiment can be implemented with the following modifications. The above embodiment and the following modification examples can be implemented in combination with each other within a technically non-conflicting range.

[0089] · As shown in FIG. 19, the portion of the heat sink 90 that is to be the cutting position may be formed to be thinner than the other portions. For example, the thickness of the heat sink 90 in the second non-product region 92 may be formed to be thinner than the thickness of the heat sink 90 in the second product region 91. For example, a recess 92X that recesses downward from the upper surface of the heat sink 90 may be formed in the heat sink 90 in the second non-product region 92. The recess 92X may be provided throughout the second non-product region 92, or may be partially provided only in the portion of the second non-product region 92 that is to be the cutting position. The recess 92X in this modification example is provided throughout the second non-product region 92. The recess 92X can be formed, for example, by etching or pressing.

[0090] According to this configuration, when cutting the second non-product region 92 with a dicing saw or the like, the cutting amount of the heat sink 90 can be reduced. Thereby, when cutting the second non-product region 92, it is possible to suitably suppress damage to a cutting machine such as a dicing saw.

[0091] · In the modification example shown in FIG. 19, the recess 92X may be formed to recess upward from the lower surface of the heat sink 90. In this case, the solder layer 95 is joined to the bottom surface of the recess 92X.

[0092] · In the modification example shown in FIG. 19, the recess 92X may be formed to extend to the lead portion 52 in the second product region 91. · As shown in FIG. 20, a recess 51X may be provided on the lower surface of the heat sink 50. The recess 51X is formed, for example, to recess upward from the lower surface of the heat sink 50. The recess 51X is provided, for example, in the main body portion 51 of the heat sink 50. The recess 51X is provided, for example, so as to overlap the semiconductor chip 30 in a plan view. The recess 51X is provided, for example, so as to overlap the entire semiconductor chip 30 in a plan view. The recess 51X can be formed, for example, by etching or pressing.

[0093] According to this configuration, by providing the concave portion 51X, the gap between the upper surface of the semiconductor chip 30 and the lower surface of the heat sink 50 (specifically, the bottom surface of the concave portion 51X) can be increased. Thereby, when forming the encapsulation resin 60, the space between the semiconductor chip 30 and the heat sink 50 can be suitably filled with the resin.

[0094] · In the modification shown in FIG. 20, the concave portion 51X may be provided, for example, so as to partially overlap with the semiconductor chip 30 in plan view. For example, the concave portion 51X may be provided so as not to overlap with the semiconductor chip 30 in plan view. For example, the concave portion 51X may be provided in the lead portion 52 of the heat sink 50.

[0095] · As shown in FIG. 21, an opening 51Y may be provided in the heat sink 50. The opening 51Y is formed so as to penetrate the heat sink 50 in the thickness direction. The opening 51Y is provided, for example, in the main body portion 51 of the heat sink 50. The opening 51Y is provided, for example, so as to overlap with the semiconductor chip 30 in plan view. The opening 51Y is provided, for example, so as to overlap with the entire semiconductor chip 30 in plan view. The planar size of the opening 51Y is formed, for example, to be slightly larger than the planar size of the semiconductor chip 30. The opening 51Y can be formed, for example, by etching or pressing.

[0096] According to this configuration, by providing the opening 51Y, the resin filling property when forming the encapsulation resin 60 can be improved. · In the modification shown in FIG. 21, the opening 51Y may be provided, for example, so as to partially overlap with the semiconductor chip 30 in plan view. For example, the opening 51Y may be provided so as not to overlap with the semiconductor chip 30 in plan view. For example, the opening 51Y may be provided in the lead portion 52 of the heat sink 50.

[0097] · As shown in FIG. 22, the semiconductor chip 30 may be disposed inside the opening 51Y of the heat sink 50. By disposing the semiconductor chip 30 inside the opening 51Y, it becomes unnecessary to form the heat sink 50 between the semiconductor chip 30 and the second substrate 20, so that the entire electronic component built-in substrate 1 can be thinned.

[0098] · The planar shape of the heat sink 50 in the above embodiment can be appropriately changed. · For example, as shown in FIG. 23, the number of lead portions 52 in the heat sink 50 may be changed. The heat sink 50 only needs to have at least one lead portion 52. The heat sink 50 in this modification example has a main body portion 51 and two lead portions 52 extending along the left-right direction in the drawing from the side surface of the main body portion 51.

[0099] · The planar shape of the main body portion 51 in the above embodiment can be appropriately changed. For example, the planar shape of the main body portion 51 may be changed to a polygon other than a rectangle, a circle, or an ellipse. · The number and arrangement of the metal posts 86 in the manufacturing method of the above embodiment are not particularly limited. Similarly, the number and arrangement of the conductive layers 15 are not particularly limited.

[0100] · In the manufacturing method of the above embodiment, after the metal post 86 is joined to the conductive layer 15 of the first substrate 80, the metal post 86 is joined to the heat sink 90, but it is not limited to this. For example, after the metal post 86 is joined to the heat sink 90, the metal post 86 may be joined to the conductive layer 15.

[0101] · In the manufacturing method of the above embodiment, the metal post 86 is joined to the conductive layer 15 and the heat sink 90 by the solder layers 85 and 95, but the joining method is not particularly limited as long as the metal post 86 can be joined to the conductive layer 15 and the heat sink 90.

[0102] · In the manufacturing method of the above embodiment, the connection member connecting the first substrate 80 and the heat sink 90 may be changed to a connection member other than the metal post 86. For example, the connection member connecting the first substrate 80 and the heat sink 90 may be embodied as solder balls.

[0103] · In the above embodiment, the core ball of the spacer member 40 is embodied as the copper core ball 41, but it is not limited thereto. For example, instead of the copper core ball 41, a conductive core ball formed of a metal other than copper such as gold or nickel may be used, or a resin core ball formed of resin may be used.

[0104] · In the above embodiment, the spacer member 40 is embodied as a solder ball with a core, but it is not limited thereto. For example, the spacer member 40 may be embodied as a solder ball in which the core ball such as the copper core ball 41 is omitted. For example, the spacer member 40 may be embodied as a metal post.

[0105] · The structure of the first substrate 10 of the above embodiment can be appropriately changed. For example, the number and arrangement of the external connection pads P1 can be appropriately changed. For example, the number and arrangement of the pads P2 can be appropriately changed. For example, the number and arrangement of the connection pads P3 can be appropriately changed.

[0106] · The structure of the second substrate 20 of the above embodiment can be appropriately changed. For example, the number and arrangement of the connection pads P4 can be appropriately changed. For example, the number and arrangement of the component connection pads P5 can be appropriately changed.

[0107] · In the electronic component built-in substrate 1 of the above embodiment, a plurality of electronic components may be mounted on the first substrate 10. · The mounting form of the semiconductor chip 30 in the above embodiment can be appropriately changed. Examples of the mounting form of the semiconductor chip 30 include flip chip mounting, wire bonding mounting, solder mounting, or a combination thereof.

[0108] ·In the above embodiment, the semiconductor chip 30 is mounted on the first substrate 10, but the present invention is not limited to this. For example, other electronic components such as capacitors and inductors may be mounted on the first substrate 10.

[0109] ·In the above embodiment, the electronic component - embedded substrate 1 having a structure in which two substrates, the first substrate 10 and the second substrate 20, are laminated on each other via the spacer member 40 is embodied. However, the present invention is not limited to this, and the electronic component - embedded substrate 1 having a structure in which three or more substrates are laminated on each other via the spacer member 40 may be embodied.

Explanation of Reference Numerals

[0110] 1 Electronic component - embedded substrate 10 First substrate 15 Conductive layer (first connection portion) 20 Second substrate 30 Semiconductor chip (electronic component) 40 Spacer member 50 Heat sink 51 Body portion 51X Recess 51Y Opening 52, 52A, 52B Lead portions 52S Outer surface (second outer surface) 60 Encapsulating resin 60S Outer surface (first outer surface) 80 First substrate 81 First product region 82 First non - product region 85 Solder layer (first connection portion, first solder layer) 86 Metal post (connection member) 90 Heat sink 91 Second product region 92 Second non - product region 95 Solder layer (second connection portion, second solder layer) 100 Second substrate 101 Third product region 102 Third non - product region

Claims

1. A first substrate; a second substrate provided above the first substrate; a spacer member that electrically connects the first substrate and the second substrate; an electronic component disposed between the first substrate and the second substrate and mounted on the first substrate; a heat sink disposed between the first substrate and the second substrate; a sealing resin that fills a space between the first substrate and the second substrate and seals the electronic components, At least an upper surface and a lower surface of the heat sink are embedded in the sealing resin, the heat sink is provided so as not to overlap the spacer member in a plan view, The heat sink has a second outer surface exposed from the first outer surface of the sealing resin, and the electronic component-embedded substrate.

2. the heat sink is disposed between the electronic component and the second substrate, 2. The electronic component-embedded substrate according to claim 1, wherein the sealing resin fills a space between the first substrate and the heat sink, a space between the heat sink and the second substrate, and a space between the electronic component and the heat sink.

3. the heat sink has a main body provided to overlap the electronic component in a plan view, and one or more lead portions protruding outward from a side surface of the main body, 2 . The electronic component built-in substrate according to claim 1 , wherein an outer surface of the lead portion located on an outer periphery of the electronic component built-in substrate is the second outer surface.

4. The main body portion has a recess that is recessed upward from a lower surface of the main body portion, The electronic component built-in substrate according to claim 3 , wherein the recess is provided so as to overlap the electronic component in a plan view.

5. The main body has a planar size that is slightly larger than the planar size of the electronic component, The main body has an opening penetrating the main body in a thickness direction, The electronic component built-in substrate according to claim 3 , wherein the opening is provided so as to overlap the electronic component in a plan view.

6. The electronic component built-in substrate according to claim 5 , wherein the electronic component is disposed inside the opening of the heat sink.

7. The electronic component built-in substrate according to claim 1 , wherein the second outer surface is formed flush with the first outer surface.

8. preparing a first substrate having a plurality of first product regions, a first non-product region, and a plurality of first connection portions provided in the first non-product region; mounting an electronic component in each of the plurality of first product areas; preparing a heat sink having a plurality of second product regions, a second non-product region, and a plurality of second connection portions provided in the second non-product regions; a step of joining a connection member to the first connection portion or the second connection portion; a step of placing the heat sink above the first substrate such that the plurality of first product regions and the plurality of second product regions face each other and the plurality of first connection portions and the plurality of second connection portions face each other, and connecting the first connection portions and the second connection portions via the connection members; providing a second substrate having a plurality of third product areas and a third non-product area; a step of: arranging the second substrate above the first substrate with the third substrate regions facing the first substrate regions and a spacer member interposed between the first substrate and the second substrate; and connecting the first substrate and the second substrate via the spacer member; forming a sealing resin that fills a space between the first substrate and the heat sink and a space between the heat sink and the second substrate and seals the electronic components and the connecting members; cutting the first substrate, the heat sink, the second substrate, and the sealing resin along an outer edge of the first product area, an outer edge of the second product area, and an outer edge of the third product area to separate the first substrate, the heat sink, the second substrate, and the sealing resin into individual pieces; the heat sink is provided so as not to overlap the spacer member in a plan view, A method for manufacturing a substrate with embedded electronic components, wherein a second outer surface, which is a cut surface of the heat sink after the individual pieces, is formed so as to be exposed from a first outer surface, which is a cut surface of the sealing resin.

9. the first connection portion has a conductive layer provided on the top surface of the first substrate in the first non-product region and a first solder layer formed on the conductive layer; the second connection portion has a second solder layer provided on a lower surface of the heat sink in the second non-product area, 9. The method for manufacturing a substrate with built-in electronic components according to claim 8, wherein the connection member is a metal post that is joined to the first solder layer and to the second solder layer.

10. the heat sink is supported by the connecting member at a position spaced apart from the electronic component, The method for manufacturing an electronic component-embedded substrate according to claim 8 , wherein the sealing resin is formed so as to fill a space between the electronic component and the heat sink.

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