Semiconductor device and manufacturing method of semiconductor device

Abstract

To provide a semiconductor device that can be easily manufactured while suppressing ringing.SOLUTION: A first buffer layer 5 and a second buffer layer 6 of a first conductive type have an impurity concentration higher than that of a drift layer 3 of the first conductive type. The first buffer layer 5 is provided in the drift layer 3. The second buffer layer 6 is provided between a second main surface SF2 and the first buffer layer 5. In a thickness direction, a separation distance DS is provided between a position where the first buffer layer 5 has an impurity peak concentration and a position where the second buffer layer 6 has the impurity peak concentration. The position where the first buffer layer 5 has the impurity peak concentration in the thickness direction includes a distribution part PDa and a non-distribution part PDb in a planar layout. The non-distribution part PDb includes an effective width WD that is smaller than the separation distance DS. The effective width WD is double the farthest distance from the distribution part PDa in the non-distribution part PDb in planar layout.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] According to Japanese Unexamined Patent Application Publication No. 2018-125537 (Patent Document 1), a semiconductor device includes an n-type drift region disposed inside a semiconductor substrate, and an n-type field stop region formed on the back surface side of the semiconductor substrate using protons as donors and having a donor concentration higher than that of the drift region. The concentration distribution of the donors in the depth direction in the field stop region has a plurality of peaks. The plurality of peaks include a first peak and a second peak having a lower concentration than the first peak on the back surface side of the semiconductor substrate with respect to the first peak. As an example of the plurality of peaks of the field stop region, the first to fourth peaks are shown in the figure. Further, according to the above publication, in the region from 5 / 7 to the back surface of the semiconductor substrate as viewed from the surface of the semiconductor substrate, although it is preferable that the carrier lifetime is short in order to reduce the tail current, if the carrier lifetime is made too short, an oscillation phenomenon may occur during reverse recovery. Therefore, the carrier lifetime in this region may be shorter than that in the region from 3 / 7 to 5 / 7 and longer than that in the region from the surface of the semiconductor substrate to 3 / 7.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] According to the technology described in the above publication, in order to sufficiently suppress the oscillation phenomenon (in other words, ringing), the adjustment of the donor concentration distribution in the depth direction (in other words, the thickness direction) of the semiconductor substrate must be carried out finely as described above. Therefore, the adjustment of the concentration distribution in the thickness direction becomes complicated. This is likely to lead to a significant increase in the manufacturing cost of the semiconductor device. Typically, in the thickness direction, it is necessary to form a large number of impurity peaks each having an optimal concentration by proton implantation. This greatly increases the labor of the process of introducing impurities.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to provide a semiconductor device that can be easily manufactured while suppressing ringing.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a drift layer of a first conductivity type provided on a semiconductor substrate having a first main surface and a second main surface facing the first main surface in the thickness direction, a base layer of a second conductivity type provided between the first main surface of the semiconductor substrate and the drift layer and having a higher impurity concentration than the drift layer, a first buffer layer of the first conductivity type provided in the drift layer and having a higher impurity concentration than the drift layer, and a second buffer layer of the first conductivity type provided between the second main surface of the semiconductor substrate and the first buffer layer and having a higher impurity concentration than the drift layer. In the thickness direction, a separation distance is provided between a position where the first buffer layer has an impurity peak concentration and a position where the second buffer layer has an impurity peak concentration. By selectively forming the first buffer layer in a plane layout perpendicular to the thickness direction, the position where the first buffer layer has the impurity peak concentration in the thickness direction forms a distribution surface having a distribution portion and a non-distribution portion in the plane layout, the non-distribution portion has an effective width smaller than the separation distance, and the effective width is twice the farthest distance from the distribution portion in the non-distribution portion of the plane layout.

Advantages of the Invention

[0007] According to the present disclosure, it is possible to easily manufacture a semiconductor device while suppressing ringing.

[0008] The object, features, aspects, and advantages of the present disclosure will become clearer from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their descriptions will not be repeated. In this specification, the impurity concentration of an n-type semiconductor is the donor concentration, and the impurity concentration of a p-type semiconductor is the acceptor concentration. Also, the term "impurity concentration" means the concentration of activated impurities. Correspondingly, the term "impurity peak concentration" means the peak concentration of activated impurities.

[0011] <Embodiment 1> FIG. 1 is a schematic top view showing the configuration of a semiconductor device 100 in Embodiment 1. The semiconductor device 100 is an Insulated Gate Bipolar Transistor (IGBT). The semiconductor device 100 has a cell portion 22, a gate pad 23 provided in the cell portion 22, and a termination portion 24 disposed around them. The cell portion 22 is a portion through which a main current flows when the semiconductor device 100 is in a conductive state. The gate pad 23 is a portion to which a gate signal for controlling the main current is to be input. In this specification, all the planar layouts described later are for the cell portion 22 (FIG. 1).

[0012] FIG. 2 is a schematic partial top view showing the region II of FIG. 1 with the illustration of the configuration on the semiconductor substrate SB (FIG. 3) omitted. FIG. 3 is a schematic partial cross-sectional view taken along the line III-III of FIG. 2.

[0013] The semiconductor device 100 has a semiconductor substrate SB having a first main surface SF1 (upper surface) and a lower surface SF2 (second main surface) facing the upper surface SF1 in the thickness direction. The semiconductor material forming the semiconductor substrate SB is, for example, Si, SiC, GaN, GaAs, GaO, or diamond.

[0014] The semiconductor device 100 has a pair of main electrodes. Specifically, a main electrode 15 (first main electrode) is provided on the upper surface SF1, and a main electrode 20 (second main electrode) is provided on the lower surface SF2. Therefore, the semiconductor device 100 is configured such that a main current flows in the thickness direction of the semiconductor substrate SB. In other words, the semiconductor device 100 is a vertical semiconductor device. In the present embodiment, the main electrode 15 is an emitter electrode, and the main electrode 20 is a collector electrode. Each of the emitter electrode and the collector electrode may have a silicide layer (not shown) at a portion in contact with the semiconductor substrate SB in order to obtain an ohmic contact with the semiconductor substrate SB.

[0015] The semiconductor substrate SB is provided with an n-type (first conductivity type) drift layer 3, a p-type (second conductivity type different from the first conductivity type) base layer 4, an n-type first buffer layer 5, and an n-type second buffer layer 6. Further, the semiconductor substrate SB is provided with an n + -type source layer 17, an n-type carrier accumulation layer 18, a p-type collector layer 19, and a p + -type contact layer 25.

[0016] The drift layer 3 is provided between the upper surface SF1 and the lower surface SF2 of the semiconductor substrate SB. The base layer 4 is provided between the upper surface SF1 of the semiconductor substrate SB and the drift layer 3. The first buffer layer 5 is provided in the drift layer 3. The second buffer layer 6 is provided between the lower surface SF2 of the semiconductor substrate SB and the first buffer layer 5. The base layer 4 has a higher impurity concentration than the drift layer 3. The first buffer layer 5 has a higher impurity concentration than the drift layer 3. The second buffer layer 6 has a higher impurity concentration than the drift layer 3.

[0017] On the upper surface SF1 of the semiconductor substrate SB, a trench gate 21 embedded in a trench is provided. The trench has a side wall including a portion facing the base layer 4. The trench gate 21 has a trench electrode 21a and a trench insulating film 21b. The interlayer insulating film 16 is provided on the upper surface SF1 of the semiconductor substrate SB. The trench electrode 21a faces the base layer 4 through the interlayer insulating film 16.

[0018] The interlayer insulating film 16 separates the trench electrode 21a and the main electrode 15 from each other. On the other hand, the interlayer insulating film 16 is patterned so that the main electrode 15 is in contact with the n + -type source layer 17 and the p + -type contact layer 25.

[0019] FIG. 4 is a graph showing schematic profiles of the impurity concentration N along each of the lines a1-a1, a2-a2, and b-b in FIG. 3. In the thickness direction, a separation distance DS is provided between the position where the first buffer layer 5 has an impurity peak concentration and the position where the second buffer layer 6 has an impurity peak concentration. The set of positions where the first buffer layer 5 has an impurity peak concentration in the thickness direction may substantially form a flat surface perpendicular to the thickness direction. The set of positions where the second buffer layer 6 has an impurity peak concentration in the thickness direction may substantially form a flat surface perpendicular to the thickness direction. The impurity peak concentration of the first buffer layer 5 (see FIG. 4) is preferably 1.0×10 16 / cm 3 or more, and more preferably 1.0×10 17 / cm 3 or more.

[0020] FIG. 5 is a schematic diagram showing the planar layout of the first buffer layer 5 in FIG. 3. By selectively forming the first buffer layer 5 in a planar layout perpendicular to the thickness direction, the positions where the first buffer layer 5 has an impurity peak concentration in the thickness direction (see FIG. 4) form a distribution surface PD having a distribution portion PDa and a non-distribution portion PDb in the planar layout. The non-distribution portion PDb is a portion where the impurity peak concentration of the second buffer layer 6 is observed in the planar layout, but the impurity peak concentration of the first buffer layer 5 in the thickness direction is not observed (see the concentration profile along the line a2-a2 shown in the upper right of FIG. 4). It is preferable that the area occupied by the distribution portion PDa in the distribution surface PD of the impurity peak concentration of the first buffer layer 5 is 5% or more and 90% or less.

[0021] The non-distributed portion PDb has an effective width WD that is smaller than the separation distance DS. That is, the following inequality WD < DS is satisfied. The effective width WD is twice the farthest distance from the distributed portion PDa in the non-distributed portion PDb of the planar layout. The farthest distance is the distance between the farthest position FR from the distributed portion PDa in the non-distributed portion PDb and the distributed portion PDa.

[0022] In the planar layout of FIG. 5, the non-distributed portion PDb has a circular shape, and the farthest position FR corresponds to the center of this circle. Therefore, in this planar layout, the farthest distance corresponds to the radius of this circle, and the effective width WD corresponds to the diameter of this circle. As a modification, a planar layout in which the distributed portion PDa and the non-distributed portion PDb shown in FIG. 5 are interchanged may be applied. This modified planar layout has a farthest position FRm and an effective width WDm.

[0023] FIG. 6 is a schematic partial cross-sectional view showing the extension of the tip ED of the depletion layer passing through the non-distributed portion PDb (FIG. 5) of the first buffer layer 5. The extension of the tip ED of the depletion layer toward the second buffer layer 6 in the thickness direction is most likely to proceed in the non-distributed portion PDb. The degree of this progress depends on the magnitude of the effective width WD. Specifically, by reducing the effective width WD, the progress of the tip ED of the depletion layer can be suppressed.

[0024] The first buffer layer 5 is provided for the purpose of obtaining a function of suppressing ringing. According to the study by the present inventors, this function is not necessarily greatly impaired even if the non-distributed portion PDb exists. On the other hand, according to the study by the present inventors, when the tip ED of the depletion layer reaches the second buffer layer 6, it leads to the occurrence of ringing. Therefore, it is necessary to make it difficult for the tip ED of the depletion layer to reach the second buffer layer 6. The above inequality WD < DS is due to this necessity.

[0025] FIG. 7 shows the impurity peak concentration of the first buffer layer 5 as 1×10 16 / cm 3and while setting the effective width WD of the non-distributed portion PDb of the first buffer layer 5 to 10 μm, the separation distance DS between the first buffer layer 5 and the second buffer layer 6 in the thickness direction is set to 5 μm (solid line), 10 μm (dashed line), and 20 μm (dash-dotted line), respectively, the collector-emitter voltage V during turn-off of the semiconductor device 100 CE is a graph showing the simulation results of the time change. According to this result, it can be seen that ringing is prevented under the condition of the dash-dotted line corresponding to WD < DS.

[0026] FIG. 8 shows that while setting the effective width WD of the non-distributed portion PDb of the first buffer layer 5 to 10 μm and setting the separation distance DS between the first buffer layer 5 and the second buffer layer 6 in the thickness direction to 20 μm, the impurity peak concentration of the first buffer layer 5 is 1×10 15 / cm 3 (solid line), 1×10 16 / cm 3 (dashed line), and 1×10 17 / cm 3 (dash-dotted line), respectively, the collector-emitter voltage V during turn-off of the semiconductor device 100 CE is a graph showing the simulation results of the time change. According to this result, the effect of suppressing ringing is more prominent under the condition where the impurity peak concentration of the first buffer layer 5 is 1×10 16 / cm 3 (dashed line) than under the condition where the impurity peak concentration of the first buffer layer 5 is 1×10 15 / cm 3 (solid line). Therefore, the impurity peak concentration of the first buffer layer 5 is preferably 1×10 16 / cm 3 or more, and ideally 1×10 17 / cm 3 or more is more preferable from the viewpoint of suppressing ringing.

[0027] FIG. 9 is a schematic partial cross-sectional view showing one step of a method for manufacturing the semiconductor device 100 in Embodiment 1. In this step, impurities are selectively implanted in a planar layout from the lower surface SF2 of the semiconductor substrate SB into the semiconductor substrate SB by using an implantation mask 12. In other words, ion implantation using the implantation mask 12 is performed. As a result, an impurity-implanted layer 5P is formed in a region that will become the first buffer layer 5 (FIG. 3). The implantation mask 12 may be formed using a photoresist. The implantation direction of the impurities (arrow 13) may be approximately in only a single direction. Although there is a space between the implantation mask 12 and the lower surface SF2 in FIG. 9, the implantation mask 12 may be provided directly on the lower surface SF2. Thereafter, the first buffer layer 5 is formed by heating the layer 5P to activate the impurities.

[0028] As a method for adding impurities at a relatively deep position, it is preferable to use proton implantation. By heating the implanted protons, hydrogen-induced donors can be formed. In this case, the first buffer layer 5 has hydrogen-induced donors. Specifically, the distribution portion Pda of the first buffer layer 5 has hydrogen-induced donors. On the other hand, the non-distribution portion Pdb of the first buffer layer 5 does not necessarily have hydrogen-induced donors. The concentration of the hydrogen-induced donors can be evaluated, for example, using the spreading resistance (SR) method.

[0029] When the first buffer layer 5 is formed by ion implantation from the lower surface SF2 as described above, specifically, proton implantation, defects occur in the region through which the protons pass, and as a result, the resistance of the region increases. Due to this effect, the resistivity of the drift layer 3 between the first buffer layer 5 and the lower surface SF2 becomes higher than the resistivity of the drift layer 3 between the first buffer layer 5 and the upper surface SF1.

[0030] Regarding the steps other than the above, the normal steps in the manufacture of an IGBT may be applied, and thus the description thereof is omitted.

[0031] According to this embodiment, first, the effective impurity concentration of the first buffer layer 5 can be adjusted not only by the actual impurity concentration of the first buffer layer 5 but also by the fact that the first buffer layer 5 is selectively provided in the planar layout. As a result, it becomes easier to suppress ringing without overly complicating the adjustment of the impurity concentration profile in the thickness direction. Second, in the planar layout, the effective width WD of the non-distributed portion PDb of the first buffer layer 5 is smaller than the separation distance DS between the first buffer layer 5 and the second buffer layer 6 in the thickness direction. As a result, it becomes difficult for the depletion layer extending through the non-distributed portion PDb of the first buffer layer 5 to reach the second buffer layer 6. Therefore, the occurrence of ringing due to the arrival of the depletion layer at the second buffer layer 6 is prevented. For these reasons, it is possible to easily manufacture a semiconductor device while suppressing ringing.

[0032] The impurity peak concentration of the first buffer layer 5 is preferably 1.0×10 16 / cm 3 or more. Thereby, the extension of the depletion layer can be more reliably suppressed. The impurity peak concentration of the first buffer layer 5 is more preferably 1.0×10 17 / cm 3 or more. Thereby, the extension of the depletion layer can be more sufficiently suppressed. When the first buffer layer 5 is formed by impurity implantation from the lower surface SF2 of the semiconductor substrate SB, defects are formed between the lower surface SF2 of the semiconductor substrate SB and the first buffer layer 5 due to the implantation. In this embodiment, specifically, defects are formed in the region through which protons have passed in the proton implantation process. When a high voltage is applied because the defects are included in the depletion layer, they become the generation sources of electrons and holes that cause leakage current. From the viewpoint of preventing this, it is preferable to set the impurity concentration of the first buffer layer 5 to be high to some extent as described above.

[0033] In the distribution plane PD of the impurity peak concentration of the first buffer layer 5, it is preferable that the area occupied by the distribution portion PDa is 5% or more. Thereby, the function of stopping the tip ED (FIG. 6) of the depletion layer extending from the base layer 4 by the first buffer layer 5 can be more sufficiently ensured.

[0034] In the distribution plane PD of the impurity peak concentration of the first buffer layer 5, the area occupied by the distribution portion PDa may be 90% or less. Thereby, it becomes easier to sufficiently avoid deterioration of electrical characteristics (for example, an increase in conduction resistance).

[0035] In the present embodiment, the semiconductor device 100 which is an IGBT has been described. However, the semiconductor device may include other elements in addition to the IGBT. For example, by including an IGBT and a freewheel diode, the semiconductor device becomes a reverse-conductive insulated gate bipolar transistor (RC-IGBT). Further, the semiconductor device may be a transistor different from the IGBT. For example, it may be a metal-insulator-semiconductor field-effect transistor (MISFET). Note that the MISFET may be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0036] <Embodiment 2> FIG. 10 is a schematic diagram showing the planar layout of the first buffer layer 5 in Embodiment 2. In this Embodiment 2, unlike the case of FIG. 5 (Embodiment 1), the non-distributed portion PDb has a square shape, and the farthest position FR corresponds to the center of this square. Therefore, in this planar layout, the farthest distance corresponds to half of the side length of this square, and the effective width WD corresponds to the side length of this square. A rectangle may be used instead of the square, and in that case, the effective width WD corresponds to the length of the short side. As a modification, a planar layout in which the distributed portion PDa and the non-distributed portion PDb shown in FIG. 10 are interchanged with each other may be applied. This planar layout of the modification has the farthest position FRm and the effective width WDm. Regarding the configuration other than the above, since it is substantially the same as the configuration of Embodiment 1 described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0037] <Embodiment 3> FIG. 11 is a schematic diagram showing the planar layout of the first buffer layer 5 in Embodiment 3. In this Embodiment 3, unlike the case of FIG. 5 (Embodiment 1), the distributed portion PDa and the non-distributed portion PDb form a stripe shape. Therefore, the non-distributed portion PDb has a band shape, and the farthest position FR corresponds to a straight line (not shown) extending along the center of this band shape along the band shape. Therefore, in this planar layout, the farthest distance corresponds to half of the width of this band shape, and the effective width WD corresponds to the width of this band shape. Regarding the configuration other than the above, since it is substantially the same as the configuration of Embodiment 1 described above, the same or corresponding elements are denoted by the same reference numerals, and the description thereof will not be repeated.

[0038] <Embodiment 4> FIG. 12 is a schematic diagram showing a plan layout of the first buffer layer 5 in the fourth embodiment. In the fourth embodiment, unlike the case of FIG. 5 (first embodiment), the non-distribution portion PDb has a complex shape, and the farthest distance DF and the farthest position FR are illustrated based on the definition described in the first embodiment above. For the configurations other than the above, since they are substantially the same as those of the first embodiment described above, the same reference numerals are assigned to the same or corresponding elements, and the description thereof will not be repeated.

[0039] <Fifth Embodiment> FIG. 13 is a schematic partial cross-sectional view showing the configuration of the semiconductor device 300 in the fifth embodiment. This semiconductor device 300 is a diode, unlike the semiconductor device 100 (FIG. 3: first embodiment). The semiconductor device 300 (FIG. 13) has a p-type anode layer 26 (the base layer in this embodiment) and an n + cathode layer 27 instead of the base layer 4 and the p-type collector layer 19 (FIG. 3), respectively. Also, the semiconductor device 300 (FIG. 13) does not require the trench gate 21 and the interlayer insulating film 16 (FIG. 3). For the configurations other than the above, since they are substantially the same as those of any of the first to fourth embodiments described above, the same reference numerals are assigned to the same or corresponding elements, and the description thereof will not be repeated. According to the fifth embodiment, substantially the same effects as those of the first to fourth embodiments can be obtained in the case of a diode.

[0040] <Sixth Embodiment> FIG. 14 is a schematic partial cross-sectional view showing the configuration of the semiconductor device 101 in Embodiment 6. The semiconductor device 101 further has an n-type third buffer layer 10 in addition to the configuration of the semiconductor device 100 (FIG. 3). The third buffer layer 10 is provided between the first buffer layer 5 and the second buffer layer 6. The third buffer layer 10 has a higher impurity concentration than the drift layer 3. For the configurations other than those described above, since they are substantially the same as the configurations of Embodiments 1 to 3 described above, the same reference numerals are assigned to the same or corresponding elements, and the description thereof will not be repeated. Note that the third buffer layer 10 in the present embodiment may also be applied to the semiconductor device 300 of Embodiment 4. According to the present embodiment, the effect of suppressing ringing can be further enhanced.

[0041] <Embodiment 7> FIG. 15 is a schematic partial cross-sectional view showing the configuration of the semiconductor device 102 in Embodiment 7. In the semiconductor device 102 (FIG. 15), unlike the semiconductor device 101 (FIG. 14: Embodiment 6), the third buffer layer 10 is selectively formed in the planar layout. As a result, the positions where the third buffer layer 10 has impurity peak concentrations in the thickness direction form a distribution plane having a distributed portion and a non-distributed portion in the planar layout. In the planar layout, the distributed portion of the third buffer layer 10 overlaps with the non-distributed portion PDb of the first buffer layer 5, and the non-distributed portion of the third buffer layer 10 overlaps with the distributed portion PDa of the first buffer layer 5. In the planar layout, it is preferable that the area of the distributed portion of the third buffer layer 10 is larger than the area of the distributed portion PDa of the first buffer layer 5.

[0042] In the example shown in FIG. 15, in the planar layout, the distributed portion PDa of the first buffer layer 5 and the non-distributed portion of the third buffer layer 10 are approximately the same, and the non-distributed portion PDb of the first buffer layer 5 and the distributed portion of the third buffer layer 10 are approximately the same. In other words, the pattern of the distribution plane of the third buffer layer 10 corresponds to a pattern that is approximately the inversion of the pattern of the distribution plane PD of the first buffer layer 5.

[0043] FIG. 16 is a schematic partial cross-sectional view showing a step in a method of manufacturing a semiconductor device 102. In this step, impurity implantation through the opening of an implantation mask 12M and impurity implantation with the implantation energy attenuated by passing through the non-opening portion of the implantation mask 12M are simultaneously performed from the lower surface SF2 of the semiconductor substrate SB into the semiconductor substrate SB by using a sufficiently thin implantation mask 12M or a sufficiently high acceleration voltage. Specifically, impurity-implanted layers 5P and 10P are formed in regions where the first buffer layer 5 and the third buffer layer 10 (FIG. 15) are to be formed, respectively. The impurity implantation direction (arrow 13) may be approximately in only a single direction. The implantation mask 12M may be formed using a photoresist. Although there is a space between the implantation mask 12M and the lower surface SF2 in FIG. 16, the implantation mask 12M may be provided directly on the lower surface SF2. Thereafter, the first buffer layer 5 and the third buffer layer 10 are formed by activating the impurities by heating the layers 5P and 10P.

[0044] As a method of adding impurities to a relatively deep position, it is preferable to use proton implantation. By heating the implanted protons, hydrogen-induced donors can be formed, and in this case, the first buffer layer 5 and the third buffer layer 10 have hydrogen-induced donors.

[0045] FIG. 17 is a schematic partial cross-sectional view showing a modification of FIG. 16. In this modification, implantation is performed while changing the impurity implantation direction (arrow 13) while using the implantation mask 12. In other words, impurity implantation is performed while changing the implantation angle while using the same implantation mask 12. In the example shown in FIG. 17, the layer 5P is formed by implantation substantially perpendicular to the lower surface SF2, and the layer 10P is formed by oblique implantation to the lower surface SF2.

[0046] For the configurations other than those described above, since they are substantially the same as the configuration of the sixth embodiment described above, the same reference numerals are given to the same or corresponding elements, and the description thereof will not be repeated. Note that the third buffer layer 10 in the present embodiment may also be applied to the semiconductor device 300 of the fourth embodiment.

[0047] According to the present embodiment, two buffer layers, namely the first buffer layer 5 and the third buffer layer 10, can be formed with a single implantation mask while imparting different distributions to them. Different from the above-described sixth embodiment, in the seventh embodiment, the third buffer layer 10 is also selectively formed in the planar layout, and thereby the effective concentration of the third buffer layer 10 can be adjusted.

[0048] In the planar layout, it is preferable that the area of the distribution portion of the third buffer layer 10 is larger than the area of the distribution portion PDa of the first buffer layer 5. Thereby, the effective concentration of the third buffer layer 10 can be increased as compared with the first buffer layer 5. Therefore, it is easy to obtain a configuration in which the effective impurity concentration is increased corresponding to the direction in which the depletion layer extends from the base layer 4 toward the second buffer layer 6, and thereby the extension of the depletion layer can be gently stopped. Therefore, the effect of suppressing ringing is further enhanced. Note that the fact that the third buffer layer 10 is formed only partially in the planar layout also contributes to gently stopping the extension of the depletion layer.

[0049] In the above-described first to seventh embodiments, the case where the semiconductor device is an IGBT or a diode has been described in detail, but the semiconductor device is not limited thereto. Also, the case where the first conductivity type is n-type and the second conductivity type is p-type has been described in detail, but for a semiconductor device that also operates when these conductivity types are interchanged, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0050] Note that the respective embodiments can be freely combined, or each embodiment can be appropriately modified or omitted.

[0051] <Supplementary Note> The following are the aspects of the present disclosure summarized as supplementary notes.

[0052] (Supplementary Note 1) A first-conductivity-type drift layer (3) provided on a semiconductor substrate (SB) having a first main surface (SF1) and a second main surface (SF2) facing the first main surface (SF1) in the thickness direction; A second-conductivity-type base layer (4) provided between the first main surface (SF1) of the semiconductor substrate (SB) and the drift layer (3), having a higher impurity concentration than the drift layer (3); A first-conductivity-type first buffer layer (5) provided in the drift layer (3), having a higher impurity concentration than the drift layer (3); A first-conductivity-type second buffer layer (6) provided between the second main surface (SF2) of the semiconductor substrate (SB) and the first buffer layer (5), having a higher impurity concentration than the drift layer (3); Comprising; In the thickness direction, a separation distance (DS) is provided between the position where the first buffer layer (5) has an impurity peak concentration and the position where the second buffer layer (6) has an impurity peak concentration; By selectively forming the first buffer layer (5) in a plane layout perpendicular to the thickness direction, the position where the first buffer layer (5) has the impurity peak concentration in the thickness direction forms a distribution plane (PD) having a distribution part (PDa) and a non-distribution part (PDb) in the plane layout. The non-distribution part (PDb) has an effective width (WD) smaller than the separation distance (DS), and the effective width (WD) is twice the farthest distance from the distribution part (PDa) in the non-distribution part (PDb) of the plane layout. Semiconductor devices (100 - 102, 300).

[0053] (Supplementary Note 2) The impurity peak concentration of the first buffer layer (5) is 1.0×10 16 / cm 3The semiconductor device (100 to 102, 300) described in Supplementary Note 1, as described above.

[0054] (Supplementary Note 3) The impurity peak concentration of the first buffer layer (5) is 1.0×10 17 / cm 3 The semiconductor device (100 to 102, 300) described in Supplementary Note 1 or 2, as described above.

[0055] (Supplementary Note 4) The area occupied by the distribution portion (PDa) in the distribution plane (PD) of the impurity peak concentration of the first buffer layer (5) is 5% or more. The semiconductor device (100 to 102, 300) described in any one of Supplementary Notes 1 to 3.

[0056] (Supplementary Note 5) The area occupied by the distribution portion (PDa) in the distribution plane (PD) of the impurity peak concentration of the first buffer layer (5) is 90% or less. The semiconductor device (100 to 102, 300) described in any one of Supplementary Notes 1 to 4.

[0057] (Supplementary Note 6) The semiconductor device (101, 102) described in any one of Supplementary Notes 1 to 5, further comprising a third buffer layer (10) of the first conductivity type having an impurity concentration higher than that of the drift layer (3) between the first buffer layer (5) and the second buffer layer (6).

[0058] (Supplementary Note 7) By selectively forming the third buffer layer (10) in the planar layout, the position where the third buffer layer (10) has an impurity peak concentration in the thickness direction forms a distribution plane having a distribution portion and a non-distribution portion in the planar layout. In the planar layout, the distribution portion of the third buffer layer (10) overlaps with the non-distribution portion (PDb) of the first buffer layer (5), and the non-distribution portion of the third buffer layer (10) overlaps with the distribution portion (PDa) of the first buffer layer (5). The semiconductor device (102) described in Supplementary Note 6.

[0059] (Supplementary Note 8) In the planar layout, the area of the distribution portion of the third buffer layer (10) is larger than the area of the distribution portion (PDa) of the first buffer layer (5). The semiconductor device (102) described in Supplementary Note 7.

[0060] (Supplementary Note 9) The resistivity of the drift layer (3) between the first buffer layer (5) and the second main surface (SF2) is higher than the resistivity of the drift layer (3) between the first buffer layer (5) and the first main surface (SF1). The semiconductor device (100 - 102, 300) described in any one of Supplementary Notes 1 to 8.

[0061] (Supplementary Note 10) The first conductivity type is n-type, and the second conductivity type is p-type. The first buffer layer (5) has a hydrogen-induced donor. The semiconductor device (100 - 102, 300) described in any one of Supplementary Notes 1 to 9.

[0062] (Supplementary Note 11) The semiconductor device (100 - 102, 300) includes an insulated gate bipolar transistor, a metal-insulator-semiconductor field effect transistor, a diode, or a reverse-conducting insulated gate bipolar transistor. The semiconductor device (100 - 102, 300) described in any one of Supplementary Notes 1 to 10.

[0063] (Supplementary Note 12) The semiconductor material forming the semiconductor substrate (SB) is Si, SiC, GaN, GaAs, GaO, or diamond. The semiconductor device (100 - 102, 300) described in any one of Supplementary Notes 1 to 11.

[0064] (Supplementary Note 13) A method for manufacturing a semiconductor device, which manufactures the semiconductor device (100 - 102, 300) described in any one of Supplementary Notes 1 to 12, A step of selectively implanting impurities in the planar layout by using an implantation mask (12, 12M) from the second main surface (SF2) of the semiconductor substrate (SB) into the semiconductor substrate (SB); A step of forming the first buffer layer (5) by activating the impurities by heating; A method for manufacturing a semiconductor device (100 to 102, 300), comprising:

[0065] (Appendix 14) The method for manufacturing a semiconductor device (100 to 102, 300) according to Appendix 13, wherein the implantation mask (12, 12M) is formed using a photoresist.

Explanation of Reference Numerals

[0066] 3 Drift layer, 4 Base layer, 5 First buffer layer, 6 Second buffer layer, 10 Third buffer layer, 12, 12M Implantation mask, 15 First main electrode, 20 Second main electrode, 26 p-type anode layer (base layer), 100 to 102, 300 Semiconductor device, DS Separation distance, PD Distribution surface, PDa Distribution part, PDb Non-distribution part, SB Semiconductor substrate, SF1 Upper surface (first main surface), SF2 Lower surface (second main surface), WD Effective width.

Claims

1. a first conductivity type drift layer provided in a semiconductor substrate having a first main surface and a second main surface facing the first main surface in a thickness direction; a second conductivity type base layer provided between the first main surface of the semiconductor substrate and the drift layer, the second conductivity type base layer having a higher impurity concentration than the drift layer; a first buffer layer of the first conductivity type provided in the drift layer and having a higher impurity concentration than the drift layer; a second buffer layer of the first conductivity type provided between the second main surface of the semiconductor substrate and the first buffer layer and having an impurity concentration higher than that of the drift layer; Equipped with a separation distance is provided between a position where the first buffer layer has a peak impurity concentration and a position where the second buffer layer has a peak impurity concentration in the thickness direction; a semiconductor device, wherein the first buffer layer is selectively formed in a planar layout perpendicular to the thickness direction, so that a position at which the first buffer layer has the impurity peak concentration in the thickness direction forms a distribution surface having a distribution portion and a non-distribution portion in the planar layout, the non-distribution portion has an effective width smaller than the separation distance, and the effective width is twice the farthest distance from the distribution portion to the non-distribution portion in the planar layout.

2. The impurity peak concentration of the first buffer layer is 1.0×10 １６ / cm ３ The semiconductor device according to claim 1 .

3. The impurity peak concentration of the first buffer layer is 1.0×10 １７ / cm ３ The semiconductor device according to claim 1 or 2.

4. 3. The semiconductor device according to claim 1, wherein an area of ​​the distribution surface of the peak impurity concentration of the first buffer layer occupied by the distribution portion is 5% or more.

5. 3. The semiconductor device according to claim 1, wherein an area of ​​the distribution surface of the peak impurity concentration of the first buffer layer occupied by the distribution portion is 90% or less.

6. 3 . The semiconductor device according to claim 1 , further comprising a third buffer layer of the first conductivity type between the first buffer layer and the second buffer layer, the third buffer layer having a higher impurity concentration than the drift layer.

7. the third buffer layer is selectively formed in the planar layout, so that a position at which the third buffer layer has an impurity peak concentration in the thickness direction forms a distribution surface having a distribution portion and a non-distribution portion in the planar layout; In the planar layout, the distributed portion of the third buffer layer overlaps with the non-distributed portion of the first buffer layer, and the non-distributed portion of the third buffer layer overlaps with the distributed portion of the first buffer layer. The semiconductor device according to claim 6.

8. 8. The semiconductor device according to claim 7, wherein, in the planar layout, an area of ​​said distribution portion of said third buffer layer is larger than an area of ​​said distribution portion of said first buffer layer.

9. 3. The semiconductor device according to claim 1, wherein a resistivity of the drift layer between the first buffer layer and the second main surface is higher than a resistivity of the drift layer between the first buffer layer and the first main surface.

10. 3. The semiconductor device according to claim 1, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the first buffer layer has hydrogen-induced donors.

11. 3. The semiconductor device according to claim 1, wherein the semiconductor device comprises an insulated gate bipolar transistor, a metal-insulator-semiconductor field effect transistor, a diode, or a reverse conducting insulated gate bipolar transistor.

12. 3. The semiconductor device according to claim 1, wherein the semiconductor material constituting the semiconductor substrate is Si, SiC, GaN, GaAs, GaO or diamond.

13. A method for manufacturing the semiconductor device according to claim 1 or 2, comprising the steps of: selectively injecting impurities into the semiconductor substrate from the second main surface of the semiconductor substrate using an implantation mask in the planar layout; forming the first buffer layer by activating the impurities by heating; A manufacturing method of a semiconductor device comprising:

14. The method for manufacturing a semiconductor device according to claim 13, wherein the implantation mask is formed using a photoresist.

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