Semiconductor package and manufacturing method of the semiconductor package

Abstract

To provide a semiconductor package, and a manufacturing method of the semiconductor package.SOLUTION: A semiconductor package comprises: a first substrate; a first semiconductor chip that is mounted onto an upper surface of the first substrate; a first bump that electrically couples the first substrate and the first semiconductor chip so as to be interposed to between the first substrate and the first semiconductor chip; a first underfill film that fills a region corresponded to a center part of a space between the first substrate and the first semiconductor chip; and a first molding member that covers the upper surface and a side surface of the first semiconductor chip, and fills the region corresponded to an outline part of the space between the first substrate and the first semiconductor chip. In the space between the first substrate and the first semiconductor chip, a volume occupied by the first molding member is larger than a volume occupied by the first underfill film in the space between the first substrate and the first semiconductor chip.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package, and more particularly to a semiconductor package with improved reliability and a method for manufacturing the semiconductor package. [Background technology]

[0002] Recently, the electronic product market has seen a rapid increase in the demand for portable devices, which has led to a continuous demand for smaller and lighter electronic components mounted in those electronic products. In order to reduce the size and weight of electronic components, the semiconductor packages mounted therein are required to process high volumes of data while minimizing defects, while still becoming smaller in volume.

[0003] At this time, a molding process is performed to mold the semiconductor chip with a sealing resin such as EMC (epoxy molding compound) to prevent the semiconductor chip from being damaged by external impact, light, etc. With the trend of semiconductor packages becoming thinner and thinner, the size of the space between the semiconductor chip and the substrate is also decreasing, and therefore, problems related to voids occurring in the space are being highlighted. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a semiconductor package that minimizes voids that occur between a first semiconductor chip and a first substrate, and a method for manufacturing the semiconductor package.

[0005] Furthermore, the problems that the technical idea of ​​the present invention is intended to solve are not limited to the problems mentioned above, and other problems will be clearly understood by those of ordinary skill in the art from the following description. [Means for solving the problem]

[0006] In order to achieve the above technical objectives, the present invention provides a semiconductor package as follows.

[0007] a first semiconductor chip mounted on an upper surface of the first substrate; first bumps interposed between the first substrate and the first semiconductor chip and electrically connecting the first substrate and the first semiconductor chip; a first underfill film filling an area corresponding to a central portion of a space between the first substrate and the first semiconductor chip; and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling an area corresponding to an outer portion of the space between the first substrate and the first semiconductor chip, wherein a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill film in the space between the first substrate and the first semiconductor chip.

[0008] a first semiconductor chip mounted on an upper surface of the first substrate; first bumps interposed between the first substrate and the first semiconductor chip, electrically connecting the first substrate and the first semiconductor chip, and having a thickness of 10 μm or less in a vertical direction; a first underfill film filling a region corresponding to a center portion of a space between the first substrate and the first semiconductor chip; and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling a region corresponding to an outer portion of the space between the first substrate and the first semiconductor chip; wherein a volume of the first molding member in the space between the first substrate and the first semiconductor chip is larger than a volume of the first underfill film, and a volume of the first underfill film in the space between the first substrate and the first semiconductor chip is in a range of 5% to 50% of the space between the first substrate and the first semiconductor chip excluding a volume of the first bumps.

[0009] The semiconductor package according to the present invention includes a first substrate including wiring and an insulating layer surrounding the wiring; a first semiconductor chip mounted on an upper surface of the first substrate; a first bump interposed between the first substrate and the first semiconductor chip, electrically connecting the first substrate and the first semiconductor chip, and having a thickness of 10 μm or less along a vertical direction; a first underfill film filling an area corresponding to a center portion of a space between the first substrate and the first semiconductor chip; and a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling an area corresponding to an outer periphery of the space between the first substrate and the first semiconductor chip; and the first underfill film each contain a filler, the filler content of the first molding member is in the range of 70% to 90%, the filler content of the first underfill film is in the range of 5% to 40%, a volume of the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume of the first underfill film, and a volume of the first underfill film in the space between the first substrate and the first semiconductor chip is in the range of 5% to 50% of the space between the first substrate and the first semiconductor chip excluding the volume of the first bump.

[0010] In order to achieve the technical objectives, the present invention provides a method for manufacturing a semiconductor package as follows.

[0011] A method for manufacturing a semiconductor package according to the present invention includes the steps of: preparing a carrier substrate; attaching a first substrate onto the carrier substrate; arranging a first semiconductor chip on an upper surface of the first substrate; arranging a first underfill ball in an area adjacent to a sidewall of the first semiconductor chip on the upper surface of the first substrate to form a first structure; providing the first structure to a molding apparatus; and closing the molding apparatus to press the first molding ball against the first structure, wherein a volume of the first underfill is smaller than a volume of a first molding member filling a space between the first substrate and the first semiconductor chip. Effect of the Invention

[0012] A semiconductor package and a method for manufacturing a semiconductor package according to the technical concept of the present invention may minimize the generation of voids inside the semiconductor package and improve the thermal conductivity and compressive strength of the semiconductor package by disposing an underfill film in a region corresponding to a center portion of the space between a substrate and a semiconductor chip, and disposing a molding member in a region corresponding to an outer periphery of the space between the substrate and the semiconductor chip.

[0013] This improves the reliability of the semiconductor package, and ultimately the yield of the semiconductor package. [Brief description of the drawings]

[0014] [Figure 1A] 1 is a cross-sectional view that illustrates a schematic diagram of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 1B] 1B is a cross-sectional view taken along line X1-X1' of FIG. 1A. [Diagram 2] 1 is a cross-sectional view that illustrates a schematic diagram of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 3A] 1 is a cross-sectional view that illustrates a schematic diagram of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 3B] FIG. 3B is an enlarged view of a portion AA in FIG. 3A. [Figure 4A] 1 is a cross-sectional view that illustrates a schematic diagram of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 4B] FIG. 4B is an enlarged view of a portion BB in FIG. 4A. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The same components in the drawings are designated by the same reference numerals, and duplicated explanations thereof will be omitted.

[0016] Fig. 1A is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention, and Fig. 1B is a cross-sectional view taken along line X1-X1' of Fig. 1A.

[0017] 1A and 1B, a semiconductor package 10 may include a first substrate 100, a first semiconductor chip 200, a conductive pillar 380, a first underfill film 270, and a first molding member 390.

[0018] The first substrate 100 may include wiring 130 electrically connected to the first semiconductor chip 200, the conductive pillars 380, and the external connection terminals 160, and an insulating layer 110 surrounding the wiring 130. In an exemplary embodiment, at least one of an upper surface and a lower surface of the first substrate 100 may have a flat shape.

[0019] In the following drawings, the X-axis direction and the Y-axis direction indicate directions parallel to the flat surface of the upper or lower surface of the first substrate 100, and the X-axis direction and the Y-axis direction may be directions perpendicular to each other. The Z-axis direction may indicate a direction perpendicular to the flat surface of the upper or lower surface of the first substrate 100. In other words, the Z-axis direction is also a direction perpendicular to the XY plane.

[0020] In addition, in the following drawings, the first horizontal direction, the second horizontal direction, and the vertical direction may be understood as follows: the first horizontal direction may be understood as the X-axis direction, the second horizontal direction may be understood as the Y-axis direction, and the vertical direction may be understood as the Z-axis direction.

[0021] The wiring 130 may be formed to penetrate the insulating layer 110 from the upper surface to the lower surface of the first substrate 100, and the insulating layers 110 surrounding the wiring 130 may be stacked on top of each other in the vertical direction (Z). Here, the wiring 130 may serve as an electrical connection path penetrating the upper and lower surfaces of the first substrate 100. The first semiconductor chip 200, the conductive pillars 380, and the external connection terminals 160 may be electrically connected to each other through the wiring 130 of the first substrate 100.

[0022] In some embodiments, the first substrate 100 may include a ceramic substrate, a printed circuit board (PCB), or an organic substrate. In this case, the wiring 130 may be made of copper, nickel, stainless steel, or beryllium copper, and the insulating layer 110 may include at least one material selected from the group consisting of Frame Retardant 4 (FR-4), tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, bismaleimide triazine (BT), Thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0023] In some embodiments, the first substrate 100 may include a redistribution structure formed through a redistribution process. In this case, the wiring 130 of the first substrate 100 may be understood as a redistribution pattern, and the insulating layer 110 of the first substrate 100 may be understood as a redistribution insulating layer. Here, the wiring 130 may be a metal or a metal alloy such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), but is not limited thereto. In some embodiments, the wiring 130 may be formed by stacking a metal or a metal alloy on a seed layer including copper, titanium, titanium nitride, or titanium tungsten. Alternatively, the insulating layer 110 may be formed from a photo imageable dielectric (PID) or a photosensitive polyimide (PSPI).

[0024] The wiring 130 may include a line pattern 133 and a via pattern 131. The line pattern 133 may have a shape extending in a horizontal direction along at least one of the upper and lower surfaces of each of the multiple insulating layers 110 stacked in the vertical direction (Z). The via pattern 131 may have a shape extending through the insulating layer 110 in the vertical direction (Z). The via pattern 131 may electrically connect the line patterns 133 located at different vertical levels. In some embodiments, at least a portion of the line pattern 133 may be formed together with a portion of the via pattern 131 and may be integrated.

[0025] The first semiconductor chip 200 may be disposed on the upper surface of the first substrate 100. According to an exemplary embodiment, the first semiconductor chip 200 may include a memory chip. The memory chip may be a volatile memory chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory chip such as a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). The first semiconductor chip 200 may also include a logic chip. The logic chip may be a microprocessor such as a central processing unit (CPU), a graphic processing unit (GPU), or an application processor (AP), an analog element, or a digital signal processor. However, the first semiconductor chip 200 is not limited to a memory chip or a logic chip, and the first semiconductor chip 200 may be a chip structure including both a memory chip and a logic chip.

[0026] The first semiconductor chip 200 may be mounted on the first substrate 100 by a flip chip method via the first bumps 250. The first semiconductor chip 200 may be electrically connected to the first substrate 100 via the first bumps 250. The first bumps 250 may be in physical contact with pads formed on an upper surface of the first substrate 100 and pads formed on a lower surface of the first semiconductor chip 200, thereby electrically connecting the first substrate 100 and the first semiconductor chip 200.

[0027] According to an exemplary embodiment, the first bump 250 may be a pillar structure, a ball structure, or a solder layer. According to an exemplary embodiment, the first bump 250 may include a microbump. Here, the microbump may be understood as a bump having a critical dimension (CD) of less than 20 μm. For example, when the first bump 250 has a spherical shape, the diameter of the first bump 250 may be less than 20 μm.

[0028] A plurality of first bumps 250 may be provided. The plurality of first bumps 250 may be provided spaced apart from each other along the first horizontal direction (X). According to an exemplary embodiment, the distance from the center of a first bump 250 to the center of a first bump 250 immediately adjacent to the first bump 250 may be less than 50 μm. According to an exemplary embodiment, the distance from the center of a first bump 250 to the center of a first bump 250 immediately adjacent to the first bump 250 may be in the range of 10 μm to 50 μm.

[0029] The first substrate 100 and the first semiconductor chip 200 may be spaced apart in the vertical direction (Z) by the first bump 250. A distance (D1) between the first substrate 100 and the first semiconductor chip 200 in the vertical direction (Z) may be 10 μm or less. A thickness of the first bump 250 in the vertical direction (Z) may be 10 μm or less.

[0030] The first substrate 100 and the first semiconductor chip 200 are spaced apart from each other in the vertical direction (Z) by the first bumps 250, so that a space may be formed between the first substrate 100 and the first semiconductor chip 200.

[0031] A first underfill film 270 and a first molding member 390 may be disposed in the space between the first substrate 100 and the first semiconductor chip 200. According to an exemplary embodiment, the first underfill film 270 and the first molding member 390 may each include an epoxy resin. The first underfill film 270 and the first molding member 390 each include a filler, and the filler content of the first underfill film 270 may range from 70% to 95%, and the filler content of the first molding member 390 may range from 5% to 40%. Here, the filler content may be understood as a mass ratio.

[0032] According to an exemplary embodiment, the first underfill film 270 may be disposed to overlap a central portion of the first semiconductor chip 200 in the vertical direction (Z). The first underfill film 270 may be formed to fill a region corresponding to the central portion of the space between the first substrate 100 and the first semiconductor chip 200. In this case, the first underfill film 270 is formed only in the central portion of the space between the first substrate 100 and the first semiconductor chip 200, and is not formed in a region corresponding to an outer periphery of the space between the first substrate 100 and the first semiconductor chip 200.

[0033] According to an exemplary embodiment, the volume of the space between the first substrate 100 and the first semiconductor chip 200, excluding the volume of the first bump 250, occupied by the first underfill film 270 may range from 5% to 50%. In some embodiments, the volume of the space between the first substrate 100 and the first semiconductor chip 200, excluding the volume of the first bump 250, occupied by the first underfill film 270 may range from 10% to 30%. When the volume ratio of the first underfill film 270 to the space between the first substrate 100 and the first semiconductor chip 200 is in the range of 10% to 30%, the first underfill film 270 can fill the area in the space between the first substrate 100 and the first semiconductor chip 200 that overlaps with the central portion of the first semiconductor chip 200 in the vertical direction (Z), while not filling the area that does not overlap with the central portion of the first semiconductor chip 200 in the vertical direction (Z).

[0034] The first molding member 390 may be formed to cover the first semiconductor chip 200 and the conductive pillars 380. The first molding member 390 may cover the entire upper surface and side surfaces of the first semiconductor chip 200. The first molding member 390 may also be formed in the space between the first substrate 100 and the first semiconductor chip 200. Specifically, the first molding member 390 may be formed to fill a region corresponding to an outer periphery of the space between the first substrate 100 and the first semiconductor chip 200. That is, the first molding member 390 may be formed to fill a region of the space between the first substrate 100 and the first semiconductor chip 200 except for a portion where the first underfill film 270 is formed. The first molding member 390 disposed between the first substrate 100 and the first semiconductor chip 200 does not overlap a center portion of the first semiconductor chip 200 in the vertical direction (Z). A first molding member 390 formed between the first substrate 100 and the first semiconductor chip 200 may surround the first bumps 250 .

[0035] A plurality of first bumps 250 may be provided between the first substrate 100 and the first semiconductor chip 200, and among the plurality of first bumps 250, the first bumps 250 that overlap the central portion of the first semiconductor chip 200 in the vertical direction (Z) may be surrounded by a first underfill film 270, and the first bumps 250 that do not overlap the central portion of the first semiconductor chip 200 in the vertical direction (Z) may be surrounded by a first molding member 390.

[0036] In the space between the first substrate 100 and the first semiconductor chip 200, the volume occupied by the first molding member 390 may be larger than the volume occupied by the first underfill film 270. According to an exemplary embodiment, in the space between the first substrate 100 and the first semiconductor chip 200, the volume occupied by the first molding member 390 may be in the range of 70% to 90% of the area excluding the volume occupied by the first bumps 250. Two different types of materials may be provided in the space between the first substrate 100 and the first semiconductor chip 200, excluding the first bumps 250.

[0037] 1B, the first underfill film 270 may be formed in a central portion of the space between the first substrate 100 and the first semiconductor chip 200. When viewed from above in the vertical direction (Z), the first underfill film 270 may have a shape in which at least a portion of a frame region protrudes toward the first molding member 390. However, the shape of the first underfill film 270 when viewed from above in the vertical direction (Z) is not limited thereto, and the frame region of the first underfill film 270 may have a shape that is a circle or an ellipse when viewed from above in the vertical direction (Z).

[0038] The conductive pillar 380 may be disposed on the upper surface of the first substrate 100 and spaced apart from the first semiconductor chip 200 in the horizontal direction. The conductive pillar 380 may extend in the vertical direction (Z) through the first molding member 390. The conductive pillar 380 may be, for example, a through mold via or a conductive post. The conductive pillar 380 may include, for example, copper (Cu). According to an exemplary embodiment, a plurality of conductive pillars 380 may be provided. In this case, the plurality of conductive pillars 380 may be disposed and spaced apart from each other in the horizontal direction.

[0039] The external connection terminal 160 may be disposed on the lower surface of the first substrate 100. The external connection terminal 160 may be electrically connected to an external connection device through a pad formed on the lower surface of the first substrate 100. The external connection device may include, for example, a motherboard PCB. According to an exemplary embodiment, the external connection terminal may be formed of a solder ball. In addition, in some embodiments, the external connection terminal 160 may have a structure including a pillar and a solder. The external connection terminal 160 may include at least one of copper (Cu), silver (Ag), gold (Au), and tin (Sb).

[0040] In the semiconductor package 10 according to the technical concept of the present disclosure, a first underfill film 270 and a first molding member 390 may be provided between the first substrate 100 and the first semiconductor chip 200. In this case, the first underfill film 270 may be formed in a region corresponding to a center portion of the space between the first substrate 100 and the first semiconductor chip 200, and the first molding member 390 may be formed in a region corresponding to an outer periphery of the space between the first substrate 100 and the first semiconductor chip 200.

[0041] Generally, when the space between the first substrate 100 and the first semiconductor chip 200 is filled with the first molding member 390 by a molded under-fill process, if the distance D1 in the vertical direction (Z) between the upper surface of the first substrate 100 and the lower surface of the first semiconductor chip 200 is 10 μm or less, the first molding member 390 is not formed uniformly, and voids are formed between the first molding member 390. In addition, the voids tend to occur in large numbers in an area corresponding to the center of the space between the first substrate 100 and the first semiconductor chip 200.

[0042] However, in the semiconductor package 10 according to the technical idea of ​​the present disclosure, the first underfill film 270 is disposed in a region corresponding to a central portion where many voids are generated in the space between the first substrate 100 and the first semiconductor chip 200, and the first molding member 390 is disposed to surround the first underfill film 270, thereby minimizing the generation of the voids. That is, by disposing the first underfill film 270 and the first molding member 390 in the space between the first substrate 100 and the first semiconductor chip 200, respectively, defects such as the space between the first substrate 100 and the first semiconductor chip 200 not being filled can be minimized.

[0043] In addition, the first underfill film 270 is disposed only in the area of ​​the space between the first substrate 100 and the first semiconductor chip 200 where voids frequently occur, and a first molding member 390 containing a material having physical properties, such as thermal conductivity and compressive strength, higher than those of the first underfill film 270 is disposed in the remaining area of ​​the space between the first substrate 100 and the first semiconductor chip 200, thereby improving the reliability of the semiconductor package 10.

[0044] Fig. 2 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. In the following, overlapping content between the semiconductor package 10 described with reference to Fig. 1 and the semiconductor package 11 in Fig. 2 will be omitted, and differences will be mainly described.

[0045] Referring to FIG. 2, the semiconductor package 11 may include a first substrate 100, a first semiconductor chip 200, a conductive pillar 380, a first underfill film 270, a first molding member 390, a second substrate 300, a second semiconductor chip 400, a second underfill film 470, and a second molding member 490.

[0046] The first substrate 100 may include wiring 130 electrically connected to the first semiconductor chip 200 , the conductive pillars 380 and the external connection terminals 160 , and an insulating layer 110 surrounding the wiring 130 .

[0047] The first semiconductor chip 200 may be disposed on the upper surface of the first substrate 100. The first semiconductor chip 200 may be mounted on the upper surface of the first substrate 100 via the first bumps 250. The conductive pillars 380 may be disposed on the upper surface of the first substrate 100 to be horizontally spaced apart from the first semiconductor chip 200. The conductive pillars 380 may be vertical connection conductors for electrically connecting the first substrate 100 and the second substrate 300.

[0048] A first underfill film 270 may be disposed between the first substrate 100 and the first semiconductor chip 200. The first underfill film 270 may be disposed in a region corresponding to a central portion of the space between the first substrate 100 and the first semiconductor chip 200. The first underfill film 270 may be formed to surround the first bump 250.

[0049] The first molding member 390 may be formed between the first substrate 100 and the second substrate 300 to surround the first semiconductor chip 200 and the conductive pillars 380. According to an exemplary embodiment, the first molding member 390 may be formed to fill an area corresponding to an outer periphery of the space between the first substrate 100 and the first semiconductor chip 200. According to an exemplary embodiment, the volume of the first molding member 390 in the space between the first substrate 100 and the first semiconductor chip 200 may be larger than the volume of the first underfill film 270 in the space between the first substrate 100 and the first semiconductor chip 200.

[0050] The second substrate 300 may be disposed on an upper surface of the first molding member 390 and may be a substrate on which the second semiconductor chip 400 is mounted. The second substrate 300 may be electrically connected to the conductive pillars 380 and the second semiconductor chip 400. The second substrate 300 may include a wiring 330 and an insulating layer 310 surrounding the wiring 330.

[0051] The wiring 330 may include a line pattern 333 and a via pattern 331. The line pattern 333 may have a shape extending in a horizontal direction along at least one of the upper and lower surfaces of each of the insulating layers 310 stacked in the vertical direction (Z). The via pattern 331 may have a shape extending through the insulating layer 310 in the vertical direction (Z). The via pattern 331 may electrically connect the line patterns 333 located at different vertical levels. In some embodiments, at least a portion of the line pattern 333 may be formed together with a portion of the via pattern 331 to be integrated.

[0052] In some embodiments, the second substrate 300 may include a ceramic substrate, a PCB, an organic substrate, etc. In some embodiments, the second substrate 300 may include a redistribution structure formed through a redistribution process.

[0053] The second semiconductor chip 400 may be disposed on an upper surface of the second substrate 300. According to an example embodiment, the second semiconductor chip 400 may include at least one of a memory chip and a logic chip.

[0054] The second semiconductor chip 400 may be mounted on the second substrate 300 by a flip chip method via the second bumps 450. The second semiconductor chip 400 may be electrically connected to the second substrate 300 via the second bumps 450. The second bumps 450 may be in physical contact with pads formed on an upper surface of the second substrate 300 and pads formed on a lower surface of the second semiconductor chip 400, and may electrically connect the second substrate 300 and the second semiconductor chip 400.

[0055] The second substrate 300 and the second semiconductor chip 400 may be spaced apart from each other in the vertical direction (Z) by the second bumps 450. Since the second substrate 300 and the second semiconductor chip 400 are spaced apart from each other in the vertical direction (Z) by the second bumps 450, a space may be formed between the second substrate 300 and the second semiconductor chip 400.

[0056] A second underfill film 470 and a second molding member 490 may be disposed in the space between the second substrate 300 and the second semiconductor chip 400. According to an exemplary embodiment, the second underfill film 470 and the second molding member 490 may each include an epoxy resin. The second underfill film 470 and the second molding member 490 each include a filler, and the filler content of the second underfill film 470 may range from 70% to 95%, and the filler content of the second molding member 490 may range from 5% to 40%. Here, the filler content may be understood as a mass ratio.

[0057] According to an exemplary embodiment, the second underfill film 470 may be disposed to overlap a central portion of the second semiconductor chip 400 in the vertical direction (Z). The second underfill film 470 may be formed to fill a region corresponding to the central portion of the space between the second substrate 300 and the second semiconductor chip 400. In this case, the second underfill film 470 is formed only in the central portion of the space between the second substrate 300 and the second semiconductor chip 400, and is not formed in a region corresponding to an outer periphery of the space between the second substrate 300 and the second semiconductor chip 400.

[0058] According to an exemplary embodiment, the volume occupied by the second underfill film 470 in the space between the second substrate 300 and the second semiconductor chip 400, excluding the volume occupied by the second bump 450, may be in the range of 5% to 50%.

[0059] The second molding member 490 may be formed on the upper surface of the second substrate 300 to cover the second semiconductor chip 400. The second molding member 490 may cover the entire upper surface and side surfaces of the second semiconductor chip 400. The second molding member 490 may also be formed in the space between the second substrate 300 and the second semiconductor chip 400. Specifically, the second molding member 490 may be formed while filling a region corresponding to an outer periphery in the space between the second substrate 300 and the second semiconductor chip 400. That is, the second molding member 490 may be formed to fill a region in the space between the second substrate 300 and the second semiconductor chip 400 except for a portion where the second underfill film 470 is formed. The second molding member 490 disposed between the second substrate 300 and the second semiconductor chip 400 does not overlap a center portion of the second semiconductor chip 400 in the vertical direction (Z). A second molding member 490 formed between the second substrate 300 and the second semiconductor chip 400 may surround the second bumps 450 .

[0060] A plurality of second bumps 450 may be provided between the second substrate 300 and the second semiconductor chip 400. Among the plurality of second bumps 450, the second bumps 450 that overlap the central portion of the second semiconductor chip 400 in the vertical direction (Z) may be surrounded by a second underfill film 470, and the second bumps 450 that do not overlap the central portion of the second semiconductor chip 400 in the vertical direction (Z) may be surrounded by a second molding member 490.

[0061] In the space between the second substrate 300 and the second semiconductor chip 400, the volume occupied by the second molding member 490 may be larger than the volume occupied by the second underfill film 470. According to an exemplary embodiment, in the space between the second substrate 300 and the second semiconductor chip 400, the volume occupied by the second molding member 490 may be in the range of 70% to 90% of the area excluding the volume occupied by the second bumps 450. Two different materials may be provided in the space between the second substrate 300 and the second semiconductor chip 400, excluding the second bumps 450.

[0062] When viewed from above in the vertical direction (Z), the second underfill film 470 may have a shape in which a portion of the frame region protrudes toward the second molding member 490. However, the shape of the second underfill film 470 when viewed from above in the vertical direction (Z) is not limited thereto, and the frame region of the second underfill film 470 may also have a shape that is circular or elliptical when viewed from above in the vertical direction (Z).

[0063] In the semiconductor package 11 according to the technical concept of the present disclosure, a first underfill film 270 and a first molding member 390 may be provided between the first substrate 100 and the first semiconductor chip 200, and a second underfill film 470 and a second molding member 490 may be provided between the second substrate 300 and the second semiconductor chip 400. As a result, voids generated inside the semiconductor package 11 may be minimized, and the reliability of the semiconductor package 11 may be improved.

[0064] Fig. 3A is a cross-sectional view showing a semiconductor package according to an exemplary embodiment of the present invention. Fig. 3B is an enlarged view of a portion AA in Fig. 3A. In the following, the overlapping contents between the semiconductor package 10 in Fig. 1 and the semiconductor package 20 in Figs. 3A and 3B will be omitted, and differences will be mainly described.

[0065] 3A and 3B, the semiconductor package 20 may include a first substrate 100, an interposer substrate 150, a first semiconductor chip 201, a second semiconductor chip 400, an underfill material layer 170, a first underfill film 270, a second underfill film 470, and a first molding member 390.

[0066] The first substrate 100 is substantially the same as or similar to that described with reference to FIG. 1, and therefore a description thereof will be omitted.

[0067] The interposer substrate 150 may be disposed on the upper surface of the first substrate 100. The interposer substrate 150 may be formed of silicon and may electrically connect the first semiconductor chip 201 and the second semiconductor chip 400 to each other. According to an exemplary embodiment, the interposer substrate 150 may be electrically connected to the first substrate 100 through the bumps 171. An underfill material layer 170 may be disposed between the first substrate 100 and the interposer substrate 150, surrounding the bumps 171. The underfill material layer 170 may be, for example, an epoxy resin formed by a capillary under-fill method. However, in some embodiments, the first molding member 390 may be directly filled into the gap between the first substrate 100 and the interposer substrate 150 through a mold under-fill process. In that case, the underfill material layer 170 may be omitted.

[0068] The interposer substrate 150 may include a wiring layer 151 and a body layer 155. The wiring layer 151 may be located on an upper surface of the body layer 155. The wiring layer 151 may include a wiring pattern 153. The wiring pattern 153 may electrically connect the first semiconductor chip 201 and the second semiconductor chip 400 to each other, or may electrically connect between the first semiconductor chip 201 and a through via 157 and between the second semiconductor chip 400 and the through via 157.

[0069] A through electrode 157 may be formed inside the body layer 155. The through electrode 157 may penetrate the body layer 155 in a vertical direction (Z). According to an exemplary embodiment, the through electrode 157 may include a through silicon via (TSV). The through electrode 157 may be electrically connected to the bump 171 via a pad formed on the lower surface of the body layer 155.

[0070] The first semiconductor chip 201 and the second semiconductor chip 400 may each be disposed on the upper surface of the interposer substrate 150. The first semiconductor chip 201 may be mounted on the upper surface of the interposer substrate 150 via the first bumps 250, and the second semiconductor chip 400 may be mounted on the upper surface of the interposer substrate 150 via the second bumps 450.

[0071] A first underfill film 270 and a first molding member 390 may be arranged between the interposer substrate 150 and the first semiconductor chip 201, and a second underfill film 470 and a first molding member 390 may be arranged between the interposer substrate 150 and the second semiconductor chip 400.

[0072] The first underfill film 270 may be disposed to overlap a central portion of the first semiconductor chip 201 in the vertical direction (Z). The first underfill film 270 may be formed to fill a region corresponding to a central portion of the space between the interposer substrate 150 and the first semiconductor chip 201. In this case, the first underfill film 270 is formed only in the central portion of the space between the interposer substrate 150 and the first semiconductor chip 201, and is not formed in a region corresponding to an outer periphery of the space between the interposer substrate 150 and the first semiconductor chip 201.

[0073] The second underfill film 470 may be disposed to overlap a central portion of the second semiconductor chip 400 in the vertical direction (Z). The second underfill film 470 may be formed to fill a region corresponding to a central portion of the space between the interposer substrate 150 and the second semiconductor chip 400. In this case, the second underfill film 470 is formed only in a central portion of the space between the interposer substrate 150 and the second semiconductor chip 400, and is not formed in a region corresponding to an outer periphery of the space between the interposer substrate 150 and the second semiconductor chip 400.

[0074] The first molding member 390 may cover the first semiconductor chip 201, the second semiconductor chip 400, and the interposer substrate 150. The first molding member 390 may fill the space between the interposer substrate 150 and the first semiconductor chip 201, and the space between the interposer substrate 150 and the second semiconductor chip 400. Specifically, the first molding member 390 may be formed while filling an area corresponding to an outer periphery in each of the space between the interposer substrate 150 and the first semiconductor chip 201 and the space between the interposer substrate 150 and the second semiconductor chip 400. That is, the first molding member 390 may be formed to fill an area in the space between the interposer substrate 150 and the first semiconductor chip 201 except for an area where the first underfill film 270 is formed, and to fill an area in the space between the interposer substrate 150 and the second semiconductor chip 400 except for an area where the second underfill film 470 is formed. The first molding member 390 arranged between the interposer substrate 150 and the first semiconductor chip 201 does not overlap the central portion of the first semiconductor chip 201 in the vertical direction (Z), and the first molding member 390 arranged between the interposer substrate 150 and the second semiconductor chip 400 does not overlap the central portion of the second semiconductor chip 400 in the vertical direction (Z).

[0075] According to an example embodiment, the volume of the space between the interposer substrate 150 and the first semiconductor chip 201 occupied by the first molding member 390 may be larger than the volume of the first underfill film 270. Also, the volume of the space between the interposer substrate 150 and the second semiconductor chip 400 occupied by the first molding member 390 may be larger than the volume of the second underfill film 470.

[0076] According to an exemplary embodiment, the first semiconductor chip 201 may include a plurality of semiconductor chips stacked in a vertical direction (Z). Here, the first semiconductor chip 201 may be understood as a chip stack structure. The semiconductor chips included in the first semiconductor chip 201 may be high bandwidth memory (HBM) DRAM (dynamic random access memory) chips, and may be semiconductor chips used in an HBM package. According to an exemplary embodiment, the first semiconductor chip 201 may include a base chip 213 and at least one HBM chip 215 stacked in a vertical direction (Z) on the base chip 213. The base chip 213 may be located at the bottom of the first semiconductor chip 201. Each of the base chip 213 and the HBM chip 215 may include a through electrode 220 therein. Note that the top layer HBM chip 211 located at the top of the HBM chip 215 may not include the through electrode 220.

[0077] According to an exemplary embodiment, the base chip 213 may include logic elements. Thus, the base chip 213 is also a logic chip. Such a base chip 213 is disposed under the HBM chip 215, and may integrate and transmit signals of the HBM chip 215 to the outside, and may transmit signals and power from the outside to the HBM chip 215. Thus, the base chip 213 may be referred to as a buffer chip or a control chip. The HBM chip 215 may be referred to as a memory chip or a core chip.

[0078] The HBM chip 215 may be stacked on the base chip 213 via pad-to-pad bonding, bonding using a bonding material, or bonding using an anisotropic conductive film (ACF). According to an exemplary embodiment, the HBM chip 215 may be stacked in a flip-chip manner via the third bumps 245. The third bumps 245 may include micro-bumps. An underfill material layer 260 may be formed between the base chip 213 and the HBM chip 215 located at the bottom, and between the HBM chips 215. The underfill material layer 260 may fix the third bumps 245, the base chip 213, and the HBM chip 215.

[0079] The through electrodes 220 formed in the base chip 213 and the HBM chip 215 may be electrically connected to the third bumps 245. The through electrodes 220 may extend in a vertical direction (Z). The through electrodes 220 may have a tapered shape in which the horizontal width becomes narrower as the vertical level decreases.

[0080] In the semiconductor package 20 according to the technical concept of the present disclosure, a first underfill film 270 and a first molding member 390 may be disposed in the space between the interposer substrate 150 and the first semiconductor chip 201, and a second underfill film 470 and a first molding member 390 may be disposed in the space between the interposer substrate 150 and the second semiconductor chip 400. As a result, voids generated in the semiconductor package 20 may be minimized, and the reliability of the semiconductor package 20 may be improved.

[0081] Fig. 4A is a schematic cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention, and Fig. 4B is an enlarged view of a portion BB in Fig. 4A.

[0082] In the following, overlapping content between the semiconductor package 10 described with reference to FIG. 1 and the semiconductor package 30 of FIGS. 4A and 4B will be omitted, and differences will be mainly described.

[0083] 4A and 4B, the semiconductor package 30 may include a first substrate 100, a first semiconductor chip 202, a second semiconductor chip 402, a first underfill film 270, and a first molding member 390.

[0084] The first substrate 100 is substantially the same as or similar to that described with reference to FIG. 1, and therefore a detailed description thereof will be omitted.

[0085] The first semiconductor chip 202 may be disposed on the upper surface of the first substrate 100 via the first bumps 250. A first underfill film 270 and a first molding member 390 may be disposed in the space between the first substrate 100 and the first semiconductor chip 202. The first underfill film 270 may be disposed to overlap a central portion of the first semiconductor chip 202 in the vertical direction (Z).

[0086] The first underfill film 270 may be formed to fill a region corresponding to a central portion of the space between the first substrate 100 and the first semiconductor chip 202. In this case, the first underfill film 270 is formed only in the central portion of the space between the first substrate 100 and the first semiconductor chip 202, and is not formed in a region corresponding to an outer periphery of the space between the first substrate 100 and the first semiconductor chip 202.

[0087] The first molding member 390 may be formed to cover the first semiconductor chip 202 and the second semiconductor chip 402. In this case, the first molding member 390 may also be formed in the space between the first substrate 100 and the first semiconductor chip 202. Specifically, the first molding member 390 may be formed to fill an area corresponding to an outer periphery of the space between the first substrate 100 and the first semiconductor chip 202. That is, the first molding member 390 may be formed to fill an area of ​​the space between the first substrate 100 and the first semiconductor chip 202 except for an area where the first underfill film 270 is formed. The first molding member 390 disposed between the first substrate 100 and the first semiconductor chip 202 does not overlap the center of the first semiconductor chip 202 in the vertical direction (Z). The first molding member 390 formed between the first substrate 100 and the first semiconductor chip 202 may surround the first bump 250.

[0088] The second semiconductor chip 402 may be mounted on an upper surface of the first semiconductor chip 202. The second semiconductor chip 402 may be electrically connected to the first semiconductor chip 202. According to an exemplary embodiment, each of the first semiconductor chip 202 and the second semiconductor chip 402 may be a logic chip or a memory chip. For example, the first semiconductor chip 202 and the second semiconductor chip 402 may be the same type of memory chip, or one of the first semiconductor chip 202 and the second semiconductor chip 402 may be a memory chip and the other may be a logic chip. In some embodiments, at least one of the first semiconductor chip 202 and the second semiconductor chip 402 may have a chiplet structure including a plurality of chiplets.

[0089] The adhesive layer 370 may be configured to adhere the first semiconductor chip 202 and the second semiconductor chip 402. The adhesive layer 370 may be located between the first semiconductor chip 202 and the second semiconductor chip 402. According to an example embodiment, the adhesive layer 370 may include a non-conductive film (NCF) and a die attach film (DAF).

[0090] The first semiconductor chip 202 may include a first semiconductor substrate 234 , a first semiconductor device layer 231 , a first bump pad 233 and a second bump pad 236 .

[0091] The first semiconductor substrate 234 may have opposing upper and lower surfaces. The upper surface may face the second semiconductor chip 402, and the lower surface may face the first substrate 100. The upper surface may be referred to as a non-active surface, and the lower surface may be referred to as an active surface.

[0092] The first semiconductor substrate 234 may include silicon (Si), for example, crystalline silicon, polycrystalline silicon, or amorphous silicon. Alternatively, the first semiconductor substrate 234 may include a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first semiconductor substrate 234 may have a silicon on insulator (SOI) structure. For example, the first semiconductor substrate 234 may include a buried oxide layer (BOX layer). The first semiconductor substrate 234 may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities. The first semiconductor substrate 234 may also have various isolation structures such as a shallow trench isolation (STI) structure.

[0093] The first semiconductor device layer 231 may include a first wiring pattern 232 electrically connected to a plurality of semiconductor devices formed on the first semiconductor substrate 234. The first wiring pattern 232 may include a metal wiring layer and a via plug. For example, the first wiring pattern 232 may have a multi-layer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

[0094] According to an exemplary embodiment, the first semiconductor device layer 231 may be formed on a lower surface, which is an active surface, of the first semiconductor substrate 234. According to an exemplary embodiment, the first semiconductor device layer 231 may be located below the first semiconductor substrate 234. The first semiconductor substrate 234 may be separated from the first substrate 100 in the vertical direction (Z) with the first semiconductor device layer 231 sandwiched therebetween. The first semiconductor chip 202 may include a through electrode 235 that penetrates at least a portion of the first semiconductor device layer 231 and the first semiconductor substrate 234.

[0095] The first bump pad 233 may be disposed on a lower surface of the first semiconductor device layer 231 and may be electrically connected to a first wiring pattern 232 inside the first semiconductor device layer 231. The first bump pad 233 may be electrically connected to a through electrode 235 via the first wiring pattern 232.

[0096] The through electrode 235 may penetrate a portion of the first semiconductor substrate 234 and the first semiconductor device layer 231. The through electrode 235 may extend in a vertical direction (Z) from the first semiconductor device layer 231 toward the upper surface of the first semiconductor substrate 234 and may be electrically connected to a first wiring pattern 232 provided in the first semiconductor device layer 231. Thus, the first bump pad 233 may be electrically connected to the through electrode 235 through the first wiring pattern 232. The through electrode 235 may have a tapered shape in which the horizontal width decreases or increases as the level in the vertical direction increases. At least a portion of the through electrode 235 may be pillar-shaped. The through electrode 235 may be a silicon through electrode.

[0097] The second bump pad 236 may be formed on an upper surface of the first semiconductor substrate 234, i.e., an inactive surface of the first semiconductor substrate 234. The second bump pad 236 may be made of substantially the same material as the first bump pad 233. Although not shown, according to an exemplary embodiment, a passivation layer may be formed on the upper surface of the first semiconductor substrate 234 to surround a portion of a side surface of the second bump pad 236.

[0098] The first bumps 250 may be disposed to contact the first bump pads 233. The first semiconductor chip 202 may receive at least one of a control signal, a power signal, and a ground signal for operating the first semiconductor chip 202 from the outside, a data signal to be stored in the first semiconductor chip 202 from the outside, or data stored in the first semiconductor chip 202 may be provided to the outside through the first bumps 250.

[0099] The second semiconductor chip 402 may include a second semiconductor substrate 434, a second semiconductor device layer 431, and a third bump pad 433. The second semiconductor chip 402 may have the same or similar features as the first semiconductor chip 202, so the following description will focus on the differences from the first semiconductor chip 202.

[0100] The second semiconductor substrate 434 may have opposing bottom and top surfaces. The bottom surface faces the first semiconductor chip 202 and the top surface is the surface opposite the bottom surface. The top surface may be referred to as a non-active surface and the bottom surface may be referred to as an active surface.

[0101] The second semiconductor device layer 431 may include a second wiring pattern 432 electrically connected to a plurality of semiconductor devices formed on the second semiconductor substrate 434. The second wiring pattern 432 may include a metal wiring layer and a via plug. For example, the second wiring pattern 432 may have a multi-layer structure in which two or more metal wiring layers or two or more via plugs are alternately stacked.

[0102] According to an example embodiment, the second semiconductor device layer 431 may be formed on a lower surface, which is an active surface, of the second semiconductor substrate 434. The second semiconductor device layer 431 may be located below the second semiconductor substrate 434. The second semiconductor substrate 434 may be separated from the first semiconductor chip 202 in the vertical direction (Z) with the second semiconductor device layer 431 sandwiched therebetween.

[0103] The third bump pad 433 may be disposed on the lower surface of the second semiconductor device layer 431 and may be electrically connected to the second wiring pattern 432 inside the second semiconductor device layer 431 .

[0104] The adhesive layer 370 may be located between the first semiconductor chip 202 and the second semiconductor chip 402. The adhesive layer 370 may secure the second semiconductor chip 402 onto the first semiconductor chip 202.

[0105] The fourth bump 371 may be disposed to contact the second bump pad 236 and the third bump pad 433. The fourth bump 371 may electrically connect the first semiconductor chip 202 and the second semiconductor chip 402. The second semiconductor chip 402 may be electrically connected to the first semiconductor chip 202 through the fourth bump 371 interposed between the first semiconductor chip 202 and the second semiconductor chip 402. The second semiconductor chip 402 may receive at least one of a control signal, a power signal, and a ground signal for operating the second semiconductor chip 402, a data signal to be stored in the second semiconductor chip 402, or provide data stored in the second semiconductor chip 402 to the outside through the fourth bump 371.

[0106] In the semiconductor package 30 according to the technical concept of the present disclosure, a first underfill film 270 and a first molding member 390 are disposed between the first substrate 100 and the first semiconductor chip 202, thereby minimizing voids that occur in the semiconductor package 30 and improving the reliability of the semiconductor package 30.

[0107] 5 to 12 are cross-sectional views each showing a schematic diagram of a method for manufacturing a semiconductor package according to an exemplary embodiment of the present invention. In the following, the same content as that described with reference to FIG. 1 will be omitted, and differences will be mainly described.

[0108] 5 and 6, a first substrate 100 is disposed on a carrier substrate 800. The first substrate 100 is substantially the same as or similar to that described with reference to FIG. 1, and therefore detailed description thereof will be omitted. According to an exemplary embodiment, the first substrate 100 may be formed without a gap on the carrier substrate 800. That is, the footprint of the first substrate 100 may be substantially the same as the footprint of the carrier substrate 800.

[0109] 7, a first semiconductor chip 200 and a conductive pillar 380 are disposed on a first substrate 100. A plurality of first semiconductor chips 200 and conductive pillars 380 may be disposed on the first substrate 100. According to an exemplary embodiment, the conductive pillars 380 may be formed by filling a photoresist opening formed by a photoresist coating, exposure process, and etching process with copper or the like. The first semiconductor chip 200 may be mounted on the first substrate 100 via the first bumps 250 in a flip chip manner.

[0110] Referring to FIG. 8, a first underfill ball 270-B is dispensed on the first substrate 100 to form a first structure 1000. The first underfill ball 270-B may include a material in a state before epoxy resin containing a filler is cured. The first underfill ball 270-B may be dispensed on the upper surface of the first substrate 100 and may not contact the conductive pillar 380. According to an exemplary embodiment, the first underfill ball 270-B may be located between the first semiconductor chip 200 and the conductive pillar 380. In some embodiments, at least a portion of the first underfill ball 270-B may overlap the first semiconductor chip 200 in the vertical direction (Z). That is, at least a portion of the first underfill ball 270-B may be located between the first substrate 100 and the first semiconductor chip 200.

[0111] 9, the first structure 1000 of FIG. 8 is provided to a molding apparatus 900. The molding apparatus 900 may include an upper mold 910 and a lower mold 930. According to an exemplary embodiment, the first structure 1000 may be provided to the upper mold 910 in an upside-down state along the vertical direction (Z). A first molding ball 390-B may be provided on the lower mold 930. The first molding ball 390-B may include a material in a pre-cured state, such as an epoxy resin containing a filler.

[0112] The upper mold 910 and the lower mold 930 may be provided in an open state. That is, the upper mold 910 and the lower mold 930 may be provided in a state spaced apart from each other along the vertical direction (Z). An empty space may be formed between the upper mold 910 and the lower mold 930. According to an exemplary embodiment, at least one of the upper mold 910 and the lower mold 930 may move along the vertical direction (Z).

[0113] 10, molding apparatus 900 is partially closed and first molding ball 390-B is brought into contact with first structure 1000 of FIG.

[0114] The first molding ball 390-B may partially cover the first structure 1001. In addition, the first underfill ball 270-B formed adjacent to the first semiconductor chip 200 may be moved into the space between the first substrate 100 and the first semiconductor chip 200 due to the pressure applied by the first molding ball 390-B to the first structure 1001. That is, the first underfill ball 270-B may be moved toward the center of the first semiconductor chip 200.

[0115] 11, the molding apparatus 900 is completely closed so that the first molding ball 390-B completely covers the first structure 1001, thereby forming the first structure 1002. The first molding ball 390-B may completely cover the first structure 1002. In addition, the first underfill ball 270-B may move to a region overlapping the center portion of the first semiconductor chip 200 in the vertical direction (Z) due to the pressure applied by the first molding ball 390-B to the first structure 1001. That is, the first underfill ball 270-B may move to a region corresponding to the center portion in the space between the first substrate 100 and the first semiconductor chip 200.

[0116] 12, after removing the first structure 1002 of FIG. 11 from the molding apparatus 900, the first underfill ball 270-B and the first molding ball 390-B of the first structure 1002 are hardened, and a grinding process is performed to provide the semiconductor package 10.

[0117] As described above, the exemplary embodiment has been disclosed by the drawings and the specification. In this specification, specific terms are used to describe the present embodiment, but they are used only for the purpose of describing the technical idea of ​​the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and other equivalent embodiments are possible. Therefore, the true technical scope of protection of the present disclosure is defined by the technical idea of ​​the claims. [Explanation of symbols]

[0118] 10,11,20,30 Semiconductor packages 100 First substrate 110 Insulating layer 130 Wiring 200 First semiconductor chip 250 1st Bump 270 First underfill film 300 Second board 380 Conductive Pillar 390 First molding member 400 Second semiconductor chip 450 2nd Bump 470 Second underfill film 490 Second molding member 800 Carrier Board 900 Molding Equipment 910 Upper mold 930 Lower mold

Claims

1. A first substrate; a first semiconductor chip mounted on an upper surface of the first substrate; a first bump interposed between the first substrate and the first semiconductor chip and electrically connecting the first substrate and the first semiconductor chip; a first underfill film filling a region corresponding to a center portion of a space between the first substrate and the first semiconductor chip; a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling an area corresponding to an outer periphery of a space between the first substrate and the first semiconductor chip, A semiconductor package, characterized in that a volume occupied by the first molding member in the space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill film in the space between the first substrate and the first semiconductor chip.

2. 2. The semiconductor package of claim 1, wherein a vertical distance between an upper surface of the first substrate and a lower surface of the first semiconductor chip is less than 10 [mu]m.

3. the first bump includes a microbump; the critical dimension of the first bump is less than 20 μm; 2. The semiconductor package of claim 1, wherein the distance from the center of the first bump to the center of the first bump immediately adjacent to the first bump is less than 50 [mu]m.

4. each of the first molding member and the first underfill film includes a filler; the filler content of the first molding member is in the range of 70% to 90%; 2. The semiconductor package of claim 1, wherein the first underfill layer has a filler content in the range of 5% to 40%.

5. the first underfill film vertically overlaps a central portion of the first semiconductor chip; The semiconductor package of claim 1 , wherein the first molding member surrounds the first underfill film.

6. a conductive pillar disposed on an upper surface of the first substrate and spaced apart from the first semiconductor chip in a horizontal direction; a second substrate disposed on an upper surface of the first molding member; a second semiconductor chip mounted on an upper surface of the second substrate; a second bump interposed between the second substrate and the second semiconductor chip; a second underfill film filling a region corresponding to a center portion of a space between the second substrate and the second semiconductor chip; 2. The semiconductor package of claim 1, further comprising a second molding member filling an area corresponding to an outer periphery of a space between the second substrate and the second semiconductor chip.

7. The semiconductor package of claim 1 , wherein the first underfill film has at least a portion of a frame portion protruding toward the first molding member when viewed vertically from above.

8. an interposer substrate is disposed on an upper surface of the first substrate, a first semiconductor chip and a second semiconductor chip are mounted on the upper surface of the interposer substrate, a first underfill film and a first molding member are disposed between the interposer substrate and the first semiconductor chip, and a second underfill film and a second molding member are disposed between the interposer substrate and the second semiconductor chip; 2. The semiconductor package of claim 1, wherein the first underfill film vertically overlaps a central portion of the first semiconductor chip, and the second underfill film vertically overlaps a central portion of the second semiconductor chip.

9. a second semiconductor chip disposed on an upper portion of the first semiconductor chip, The semiconductor package of claim 1 , wherein the first semiconductor chip includes a first semiconductor substrate and a through electrode that vertically passes through the first semiconductor substrate.

10. 2. The semiconductor package of claim 1, wherein a volume occupied by the first underfill film in the space between the first substrate and the first semiconductor chip is in the range of 5% to 50% of a volume of the space between the first substrate and the first semiconductor chip excluding a volume of the first bump.

11. A first substrate; a first semiconductor chip mounted on an upper surface of the first substrate; a first bump interposed between the first substrate and the first semiconductor chip, electrically connecting the first substrate and the first semiconductor chip, the first bump having a thickness of 10 μm or less along a vertical direction; a first underfill film filling a region corresponding to a center portion of a space between the first substrate and the first semiconductor chip; a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling an area corresponding to an outer periphery of a space between the first substrate and the first semiconductor chip, a volume occupied by the first molding member in a space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill film; A semiconductor package characterized in that a volume occupied by the first underfill film in the space between the first substrate and the first semiconductor chip is in the range of 5% to 50% of the space between the first substrate and the first semiconductor chip excluding the volume of the first bump.

12. a conductive pillar disposed on an upper surface of the first substrate and spaced apart from the first semiconductor chip in a horizontal direction; a second substrate disposed on an upper surface of the first molding member; a second semiconductor chip mounted on an upper surface of the second substrate; a second bump interposed between the second substrate and the second semiconductor chip; a second underfill film filling a region corresponding to a center portion of a space between the second substrate and the second semiconductor chip; a second molding member filling an area corresponding to an outer periphery of a space between the second substrate and the second semiconductor chip, 12. The semiconductor package of claim 11, wherein a vertical distance between an upper surface of the second substrate and a lower surface of the second semiconductor chip is less than 10 [mu]m.

13. The semiconductor package of claim 11 , wherein at least a portion of a frame of the first underfill film protrudes toward the first molding member when viewed vertically from above.

14. an interposer substrate is disposed on an upper surface of the first substrate, a first semiconductor chip and a second semiconductor chip are mounted on the upper surface of the interposer substrate, a first underfill film and a first molding member are disposed between the interposer substrate and the first semiconductor chip, and a second underfill film and a second molding member are disposed between the interposer substrate and the second semiconductor chip; the second semiconductor chip includes a base chip and a high bandwidth memory (HBM) chip, the HBM chip being mounted on the base chip; 12. The semiconductor package of claim 11, wherein the first underfill film vertically overlaps a central portion of the first semiconductor chip, and the second underfill film vertically overlaps a central portion of the second semiconductor chip.

15. a second semiconductor chip disposed on an upper portion of the first semiconductor chip, the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer, and a through electrode that vertically passes through the first semiconductor substrate; 12. The semiconductor package of claim 11, wherein the second semiconductor chip includes a second semiconductor substrate and a second semiconductor device layer, and the first semiconductor chip is disposed such that the first semiconductor substrate faces the second semiconductor chip.

16. each of the first molding member and the first underfill film includes a filler; the filler content of the first molding member is in the range of 70% to 90%; 12. The semiconductor package of claim 11, wherein the filler content of the first underfill layer is in the range of 5% to 40%.

17. The semiconductor package of claim 11 , wherein the footprint of the first substrate is larger than the footprint of the first semiconductor chip.

18. A first substrate including a wiring and an insulating layer surrounding the wiring; a first semiconductor chip mounted on an upper surface of the first substrate; a first bump interposed between the first substrate and the first semiconductor chip, electrically connecting the first substrate and the first semiconductor chip, the first bump having a thickness of 10 μm or less along a vertical direction; a first underfill film filling a region corresponding to a center portion of a space between the first substrate and the first semiconductor chip; a first molding member covering an upper surface and a side surface of the first semiconductor chip and filling an area corresponding to an outer periphery of a space between the first substrate and the first semiconductor chip, each of the first molding member and the first underfill film includes a filler, the filler content of the first molding member being in a range of 70% to 90% and the filler content of the first underfill film being in a range of 5% to 40%; a volume occupied by the first molding member in a space between the first substrate and the first semiconductor chip is greater than a volume occupied by the first underfill film; A semiconductor package characterized in that the volume occupied by the first underfill film in the space between the first substrate and the first semiconductor chip is in the range of 5% to 50% of the space between the first substrate and the first semiconductor chip excluding the volume of the first bump.

19. a conductive pillar disposed on an upper surface of the first substrate and spaced apart from the first semiconductor chip in a horizontal direction; a second substrate disposed on an upper surface of the first molding member; a second semiconductor chip mounted on an upper surface of the second substrate; a second bump interposed between the second substrate and the second semiconductor chip; a second underfill film filling a region corresponding to a center portion of a space between the second substrate and the second semiconductor chip; a second molding member filling an area corresponding to an outer periphery of a space between the second substrate and the second semiconductor chip, 20. The semiconductor package of claim 18, wherein a vertical distance between an upper surface of the second substrate and a lower surface of the second semiconductor chip is less than 10 [mu]m.

20. an interposer substrate is disposed on an upper surface of the first substrate, a first semiconductor chip and a second semiconductor chip are mounted on the upper surface of the interposer substrate, a first underfill film and a first molding member are disposed between the interposer substrate and the first semiconductor chip, and a second underfill film and a second molding member are disposed between the interposer substrate and the second semiconductor chip; the second semiconductor chip includes a base chip and a high bandwidth memory (HBM) chip, the HBM chip being mounted on the base chip; 20. The semiconductor package of claim 18, wherein the first underfill film vertically overlaps a central portion of the first semiconductor chip, and the second underfill film vertically overlaps a central portion of the second semiconductor chip.

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