Pulse generation circuit

Abstract

To provide a pulse generation circuit that receives a clock signal and outputs a delayed pulse signal and improves the performance of the pulse generation circuit.SOLUTION: A pulse generation circuit 10 includes a first delay locked loop circuit that receives a clock signal and generates a first delayed signal by delaying the clock signal, a second delay locked loop circuit 60 that generates a second delayed signal on the basis of the first delayed signal, and an output unit 70 that outputs a delayed pulse signal according to the first delayed signal and the second delayed signal. The second delay locked loop circuit includes a second charge pump 630 that outputs a current according to the clock signal and the delayed pulse signal, and a second delay unit 270 that outputs a second delayed signal FB2 by delaying the clock signal according to the current I_UP2 / I_DN2 output by the second charge pump.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a pulse generating circuit. [Background technology]

[0002] Patent document 1 states that "the first DLL circuit 5A compares the first timing signal 101A with the first edge separated signal 111A to determine the phase of the rising edge of the light emission control signal 104. The second DLL circuit 5B compares the second timing signal 101B with the second edge separated signal 111B to determine the phase of the falling edge of the light emission control signal 104." [Prior art document] [Patent documents] Patent Document 1: International Publication No. 2020 / 129954 Summary of the Invention

[0003] In a first aspect of the present invention, there is provided a pulse generation circuit that receives a clock signal as input and outputs a delayed pulse signal, the pulse generation circuit comprising: a first delay locked loop circuit that receives the clock signal as input and generates a first delayed signal by delaying the clock signal; a second delay locked loop circuit that generates a second delayed signal based on the first delayed signal; and an output section that outputs a delayed pulse signal in accordance with the first delayed signal and the second delayed signal.

[0004] In the above pulse generating circuit, the first delay locked loop circuit may have a first charge pump that outputs a current according to a clock signal and a delayed pulse signal, and a first delay section that outputs a first delayed signal by delaying the clock signal according to the current output by the first charge pump.

[0005] In any of the pulse generating circuits described above, the second delay locked loop circuit may have a second charge pump that outputs a current corresponding to a delay amount of the second delay signal, and a second delay section that outputs a second delay signal obtained by delaying the first delay signal by the delay amount in accordance with the current output by the second charge pump.

[0006] In the above pulse generating circuit, the second delay locked loop circuit may have a capacitor connected between a node to which the output of the second charge pump is connected and a reference potential, and the second delay section may output a second delay signal obtained by delaying the first delay signal by an amount of delay corresponding to a ratio between a charging current for charging the capacitor output by the second charge pump and a discharging current for discharging the capacitor.

[0007] In any of the above pulse generating circuits, the second charge pump may output a current according to the first delay signal and the second delay signal.

[0008] In any of the pulse generating circuits described above, the second delay locked loop circuit may have a third delay section that receives a reference signal and outputs a third delayed signal that delays the reference signal in accordance with a current output by the second charge pump, and the second charge pump may output a current in accordance with the reference signal and the third delayed signal.

[0009] In the above-mentioned pulse generating circuit, the second delay section has a plurality of buffers, and the third delay section has a plurality of buffers, and each buffer of the third delay section may have the same size as each buffer of the second delay section, or may have a size that differs by a predetermined ratio from each buffer of the second delay section.

[0010] In any of the above pulse generating circuits, the second charge pump may output a current according to the clock signal and the delayed pulse signal.

[0011] In any of the pulse generating circuits described above, the output section may include a combining circuit that combines the first delay signal and the second delay signal, and a driver that outputs a delayed pulse signal that rises when the first delay signal changes and that falls when the second delay signal changes.

[0012] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0013] [Figure 1] 1 shows a schematic diagram of a pulse generating circuit 10 according to the present embodiment. [Diagram 2] 1 shows a first configuration example of a pulse generating circuit 10. [Diagram 3] 2 shows a more detailed configuration of the first delay locked loop circuit 50. [Figure 4] 2 shows a more detailed configuration example of the first charge pump 330. [Diagram 5] A more detailed configuration example of the first current application section 340 is shown together with a number of buffers. [Figure 6] A more detailed configuration of the second delay locked loop circuit 60 is shown together with the output section 70. [Figure 7] 2 shows a more detailed configuration example of the second charge pump 630. [Figure 8] A more detailed configuration example of the second current application section 640 is shown together with a number of buffers. [Figure 9] 2 shows an example of a timing chart of the first delay locked loop circuit 50 of the present embodiment. [Figure 10] 2 shows an example of a timing chart of the second delay locked loop circuit 60 of the present embodiment. [Figure 11] 13 shows a timing chart of a reference example when frequency hopping is performed in a ToF system. [Figure 12] 2 shows a second configuration example of the pulse generating circuit 10. [Figure 13] 2 shows a more detailed configuration of the second delay locked loop circuit 60 of the second configuration example. [Figure 14] 13 shows an example of a timing chart of the second delay locked loop circuit 60 in the second configuration example. [Figure 15] 1 shows a third configuration example of the pulse generating circuit 10. [Figure 16] 13 shows a more detailed configuration of the second delay locked loop circuit 60 of the third configuration example. [Figure 17]13 shows an example of a timing chart of the second delay locked loop circuit 60 in the third configuration example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0015] 1 shows a schematic diagram of a pulse generating circuit 10 of this embodiment. The pulse generating circuit 10 receives a clock signal at an input terminal 20, delays the clock signal, and outputs a delayed pulse signal. The pulse generating circuit 10 may be included in a ToF (Time of Flight) system that irradiates light and measures the distance to an object using the time it takes for the reflected light from the object to return. In the ToF system, the pulse generating circuit 10 can be used as a current driver that outputs an optical pulse corresponding to the delayed pulse signal generated by the pulse generating circuit 10.

[0016] The pulse generating circuit 10 includes an input buffer 40, a first delay locked loop circuit 50 (first DLL in FIG. 1), a second delay locked loop circuit 60 (second DLL in FIG. 1), and an output section .

[0017] The input buffer 40 is connected to the input terminal 20. The input buffer 40 outputs the clock signal input to the input terminal 20 to the first delay locked loop circuit 50.

[0018] The first delay locked loop circuit 50 is connected to the input buffer 40 and generates a first delay signal by delaying the input clock signal. The first delay locked loop circuit 50 may generate the first delay signal by delaying the clock signal in response to the clock signal and the feedback delayed pulse signal. The first delay locked loop circuit 50 may generate a constant delay by locking the phases of the clock signal and the delayed pulse signal. A more detailed configuration will be described with reference to FIGS. 2 to 5.

[0019] The second delay locked loop circuit 60 is connected in series to the first delay locked loop circuit 50, and generates a second delay signal based on the first delay signal from the first delay locked loop circuit 50. A more detailed configuration will be described with reference to Figures 6 to 8.

[0020] The output section 70 is connected to the first delay locked loop circuit 50, the second delay locked loop circuit 60, and the output terminal 30. The output section 70 outputs to the output terminal 30 a delayed pulse signal that corresponds to the first delay signal and the second delay signal.

[0021] Fig. 2 shows a first configuration example of the pulse generating circuit 10. Fig. 2 shows a more detailed example of the pulse generating circuit 10 shown in Fig. 1. The pulse generating circuit 10 includes an output driver 200 and a dummy input buffer 210 in addition to the configuration shown in Fig. 1.

[0022] The output driver 200 is connected to the output section 70 and may be a MOS or bipolar transistor. The output driver 200 passes a current in response to the delayed pulse signal output by the output section 70.

[0023] The dummy input buffer 210 has an input connected to the output section 70 and an output connected to the first delay locked loop circuit 50. The dummy input buffer 210 feeds back the delayed pulse signal output from the output section 70 to the first delay locked loop circuit 50. The dummy input buffer 210 may be arranged to adjust the phase of the signal to the input buffer 40, etc.

[0024] The first delay locked loop circuit 50 has a first delay control section 220, a first capacitor 230, and a first delay section 240. The first delay control section 220 has an input connected to the input buffer 40 and the dummy input buffer 210. The first delay control section 220 outputs a current according to the clock signal and the delayed pulse signal. The first delay control section 220 may output a current corresponding to the delay amount by which the clock signal is delayed in the first delay locked loop circuit 50.

[0025] The first capacitor 230 is connected between a reference potential and a node to which the output of the first delay control unit 220 is connected. The first capacitor 230 is charged or discharged by a current output from the first delay control unit 220.

[0026] The first delay unit 240 is connected between the input buffer 40 and the second delay locked loop circuit 60, and is connected to the side opposite to the reference potential of the first capacitor 230. The first delay unit 240 delays the clock signal according to the voltage at the node to which the output of the first delay control unit 220 is connected, and outputs a first delay signal.

[0027] The second delay locked loop circuit 60 has a second delay control section 250, a second capacitor 260, and a second delay section 270. The input of the second delay control section 250 is connected to the outputs of the first delay section 240 and the second delay section 270 of the first delay locked loop circuit 50. The second delay control section 250 outputs a current according to the first delay signal output by the first delay locked loop circuit 50 and the second delay signal fed back from the second delay section 270. The second delay control section 250 may output a current corresponding to the delay amount by which the first delay signal is delayed in the second delay locked loop circuit 60.

[0028] The second capacitor 260 is connected between a reference potential and a node to which the output of the second delay control section 250 is connected. The second capacitor 260 is charged or discharged by a current output from the second delay control section 250.

[0029] The second delay unit 270 is connected to the output of the first delay unit 240 and is connected to the opposite side of the reference potential of the second capacitor 260. The second delay unit 270 delays the first delay signal according to the voltage at the node to which the output of the second delay control unit 250 is connected, to generate and output a second delay signal.

[0030] The output section 70 includes a coupling circuit 280, a pre-driver 290, and a pre-driver 295. One input of the coupling circuit 280 is connected to the first delay locked loop circuit 50, and the other input is connected to the second delay locked loop circuit 60. The coupling circuit 280 couples the first delay signal and the second delay signal. The coupling circuit 280 may generate and output a delayed pulse signal that rises when the first delay signal changes and falls when the second delay signal changes by performing a logical AND between the first delay signal at one input and the second delay signal at the other input.

[0031] The pre-driver 290 and the pre-driver 295 output a delayed pulse signal. A feedback path connected to the first delay control section 220 of the first delay locked loop circuit 50 is connected to a node between the pre-driver 290 and the pre-driver 295.

[0032] 3 shows a more detailed configuration of the first delay locked loop circuit 50. The first delay control section 220 has a first pulse generating section 300, a second pulse generating section 310, a first latch section 320, and a first charge pump 330.

[0033] The first pulse generating section 300 has an input connected to the input terminal 20 and an output connected to the first latch section 320. The first pulse generating section 300 may generate a first pulse signal having a predetermined pulse width that rises when the input clock signal CKREF changes. The first pulse generating section 300 may output the first pulse signal to one input of the first latch section 320.

[0034] The second pulse generating section 310 has an input connected to the output section 70 and an output connected to the first latch section 320. The second pulse generating section 310 generates a second pulse signal having a predetermined pulse width that rises when the feedback delayed pulse signal FB changes. The second pulse generating section 310 may output the second pulse signal to the other input of the first latch section 320.

[0035] The output of the first latch section 320 is connected to one input of the first charge pump 330. The first latch section 320 outputs a first control signal CKUP1 in response to the input first pulse signal and second pulse signal. The first latch section 320 may perform SR latch in response to the first pulse signal and the second pulse signal, and output the first control signal CKUP1.

[0036] The first charge pump 330 has the other input connected to the input terminal 20 and an output connected to a node between the first capacitor 230 and the first delay unit 240. The first charge pump 330 outputs a current in response to the clock signal CKREF and the delay pulse signal FB. The first charge pump 330 receives the clock signal CKREF as a second control signal CKDN1 and outputs a current I_UP1 / I_DN1 in response to the first control signal CKUP and the second control signal CKDN. The first charge pump 330 may change the direction of the current I_UP1 / I_DN1 in response to the first control signal CKUP1 and the second control signal CKDN1 to charge or discharge the first capacitor 230. By charging or discharging the first capacitor 230 in this way, the voltage VCAP1 at the node between the first capacitor 230 and the first delay unit 240 increases or decreases.

[0037] The first delay unit 240 outputs a first delay signal OUT1 obtained by delaying the clock signal CKREF according to the current output by the first charge pump 330. The first delay unit 240 has a first current application unit 340 and a plurality of buffers 350, 352, 354, 356. The first current application unit 340 is connected to the side opposite to the reference potential of the first capacitor 230 (a node between the first capacitor 230 and the first delay unit 240). The first current application unit 340 supplies a current according to a voltage VCAP1 at a node between the first capacitor 230 and the first delay unit 240 to the plurality of buffers 350, 352, 354, 356. The plurality of buffers 350, 352, 354, 356 are connected to the first current application unit 340 and are connected in series in a plurality of stages between the input terminal 20 and the output unit 70 (and the second delay locked loop circuit 60). Each of the buffers 350, 352, 354, and 356 may, for example, include two inverters connected in series.

[0038] 4 shows a more detailed configuration example of the first charge pump 330. The first charge pump 330 may receive the first control signal CKUP1 output from the first latch unit 320 and the second control signal CKDN1 from the input terminal 20, and output a current I_UP1 / I_DN1 in response to the first control signal CKUP1 and the second control signal CKDN1. The first charge pump 330 has an inverter 400, a first current source 410, a second current source 420, a first transistor 430, and a second transistor 440.

[0039] The inverter 400 may be connected between a terminal UP to which a first control signal CKUP1 is input and the first transistor 430, and may invert the logic level of the input first control signal CKUP1 and output it. The first current source 410 may be connected to the first transistor 430, and may pass a current I_UP1 having a magnitude according to the signal CNT_IUP to the first transistor 430. The first current source 410 may be a constant current source. The first transistor 430 is connected to the output, and controls the flow / cut-off of the current I_UP1 toward the output according to the first control signal CKUP1 applied to a control terminal (gate terminal).

[0040] The second current source 420 may be connected to the second transistor 440 and may cause a current I_DN1 having a magnitude corresponding to the signal CNT_IDN to flow from the second transistor 440. The second current source 420 may be a constant current source. The second transistor 440 is connected to the output and controls the flow / cut-off of the current I_DN1 from the output to the second current source 420 in response to a second control signal CKDN1 flowing from the terminal DN to the control terminal. With this configuration, the first charge pump 330 may, for example, output the current I_UP1 when only the first control signal CKUP1 is high, sink the current I_DN1 when only the second control signal CKDN1 is high, and output the current difference (I_UP1-I_DN1) when both the first control signal CKUP1 and the second control signal CKDN1 are high.

[0041] The first current source 410 can control the magnitude of the current I_UP1 by the signal CNT_IUP, and the second current source 420 can control the magnitude of the current I_DN1 by the signal CNT_IDN. This allows the first charge pump 330 to control the ratio between the current I_UP1 of the first current source 410 and the current I_DN1 of the second current source 420 according to the input condition of the clock signal CKREF and the delay time (delay amount) required for the delayed pulse signal OUT.

[0042] FIG. 5 shows a more detailed configuration example of the first current applying section 340 together with a plurality of buffers 350, 352, 354, and 356. The first current applying section 340 has a third transistor 500, a resistor 510, a fourth transistor 520, a fifth transistor 530, and a sixth transistor 540. The third transistor 500 is connected to one end of the resistor 510, and a control terminal is connected to the first capacitor 230. The other end of the resistor 510 is connected to a reference potential. The fourth transistor 520 is connected between a power supply and the third transistor 500, and a control terminal is connected to a control terminal of the fifth transistor 530 and a node between the third transistor 500 and the fourth transistor 520. The fifth transistor 530 is connected between a power supply and one end of the sixth transistor 540. The other end of the sixth transistor 540 is connected to a reference potential, and a control terminal is connected to a node between the fifth transistor 530 and one end of the sixth transistor 540.

[0043] The multiple buffers 350 , 352 , 354 , and 356 are each connected between a node between one end of the fifth transistor 530 and the sixth transistor 540 and a reference potential, and are connected in series between the input terminal 20 and the output section 70 .

[0044] The first delay unit 240 receives the voltage VCAP1 charged / discharged in the first capacitor 230 through the third transistor 500 and generates a current. The first delay unit 240 supplies the generated current to the multiple buffers 350, 352, 354, 356 via a current mirror formed by the fourth transistor 520 and the fifth transistor 530. The larger the current supplied, the smaller the delay of each of the buffers 350, 352, 354, 356 becomes, and the smaller the current supplied, the larger the delay of each of the buffers 350, 352, 354, 356 becomes.

[0045] In this embodiment, four stages of buffers 350, 352, 354, and 356 are used, but the number of stages of buffers in the first delay unit 240 may be five or more or less than four depending on the circuit application. Also, it is possible to output signals from each of the buffers 350, 352, 354, and 356 to generate a multiphase clock.

[0046] 6 shows a more detailed configuration of the second delay locked loop circuit 60 together with the output section 70. The second delay control section 250 has a third pulse generating section 600, a fourth pulse generating section 610, a second latch section 620, and a second charge pump 630.

[0047] The third pulse generating section 600 has an input connected to the output of the first delay locked loop circuit 50 and an output connected to the second latch section 620. The third pulse generating section 600 may generate a third pulse signal having a predetermined pulse width that rises when the first delay signal CKREF2 (OUT1) output from the first delay locked loop circuit 50 changes (for example, rises). The third pulse generating section 600 may output the third pulse signal to one input of the second latch section 620.

[0048] The fourth pulse generating section 610 has an input connected to the output of the second delay section 270 and an output connected to the second latch section 620. The fourth pulse generating section 610 generates a fourth pulse signal according to the second delay signal FB2 fed back from the second delay section 270. The fourth pulse generating section 610 generates a fourth pulse signal having a predetermined pulse width that rises when the second delay signal FB2 changes (for example, rises). The fourth pulse generating section 610 may output the fourth pulse signal to the other input of the second latch section 620.

[0049] The output of the second latch section 620 is connected to one input of the second charge pump 630. The second latch section 620 outputs a third control signal CKUP2 in response to the input third pulse signal and fourth pulse signal. The second latch section 620 may perform SR latching in response to the third pulse signal and the fourth pulse signal, and output the third control signal CKUP2 in response to the second delay signal FB2.

[0050] The second charge pump 630 has the other input connected to the output of the first delay lock loop circuit 50, and the output connected to a node between the second capacitor 260 and the second delay unit 270. The second charge pump 630 outputs a current corresponding to a predetermined delay amount of the second delay signal FB2. The second charge pump 630 may output a current according to the first delay signal CKREF2 and the second delay signal FB2. The second charge pump 630 may receive the first delay signal CKREF2 as a fourth control signal CKDN2, and output a current I_UP2 / I_DN2 according to a third control signal CKUP2 and a fourth control signal CKDN2 according to the second delay signal FB2. The second charge pump 630 may change the direction of the current I_UP2 / I_DN2 according to the third control signal CKUP2 and the fourth control signal CKDN2, and charge or discharge the second capacitor 260. The second capacitor 260 is connected between a node to which the output of the second charge pump 630 is connected and a reference potential. By charging or discharging the second capacitor 260 in this manner, the voltage VCAP2 at the node between the second capacitor 260 and the second delay unit 270 increases or decreases.

[0051] The second delay unit 270 outputs a second delay signal FB2 obtained by delaying the first delay signal CKREF2 by a predetermined delay amount according to the current output by the second charge pump 630. The second delay unit 270 may output the second delay signal FB2 obtained by delaying the first delay signal CKREF2 by an amount of delay according to the ratio between a charging current I_UP2 for charging the second capacitor 260 output by the second charge pump 630 and a discharging current I_DN2 for discharging the second capacitor 260.

[0052] The second delay unit 270 has a second current application unit 640 and a plurality of buffers 650, 652, 654, 656, and 658. The second current application unit 640 is connected to the opposite side of the second capacitor 260 from the reference potential (the node between the second capacitor 260 and the second delay unit 270). The second current application unit 640 supplies a current according to a voltage VCAP2 of the node between the second capacitor 260 and the second delay unit 270 to the plurality of buffers 650, 652, 654, 656, and 658. The plurality of buffers 650, 652, 654, 656, and 658 are connected to the second current application unit 640 and are connected in series between the first delay locked loop circuit 50 and the output unit 70. In FIG. 6, the output of the buffer 650 is connected to the combining circuit 280, but this is not limited thereto, and the output of any one of the buffers 650, 652, 654, 656, and 658 may be connected to the combining circuit 280 depending on the required delay amount (the pulse width of the delayed pulse signal).

[0053] 7 shows a more detailed configuration example of the second charge pump 630. The second charge pump 630 may receive the third control signal CKUP2 output from the second latch unit 620 and the fourth control signal CKDN2 (CKREF2) from the first delay locked loop circuit 50, and output a current I_UP2 / I_DN2 in response to the third control signal CKUP2 and the fourth control signal CKDN2. The second charge pump 630 has an inverter 405, a third current source 415, a fourth current source 425, a seventh transistor 435, and an eighth transistor 445.

[0054] The inverter 405 may be connected between a terminal UP to which the third control signal CKUP2 is input and the seventh transistor 435, and may invert the logical level of the input third control signal CKUP2 and output it. The third current source 415 may be connected to the seventh transistor 435, and may cause a current I_UP2 having a magnitude according to the signal CNT_IUP to flow to the seventh transistor 435. The third current source 415 may be a constant current source. The seventh transistor 435 is connected to the output of the second charge pump 630, and controls the flow / cut-off of the current I_UP2 toward the output according to the third control signal CKUP2 applied to the control terminal (gate terminal).

[0055] The fourth current source 425 may be connected to the eighth transistor 445 and may cause the eighth transistor 445 to flow a current I_DN2 having a magnitude corresponding to the signal CNT_IDN. The fourth current source 425 may be a constant current source. The eighth transistor 445 is connected to the output of the second charge pump 630 and controls the flow / cut-off of the current I_DN2 from the output to the fourth current source 425 according to a fourth control signal CKDN2 flowing from the terminal DN to the control terminal. With this configuration, the second charge pump 630 may, for example, output the current I_UP2 when only the third control signal CKUP2 is high, sink the current I_DN2 when only the fourth control signal CKDN2 is high, and output the current difference (I_UP2-I_DN2) when both the third control signal CKUP2 and the fourth control signal CKDN2 are high.

[0056] The third current source 415 can control the magnitude of the current I_UP2 by the signal CNT_IUP, and the fourth current source 425 can control the magnitude of the current I_DN2 by the signal CNT_IDN. This allows the second charge pump 630 to control the ratio between the current I_UP2 of the third current source 415 and the current I_DN2 of the fourth current source 425 according to the pulse width required for the delayed pulse signal OUT. Here, the signals CNT_IUP and CNT_IDN in the second charge pump 630 may be the same as or different from the signals CNT_IUP and CNT_IDN in the first charge pump 330.

[0057] FIG. 8 shows a more detailed configuration example of the second current applying unit 640 together with a plurality of buffers 650, 652, 654, 656, and 658. The second current applying unit 640 has a ninth transistor 505, a resistor 515, a tenth transistor 525, an eleventh transistor 535, and a twelfth transistor 545. The ninth transistor 505 is connected to one end of the resistor 515, and a control terminal is connected to the second capacitor 260. The other end of the resistor 515 is connected to a reference potential. The tenth transistor 525 is connected between a power supply and the ninth transistor 505, and a control terminal is connected to a control terminal of the eleventh transistor 535 and a node between the ninth transistor 505 and the tenth transistor 525. The eleventh transistor 535 is connected between a power supply and one end of the twelfth transistor 545. The other end of the twelfth transistor 545 is connected to a reference potential, and a control terminal is connected to a node between one end of the eleventh transistor 535 and the twelfth transistor 545 .

[0058] A number of buffers 650, 652, 654, 656, and 658 are each connected between a node between one end of the eleventh transistor 535 and the twelfth transistor 545 and a reference potential, and are connected in series between the first delay section 240 and the second delay control section 250 (and the output section 70) of the first delay locked loop circuit 50.

[0059] The second delay unit 270 receives the voltage VCAP2, which is charged and discharged in the second capacitor 260, at the ninth transistor 505 and generates a current. The second delay unit 270 supplies the generated current to the multiple buffers 650, 652, 654, 656, and 658 via a current mirror formed by the tenth transistor 525 and the eleventh transistor 535. The larger the current supplied, the smaller the delay of each of the buffers 650, 652, 654, 656, and 658 becomes, and the smaller the current supplied, the larger the delay of each of the buffers 650, 652, 654, 656, and 658 becomes.

[0060] In this embodiment, five stages of buffers 650, 652, 654, 656, and 658 are used, but the number of stages of buffers in the second delay unit 270 may be six or more or less than five depending on the circuit application.

[0061] 9 shows an example of a timing chart of the first delay locked loop circuit 50 of this embodiment. In the timing chart, CKREF indicates the input clock signal CKREF, FB indicates the delayed pulse signal OUT output from the output unit 70, CKUP1 indicates the first control signal output from the first latch unit 320, CKDN1 indicates the clock signal CKREF input to the first charge pump 330, I_UP1 / I_DN1 indicates the current output from the first charge pump 330, and VCAP1 indicates the voltage of the first capacitor 230.

[0062] 9, the first latch unit 320 detects the first edge (hereinafter, odd-numbered edges) of the clock signal CKREF and the delayed pulse signal FB, and inputs a first control signal CKUP1 according to the detection to the first charge pump 330. The first control signal CKUP1 changes to one logic (first logic) when the clock signal CKREF changes to a first logic (high, for example), and changes to the other logic (second logic (low, for example)) when the delayed pulse signal FB changes to the first logic. The second control signal CKDN1 changes to one logic (first logic) when the clock signal CKREF changes to the first logic, and changes to the other logic (second logic) when the clock signal CKREF changes to the second logic.

[0063] The first charge pump 330 charges the first capacitor 230 with a current I_UP1 from the first edge of the clock signal CKREF to the first edge of the delayed pulse signal FB in response to the first control signal CKUP1. Meanwhile, the first charge pump 330 discharges the current I_DN1 from the first capacitor 230 from the first edge to the second edge (hereafter, even-numbered edges) of the clock signal CKREF in response to the second control signal CKDN1. The current values ​​of the current I_UP1 and the current I_DN1 may be set according to the delay relationship between the clock signal CKREF and the delayed pulse signal FB. The first charge pump 330 charges the second capacitor 260 with a current difference I_UP2-I_DN2 from the first edge of the clock signal CKREF to the first edge of the delayed pulse signal FB to increase the voltage VCAP2, and discharges the current I_DN1 from the first capacitor 230 from the first edge of the delayed pulse signal FB to the second edge of the clock signal CKREF to reduce the voltage VCAP1 and return it to the original level. This allows the generated delay time to be constant.

[0064] 10 shows an example of a timing chart of the second delay locked loop circuit 60 of the present embodiment. In the timing chart, CKREF2 indicates the first delay signal OUT1 output by the first delay locked loop circuit 50, D1 indicates the signal output from the buffer 650, D2 indicates the signal output from the buffer 652, D3 indicates the signal output from the buffer 654, D4 indicates the signal output from the buffer 656, FB2 indicates the signal output from the buffer 658, OUT indicates the delayed pulse signal OUT output from the output unit 70, CKUP2 indicates the third control signal output from the second latch unit 620, CKDN2 indicates the fourth control signal CKREF2 input to the second charge pump 630, I_UP2 / I_DN2 indicates the current output from the second charge pump 630, and VCAP2 indicates the voltage of the second capacitor 260.

[0065] In FIG. 10, the second delay unit 270 delays the first delay signal CKREF2 by using each of the buffers 650, 652, 654, 656, and 658 to output the signals D1 to D4 and FB2. The second latch unit 620 detects the first edges (hereinafter, odd-numbered edges) of the first delay signal CKREF2 and the signal FB2, and inputs a third control signal CKUP2 according to the detection. The third control signal CKUP2 changes to one logic (first logic) when the first delay signal CKREF2 changes to the first logic (high, for example), and changes to the other logic (second logic (low, for example)) when the signal FB2 changes to the first logic. The fourth control signal CKDN2 changes to one logic (first logic) when the first delay signal CKREF2 changes to the first logic, and changes to the other logic (second logic) when the first delay signal CKREF2 changes to the second logic.

[0066] The second charge pump 630 charges the second capacitor 260 with a current I_UP2 from the first edge of the first delay signal CKREF2 to the first edge of the signal FB2 in response to the third control signal CKUP2. Meanwhile, the second charge pump 630 discharges the current I_DN2 from the second capacitor 260 from the first edge to the second edge (hereafter, even-numbered edges) of the first delay signal CKREF2 in response to the fourth control signal CKDN2. The current values ​​of the current I_UP2 and the current I_DN2 may be set according to the delay relationship between the first delay signal CKREF2 and the signal FB2. The second charge pump 630 charges the second capacitor 260 with a current difference I_UP2-I_DN2 from the first edge of the first delay signal CKREF2 to the first edge of the signal FB2 to increase the voltage VCAP2, and discharges the current I_DN1 from the second capacitor 260 from the first edge of the signal FB2 to the second edge of the first delay signal CKREF2 to decrease the voltage VCAP2 back to the original level. This allows the generated delay time to be constant.

[0067] The delay amount P of the delayed pulse signal OUT relative to the clock signal CKREF in this embodiment delay and the pulse width of the clock signal CKREF, IN WidthThe relationship between the current ratio (I_UP / I_DN) of the first charge pump 330 is given by the equation P delay =IN Width ×I_UP / I_DN.

[0068] The pulse generating circuit 10 of the present embodiment as described above can set a delay by the first delay locked loop circuit 50, and can delay the first delayed signal output by the first delay locked loop circuit 50 to set a pulse width by the second delay locked loop circuit 60, so that it can output a delayed pulse signal with high accuracy with an efficient structure. Furthermore, since the delay amount of the delayed pulse signal can be determined by the current ratio between the clock signal CKREF and the first charge pump 330, a constant delay can be generated even if the period of the clock signal CKREF varies due to frequency spreading or the like, as long as the pulse width of the clock signal CKREF does not vary.

[0069] Fig. 11 shows a timing chart of a reference example when frequency hopping is performed in a ToF system. As an example, Fig. 11 shows a timing chart of a circuit in which a plurality of delay-locked loop circuits are connected in parallel, one delay-locked loop circuit delays a clock signal to set the phase of an output pulse signal, and another delay-locked loop circuit delays the clock signal to set the pulse width of the output pulse signal, as in Patent Document 1. In Fig. 11, the input indicates the clock signal input to the plurality of delay-locked loop circuits, and the output indicates the delayed pulse signal output according to the output of the plurality of delay-locked loop circuits.

[0070] In a ToF system, the output pulse signal has a peak of several amperes, and therefore has energy at a specific frequency. If this energy is too large, the emitted energy may affect surrounding electronic devices, preventing the ToF system from achieving its intended performance. Since the peak current increases for long-distance measurements using ToF, it is desirable to mitigate electromagnetic interference (EMI). One example of a solution to this problem is to set the frequency of the input clock signal to f, as shown in "Input" in Figure 11. 1 , f 2 , f 3By using frequency spreading that changes the frequency as shown in Fig. 11, it is possible to prevent energy from concentrating on a specific frequency, alleviating radio interference and reducing the impact on other electronic devices. However, when multiple delay-locked loop circuits are connected in parallel, the delay is synchronized with the clock (edge) of the next period, so that in frequency spreading, a different delay amount is reflected in the next period (in other words, the delay and pulse width adjusted in the previous period are reflected), resulting in fluctuations in the delay amount and pulse width as shown in "Output" in Fig. 11. This affects the accuracy of ranging, and is a problem in ToF systems where the propagation delay between input and output is important.

[0071] On the other hand, in the pulse generating circuit 10 of this embodiment, the first delay locked loop circuit 50 and the second delay locked loop circuit 60 are connected in series, so that the second delay locked loop circuit 60 can generate a delay for the pulse width based on the first delay signal output by the first delay locked loop circuit 50. The pulse generating circuit 10 of this embodiment can determine the amount of delay based on the pulse width of the input clock signal and the current ratio (I_UP2 / I_DN2) of the charge pump of the second delay locked loop circuit 60, so that a predetermined delay can be generated even when the clock signal is frequency spread.

[0072] 12 shows a second configuration example of the pulse generating circuit 10. The second configuration example of the pulse generating circuit 10 will be described below, focusing mainly on the differences from the first configuration example.

[0073] The first delay locked loop circuit 50 in the second configuration example has a configuration and operates similarly to that of the first configuration example, except that the first delay section 240 has three buffers. The three buffers may have configurations and operate similarly to the buffers 350, 352, and 354 of the first delay section 240 in the first configuration example.

[0074] The output section 70 in the second configuration example has a coupling circuit 280, n pre-drivers 290-1 to 290-n (n≧2), and a pre-driver 295. The coupling circuit 280 and the pre-driver 295 may have the same configuration as in the first configuration example and perform the same operation. The n pre-drivers 290-1 to 290-n are connected in series between the coupling circuit 280 and the pre-driver 295.

[0075] The second delay lock loop circuit 60 includes a second delay control section 700, a second capacitor 260, a second delay section 720, a third delay section 710, and a switching section 730. The second delay control section 700 has one input to which a reference signal MCLK is input, and the other input to which the output of the third delay section 710 is connected. The second capacitor 260 is connected between a node to which the output of the second delay control section 700 is connected and a reference potential. The second delay section 720 is connected to the first delay section 240 and the side of the second capacitor 260 opposite to the reference potential. The third delay section 710 receives the reference signal MCLK. Here, the reference signal MCLK may be a master clock signal, and may be a signal different from the clock signal CKREF.

[0076] The switching section 730 has a plurality of inputs connected to the second delay section 720, and an output connected to the output section 70. The switching section 730 may switch the second delayed signal delayed in the second delay section 720 according to the pulse width (1 ns or 2 ns) of the delayed pulse signal, and output it to the output section 70.

[0077] 13 shows a more detailed configuration of the second delay locked loop circuit 60 of the second configuration example. The second delay control section 700 has a third pulse generating section 740, a fourth pulse generating section 750, a second latch section 760, and a second charge pump 770.

[0078] The third pulse generating section 740 has an input connected to a terminal to which the reference signal MCLK is input, and an output connected to the second latch section 760. The third pulse generating section 740 may generate a third pulse signal having a predetermined pulse width that rises when the reference signal MCLK changes (for example, when it rises). The third pulse generating section 740 may output the third pulse signal to one input of the second latch section 760.

[0079] The fourth pulse generating section 750 has an input connected to the output of the third delay section 710 and an output connected to the second latch section 760. The fourth pulse generating section 750 generates a fourth pulse signal according to the third delay signal FB2 fed back from the third delay section 710. The fourth pulse generating section 750 may generate a fourth pulse signal having a predetermined pulse width that rises when the third delay signal FB2 changes (for example, when it rises). The fourth pulse generating section 750 may output the fourth pulse signal to the other input of the second latch section 760.

[0080] The output of the second latch section 760 is connected to one input of the second charge pump 770. The second latch section 760 outputs a third control signal CKUP2 in response to the input third pulse signal and fourth pulse signal. The second latch section 760 may perform SR latching in response to the third pulse signal and the fourth pulse signal, and output the third control signal CKUP2.

[0081] The second charge pump 770 has the other input connected to a terminal to which the reference signal MCLK is input, and the output connected to a node between the second capacitor 260 and the second delay unit 720. The second charge pump 770 may output a current according to the reference signal MCLK and the third delay signal FB2. The second charge pump 770 may receive a signal fixed to high as the fourth control signal CKDN2, and output a current I_UP2 / I_DN2 according to the third control signal CKUP2 and the fourth control signal CKDN2 according to the third delay signal FB2. The second charge pump 770 may change the direction of the current I_UP2 / I_DN2 according to the third control signal CKUP2 and the fourth control signal CKDN2, and charge or discharge the second capacitor 260. By charging or discharging the second capacitor 260 in this way, the voltage VCAP2 at the node between the second capacitor 260 and the second delay unit 720 increases or decreases.

[0082] The second delay section 720 has a second current application section 640 and a plurality of buffers 790, 792, and 794. The second current application section 640 and the plurality of buffers 790, 792, and 794 may have the same configuration as the second current application section 640 and the plurality of buffers 650 to 654 in the first configuration example, and may perform the same operation.

[0083] The third delay unit 710 receives the reference signal MCLK, and outputs a third delay signal FB2 obtained by delaying the reference signal MCLK in accordance with the current output by the second charge pump 770. The third delay unit 710 has a plurality of buffers 780, 782, 784, 786, and 788 connected in series between a terminal to which the reference signal MCLK is input and the fourth pulse generating unit 750. The plurality of buffers 780, 782, 784, 786, and 788 may be connected between the output of the second current applying unit 640 and a reference potential. The plurality of buffers 780, 782, 784, 786, and 788 may receive a current corresponding to the voltage VCAP2 from the second current applying unit 640, and output a third delay signal FB2 obtained by delaying the reference signal MCLK, similar to the buffers 790, 792, and 794 of the second delay unit 720.

[0084] The buffers 780, 782, 784, 786, and 788 of the third delay section 710 may have the same size as the buffers 790, 792, and 794 of the second delay section 720. As an example, the buffers 780, 782, 784, 786, and 788 of the third delay section 710 may generate the same amount of delay in a signal when the same amount of current is supplied from the second current application section 640 to the buffers 790, 792, and 794 of the second delay section 720. Also, the buffers 780, 782, 784, 786, and 788 of the third delay section 710 may have sizes different from the buffers 790, 792, and 794 of the second delay section 720 at a predetermined rate. As an example, when the same amount of current is supplied to the second delay section 720 and the third delay section 710 from the second current application section 640, each buffer 780, 782, 784, 786, 788 of the third delay section 710 may cause a delay amount x to the signal, and each buffer 790, 792, 794 of the second delay section 720 may cause a delay amount y×x (y>1 or y<1) to the signal.

[0085] The switching unit 730 is connected to the outputs of the multiple buffers 790, 792 of the second delay unit 720, and multiple second delay signals with different delay amounts are input to the switching unit 730. Of the multiple second delay signals input, the switching unit 730 may output a second delay signal with a delay amount corresponding to a pulse width that is predetermined or specified by a user to the output unit 70. Note that the switching unit 730 may be connected to the outputs of all of the buffers 790, 792, 794 of the second delay unit 720.

[0086] 14 shows an example of a timing chart of the second delay locked loop circuit 60 of the second configuration example. In the timing chart, MCLK indicates a reference signal, D1 indicates a signal output from the buffer 780, D2 indicates a signal output from the buffer 782, D3 indicates a signal output from the buffer 784, D4 indicates a signal output from the buffer 786, FB2 indicates a signal output from the buffer 788, CKUP2 indicates a signal output from the second latch unit 760, CKDN2 indicates a signal fixed to high input to the second charge pump 770, I_UP2 / I_DN2 indicates a current output from the second charge pump 770, VCAP2 indicates a voltage of the second capacitor 260, OUT1 indicates a first delay signal, D1' indicates a signal output from the buffer 790, D2' indicates a signal output from the buffer 792, D3' indicates a signal output from the buffer 794, and OUT indicates a delayed pulse signal output from the output unit 70.

[0087] 14, the third delay unit 710 delays the reference signal MCLK using each of the buffers 780, 782, 784, 786, and 788 to output signals D1 to D4 and FB2. The second latch unit 760 detects the first edges (hereinafter, odd-numbered edges) of the reference signal MCLK and the third delayed signal FB2, and inputs a third control signal CKUP2 corresponding to the detection to the second charge pump 770. The third control signal CKUP2 changes to one logic (first logic) when the reference signal MCLK changes to the first logic (high, for example), and changes to the other logic (second logic (low, for example)) when the third delayed signal FB2 changes to the first logic.

[0088] The second charge pump 770 charges the second capacitor 260 with a current I_UP2 from the first edge of the reference signal MCLK to the first edge of the signal FB2 in response to the third control signal CKUP2. Meanwhile, the second charge pump 770 discharges the current I_DN2 from the second capacitor 260 in response to the fourth control signal CKDN2. The second charge pump 770 charges the second capacitor 260 with the current difference I_UP2-I_DN2 while the third control signal CKUP2 is high to increase the voltage VCAP2, and discharges the current I_DN1 from the second capacitor 260 while the third control signal CKUP2 is low to reduce the voltage VCAP2 and return it to its original level. This makes it possible to make the generated delay time constant. The second delay unit 720 delays the first delay signal OUT1 using the buffers 790, 792, and 794 to output the signals D1' to D3'. The switching unit 730 outputs the signal D1' to the output unit 70. The output section 70 may output a delayed pulse signal OUT having a pulse width from the rising edge of the first delayed signal OUT to the rising edge of the signal D1'.

[0089] In this embodiment, the pulse width P of the delayed pulse signal OUT Width and the period of the reference signal MCLK period and the current ratio (I_UP2 / I_DN2) of the second charge pump 770 is expressed by the formula P Width =(MCLK period ×I_UP2 / I_DN2) / 5.

[0090] In the pulse generating circuit 10 of the present embodiment as described above, only the delay information, which is a voltage, is input to the path between the input terminal 20 and the output terminal 30, so that the reference signal MCLK input to the second delay locked loop circuit 60 for delay generation and the clock signal input to the first delay locked loop circuit 50 are uncorrelated. Therefore, even if the clock signal is hopping, the second delay locked loop circuit 60 can use a stable reference signal MCLK (period or HorL width) that is not hopping. In addition, since the path of the feedback loop in the second delay locked loop circuit 60 is different from the output path of the output unit 70, if the second delay locked loop circuit 60 for the pulse width is locked first, a delayed pulse signal with a width in the middle of being locked is not output. In addition, the pulse width of the delayed pulse signal can be finely adjusted by the current ratio of the second charge pump 770, and rough correction of 1x and 2x is possible by switching by the switching unit 730.

[0091] 15 shows a third configuration example of the pulse generating circuit 10. The third configuration example of the pulse generating circuit 10 will be described below, focusing mainly on the differences from the first configuration example.

[0092] The first delay locked loop circuit 50 in the third configuration example has a configuration and operates similarly to that in the first configuration example, except that the first delay section 240 has three buffers. The three buffers may have configurations and operate similarly to the buffers 350, 352, and 354 of the first delay section 240 in the first configuration example. The output section 70 in the third configuration example may have a configuration and operate similarly to that in the second configuration example.

[0093] The second delay locked loop circuit 60 in the third configuration example has a second delay control section 800, a second capacitor 260, a second delay section 810, and a switching section 820. The second capacitor 260, the second delay section 810, and the switching section 820 may have the same configurations as the second capacitor 260, the second delay section 720, and the switching section 730 in the second configuration example, and may perform the same operations.

[0094] The second delay control unit 800 has one input connected to the output unit 70 and the other input connected to the input terminal 20. The second delay control unit 800 may control charging / discharging of the second capacitor 260 in response to a clock signal and the delayed pulse signal output by the output unit 70.

[0095] FIG. 16 shows a more detailed configuration of the second delay locked loop circuit 60 of the third configuration example. The second delay control section 800 has a second charge pump 830. The second charge pump 830 has one input connected to the output section 70, the other input connected to the input terminal 20, and an output connected to a node between the second capacitor 260 and the second delay section 810. The second charge pump 830 may output a current according to the clock signal and the delayed pulse signal to the second capacitor 260. The second charge pump 830 may receive the delayed pulse signal as the third control signal CKUP2 and the clock signal as the fourth control signal CKDN2, and output the current I_UP2 / I_DN2 according to the third control signal CKUP2 and the fourth control signal CKDN2. The second charge pump 830 may change the direction of the current I_UP2 / I_DN2 according to the third control signal CKUP2 and the fourth control signal CKDN2 to charge or discharge the second capacitor 260. By charging or discharging the second capacitor 260 in this manner, the voltage VCAP2 at the node between the second capacitor 260 and the second delay unit 810 increases or decreases.

[0096] The second delay section 810 has a second current application section 640 and a plurality of buffers 840, 842, 846, 848, and 850. The second current application section 640 and the plurality of buffers 840, 842, 846, 848, and 850 may have the same configuration as the second current application section 640 and the plurality of buffers 650 to 658 in the first configuration example, and may perform the same operation.

[0097] The switching unit 820 is connected to the outputs of the multiple buffers 840, 842, 846, and 848 of the second delay unit 810, and multiple second delay signals with different delay amounts are input to the switching unit 820. The switching unit 820 may output, from the multiple second delay signals input, a second delay signal with a delay amount corresponding to a pulse width that is predetermined or specified by a user to the output unit 70. The switching unit 820 may be connected to the outputs of all of the buffers 840, 842, 846, 848, and 850 of the second delay unit 810.

[0098] 17 shows an example of a timing chart of the second delay locked loop circuit 60 of the third configuration example. In the timing chart, CKREF (CKDN2) indicates a clock signal, FB (CKUP2) indicates a delayed pulse signal OUT output from the output unit 70, I_UP2 / I_DN2 indicates a current output from the second charge pump 830, VCAP2 indicates a voltage of the second capacitor 260, OUT1 indicates a first delayed signal output from the first delay locked loop circuit 50, D1 indicates a signal output from the buffer 840, D2 indicates a signal output from the buffer 842, D3 indicates a signal output from the buffer 846, and D4 indicates a signal output from the buffer 848.

[0099] 17, the second delay unit 810 outputs signals D1-D4 by delaying the first delayed signal OUT1 using each of buffers 840, 842, 846, and 848. Fig. 17 shows a case where the switching unit 820 selects and outputs the signal D2 output by the buffer 842.

[0100] The second charge pump 830 discharges the current I_DN2 from the second capacitor 260 from the first edge to the second edge of the clock signal CKREF in response to the third control signal CKUP2. Meanwhile, the second charge pump 830 charges the second capacitor 260 with the current I_UP2 from the first edge to the second edge (hereafter, even-numbered edges) of the delayed pulse signal FB in response to the fourth control signal CKDN2. The current values ​​of the current I_UP2 and the current I_DN2 may be set according to the delay relationship between the first delay signal OUT1 and the delayed pulse signal FB. The second charge pump 830 discharges the current I_DN1 from the second capacitor 260 from the first edge to the second edge of the clock signal CKREF to reduce the voltage VCAP2, and charges the second capacitor 260 with the current difference (I_UP2-I_DN2) from the first edge to the second edge of the delayed pulse signal FB to increase the voltage VCAP2 and return it to the original level. This allows the generated delay time to be constant.

[0101] The pulse width P of the delayed pulse signal FB in this embodiment Width and the pulse width of the clock signal CKREF, IN Width and the current ratio (I_UP2 / I_DN2) of the second charge pump 830 is expressed by the formula P Width =IN Width ×I_UP2 / I_DN2.

[0102] The pulse generating circuit 10 of the present embodiment as described above feeds back the output of the pre-driver 290 to the second delay locked loop circuit 60, and adjusts / corrects the output of the second delay locked loop circuit 60 by the pulse width of the clock signal and the current ratio of the charge pump circuit, thereby making it possible to reduce the effects on the delay amount of process variations, fluctuations in temperature characteristics, and the like.

[0103] In addition, the number of buffers in the second delay section of the second delay locked loop circuit 60 in the first to third configuration examples is not limited to the above embodiment, and by increasing the number of stages, the range of the pulse width of the delayed pulse signal can be expanded.

[0104] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0105] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0106] 10 Pulse Generation Circuit 20 Input terminal 30 Output terminal 40 Input Buffer 50 First delay lock loop circuit 60 Second Delay Lock Loop Circuit 70 Output section 200 Output Driver 210 Dummy Input Buffer 220 First delay control section 230 First Capacitor 240 First Delay Section 250 Second delay control section 260 Second Capacitor 270 Second Delay Division 280 Combined circuit 290 Pre-driver 295 Pre-driver 300 First pulse generating unit 310 Second pulse generating unit 320 First latch part 330 First charge pump 340 1st current application section 350 Buffer 352 Buffer 354 Buffer 356 buffers 400 Inverter 405 Inverter 410 1st current source 415 Third current source 420 2nd current source 425 4th current source 430 First Transistor 435 7th Transistor 440 Second Transistor 445 8th transistor 500 3rd transistor 510 Resistance 520 4th transistor 530 5th transistor 540 6th Transistor 505 9th transistor 515 Resistance 525 10th transistor 535 11th transistor 545 12th Transistor 600 Third Pulse Generator 610 4th pulse generator 620 Second latch part 630 Second Charge Pump 640 2nd current application section 650 Buffer 652 Buffer 654 Buffer 656 buffers 658 Buffer 700 Second delay control section 710 3rd Delay Division 720 Second Delay Section 730 Switching section 740 Third Pulse Generator 750 4th Pulse Generator 760 Second latch part 770 Second Charge Pump 780 Buffer 782 Buffer 784 Buffer 786 Buffers 788 Buffer 790 Buffer 792 Buffer 794 Buffer 800 Second delay control section 810 Second Delay Division 820 Switching section 830 Second Charge Pump 840 Buffer 842 Buffer 846 Buffer 848 Buffer 850 Buffer

Claims

1. A pulse generating circuit that receives a clock signal and outputs a delayed pulse signal, a first delay locked loop circuit that receives the clock signal and generates a first delayed signal by delaying the clock signal; a second delay locked loop circuit that generates a second delay signal based on the first delay signal; an output section that outputs the delayed pulse signal in response to the first delay signal and the second delay signal; Pulse generation circuit.

2. The second delay locked loop circuit comprises: a second charge pump that outputs a current corresponding to a delay amount of the second delay signal; a second delay unit that outputs the second delay signal by delaying the first delay signal by the delay amount in response to a current output by the second charge pump.

2. The pulse generating circuit according to claim 1.

3. The first delay locked loop circuit comprises: a first charge pump that outputs a current in response to the clock signal and the delayed pulse signal; a first delay unit that outputs the first delayed signal by delaying the clock signal in response to a current output by the first charge pump; 2. The pulse generating circuit according to claim 1.

4. the second delay lock loop circuit has a capacitor connected between a node to which an output of the second charge pump is connected and a reference potential; The second delay unit outputs the second delay signal by delaying the first delay signal by the delay amount corresponding to a ratio of a charging current for charging the capacitor outputted by the second charge pump to a discharging current for discharging the capacitor.

3. The pulse generating circuit according to claim 2.

5. The second charge pump outputs a current according to the first delay signal and the second delay signal.

3. The pulse generating circuit according to claim 2.

6. The second delay locked loop circuit comprises: a third delay unit that receives a reference signal and outputs a third delayed signal by delaying the reference signal in response to a current output from the second charge pump; The second charge pump outputs a current according to the reference signal and the third delay signal.

3. The pulse generating circuit according to claim 2.

7. the second delay unit has a plurality of buffers, the third delay unit has a plurality of buffers, Each buffer of the third delay unit has the same size as each buffer of the second delay unit, or has a size that differs from each buffer of the second delay unit by a predetermined ratio.

7. The pulse generating circuit according to claim 6.

8. The second charge pump outputs a current according to the clock signal and the delayed pulse signal.

3. The pulse generating circuit according to claim 2.

9. The output unit is a combining circuit for combining the first delayed signal and the second delayed signal; a driver that outputs the delayed pulse signal that rises when the first delayed signal changes and that falls when the second delayed signal changes.

2. The pulse generating circuit according to claim 1.

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