Double-side circuit board and method for manufacturing the same

Abstract

To prevent generation of floating of a plated surface of a double-side plating by providing a predetermined plating missing part to a circuit pattern formed on a base material of the double-side circuit board.SOLUTION: The present invention relates to a double-side circuit board having a copper plating layer in the front and back surfaces of an insulating base material. The plating region of the copper plating layer has a sintered layer formed by sintering an ink layer printed in a pattern with a conductive ink. In an arbitrary point 99 in the plating region of at least one of the plating regions facing each other in the front and back surfaces, a plating missing part 90 is formed in the plating region so that the point 99 is within the region of a predetermined distance X from the plating end part closest to the point 99.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] The present invention relates to a double-sided circuit board having plating layers on both the front and back surfaces of an insulating base material and a method for manufacturing the same.

Background Art

[0002] Conventionally, circuit boards have been manufactured by a subtractive method in which a metal layer is formed on an insulating base material (base material) such as resin, and then unnecessary portions of this metal layer are removed by etching to form a wiring pattern. In this method, a large amount of water and excess metal discarded by etching are used, and many processes have to be gone through.

[0003] On the other hand, the present applicant has proposed a method in which a conductive ink containing metal nanoparticles (metal fine particles) is applied only to necessary portions on an insulating base material composed of a thermoplastic resin such as a polyimide film by an inkjet method or the like, and further a metal layer is thickened by a plating process to reduce the resistance value (Patent Document 1). Such a method (non-subtractive method) different from the conventional subtractive method enables a significant simplification of the substrate manufacturing process, particularly significantly reducing the amount of water used and further succeeding in reducing the carbon dioxide emission amount. Such a non-subtractive method can be said to be a method for manufacturing a circuit board that is environmentally friendly and has few process steps. Also, the inkjet method is a reliable method that can produce a small amount of circuit boards on demand in a minimum of time and cost.

[0004] Patent Document 2 discloses measures such as applying a resin layer (underlayer) called a primer on a substrate when forming a circuit by applying an ink of metal nanoparticles on a polyether ether ketone substrate, forming a photo-sintered film, and forming a plating layer thereon. Photo-sintering performs sintering (firing) of metal nanoparticles using a xenon lamp or the like as a heat source, and enables selective heating of the ink portion of the metal nanoparticles while suppressing the temperature rise of the substrate. Thereby, sintering in a short time with minimal heat impact is achieved even for substrates with low heat resistance.

[0005] Generally, when a single-sided substrate can be fabricated by a certain technology, a substrate is fabricated by using the same principle to fabricate circuits on both sides of the substrate and stacking a plurality of such circuit boards. Therefore, in the multi-layerization of such circuit boards, it is essential to form circuits on both sides of the substrate.

[0006] When manufacturing a conductive circuit by printing a circuit on a substrate by an inkjet method using a conductive ink containing metal nanoparticles and sintering the metal nanoparticle layer on the surface, a method of printing on both sides of the substrate to form a circuit is similarly required.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Non-Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0009] Against the backdrop described above, when implementing a seed layer on a polyimide-based substrate (e.g., a polyimide film) as an insulating substrate using a non-subtractive method with a conductive ink containing metal nanoparticles by utilizing the PS (Photo Sintering) sintering phenomenon of the metal nanoparticles, when circuit patterns are printed on both the front and back surfaces of the substrate, sintered (photo-sintered), and electroless plated, it was found that a large number of defects called "blisters" occur. "Blisters" refer to a phenomenon where, as shown in FIG. 1, the plated surface partially swells into a dome shape (convex shape) (see blister 17).

[0010] When such blisters 17 occur, in terms of the circuit, since that part is easily damaged and leads to disconnection, the occurrence of blisters can be said to be a fatal defect.

[0011] It was reproducibly found that blisters that do not occur at all when printing and plating a circuit pattern on one side of the substrate appear in large quantities when printing and plating on both sides under the same conditions. Therefore, unless this problem is solved, a practical double-sided circuit board cannot be constructed. In the present disclosure, two hypotheses are used to explain the cause of blisters and show a solution to the problem.

[0012] It is known that hydrogen is involved in one of the causes of blisters occurring in electroless plating, and there are many documents referring to this. Non-Patent Document 1 describes that when plating with a formaldehyde bath, hydrogen is involved and blisters are likely to occur. Also, this paper describes that in some cases, the occurrence of blisters can be suppressed by cleaning the surface by ultraviolet (UV) irradiation. This indicates that surface contamination is related to the occurrence of blisters. Among these descriptions, the involvement of hydrogen is as follows.

[0013] That is, a reaction as shown in the following formula 1 occurs on the surface of copper in the plating bath, and it is assumed that the plating grows by the autocatalytic action of copper. Hydrogen is generated in this process. Cu 2++ 2HCHO + 4OH - → Cu + 2HCOO - + H 2 O +H 2 ↑ (Equation 1)

[0014] The hydrogen generation rate is determined by the rate of the above chemical reaction. For example, if the temperature is high, the amount of hydrogen generated increases. Also, in a plating bath with a high copper ion concentration, it is known that floating is likely to occur, which is considered to be related to the increase in the above reaction rate.

[0015] Therefore, the following hypothesis can be considered. Hypothesis 1: The occurrence of floating is caused by the hydrogen that could not be sufficiently discharged when the amount of hydrogen generated exceeds the amount of hydrogen that can be discharged from the gaps in the plating area, resulting in a pressure factor under the plating surface that pushes up the plating surface.

[0016] The mechanism by which hydrogen is discharged from the gaps in the plating area is disclosed in detail in Non-Patent Document 2. This paper describes that hydrogen passes through the spaces between the crystal planes formed during copper plating and is released to the outside.

[0017] On the other hand, it is known that the occurrence of floating increases when there is dirt on the surface of the substrate. Furthermore, when using a conductive ink containing metal nanoparticles, it has been found that floating often occurs in places where sintering is insufficient, and by strengthening the sintering, the occurrence of floating decreases. The dirty areas do not receive a sufficient amount of ink, that is, the amount of metal nanoparticles, so when sintered, they become areas where the sintering density is insufficient. Sintering being insufficient means that the metal nanoparticles have not sufficiently melted and solidified to form a single mass. That is, the surface area of the metal nanoparticles remains large. Therefore, when the plating reaction occurs, due to its large surface area, the amount of hydrogen released by the reaction also relatively increases. In such places, since hydrogen is generated in excess of the amount of hydrogen to be discharged, it is considered that the internal pressure of the plating surface being formed by the non-discharged hydrogen increases and floating occurs. This is not contradictory to the above hypothesis.

[0018] Next, consider the case where lifting occurs only when circuits are printed on both sides of the base material and plating is performed on both sides. Under the condition that no lifting occurs during single-sided plating, when double-sided plating is performed, the phenomenon that both surfaces become completely lifted can be explained by the above hydrogen cause hypothesis. At this time, it is necessary to consider the role of the polyimide film as the base material. As shown in Non-Patent Document 3, the polyimide film has very high hydrogen permeability.

[0019] Hypothesis 2: When no lifting occurs on one side, hydrogen is discharged to the back surface through the polyimide base material, so the internal pressure of the plating layer 14 does not increase. This state is shown in Fig. 2(a). On the other hand, when printing and plating are performed on both sides, as shown in Fig. 2(b), the amount of hydrogen generated doubles, and due to the presence of the plating layer 14 on the back surface, hydrogen cannot escape from the back surface through the polyimide base material 11. For this reason, the internal pressure of the plating layer 14 increases, and lifting 17 is likely to occur. At this time, if there are dirt or other parts where lifting is likely to occur, that will be the starting point of lifting. At this time, it is considered that there is a void 18 filled with hydrogen on the back side of the lifting 17 of the plating layer 14.

[0020] The reasons for the occurrence of lifting in the case of double-sided printing can be explained by these two hypotheses.

[0021] From the above considerations regarding the causes of lifting, several facts can be explained by the hypothesis involving hydrogen. Therefore, based on this hypothesis, countermeasures were studied, which is the present invention. As will be described later, it is shown that the problem of lifting can be solved by an efficient method of discharging the generated hydrogen.

[0022] The present invention has been made under such a background, and its object is to provide a double-sided circuit board and a method for manufacturing the same, which can prevent the occurrence of lifting on the plated surfaces in double-sided plating by providing predetermined plating missing portions in the circuit patterns formed on both sides of an insulating base material using conductive ink.

Means for Solving the Problems

[0023] In the present disclosure, in order to solve the above problems, when forming circuit patterns on both sides of a polyimide film, based on the hypothesis that hydrogen is the cause of the lifting that occurs in the case of double-sided printing, a method of presetting the release route of hydrogen generated during the reaction is used.

[0024] That is, it is to avoid creating circuit patterns with a relatively large area that face each other on the front and back sides of the base material (that overlap each other when projected perpendicular to the base material surface), and to design the circuit pattern so that excess hydrogen does not accumulate and is released to the outside from the plating edges or the like. Also, the width of the circuit pattern is designed to avoid being unnecessarily large.

[0025] Furthermore, it was found that lifting does not occur in the case of a fine line pattern with a line width below a predetermined value. Based on this finding, a hypothesis was established that hydrogen can be released from the plating edge on the surface even when the back surface is plated with a large area.

[0026] Based on this hypothesis, guidelines for circuit pattern design can be created. More specifically, according to one aspect of the present invention, the double-sided circuit board has copper plating layers on both the front and back sides of an insulating base material. The plating region of the copper plating layer has a sintered layer obtained by sintering an ink layer printed in a pattern with conductive ink. At any point within the plating region of at least one of the plating regions facing each other on the front and back sides, a plating omission portion is formed within the plating region so that the point falls within a range of a predetermined distance from the nearest plating edge. With this configuration, hydrogen generated under the plating surface during the plating process is properly released to the outside, so a high-quality double-sided circuit board without lifting on the plating surface can be obtained.

[0027] In one aspect of the present invention, the shape of the plating omission portion is, for example, any one of linear, rectangular, circular, polygonal, or a combination thereof that removes a part of the plating region.

[0028] In one aspect of the present invention, the plating missing portion is formed in a printed image corresponding to the circuit pattern of the conductive ink.

[0029] In one aspect of the present invention, the plating end portion is composed of the end portion of the base material in addition to the plating missing portion.

[0030] In one aspect of the present invention, the plating end portion is composed of the peripheral edge portion of the hole for the via hole provided in the base material in addition to the plating missing portion.

[0031] In one aspect of the present invention, the predetermined distance is a distance of 1 / 2 or less of the maximum width of the fine line pattern in which even if the plating region covering the entire surface is present on the opposite surface, no floating of the plating surface occurs.

[0032] In one aspect of the present invention, the peripheral edge of the plating missing portion forms a closed loop within the plating region.

[0033] In one aspect of the present invention, the base material is made of polyimide.

[0034] In one aspect of the present invention, the conductive ink is an ink containing metal nanoparticles.

[0035] In one aspect of the present invention, the metal nanoparticles are copper nanoparticles.

[0036] In one aspect of the present invention, the printing method is an inkjet method.

[0037] In one aspect of the present invention, the thickness of the copper plating layer is a value within the range of 3 μm to 100 μm.

[0038] In one aspect of the present invention, the sintered layer is a photo-sintered layer.

[0039] According to another aspect, the double-sided circuit board of the present invention is a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating base material. In the plating area of the copper plating layer, there is a sintered layer obtained by sintering an ink layer printed in a pattern with conductive ink. At least one surface of the plating area has a plating omission portion formed so that plating areas with a relatively large area on the front and back surfaces do not face each other. With this configuration, hydrogen generated under the plating surface during the plating process is released to the outside, so a high-quality double-sided circuit board with no floating on the plating surface can be obtained.

[0040] According to one aspect, a method for manufacturing a double-sided circuit board according to the present invention is a method for manufacturing a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating base material. The method includes a step of applying a conductive ink containing metal nanoparticles in a pattern on the surface of the base material, a step of sintering the applied conductive ink, and a step of performing electroless copper plating on the sintered layer formed by the sintering. In the pattern of the conductive ink, a plating omission portion is formed in the plating area on at least one surface of the plating areas facing each other on the front and back surfaces such that any point in the plating area falls within a range of a predetermined distance from the nearest plating end. With this configuration, hydrogen generated under the plating surface during the plating process is released to the outside without causing floating on the plating surface. Also, since electroless copper plating is performed on the sintered layer formed by the conductive ink in a pattern, there is no need for a step of removing a part of the once-formed sintered layer or plating layer afterwards.

[0041] This method for manufacturing a double-sided circuit board may further include a step of applying a resin solution for a resin layer on the surface of the base material and curing it at a predetermined temperature before the step of applying the conductive ink in a pattern.

[0042] In one aspect of this method for manufacturing a double-sided circuit board, the sintering step is a step of photo-sintering the applied conductive ink.

Advantages of the Invention

[0043] According to the double-sided circuit board and its manufacturing method of the present disclosure, by providing a predetermined plating omission portion in the circuit pattern formed on both sides of the insulating base material using conductive ink, it is possible to prevent the occurrence of lifting of the plating surface in double-sided plating.

Brief Description of the Drawings

[0044]

Figure 1

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Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Mode for Carrying Out the Invention

[0045] Hereinafter, embodiments of the present invention will be described in detail. In this embodiment, an approach of securing a hydrogen release route that occurs during plating treatment after double-sided printing with conductive ink on an insulating base material is adopted at the stage of designing a circuit pattern (wiring diagram) in advance.

[0046] <Configuration of Circuit Board> FIG. 3 shows a cross-sectional view schematically showing the basic configuration of a circuit board having a circuit pattern on one side of a base material. FIG. 3(a) shows a schematic configuration, and FIG. 3(b) shows a specific configuration example.

[0047] As shown in FIG. 3(a), the circuit board 10 basically includes a polyimide-based substrate 11 as an insulating substrate, a resin layer 12 coated on the substrate 11, and a sintered layer 13 (conductive film) formed by sintering a metal nanoparticle layer (ink layer) formed by applying a conductive ink containing metal nanoparticles on the resin layer 12, and a plating layer 14 formed on the sintered layer 13. The plating layer 14 constitutes a conductive layer for the circuit. The resin layer 12 is not necessarily an essential element, but by providing the resin layer 12, the adhesion between the sintered layer and the plating layer and the substrate can be improved. The same applies to the configurations described later.

[0048] FIG. 3(b) shows a cross-sectional view of a circuit board in a state of partial printed wiring. In this figure, the sintered layer 13a is obtained by sintering an ink layer as a metal nanoparticle layer formed in a pattern. A plating layer 14a is formed on the sintered layer 13a. The plating layer 14a is formed in the same pattern following the sintered layer 13a.

[0049] FIG. 4 shows a cross-sectional view of a double-sided circuit board when circuit patterns exist on both the front and back surfaces of the substrate 11. The specific configuration of the components of the double-sided circuit board 10a is as follows.

[0050] (Substrate 11) The material of the insulating substrate (insulating substrate) 11 in this embodiment is typically polyimide, but is not necessarily limited to this. For example, it can be polyamideimide, liquid crystal polymer (LCP), polyether ketone, polyamide, polyester, epoxy resin, polyethylene terephthalate. Its thickness is, for example, about 25 μm in this embodiment, but is not limited thereto.

[0051] (Metal nanoparticle layer 13: Ink layer: Layer containing metal nanoparticles: Sintered layer: Conductive film) In this embodiment, the thickness of the metal nanoparticle layer 13 is preferably from 100 nm to 20 μm, more preferably from 200 nm to 5 μm, and most preferably from 500 nm to 2 μm. If this layer is too thin, the mechanical strength may decrease. Conversely, if the ink coating layer is too thick, since metal nanoparticles are generally more expensive than ordinary metals, the manufacturing cost may increase.

[0052] Typically, copper, which is advantageous in terms of cost, is used as the metal of the metal nanoparticles, but it is not necessarily limited to this.

[0053] The average particle diameter of the metal nanoparticles is preferably from 1 nm to 200 nm, more preferably from 10 nm to 100 nm. If the particle diameter is too small, the reactivity of the particles may increase, which may adversely affect the storage stability of the ink. If the particle diameter is too large, it may be difficult to form a uniform thin film, and precipitation of the ink particles may easily occur.

[0054] In ordinary inks, even if metal nanoparticles are mixed, there is no reason to strongly fix the metal nanoparticles to a resin substrate such as polyimide, and a large number of metal nanoparticles can adhere to the resin substrate only after being sintered. Also, in inks using a binder, it is possible to fix the metal particles with a certain degree of strength, but this is not the case when the concentration of the metal nanoparticles is reduced. When the metal nanoparticles are not sintered, the metal nanoparticles may fall off or flow out, resulting in not only a lack of adhesion but also a possible adverse effect on the plating bath.

[0055] (Plating layer 14) The plating layer 14 as the conductive layer is formed on the metal nanoparticle layer 13 by plating treatment (electroless plating). For electroless plating, a standard copper sulfate solution using formaldehyde as a reducing agent with a pH of 10 or more can be used.

[0056] As the plating metal, copper, nickel, tin, silver, gold, etc. can be used, but from the viewpoints of economy and conductivity, it is preferable to use copper. However, copper plating may be used in combination with plating of other metals. For example, in order to prevent oxidation of copper plating, it is conceivable to provide a nickel plating layer on the copper plating layer and further perform gold plating. In this case, the nickel plating layer is provided as a barrier layer to prevent the gold plating layer from diffusing metal into the copper plating layer.

[0057] The thickness of the plating layer 14 is preferably from 3 μm to 100 μm, and more preferably from 3 μm to 35 μm. If the plating layer 14 is too thin, the mechanical strength may be insufficient and the conductivity may not be practically obtained sufficiently. On the contrary, if the plating layer 14 is too thick, the time required for the plating process may become long and the manufacturing cost may increase. In this embodiment, electroless plating is adopted as the plating process, but electrolytic plating may be used after the electroless plating to increase the layer thickness.

[0058] <Method for manufacturing a circuit board> (Primer application step) In this step, a resin solution for the resin layer 12 as a primer is applied to the surface of the polyimide base material. Although the application of the primer is not limited, considering productivity, the roll-to-roll coating method of the polyimide film is preferable. The resin layer as the applied primer is cured at a temperature within the range of 150°C to 200°C. Note that this step is not an essential step in the present invention.

[0059] (Ink application step) In this step, ink containing metal nanoparticles is applied to the surface of a substrate on which a primer has been applied and cured. This application is performed in a pattern on the substrate. At this time, a method by printing can be adopted, typically using an inkjet method. However, it is not necessarily limited to the inkjet method, and other application methods may be used. The pattern of this conductive ink is designed in advance such that in at least one of the plating regions facing each other on both the front and back surfaces, a plating omission portion is formed within the plating region so that a point within the plating region falls within a predetermined distance range from the nearest plating end portion.

[0060] After applying the conductive ink containing metal nanoparticles to the substrate, if there is a solvent, a drying step of removing this is performed. This step is the same as the known drying step for conductive ink. As the drying method for the conductive ink, heating by an oven or the like, hot air drying, etc. can be adopted.

[0061] (Sintering step) After the above ink application step and drying step, a sintering step is executed. As the sintering method, in addition to photo-sintering, heating sintering by an oven or the like, sintering by reduction treatment, etc. can also be adopted, but photo-sintering is adopted in this embodiment. For this purpose, a commercially available photo-sintering apparatus, for example, a photo-sintering apparatus (B0320 - A) manufactured by Ushio Inc. can be used. At that time, the distance between the substrate and the lamp is set, and the voltage, irradiation time, etc. are adjusted. Since photo-sintering ends instantaneously, the time until proceeding to the next step can be short.

[0062] (Plating step) Plating treatment is performed on the formed sintered layer. Thereby, a plated metal is deposited on the surface and inside of the sintered layer. The plating method is the same as the known plating treatment using a known plating solution, specifically electroless copper plating.

[0063] (Lifting generation test pattern 1) To verify the relationship between the size of the circuit pattern and the occurrence of lifting, the inventors used an inkjet device (manufactured by Elefantec Co., Ltd., ELP03) to print the lifting test pattern 1 on both sides of a 25-μm-thick polyimide film 51 (manufactured by Toray DuPont, Kapton 100EN) using a conductive ink containing copper nanoparticles. This printed film was sintered by light on each side using a light sintering device (B0320-A) manufactured by USHIO Inc., and a test double-sided circuit board 50 was fabricated by electroless plating in a formaldehyde bath to a thickness of 12 μm.

[0064] Figures 5 and 6 are photographs showing the appearance of the front (front surface) and back (back surface) of this lifting test pattern 1, respectively. The numbers printed simultaneously in the test pattern of this photograph indicate the line width in millimeters. For example, if it says 0.5, it is a line width of 0.5 mm.

[0065] In the lifting test pattern 1 shown in Figure 5, the rectangular and linear white portions are the plated portions. The plated area on the back surface is a single solid pattern of a large rectangular area. In the photograph of Figure 5, the solid pattern on the back surface appears as a black area through transmission from the front side.

[0066] Looking at the details of these photographs, crater-like depressed portions can be seen. These are the portions where the "lifting" has collapsed. The lifting initially swells in a dome shape, but as it grows, it becomes soft and collapses when the entire substrate is washed with water and the water droplets are blown off with high-pressure air after plating.

[0067] From these two front and back photographs, it can be seen that the locations where lifting occurs are characteristic. That is, first, when looking from the front surface (Figure 5), the following can be confirmed. In Figure 5, for the sake of convenience, the locations where lifting has occurred are shown surrounded by a white line in a circle or ellipse. 1) There is no example of lifting occurring even when there is a pattern with a large area on the back side with a line thinner than 0.6 mm. 2) With a line width of 1.6 mm, there is a portion where a little lifting has occurred (portion 52). 3) In the pattern where the upper width of the figure is wide, there is no bulge in the area without the pattern on the back surface (see area 53).

[0068] Furthermore, when viewed from the back surface having the thick plating area 55 with a large area (Fig. 6), the following can be confirmed. 4) If the plating area with a large area is on the opposite side, a bulge can occur in that area (the area of arrow 61). 5) If the opposite side is a fine line pattern, no bulge will occur even if the area on this side is large (the area of arrow 62).

[0069] As described above, if an appropriate arrangement (size and positional relationship) of the patterns on the back surface and the front surface can be achieved, it becomes possible to prevent the occurrence of bulges. That is, from the experimental results of the bulge generation test pattern 1, it was found that the following requirements are generally needed to suppress the occurrence of bulges.

[0070] · With an area larger than a certain value, ensure that the front and back do not overlap. · When the line width is more than 0.6 mm, do not arrange a pattern with a large area on the back side.

[0071] (Bulge generation test pattern 2) However, in the bulge generation test pattern 1 shown in Figs. 5 and 6, it is not possible to confirm for the line width in the range greater than 0.6 mm and less than 1.6 mm. Fig. 7 shows an example of another bulge generation test pattern 2 with a narrowed range. This is a pattern in which a fine line pattern 72 from 0.4 mm to 1.6 mm at intervals of 0.1 mm is printed on the surface of the polyimide film 71, and a large area (rectangular) solid pattern 74 that covers a part of these fine line patterns 72 is printed on the back surface. A double-sided circuit board 70 for testing based on this test pattern was fabricated. The fabrication process is the same as that of the double-sided circuit board 50 described above.

[0072] Fig. 8 shows the experimental result data obtained by repeatedly producing a large number (here, six) of double-sided circuit boards 70 for testing using the floating generation test pattern 2 and checking for the presence or absence of blisters for each line width. In the figure, the mark "〇" indicates the presence of blisters, and the mark "×" indicates the absence of blisters. "Presence of blisters" corresponds to the case where blisters are generated at one or more locations on at least one of the front and back sides of the substrate.

[0073] As can be seen from this experimental result, it was confirmed that no blisters occurred for fine lines with a line width from 0.4 mm to 1.0 mm.

[0074] Based on the above results, the following considerations were made. Fig. 9 is a cross-sectional view of a double-sided circuit board in the case where the back surface has a solid pattern plating layer 14 with a relatively large area (the entire area in this example), and a linear circuit pattern is formed on the surface facing this. From the above experimental results, if the line width a is 1.0 mm or less, no floating occurs even if the back surface is covered with a pattern having a large area. That is, if the distance b, which is half of the line width, is 0.5 mm or less, the hydrogen generated by the plating reaction at the center of this line can also escape from the plating end. Therefore, in this case, even if the back surface has a solid pattern with a large area, for a single point on the plating layer 14 on the surface, if the distance from that point to the end of the plating layer 14 (the plating end) is 0.5 mm or less, the occurrence of floating at that point is avoided.

[0075] On the other hand, it is considered that hydrogen can also escape from the lateral cross-section of the substrate. That is, the end of the substrate functions to release hydrogen in the same way as the plating end. Therefore, even if the surface of the substrate is covered with the plating surface with c = 0, if the line width a is 1.0 mm or less, hydrogen is released from the end of the substrate and the occurrence of floating is avoided.

[0076] As described above, one solution regarding circuit design can be presented based on the pattern linewidth without the occurrence of lifting. That is, by creating a hydrogen outlet within a range of 0.5 mm from the center of any circuit pattern, the same result as a linewidth without lifting of 1.0 mm or less can be achieved. In this case, the predetermined distance can be said to be a distance equal to or less than 1 / 2 of the maximum width of the fine line pattern without lifting of the plating surface even if the entire surface plating region is on the opposite surface.

[0077] With reference to Fig. 10, the locations where hydrogen generated under the plating surface during the plating process on a double-sided circuit board can be discharged to the outside without causing lifting even when no plating omission part is provided will be collectively described. Fig. 10(a) shows the via hole part 81 and the hole 83. Since there is a hole 84 in the central part of these, the region (hatched part) shown within the circle from the peripheral edge of the hole 84 to a predetermined distance is free from the concern of lifting. Also, as shown in Fig. 10(b), the region (hatched part) within a predetermined distance from the inside of the end 85 of the substrate is also free from the concern of lifting. Furthermore, as shown in Fig. 10(c), the region (hatched part) within a predetermined distance from the inside of the end (plating end) 86 of the plating region on the base material is also free from the concern of lifting. The plurality of types of regions hatched in Figs. 10(a) to 10(c) function complementarily with each other. That is, hydrogen generated under the plating surface at any point on one substrate can have its dissipation guaranteed if the point is within any of the hatched regions. Conversely, if there is a plating region that is not covered even when combining these multiple types of hatched regions, it is necessary to provide a plating omission part with a predetermined shape and size so that the points within such a plating region are included within the plating omission part or the resulting hatched region.

[0078] (Application Example 1) Fig. 11 shows an example of a design drawing of a double-sided circuit board in a square shape with a size of 7 mm × 7 mm and wiring patterns on both sides. Fig. 11(a) shows the wiring diagram of the front surface of this board, and Fig. 11(b) shows the wiring diagram of the back surface. In Fig. 11(b), for the convenience of front-back comparison, it shows the back surface image seen through from the front surface side without inverting the board. In this figure, the filled parts are the places where plating is planned. In this example, the plating metal is copper. The round gray part 81 indicates a via hole, which is a hole penetrating between the front and back surfaces of the board. Also, the part indicated by a white-outlined gray circle represents the position of a common hole 83 with another board to be stacked on this board. Although the via hole part 81 is not shown in white, the hole is open.

[0079] If a board like the one shown in Fig. 11 is to be manufactured by using an inkjet method to draw a circuit pattern with conductive ink on a polyimide-based substrate and then sintering and electroless plating, there may be some raised areas in several places. The following shows the procedure for preventing the occurrence of raised areas in this board.

[0080] Fig. 12(a) republishes the wiring diagram of the front surface of the board shown in Fig. 11(a). Fig. 12(b) shows an image of a partial area cut out from the wiring diagram of Fig. 12(a), where there is no problem even if the plated surface of a wide-area solid pattern on the back surface faces it. The black parts are the places where plating is planned. Regarding the cut-out range in Fig. 12(b), since it is composed only of relatively fine wiring patterns, there is no risk of raised areas even when overlaid with the back surface circuit pattern in Fig. 10(b).

[0081] Regarding the areas other than this cut-out area, it is necessary to consider the relationship with the back surface. When cutting out the part on the back surface that becomes a solid plated surface facing each other on both sides and is problematic, it will be like the image shown in Fig. 13(a). In this example, the image in Fig. 13(a) is a part of the back surface circuit pattern (Fig. 11(b)).

[0082] Therefore, for the circuit pattern (image) in Fig. 13(a), a plating omission part is intentionally provided at the design stage. The plating omission part is a blank part where the plating layer (and the underlying metal nanoparticle layer) is missing. In Fig. 13(b), slits 91 to 94 are shown as an example of the plating omission part. A slit is an elongated, almost linear blank part, regardless of whether it is a straight line or a curve. These slits 91 to 94 satisfy the requirements of the plating omission part in the present disclosure described in detail below.

[0083] When the image in Fig. 13(b) is returned to the circuit pattern of the original Fig. 11(b), it becomes like Fig. 13(c).

[0084] In the case of such a double-sided wiring diagram, by providing a plating omission part as described above, it is possible to prevent the occurrence of floating of the plating surface in double-sided plating.

[0085] (Requirements for the plating omission part) Next, the requirements for forming the plating omission part are examined. Four locations are indicated by star marks as positions (floating generation candidate positions) where floating may occur on the circuit pattern in Fig. 14(a). The shaded part is the area to be plated. Each position of star marks #1 to #4 is a floating generation candidate position in the plating surface where the distance to the plating end is 0.5 mm or more. Here, as the plating end, the peripheral part of the plating area, the peripheral part of the base material, the via hole part 81 and the peripheral part of the hole 83 indicated by circles are included.

[0086] Therefore, as shown in Fig. 14(b), in the present disclosure, for any position in the plating area where floating may occur, a plating omission part 90 is provided on the plating surface so that the distance from that position to the non-plated part is within a predetermined distance. The plating omission part 90 in this example is a combination of rectangular slits 95, 96 and a circular hole 97.

[0087] When the portion of the plating defect 90 is enlarged, it becomes as shown in Fig. 15. As can be seen from this figure, for any point 99 within the plating region where floating may occur when there is no plating defect 90, by providing the plating defect 90, the arbitrary point 99 comes to be within the range of a predetermined distance X from the nearest plating end. Conversely, the shortest distance from that point 99 to the plating end becomes equal to or less than the predetermined distance X set in advance. In other words, when the plating regions on both sides projected perpendicularly to the substrate surface overlap in a relatively wide range, at any point within the overlapping range, the plating defect 90 is formed so that the point is within the range of a predetermined distance X from the nearest plating end. With such a configuration, the cause of floating is eliminated.

[0088] (Other forms of the plating defect portion) Here, as a method for eliminating floating, two types of forms are exemplified. Fig. 16(a) shows the front and back surfaces of the circuit pattern arranged vertically. The region 65 enclosed by the dotted line is a candidate for the location where floating occurs during plating. Here, as the plating defect portion for solving the problem, Fig. 16(b) shows the case where a slit 66 is provided, and Fig. 16(c) shows the case where a circular hole 68 is opened. Whether to select the slit 66 or the circular hole 68 as the plating defect portion can be countered by assuming the generation of hydrogen and having slits or holes within an appropriate distance range as escape paths for hydrogen. If there is a necessary and sufficient hydrogen escape path, there is no problem even if there are an excessive number of slits or holes.

[0089] (Other forms of the plating defect portion) Here, it is shown that holes for the hydrogen escape path are set on the plating surface in a combination of figures. Figs. 17(a) and (b) show images of the original front and back printing patterns. In contrast, Figs. 18(a) and (b) show images of the printing patterns on the front and back surfaces after countermeasures. As shown in Fig. 18(b), in this example, as a more complex shape, the plating defect portions 101 to 106 are configured by combining a slit and circular holes.

[0090] In the above example, all the plating defects are closed within the plating region, that is, the periphery of the plating defect forms a closed loop within the plating region. Such a closed plating defect is a typical plating defect of the present disclosure. However, as shown in part 107 of FIG. 18(b), the plating defect may be in an open form (open loop) extending outside the substrate or to the plating edge, and the present invention does not exclude such a form of plating defect.

[0091] (Modification example) Although the preferred embodiments have been described above, various modifications and changes other than those mentioned above are possible. The materials, sizes, distances, thicknesses, shapes, ratios, etc. used are merely examples and are not necessarily limited thereto.

Explanation of reference numerals

[0092] 10 Circuit board 10a Double-sided circuit board 11 Base material (insulating base material) 12 Resin layer (primer layer) 13, 13a Metal nanoparticle layer (ink layer, sintered layer, conductive film) 14, 14a Plating layer 17 Blister 50 Double-sided circuit board 51 Base material made of polyimide (polyimide film) 52 Portion 53 Region 55 Region 61 Arrow 62 Arrow 65 Region 66 Slit 68 Hole 70 Double-sided circuit board 71 Base material made of polyimide (polyimide film) 72 Fine line pattern 74 Large area (solid) pattern 81 Via hole portion 83 Hole 84 Hole 85 Substrate edge 86 Plating end 90 Plating missing part 91 - 96 Slit 97 Hole 99 Point 101 - 106 Plating missing part 107 Part

Claims

1. A double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating substrate, wherein the plating regions of the copper plating layers have a sintered layer obtained by sintering an ink layer printed in a pattern with conductive ink, and at any point within the plating region of at least one of the plating regions facing each other on the front and back surfaces, a plating defect portion is formed within the plating region such that the point falls within a range of a predetermined distance from the nearest plating end portion.

2. The double-sided circuit board according to claim 1, wherein the shape of the plating defect portion is any one of a linear shape, a rectangular shape, a circular shape, a polygonal shape, or a combination thereof that removes a part of the plating region.

3. The double-sided circuit board according to claim 1, wherein the plating defect portion is formed in a printed image corresponding to the circuit pattern of the conductive ink.

4. The double-sided circuit board according to claim 1, wherein the plating end portion is constituted by an end portion of the substrate in addition to the plating defect portion.

5. The double-sided circuit board according to claim 1, wherein the plating end portion is constituted by a peripheral portion of a hole for a via hole provided in the substrate in addition to the plating defect portion.

6. The double-sided circuit board according to claim 1, wherein the predetermined distance determined in advance is a distance of 1 / 2 or less of the maximum width of a fine line pattern in which even if the plating region is entirely solid on the opposite surface, no lifting of the plating surface occurs.

7. The double-sided circuit board according to claim 1, wherein the peripheral edge of the plating defect portion forms a closed loop within the plating region.

8. The double-sided circuit board according to claim 1, wherein the substrate is made of polyimide.

9. The double-sided circuit board according to claim 3, wherein the conductive ink is an ink containing metal nanoparticles.

10. The double-sided circuit board according to claim 9, wherein the metal nanoparticles are copper nanoparticles.

11. The double-sided circuit board according to claim 1, wherein the printing method is an inkjet method.

12. The double-sided circuit board according to claim 1, wherein the thickness of the copper plating layer is a value within the range of 3 μm to 100 μm.

13. The double-sided circuit board according to claim 1, wherein the sintered layer is a photo-sintered layer.

14. In a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating substrate, the plating region of the copper plating layer has a sintered layer obtained by sintering an ink layer printed in a pattern with conductive ink, and at least one of the plating regions on one of the front and back surfaces has a plating omission portion formed therein so that plating regions with a relatively large area on the front and back surfaces do not face each other.

15. The double-sided circuit board according to claim 14, wherein the shape of the plating omission portion is any one of a slit, a rectangle, a circle, a polygon, or a combination thereof that removes a part of the plating region of the plating layer.

16. The double-sided circuit board according to claim 14, wherein the periphery of the plating omission portion forms a closed loop within the plating region.

17. A method for manufacturing a double-sided circuit board having copper plating layers on both the front and back surfaces of an insulating substrate, a step of applying a conductive ink containing metal nanoparticles in a pattern on the surface of the substrate; a step of sintering the applied conductive ink; a step of performing electroless copper plating treatment on the sintered layer formed by the sintering, and in the pattern of the conductive ink, a plating omission portion is formed within the plating region such that at any point within the plating region of at least one of the plating regions facing each other on the front and back surfaces, the point falls within a predetermined distance range from the nearest plating end portion. A method for manufacturing a double-sided circuit board, characterized in that.

18. The method for manufacturing a double-sided circuit board according to claim 17, further comprising a step of applying a resin solution for a resin layer on the surface of the substrate and curing it at a predetermined temperature before the step of applying the conductive ink in a pattern.

19. The method for manufacturing a double-sided circuit board according to claim 17, wherein the sintering step is a step of photo-sintering the applied conductive ink.

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