Printed circuit board and method for manufacturing the same
The printed circuit board design addresses the challenge of forming cavities with desired depths by using multiple insulating layers and a dummy layer to protect connection patterns, resulting in improved mounting accuracy and reliability.
Patent Information
- Application Number
- JP2024188432
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-11-15
- Filing Date
- 2024-10-25
- Publication Date
- 2025-05-27
AI Technical Summary
Conventional printed circuit boards face challenges in forming cavities with desired depths without damaging connection patterns, which affects mounting accuracy and reliability.
The printed circuit board design includes multiple insulating layers with a cavity formed in some layers, featuring connection portions and a dummy layer at the cavity's bottom. The dummy layer's thickness is adjusted to prevent damage to connection patterns during cavity formation.
This design allows for precise formation of cavities with desired depths, enhancing mounting accuracy and preventing damage to connection patterns, thus maintaining reliable connection characteristics with semiconductor chips.
Smart Images
Figure 2025081241000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a printed circuit board capable of forming a cavity having a desired depth and enhancing mounting accuracy without damaging connection patterns in the cavity, and a method for manufacturing the same.
Background Art
[0002] A printed circuit board is formed by forming a circuit pattern with a conductive material such as copper on an insulating material. As electronic devices in the IT field such as mobile phones are miniaturized, a method has been proposed in which a cavity is formed in the printed circuit board and electronic components such as ICs, active elements, or manual elements are mounted in the cavity. The deeper the cavity of the printed circuit board, the more parts of the electronic component can be mounted in the cavity, and the overall thickness of the product in which the electronic component and the printed circuit board are packaged can be reduced.
[0003] When forming a cavity in a printed circuit board, it is difficult to adjust the depth of the cavity, and the connection pattern for connection with an electronic component in the cavity may be damaged, making it difficult to accurately mount the electronic component in the cavity.
Summary of the Invention
Problems to be Solved by the Invention
[0004] The present invention has been made in view of the above problems in the conventional printed circuit board, and an object of the present invention is to provide a printed circuit board capable of forming a cavity having a desired depth and enhancing mounting accuracy without damaging connection patterns in the cavity, and a method for manufacturing the same.
Means for Solving the Problems
[0005] The printed circuit board according to the present invention made to achieve the above object includes a plurality of insulating layers, a cavity formed in at least a part of the plurality of insulating layers, a plurality of connection portions disposed in the cavity, and a dummy layer disposed at the bottom of the side wall of the cavity and located under the plurality of insulating layers, wherein a first thickness of the dummy layer is smaller than a second thickness of the plurality of connection portions.
[0006] Preferably, along a height direction perpendicular to an upper surface of the plurality of insulating layers, an edge of a side wall of the cavity and an edge of the dummy layer are aligned. Preferably, the dummy layer includes a first dummy layer and a second dummy layer located on the first dummy layer, and an upper surface of the second dummy layer is covered with the plurality of insulating layers. Preferably, it further has a seed layer disposed under the plurality of connection portions, and the first dummy layer includes the same layer as the seed layer. Preferably, the first dummy layer and the second dummy layer include different layers from each other. Preferably, along a height direction perpendicular to an upper surface of the plurality of insulating layers, an edge of a side wall of the cavity, an edge of the first dummy layer, and an edge of the second dummy layer are aligned. Preferably, the dummy layer further includes a third dummy layer located on a side surface of the first dummy layer. Preferably, it further has a cover layer disposed on the plurality of connection portions, and the third dummy layer includes the same layer as the cover layer. Preferably, it further has a seed layer disposed under the plurality of connection portions, and the dummy layer preferably includes a layer different from the seed layer. Preferably, along a height direction perpendicular to an upper surface of the plurality of insulating layers, an edge of a side wall of the cavity and an edge of the dummy layer are aligned. Preferably, along a height direction perpendicular to an upper surface of the plurality of insulating layers, a width of the cavity is not constant.
[0007] The method for manufacturing a printed circuit board according to the present invention, which is made to achieve the above object, includes a step of forming a plurality of connection parts on a first insulating layer, a step of forming a blocking layer on the plurality of connection parts, a step of forming a plurality of insulating layers having a cavity that exposes the blocking layer and covering an edge of the blocking layer, a step of forming a sacrificial layer on the blocking layer within the cavity, a step of removing the sacrificial layer, and a step of removing the blocking layer exposed by the cavity to form a dummy layer disposed at a bottom of a side wall of the cavity and located under the plurality of insulating layers.
[0008] It is preferable to further include a step of forming a seed layer disposed under the plurality of connection parts and the blocking layer. In the step of removing the sacrificial layer, it is preferable that the seed layer not covered by the plurality of insulating layers and the plurality of connection parts is removed. The dummy layer includes a first dummy layer and a second dummy layer located on the first dummy layer, and an upper surface of the second dummy layer is preferably covered with the plurality of insulating layers. It is preferable that the first dummy layer is formed as the same layer as the seed layer, and the second dummy layer is formed as the same layer as the blocking layer. It is preferable to further include a step of forming a cover layer on a surface of the plurality of connection parts. Preferably, the dummy layer further includes a third dummy layer located on a side surface of the first dummy layer. It is preferable that the third dummy layer is formed as the same layer as the cover layer. Preferably, along a height direction perpendicular to an upper surface of the plurality of insulating layers, a width of the cavity is formed not to be constant.
Advantages of the Invention
[0009] According to the printed circuit board and its manufacturing method according to the present invention, the cavity is formed in a part of the plurality of insulating layers, and by adjusting the thickness and number of the insulating layers in which the cavity is formed, a cavity having a desired depth can be formed. Also, during the formation of the cavity, after covering and protecting a plurality of connection parts using a second dummy layer, the second dummy layer is removed during the manufacturing process, and the cavity is formed so that the plurality of connection parts in the cavity are not damaged, thereby preventing a decrease in the connection characteristics between the semiconductor chip mounted in the cavity and the plurality of connection parts.
Brief Description of the Drawings
[0010]
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Mode for Carrying Out the Invention
[0011] Next, specific examples of embodiments for implementing the printed circuit board and the manufacturing method thereof according to the present invention will be described with reference to the drawings. Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those having ordinary knowledge in the technical field to which the present invention pertains can easily implement them. The present invention can be realized in various different forms and is not limited to the embodiments described herein.
[0012] For the sake of clarity in explaining the present invention, parts that are unnecessary for the explanation are omitted, and the same or similar components throughout the specification are denoted by the same reference numerals. In addition, the attached drawings are only for facilitating the understanding of the embodiments disclosed in this specification, and the technical idea disclosed in this specification is not limited by the attached drawings. It should be understood that all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention are included. Also, the sizes and thicknesses of the respective components shown in the drawings are arbitrarily shown for the convenience of explanation, and thus the present invention is not necessarily limited to the places shown in the drawings. In the drawings, the thickness is enlarged to clearly show various layers and regions. And in the drawings, for the convenience of explanation, the thicknesses of some layers and regions are exaggerated.
[0013] Also, when a part such as a layer, film, region, or plate is "on" or "above" another part, this includes not only the case where it is "directly above" the other part, but also the case where there are other parts in between. Conversely, when a part is "directly above" another part, it means that there are no other parts in between. Also, when a part is "on" or "above" a reference part, it means that it is located above or below the reference part, and it does not necessarily mean that it is located "on" or "above" in the direction opposite to gravity. Also, throughout the specification, when a part "includes" a certain component, this means that it can further include other components, rather than excluding other components unless otherwise stated to the contrary.
[0014] Also, throughout the specification, when it is said "on a plane", this means when the target part is viewed from above, and when it is said "in a cross-section", this means when the cross-section obtained by vertically cutting the target part is viewed from the side. Also, throughout the specification, when it says "connected", this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, not only physically connected but also electrically connected, or can be meant to be integral although referred to by different names depending on position or function. Hereinafter, various embodiments and modifications will be described in detail with reference to the drawings.
[0015] Referring to FIGS. 1 and 2, a printed circuit board 100 according to an embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a schematic configuration of a printed circuit board according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a part of FIG. 1. Referring to FIGS. 1 and 2, a printed circuit board 100 according to an embodiment of the present invention includes a plurality of stacked insulating layers IL, a plurality of wiring layers ML embedded in the plurality of insulating layers IL, a plurality of vias VL disposed in a plurality of via holes VA of the plurality of insulating layers IL, a plurality of pad layers PD, a solder resist layer SR, a cavity CV formed in a part of the plurality of insulating layers IL, a plurality of connection parts CM disposed in the cavity CV, and a dummy layer SM disposed along a lower edge of the cavity CV.
[0016] The plurality of insulating layers IL include a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5 stacked along a height direction DRH. The plurality of wiring layers ML include a first wiring layer ML1 embedded by the second insulating layer IL2, a second wiring layer ML2 embedded by the third insulating layer IL3, a third wiring layer ML3 embedded by the fourth insulating layer IL4, and a fourth wiring layer ML4 embedded by the fifth insulating layer IL5. The plurality of vias VL includes a first via VL1 disposed in a first via hole VA1 formed in the first insulating layer IL1, a second via VL2 disposed in a second via hole VA2 formed in the second insulating layer IL2, a third via VL3 disposed in a third via hole VA3 formed in the third insulating layer IL3, a fourth via VL4 disposed in a fourth via hole VA4 formed in the fourth insulating layer IL4, and a fifth via VL5 disposed in a fifth via hole VA5 formed in the fifth insulating layer IL5.
[0017] The plurality of pad layers PD includes a first pad layer PD1 located under the first insulating layer IL1 and a second pad layer PD2 located above the fifth insulating layer IL5. A part of the first wiring layer ML1 and the first pad layer PD1 are connected to each other through the first via VL1, a part of the first wiring layer ML1 and a part of the second wiring layer ML2 are connected to each other through the second via VL2, a part of the second wiring layer ML2 and a part of the third wiring layer ML3 are connected to each other through the third via VL3, a part of the third wiring layer ML3 and a part of the fourth wiring layer ML4 are connected to each other through the fourth via VL4, and a part of the fourth wiring layer ML4 and the second pad layer PD2 are connected to each other through the fifth via VL5. The solder resist layer SR includes a first solder resist layer SR1 disposed under the first insulating layer IL1 and exposing a part of the first pad layer PD1, and a second solder resist layer SR2 disposed above the fifth insulating layer IL5 and exposing a part of the second pad layer PD2.
[0018] The cavity CV is formed in the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5. A plurality of connection portions CM are disposed inside the cavity CV. The plurality of connection portions CM are formed as the same layer as the second wiring layer ML2 embedded in the third insulating layer IL3 and have the same thickness.
[0019] The dummy layer SM is disposed along the bottom edge of the side wall of the cavity CV and includes a first dummy layer SM1, a second dummy layer SM2, and a third dummy layer SM3. The second dummy layer SM2 is disposed on the first dummy layer SM1, the upper surface of the second dummy layer SM2 is covered by the third insulating layer IL3, and the third dummy layer SM3 is disposed on the side surface of the cavity CV side of the second dummy layer SM2. The first dummy layer SM1 and the second dummy layer SM2 include different layers from each other. For example, the first dummy layer SM1 may include copper (Cu), and the second dummy layer SM2 may include nickel (Ni), but the embodiments are not limited thereto. A cover layer CT is disposed on the second pad layer PD2, and a first cover layer CT1 is disposed on the plurality of connection portions CM. The third dummy layer SM3 is formed as the same layer as the first cover layer CT1 and has the same thickness.
[0020] A seed layer SD is disposed under the plurality of wiring layers ML and under the plurality of connection portions CM. The seed layer SD includes the same metal as the plurality of wiring layers ML and the plurality of connection portions CM. Referring to FIG. 2, the cavity CV includes a first cavity CV1 formed in the third insulating layer IL3, second cavities (CV21, CV22) formed in the fourth insulating layer IL4, and third cavities (CV31, CV32) formed in the fifth insulating layer IL5.
[0021] The second cavities (CV21, CV22) formed in the fourth insulating layer IL4 include a first portion CV21 having a first width W1 along a plane direction DRW perpendicular to the height direction DRH, and a second portion CV22 having a second width W2 different from the first width W1. The first portion CV21 of the second cavity CV2 is disposed on the side surface of the third wiring layer ML3 embedded in the fourth insulating layer IL4 and has the same thickness as the third wiring layer ML3 along the height direction DRH, and the second portion CV22 of the second cavity CV2 is disposed on the side surface of the fourth via VL4 located in the fourth via hole VA4 formed in the fourth insulating layer IL4 and has the same thickness as the fourth via VL4 along the height direction DRH. The first width W1 of the first portion CV21 is wider than the second width W2 of the second portion CV22.
[0022] The third cavities (CV31, CV32) formed in the fifth insulating layer IL5 include a first portion CV31 having a third width W3 along a planar direction DRW and a second portion CV32 having a fourth width W4 different from the third width W3. The first portion CV31 of the third cavity CV3 is disposed on a side surface of the fourth wiring layer ML4 embedded in the fifth insulating layer IL5 and has the same height as the fourth wiring layer ML4 along a height direction DRH, and the second portion CV32 of the third cavity CV3 is disposed on a side surface of the fifth via VL5 located in a fifth via hole VA5 formed in the fifth insulating layer IL5 and has the same thickness as the fifth via VL5 along the height direction DRH. The third width W3 of the first portion CV31 is wider than the fourth width W4 of the second portion CV32.
[0023] The dummy layer SM is disposed along a bottom edge of a side wall of the cavity CV, and the dummy layer SM includes a first dummy layer SM1, a second dummy layer SM2, and a third dummy layer SM3. The second dummy layer SM2 is disposed on the first dummy layer SM1, an upper surface of the second dummy layer SM2 is covered with the third insulating layer IL3, and the third dummy layer SM3 is disposed on a side surface of the second dummy layer SM2. The first dummy layer SM1 and the second dummy layer SM2 are inserted into the insulating layer IL, and one side surface of the first dummy layer SM1 and the second dummy layer SM2 forms a part of a side wall of the cavity CV.
[0024] A first cover layer CT1 is disposed on a plurality of connection portions CM. The first cover layer CT1 surrounds side surfaces and an upper surface of the plurality of connection portions CM. The third dummy layer SM3 is located on a side surface of the second dummy layer SM2, and the third dummy layer SM3 is formed as the same layer as the first cover layer CT1 and has the same thickness. A first thickness T1 of the first dummy layer SM1 and the second dummy layer SM2 is smaller than a second thickness T2 of the plurality of connection portions CM. Along a height direction DRH, a first edge E1 of the first dummy layer SM1 and the second dummy layer SM2 is aligned with a second edge E2 of a first cavity CV1 formed in the third insulating layer IL3 inside the cavity CV.
[0025] A seed layer SD is disposed under a plurality of connection portions CM, and the first dummy layer SM1 is formed as the same layer as the seed layer SD located under the plurality of connection portions CM and has the same thickness. During the formation of the cavity CV, after the second dummy layer SM2 covers and protects the plurality of connection portions CM, the second dummy layer SM2 is removed during the manufacturing process.
[0026] According to the printed circuit board according to an embodiment of the present invention, the cavity CV is formed in some of the plurality of insulating layers IL (IL3, IL4, IL5), and by adjusting the thickness and number of the insulating layers in which the cavity CV is formed, a cavity CV having a desired depth can be formed. Also, during the formation of the cavity CV, after covering and protecting the plurality of connection portions CM using the second dummy layer SM2, the second dummy layer SM2 is removed during the manufacturing process, and the cavity CV is formed so that the plurality of connection portions CM in the cavity CV are not damaged, thereby preventing a decrease in the connection characteristics between the semiconductor chip mounted in the cavity CV and the plurality of connection portions CM.
[0027] With reference to FIGS. 1 and 2 and FIGS. 3 to 14, a method for manufacturing a printed circuit board according to an embodiment of the present invention will be described. FIGS. 3 to 14 are cross-sectional views for explaining a method for manufacturing a printed circuit board according to an embodiment of the present invention. Referring to FIG. 3, a second via VL2 located in a second via hole VA2 formed in a second insulating layer IL2 and a second wiring layer ML2 located on the second insulating layer IL2 and connected to the second via VL2 are formed, and a first seed layer SD1 and a plurality of connection portions CM located on the first seed layer SD1 are formed on the second insulating layer IL2.
[0028] Next, a blocking layer CPL is formed so as to cover the first seed layer SD1 and the plurality of connection portions CM. The blocking layer CPL includes a metal layer different from the first seed layer SD1 and the plurality of connection portions CM, and the blocking layer CPL has an etching rate different from that of the first seed layer SD1 and the plurality of connection portions CM. The first seed layer SD1 is formed together with a seed layer SD positioned under the second wiring layer ML2.
[0029] Referring to FIG. 4, a third insulating layer IL3 is laminated on the second wiring layer ML2, the blocking layer CPL, and the second insulating layer IL2, and a second seed layer SD2 is laminated on the third insulating layer IL3. Referring to FIG. 5, the second seed layer SD2 and the third insulating layer IL3 are etched to form a first hole CV1A at a position where a first cavity CV1 of the cavity CV is formed, and at the same time, a third via hole VA3 is formed in the third insulating layer IL3. The edge portions of the blocking layer CPL and the first seed layer SD1 are not exposed in the first hole CV1A, and the third insulating layer IL3 and the second seed layer SD2 are disposed on the edge portions of the blocking layer CPL and the first seed layer SD1. At this time, the blocking layer CPL can prevent the plurality of connection portions CM from being damaged when forming the first hole CV1A by covering and protecting the first seed layer SD1 and the plurality of connection portions CM.
[0030] Referring to FIG. 6, after forming a dry film DF1 on a part of the second seed layer SD2, a metal layer is laminated on the second wiring layer ML2 and the second seed layer SD2 exposed by the third via hole VA3 formed in the third insulating layer IL3, the metal layer is patterned, the dry film DF1 is removed, and the exposed second seed layer SD2 is removed to form a third via VL3 and a third wiring layer ML3, and a first sacrificial layer SFL1 is formed in the first hole CV1A.
[0031] Referring to FIG. 7, a fourth insulating layer IL4 is laminated on the third wiring layer ML3, the first sacrificial layer SFL1, and the third insulating layer IL3, and a third seed layer SD3 is laminated on the fourth insulating layer IL4. Next, the third seed layer SD3 and the fourth insulating layer IL4 are etched to form a second hole CV2A at a position where a second cavity CV2 of the cavity CV is formed, and at the same time, a fourth via hole VA4 is formed in the fourth insulating layer IL4. At this time, together with the blocking layer CPL, the first sacrificial layer SFL1 covers and protects the first seed layer SD1 and the plurality of connection portions CM, so that when forming the second hole CV2A, damage to the plurality of connection portions CM can be prevented.
[0032] Referring to FIG. 8, a fourth via VL4 connected to the third wiring layer ML3 is formed in the fourth via hole VA4, a fourth wiring layer ML4 connected to the fourth via VL4 is formed on the fourth insulating layer IL4, and a second sacrificial layer SFL2 is formed in the second hole CV2A. Referring to FIG. 9, a fifth insulating layer IL5 is laminated on the fourth wiring layer ML4, the second sacrificial layer SFL2, and the fourth insulating layer IL4, and a fourth seed layer SD4 is laminated on the fifth insulating layer IL5. Next, the fourth seed layer SD4 and the fifth insulating layer IL5 are etched to form a third hole CV3A at a position where the third cavity CV3 of the cavity CV is formed, and at the same time, a fifth via hole VA5 is formed in the fifth insulating layer IL5. At this time, together with the blocking layer CPL, the first sacrificial layer SFL1 and the second sacrificial layer SFL2 cover and protect the first seed layer SD1 and the plurality of connection portions CM, so that when forming the third hole CV3A, damage to the plurality of connection portions CM can be prevented.
[0033] Referring to FIG. 10, a fifth via VL5 connected to the fourth wiring layer ML4 is formed in the fifth via hole VA5, a second pad layer PD2 connected to the fifth via VL5 is formed on the fifth insulating layer IL5, and a third sacrificial layer SFL3 is formed in the third hole CV3A. Referring to FIG. 11, a first solder resist layer SR1 that exposes a part of the first pad layer PD1 is formed under the first insulating layer IL1, and a second solder resist layer SR2 that exposes a part of the second pad layer PD2 is formed on the fifth insulating layer IL5.
[0034] Referring to FIG. 12, a mask layer MSK is formed on the second solder resist layer SR2. The mask layer MSK exposes the third sacrificial layer SFL3. Referring to FIG. 13, using the mask layer MSK as an etching mask, the third sacrificial layer SFL3, the second sacrificial layer SFL2, and the first sacrificial layer SFL1 are etched and removed. At this time, the blocking layer CPL can prevent the plurality of connection portions CM from being damaged by covering and protecting the first seed layer SD1 and the plurality of connection portions CM.
[0035] Referring to FIG. 14, using the mask layer MSK as an etching mask, the blocking layer CPL and the first seed layer SD1 exposed by the cavity CV are sequentially removed, and the seed layer SD located under the plurality of connection portions CM, the first dummy layer SM1 located at the lower surface edge of the first cavity CV1, and the second dummy layer SM2 are formed. Next, the plurality of connection portions CM, the second pad layer PD2, and the exposed portions of the first dummy layer SM1 are surface-treated to form a cover layer CT on the second pad layer PD2, form a first cover layer CT1 on the plurality of connection portions CM, form a third dummy layer SM3 on the side surface of the first dummy layer SM1, thereby forming the printed circuit board 100 shown in FIGS. 1 and 2.
[0036] Thus, according to the method for manufacturing a printed circuit board according to an embodiment of the present invention, the cavity CV is formed in a plurality of insulating layers (IL3, IL4, IL5). Therefore, by adjusting the thickness and number of the plurality of insulating layers (IL3, IL4, IL5) in which the cavity CV is formed, a cavity CV having a desired thickness can be formed. Also, during the formation of the cavity CV, by covering and protecting the plurality of connection portions CM located in the cavity CV with the blocking layer CPL and the sacrificial layers (SFL1, SFL2, SFL3), the plurality of connection portions CM in the cavity CV are not damaged during the formation of the cavity CV, so that a decrease in the connection characteristics between the semiconductor chip mounted in the cavity CV and the plurality of connection portions CM can be prevented.
[0037] Referring to FIGS. 15 and 16, a printed circuit board 200 according to another embodiment of the present invention will be described. FIG. 15 is a cross-sectional view showing a schematic configuration of a printed circuit board according to another embodiment of the present invention, and FIG. 16 is an enlarged view of a part of FIG. 15. Referring to FIG. 15, the printed circuit board 200 according to the present embodiment is similar to the printed circuit board 100 according to the foregoing embodiment. Specific descriptions of the same components are omitted.
[0038] The printed circuit board 200 according to the present embodiment includes a plurality of stacked insulating layers IL, a plurality of wiring layers ML embedded in the plurality of insulating layers IL, a plurality of vias VL located in a plurality of via holes VA of the plurality of insulating layers IL, a plurality of pad layers PD, a solder resist layer SR, a cavity CV formed in a part of the plurality of insulating layers IL, a plurality of connection parts CM located in the cavity CV, and a dummy layer SM2 located along the lower edge of the cavity CV. The plurality of insulating layers IL includes a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, and a fifth insulating layer IL5 stacked along the height direction DRH. The plurality of wiring layers ML includes a first wiring layer ML1 embedded by the second insulating layer IL2, a second wiring layer ML2 embedded by the third insulating layer IL3, a third wiring layer ML3 embedded by the fourth insulating layer IL4, and a fourth wiring layer ML4 embedded by the fifth insulating layer IL5.
[0039] The plurality of vias VL includes a first via VL1 located in a first via hole VA1 formed in the first insulating layer IL1, a second via VL2 located in a second via hole VA2 formed in the second insulating layer IL2, a third via VL3 located in a third via hole VA3 formed in the third insulating layer IL3, a fourth via VL4 located in a fourth via hole VA4 formed in the fourth insulating layer IL4, and a fifth via VL5 located in a fifth via hole VA5 formed in the fifth insulating layer IL5. The plurality of pad layers PD includes a first pad layer PD1 located under the first insulating layer IL1 and a second pad layer PD2 located on the fifth insulating layer IL5.
[0040] A part of the first wiring layer ML1 and the first pad layer PD1 are connected to each other through the first via VL1. A part of the first wiring layer ML1 and a part of the second wiring layer ML2 are connected to each other through the second via VL2. A part of the second wiring layer ML2 and a part of the third wiring layer ML3 are connected to each other through the third via VL3. A part of the third wiring layer ML3 and a part of the fourth wiring layer ML4 are connected to each other through the fourth via VL4. A part of the fourth wiring layer ML4 and the second pad layer PD2 are connected to each other through the fifth via VL5. The solder resist layer SR includes a first solder resist layer SR1 located under the first insulating layer IL1 and exposing a part of the first pad layer PD1, and a second solder resist layer SR2 located on the fifth insulating layer IL5 and exposing a part of the second pad layer PD2.
[0041] The cavity CV is formed in the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5. A plurality of connection parts CM are arranged inside the cavity CV. The plurality of connection parts CM are formed as the same layer as the second wiring layer ML2 embedded in the third insulating layer IL3 and have the same thickness.
[0042] The second dummy layer SM2 is arranged along the bottom edge of the side wall of the cavity CV. Different from the printed circuit board 100 according to the foregoing embodiment, the printed circuit board 200 according to the present embodiment does not include a first dummy layer SM1 formed as the same layer as the seed layer SD, and a third dummy layer SM3 formed as the same layer as the cover layer CT and the first cover layer CT1. The upper surface of the second dummy layer SM2 is covered by the third insulating layer IL3. The second dummy layer SM2 may contain nickel (Ni), but the embodiment is not limited thereto. The second dummy layer SM2 is inserted into the insulating layer IL, and one side surface of the second dummy layer SM2 forms a part of the side wall of the cavity CV.
[0043] The cavity CV includes a first cavity CV1 formed in the third insulating layer IL3, a second cavity (CV21, CV22) formed in the fourth insulating layer IL4, and a third cavity (CV31, CV32) formed in the fifth insulating layer IL5. The second cavity (CV21, CV22) formed in the fourth insulating layer IL4 includes a first portion CV21 having a first width W1 along a plane direction DRW perpendicular to the height direction DRH, and a second portion CV22 having a second width W2 different from the first width W1. The first portion CV21 of the second cavity CV2 is disposed on a side surface of the third wiring layer ML3 embedded in the fourth insulating layer IL4 and has the same thickness as the third wiring layer ML3 along the height direction DRH. The second portion CV22 of the second cavity CV2 is disposed on a side surface of the fourth via VL4 located in the fourth via hole VA4 formed in the fourth insulating layer IL4 and has the same thickness as the fourth via VL4 along the height direction DRH. The first width W1 of the first portion CV21 is wider than the second width W2 of the second portion CV22.
[0044] The third cavity (CV31, CV32) formed in the fifth insulating layer IL5 includes a first portion CV31 having a third width W3 along the plane direction DRW, and a second portion CV32 having a fourth width W4 different from the third width W3. The first portion CV31 of the third cavity CV3 is disposed on a side surface of the fourth wiring layer ML4 embedded in the fifth insulating layer IL5 and has the same height as the fourth wiring layer ML4 along the height direction DRH. The second portion CV32 of the third cavity CV3 is disposed on a side surface of the fifth via VL5 located in the fifth via hole VA5 formed in the fifth insulating layer IL5 and has the same thickness as the fifth via VL5 along the height direction DRH. The third width W3 of the first portion CV31 is wider than the fourth width W4 of the second portion CV32.
[0045] The first thickness T1 of the second dummy layer SM2 is smaller than the second thickness T2 of the plurality of connection portions CM. Along the height direction DRH, the first edge E1 of the second dummy layer SM2 is aligned in a row with the second edge E2 of the first cavity CV1 formed in the third insulating layer IL3 within the cavity CV. During the formation of the cavity CV, after the second dummy layer SM2 covers and protects the plurality of connection parts CM, the second dummy layer SM2 is removed during the manufacturing process.
[0046] According to the printed circuit board of the present embodiment, the cavity CV is formed in some of the plurality of insulating layers (IL3, IL4, IL5) of the plurality of insulating layers IL, and by adjusting the thickness and number of the insulating layers in which the cavity CV is formed, a cavity CV having a desired depth can be formed. Also, during the formation of the cavity CV, after covering and protecting the plurality of connection parts CM using the second dummy layer SM2, the second dummy layer SM2 is removed during the manufacturing process, and the cavity CV is formed so that the plurality of connection parts CM in the cavity CV are not damaged, thereby preventing a decrease in the connection characteristics between the semiconductor chip mounted in the cavity CV and the plurality of connection parts CM.
[0047] Hereinafter, with reference to FIGS. 15 and 16 and FIGS. 17 to 21, a method for manufacturing a printed circuit board according to another embodiment of the present invention will be described. FIGS. 17 to 21 are cross-sectional views for explaining a method for manufacturing a printed circuit board according to another embodiment of the present invention. Referring to FIGS. 17 to 21, the method for manufacturing a printed circuit board according to another embodiment of the present invention is similar to the method for manufacturing a printed circuit board according to the foregoing embodiment. Specific descriptions regarding the same manufacturing process will be omitted.
[0048] Referring to FIG. 17, when forming the second wiring layer ML2 on the second insulating layer IL2, a portion that is not located under the plurality of connection parts CM in the first seed layer SD1 is removed, and a seed layer SD is formed under the plurality of connection parts CM. Referring to FIG. 18, a blocking layer CPL that covers the plurality of connection parts CM is formed on the second insulating layer IL2. The blocking layer CPL includes a metal layer different from the seed layer SD and the plurality of connection parts CM, and the blocking layer CPL has an etching rate different from that of the seed layer SD and the plurality of connection parts CM.
[0049] Referring to FIG. 19, a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a third via hole VA3, a fourth via hole VA4, a fifth via hole VA5, a third via VL3, a fourth via VL4, a fifth via VL5, a second pad layer PD2, a first sacrificial layer SFL1, a second sacrificial layer SFL2, a third sacrificial layer SFL3, solder resist layers SR1, SR2, and a mask layer MSK are formed. The third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5 are disposed on the edge portion of the blocking layer CPL. Referring to FIG. 20, using the mask layer MSK as an etching mask, the third sacrificial layer SFL3, the second sacrificial layer SFL2, and the first sacrificial layer SFL1 are etched and removed. At this time, the blocking layer CPL can prevent the plurality of connection portions CM from being damaged by covering and protecting the plurality of connection portions CM.
[0050] Referring to FIG. 21, using the mask layer MSK as an etching mask, the blocking layer CPL exposed by the cavity CV is removed, and a second dummy layer SM2 located at the lower surface edge of the first cavity CV1 is formed. Next, the exposed portions of the plurality of connection portions CM and the second pad layer PD2 are surface-treated to form a cover layer CT on the second pad layer PD2 and a first cover layer CT1 on the plurality of connection portions CM, thereby forming the printed circuit board 100 shown in FIGS. 15 and 16.
[0051] Thus, according to the method for manufacturing a printed circuit board according to this embodiment, the cavity CV can be formed in a plurality of insulating layers (IL3, IL4, IL5). Therefore, by adjusting the thickness and number of the plurality of insulating layers (IL3, IL4, IL5) in which the cavity CV is formed, a cavity CV having a desired thickness can be formed. Also, while forming the cavity CV, by covering a plurality of connection parts CM located in the cavity CV with a blocking layer CPL and sacrificial layers (SFL1, SFL2, SFL3) for protection, during the formation of the cavity CV, the plurality of connection parts CM in the cavity CV are prevented from being damaged, so that it is possible to prevent a deterioration in the connection characteristics between the semiconductor chip mounted in the cavity CV and the plurality of connection parts CM.
[0052] Note that the present invention is not limited to the above-described embodiments. Various modifications can be made without departing from the technical scope of the present invention.
Explanation of Reference Numerals
[0053] 100, 200 Printed Circuit Board CM Connection Part CPL Blocking Layer CT Cover Layer CT1 First Cover Layer CV Cavity CV1, CV2, CV3 (First to Third) Cavities CV21, CV22 First and Second Parts of the Second Cavity CV31, CV32 First and Second Parts of the Third Cavity IL Insulating Layer IL1, IL2, IL3, IL4, IL5 (First to Fifth) Insulating Layers ML Wiring Layer ML1, ML2, ML3, ML4 (First to Fourth) Wiring Layers MSK Mask Layer PD Pad Layer PD1, PD2 (First and Second) Pad Layers SFL1, SFL2, SFL3 (First to Third) Sacrificial Layers SD Seed Layer SD1, SD2, SD3, SD4 (First to Fourth) Seed Layers SM Dummy Layer SM1, SM2, SM3 (First to Third) Dummy Layers SR Solder Resist Layer SR1, SR2 (First and Second) Solder Resist Layers VA via hole VA1, VA2, VA3, VA4, VA5 (1st - 5th) via holes VL via VL1, VL2, VL3, VL4, VL5 (1st - 5th) vias
Claims
1. A plurality of insulating layers; a cavity formed in at least a portion of the plurality of insulating layers; a plurality of connectors disposed within the cavity; a dummy layer disposed at a bottom of a sidewall of the cavity and located below the insulating layers; The printed circuit board according to claim 1, wherein a first thickness of the dummy layer is smaller than a second thickness of the plurality of connecting portions.
2. 2. The printed circuit board according to claim 1, wherein edges of the sidewalls of the cavity and edges of the dummy layers are aligned along a height direction perpendicular to the upper surfaces of the insulating layers.
3. the dummy layer includes a first dummy layer and a second dummy layer located on the first dummy layer, The printed circuit board of claim 1 , wherein an upper surface of the second dummy layer is covered with the plurality of insulating layers.
4. a seed layer disposed under the plurality of connections; The printed circuit board of claim 3 , wherein the first dummy layer comprises the same layer as the seed layer.
5. The printed circuit board of claim 4 , wherein the first dummy layer and the second dummy layer include different layers.
6. 6. The printed circuit board of claim 5, wherein edges of the sidewalls of the cavity and edges of the first dummy layer and the second dummy layer are aligned along a height direction perpendicular to the upper surfaces of the insulating layers.
7. The printed circuit board of claim 5 , wherein the dummy layer further comprises a third dummy layer located on a side of the first dummy layer.
8. a cover layer disposed over the plurality of connections; The printed circuit board of claim 7 , wherein the third dummy layer comprises the same layer as the cover layer.
9. a seed layer disposed under the plurality of connections; The printed circuit board of claim 1 , wherein the dummy layer comprises a layer different from the seed layer.
10. 10. The printed circuit board of claim 9, wherein an edge of a sidewall of the cavity and an edge of the dummy layer are aligned along a height direction perpendicular to the upper surfaces of the insulating layers.
11. 2. The printed circuit board of claim 1, wherein the width of the cavity is not constant along a height direction perpendicular to the upper surfaces of the insulating layers.
12. forming a plurality of contacts on the first insulating layer; forming a barrier layer over the plurality of connections; forming a plurality of insulating layers having cavities exposing the barrier layer and covering edges of the barrier layer; forming a sacrificial layer on the barrier layer within the cavity; removing the sacrificial layer; removing the blocking layer exposed by the cavity to form a dummy layer disposed at a bottom of a sidewall of the cavity and below the plurality of insulating layers.
13. 13. The method of claim 12, further comprising forming a seed layer disposed under the plurality of connections and the barrier layer.
14. 14. The method of claim 13, wherein the removing of the sacrificial layer comprises removing the seed layer that is not covered by the insulating layers and the connecting portions.
15. the dummy layer includes a first dummy layer and a second dummy layer located on the first dummy layer, The method of claim 14, wherein an upper surface of the second dummy layer is covered with the plurality of insulating layers.
16. the first dummy layer is formed as the same layer as the seed layer; The method of claim 15, wherein the second dummy layer is formed as the same layer as the blocking layer.
17. 16. The method of claim 15, further comprising forming a cover layer on the surfaces of the plurality of connection portions.
18. 20. The method of claim 17, wherein the dummy layer further comprises a third dummy layer located on a side of the first dummy layer.
19. The method of claim 18, wherein the third dummy layer is formed as the same layer as the cover layer.
20. 13. The method of claim 12, wherein the width of the cavity is not uniform along a height direction perpendicular to the upper surfaces of the insulating layers.